1 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s 2 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck \ 3 ; RUN: -check-prefix=CHECK-REG %s 4 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \ 5 ; RUN: FileCheck %s 6 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \ 7 ; RUN: FileCheck -check-prefix=CHECK-FISL %s 8 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck \ 9 ; RUN: -check-prefix=CHECK-P9-REG %s 10 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 < %s | FileCheck \ 11 ; RUN: -check-prefix=CHECK-P9-FISL %s 12 target datalayout = "E-m:e-i64:64-n32:64" 13 target triple = "powerpc64-unknown-linux-gnu" 14 15 define double @foo1(double %a) nounwind { 16 entry: 17 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind 18 br label %return 19 20 ; CHECK-REG: @foo1 21 ; CHECK-REG: xxlor [[R1:[0-9]+]], 1, 1 22 ; CHECK-REG: xxlor 1, [[R1]], [[R1]] 23 ; CHECK-REG: blr 24 25 ; CHECK-FISL: @foo1 26 ; CHECK-FISL-NOT: lis 27 ; CHECK-FISL-NOT: ori 28 ; CHECK-FISL: li 3, -152 29 ; CHECK-FISL-NOT: lis 30 ; CHECK-FISL-NOT: ori 31 ; CHECK-FISL: stxsdx 1, 1, 3 32 ; CHECK-FISL: blr 33 34 ; CHECK-P9-REG: @foo1 35 ; CHECK-P9-REG: xxlor [[R1:[0-9]+]], 1, 1 36 ; CHECK-P9-REG: xxlor 1, [[R1]], [[R1]] 37 ; CHECK-P9-REG: blr 38 39 ; CHECK-P9-FISL: @foo1 40 ; CHECK-P9-FISL: stfd 31, -8(1) 41 ; CHECK-P9-FISL: blr 42 43 return: ; preds = %entry 44 ret double %a 45 } 46 47 define double @foo2(double %a) nounwind { 48 entry: 49 %b = fadd double %a, %a 50 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind 51 br label %return 52 53 ; CHECK-REG: @foo2 54 ; CHECK-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1 55 ; CHECK-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]] 56 ; CHECK-REG: blr 57 58 ; CHECK-FISL: @foo2 59 ; CHECK-FISL: xsadddp [[R1:[0-9]+]], 1, 1 60 ; CHECK-FISL: stxsdx [[R1]], [[R1]], 3 61 ; CHECK-FISL: lxsdx [[R1]], [[R1]], 3 62 ; CHECK-FISL: blr 63 64 ; CHECK-P9-REG: @foo2 65 ; CHECK-P9-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1 66 ; CHECK-P9-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]] 67 ; CHECK-P9-REG: blr 68 69 ; CHECK-P9-FISL: @foo2 70 ; CHECK-P9-FISL: xsadddp [[R1:[0-9]+]], 1, 1 71 ; CHECK-P9-FISL: stfd [[R1]], [[OFF:[0-9\-]+]](1) 72 ; CHECK-P9-FISL: lfd [[R1]], [[OFF]](1) 73 ; CHECK-P9-FISL: blr 74 75 return: ; preds = %entry 76 ret double %b 77 } 78 79 define double @foo3(double %a) nounwind { 80 entry: 81 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind 82 br label %return 83 84 ; CHECK: @foo3 85 ; CHECK: stxsdx 1, 86 ; CHECK: lxsdx [[R1:[0-9]+]], 87 ; CHECK: xsadddp 1, [[R1]], [[R1]] 88 ; CHECK: blr 89 90 ; CHECK-P9-REG-LABEL: foo3 91 ; CHECK-P9-REG: stfd 1, [[OFF:[0-9\-]+]](1) 92 ; CHECK-P9-REG: lfd [[FPR:[0-9]+]], [[OFF]](1) 93 ; CHECK-P9-REG: xsadddp 1, [[FPR]], [[FPR]] 94 95 ; CHECK-P9-FISL-LABEL: foo3 96 ; CHECK-P9-FISL: stfd 1, [[OFF:[0-9\-]+]](1) 97 ; CHECK-P9-FISL: lfd [[FPR:[0-9]+]], [[OFF]](1) 98 ; CHECK-P9-FISL: xsadddp 1, [[FPR]], [[FPR]] 99 return: ; preds = %entry 100 %b = fadd double %a, %a 101 ret double %b 102 } 103 104
