1 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s 2 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s 3 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s 4 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s 5 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-LE %s 6 7 define double @test1(double %a, double %b) { 8 entry: 9 %v = fmul double %a, %b 10 ret double %v 11 12 ; CHECK-LABEL: @test1 13 ; CHECK: xsmuldp 1, 1, 2 14 ; CHECK: blr 15 16 ; CHECK-LE-LABEL: @test1 17 ; CHECK-LE: xsmuldp 1, 1, 2 18 ; CHECK-LE: blr 19 } 20 21 define double @test2(double %a, double %b) { 22 entry: 23 %v = fdiv double %a, %b 24 ret double %v 25 26 ; CHECK-LABEL: @test2 27 ; CHECK: xsdivdp 1, 1, 2 28 ; CHECK: blr 29 30 ; CHECK-LE-LABEL: @test2 31 ; CHECK-LE: xsdivdp 1, 1, 2 32 ; CHECK-LE: blr 33 } 34 35 define double @test3(double %a, double %b) { 36 entry: 37 %v = fadd double %a, %b 38 ret double %v 39 40 ; CHECK-LABEL: @test3 41 ; CHECK: xsadddp 1, 1, 2 42 ; CHECK: blr 43 44 ; CHECK-LE-LABEL: @test3 45 ; CHECK-LE: xsadddp 1, 1, 2 46 ; CHECK-LE: blr 47 } 48 49 define <2 x double> @test4(<2 x double> %a, <2 x double> %b) { 50 entry: 51 %v = fadd <2 x double> %a, %b 52 ret <2 x double> %v 53 54 ; CHECK-LABEL: @test4 55 ; CHECK: xvadddp 34, 34, 35 56 ; CHECK: blr 57 58 ; CHECK-LE-LABEL: @test4 59 ; CHECK-LE: xvadddp 34, 34, 35 60 ; CHECK-LE: blr 61 } 62 63 define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) { 64 entry: 65 %v = xor <4 x i32> %a, %b 66 ret <4 x i32> %v 67 68 ; CHECK-REG-LABEL: @test5 69 ; CHECK-REG: xxlxor 34, 34, 35 70 ; CHECK-REG: blr 71 72 ; CHECK-FISL-LABEL: @test5 73 ; CHECK-FISL: xxlxor 34, 34, 35 74 ; CHECK-FISL: blr 75 76 ; CHECK-LE-LABEL: @test5 77 ; CHECK-LE: xxlxor 34, 34, 35 78 ; CHECK-LE: blr 79 } 80 81 define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) { 82 entry: 83 %v = xor <8 x i16> %a, %b 84 ret <8 x i16> %v 85 86 ; CHECK-REG-LABEL: @test6 87 ; CHECK-REG: xxlxor 34, 34, 35 88 ; CHECK-REG: blr 89 90 ; CHECK-FISL-LABEL: @test6 91 ; CHECK-FISL: xxlxor 34, 34, 35 92 ; CHECK-FISL: blr 93 94 ; CHECK-LE-LABEL: @test6 95 ; CHECK-LE: xxlxor 34, 34, 35 96 ; CHECK-LE: blr 97 } 98 99 define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) { 100 entry: 101 %v = xor <16 x i8> %a, %b 102 ret <16 x i8> %v 103 104 ; CHECK-REG-LABEL: @test7 105 ; CHECK-REG: xxlxor 34, 34, 35 106 ; CHECK-REG: blr 107 108 ; CHECK-FISL-LABEL: @test7 109 ; CHECK-FISL: xxlxor 34, 34, 35 110 ; CHECK-FISL: blr 111 112 ; CHECK-LE-LABEL: @test7 113 ; CHECK-LE: xxlxor 34, 34, 35 114 ; CHECK-LE: blr 115 } 116 117 define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) { 118 entry: 119 %v = or <4 x i32> %a, %b 120 ret <4 x i32> %v 121 122 ; CHECK-REG-LABEL: @test8 123 ; CHECK-REG: xxlor 34, 34, 35 124 ; CHECK-REG: blr 125 126 ; CHECK-FISL-LABEL: @test8 127 ; CHECK-FISL: xxlor 34, 34, 35 128 ; CHECK-FISL: blr 129 130 ; CHECK-LE-LABEL: @test8 131 ; CHECK-LE: xxlor 34, 34, 35 132 ; CHECK-LE: blr 133 } 134 135 define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) { 136 entry: 137 %v = or <8 x i16> %a, %b 138 ret <8 x i16> %v 139 140 ; CHECK-REG-LABEL: @test9 141 ; CHECK-REG: xxlor 34, 34, 35 142 ; CHECK-REG: blr 143 144 ; CHECK-FISL-LABEL: @test9 145 ; CHECK-FISL: xxlor 34, 34, 35 146 ; CHECK-FISL: blr 147 148 ; CHECK-LE-LABEL: @test9 149 ; CHECK-LE: xxlor 34, 34, 35 150 ; CHECK-LE: blr 151 } 152 153 define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) { 154 entry: 155 %v = or <16 x i8> %a, %b 156 ret <16 x i8> %v 157 158 ; CHECK-REG-LABEL: @test10 159 ; CHECK-REG: xxlor 34, 34, 35 160 ; CHECK-REG: blr 161 162 ; CHECK-FISL-LABEL: @test10 163 ; CHECK-FISL: xxlor 34, 34, 35 164 ; CHECK-FISL: blr 165 166 ; CHECK-LE-LABEL: @test10 167 ; CHECK-LE: xxlor 34, 34, 35 168 ; CHECK-LE: blr 169 } 170 171 define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) { 172 entry: 173 %v = and <4 x i32> %a, %b 174 ret <4 x i32> %v 175 176 ; CHECK-REG-LABEL: @test11 177 ; CHECK-REG: xxland 34, 34, 35 178 ; CHECK-REG: blr 179 180 ; CHECK-FISL-LABEL: @test11 181 ; CHECK-FISL: xxland 34, 34, 35 182 ; CHECK-FISL: blr 183 184 ; CHECK-LE-LABEL: @test11 185 ; CHECK-LE: xxland 34, 34, 35 186 ; CHECK-LE: blr 187 } 188 189 define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) { 190 entry: 191 %v = and <8 x i16> %a, %b 192 ret <8 x i16> %v 193 194 ; CHECK-REG-LABEL: @test12 195 ; CHECK-REG: xxland 34, 34, 35 196 ; CHECK-REG: blr 197 198 ; CHECK-FISL-LABEL: @test12 199 ; CHECK-FISL: xxland 34, 34, 35 200 ; CHECK-FISL: blr 201 202 ; CHECK-LE-LABEL: @test12 203 ; CHECK-LE: xxland 34, 34, 35 204 ; CHECK-LE: blr 205 } 206 207 define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) { 208 entry: 209 %v = and <16 x i8> %a, %b 210 ret <16 x i8> %v 211 212 ; CHECK-REG-LABEL: @test13 213 ; CHECK-REG: xxland 34, 34, 35 214 ; CHECK-REG: blr 215 216 ; CHECK-FISL-LABEL: @test13 217 ; CHECK-FISL: xxland 34, 34, 35 218 ; CHECK-FISL: blr 219 220 ; CHECK-LE-LABEL: @test13 221 ; CHECK-LE: xxland 34, 34, 35 222 ; CHECK-LE: blr 223 } 224 225 define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) { 226 entry: 227 %v = or <4 x i32> %a, %b 228 %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1> 229 ret <4 x i32> %w 230 231 ; CHECK-REG-LABEL: @test14 232 ; CHECK-REG: xxlnor 34, 34, 35 233 ; CHECK-REG: blr 234 235 ; CHECK-FISL-LABEL: @test14 236 ; CHECK-FISL: xxlor 0, 34, 35 237 ; CHECK-FISL: xxlnor 34, 34, 35 238 ; CHECK-FISL-NOT: lis 239 ; CHECK-FISL-NOT: ori 240 ; CHECK-FISL: li 3, -16 241 ; CHECK-FISL-NOT: lis 242 ; CHECK-FISL-NOT: ori 243 ; CHECK-FISL: stxvd2x 0, 1, 3 244 ; CHECK-FISL: blr 245 246 ; CHECK-LE-LABEL: @test14 247 ; CHECK-LE: xxlnor 34, 34, 35 248 ; CHECK-LE: blr 249 } 250 251 define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) { 252 entry: 253 %v = or <8 x i16> %a, %b 254 %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 255 ret <8 x i16> %w 256 257 ; CHECK-REG-LABEL: @test15 258 ; CHECK-REG: xxlnor 34, 34, 35 259 ; CHECK-REG: blr 260 261 ; CHECK-FISL-LABEL: @test15 262 ; CHECK-FISL: xxlor 0, 34, 35 263 ; CHECK-FISL: xxlor 36, 0, 0 264 ; CHECK-FISL: xxlnor 0, 34, 35 265 ; CHECK-FISL: xxlor 34, 0, 0 266 ; CHECK-FISL-NOT: lis 267 ; CHECK-FISL-NOT: ori 268 ; CHECK-FISL: li 3, -16 269 ; CHECK-FISL-NOT: lis 270 ; CHECK-FISL-NOT: ori 271 ; CHECK-FISL: stxvd2x 36, 1, 3 272 ; CHECK-FISL: blr 273 274 ; CHECK-LE-LABEL: @test15 275 ; CHECK-LE: xxlnor 34, 34, 35 276 ; CHECK-LE: blr 277 } 278 279 define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) { 280 entry: 281 %v = or <16 x i8> %a, %b 282 %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 283 ret <16 x i8> %w 284 285 ; CHECK-REG-LABEL: @test16 286 ; CHECK-REG: xxlnor 34, 34, 35 287 ; CHECK-REG: blr 288 289 ; CHECK-FISL-LABEL: @test16 290 ; CHECK-FISL: xxlor 0, 34, 35 291 ; CHECK-FISL: xxlor 36, 0, 0 292 ; CHECK-FISL: xxlnor 0, 34, 35 293 ; CHECK-FISL: xxlor 34, 0, 0 294 ; CHECK-FISL-NOT: lis 295 ; CHECK-FISL-NOT: ori 296 ; CHECK-FISL: li 3, -16 297 ; CHECK-FISL-NOT: lis 298 ; CHECK-FISL-NOT: ori 299 ; CHECK-FISL: stxvd2x 36, 1, 3 300 ; CHECK-FISL: blr 301 302 ; CHECK-LE-LABEL: @test16 303 ; CHECK-LE: xxlnor 34, 34, 35 304 ; CHECK-LE: blr 305 } 306 307 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) { 308 entry: 309 %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1> 310 %v = and <4 x i32> %a, %w 311 ret <4 x i32> %v 312 313 ; CHECK-REG-LABEL: @test17 314 ; CHECK-REG: xxlandc 34, 34, 35 315 ; CHECK-REG: blr 316 317 ; CHECK-FISL-LABEL: @test17 318 ; CHECK-FISL: xxlnor 35, 35, 35 319 ; CHECK-FISL: xxland 34, 34, 35 320 ; CHECK-FISL: blr 321 322 ; CHECK-LE-LABEL: @test17 323 ; CHECK-LE: xxlandc 34, 34, 35 324 ; CHECK-LE: blr 325 } 326 327 define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) { 328 entry: 329 %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 330 %v = and <8 x i16> %a, %w 331 ret <8 x i16> %v 332 333 ; CHECK-REG-LABEL: @test18 334 ; CHECK-REG: xxlandc 34, 34, 35 335 ; CHECK-REG: blr 336 337 ; CHECK-FISL-LABEL: @test18 338 ; CHECK-FISL: xxlnor 0, 35, 35 339 ; CHECK-FISL: xxlor 36, 0, 0 340 ; CHECK-FISL: xxlandc 0, 34, 35 341 ; CHECK-FISL: xxlor 34, 0, 0 342 ; CHECK-FISL-NOT: lis 343 ; CHECK-FISL-NOT: ori 344 ; CHECK-FISL: li 3, -16 345 ; CHECK-FISL-NOT: lis 346 ; CHECK-FISL-NOT: ori 347 ; CHECK-FISL: stxvd2x 36, 1, 3 348 ; CHECK-FISL: blr 349 350 ; CHECK-LE-LABEL: @test18 351 ; CHECK-LE: xxlandc 34, 34, 35 352 ; CHECK-LE: blr 353 } 354 355 define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) { 356 entry: 357 %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 358 %v = and <16 x i8> %a, %w 359 ret <16 x i8> %v 360 361 ; CHECK-REG-LABEL: @test19 362 ; CHECK-REG: xxlandc 34, 34, 35 363 ; CHECK-REG: blr 364 365 ; CHECK-FISL-LABEL: @test19 366 ; CHECK-FISL: xxlnor 0, 35, 35 367 ; CHECK-FISL: xxlor 36, 0, 0 368 ; CHECK-FISL: xxlandc 0, 34, 35 369 ; CHECK-FISL: xxlor 34, 0, 0 370 ; CHECK-FISL-NOT: lis 371 ; CHECK-FISL-NOT: ori 372 ; CHECK-FISL: li 3, -16 373 ; CHECK-FISL-NOT: lis 374 ; CHECK-FISL-NOT: ori 375 ; CHECK-FISL: stxvd2x 36, 1, 3 376 ; CHECK-FISL: blr 377 378 ; CHECK-LE-LABEL: @test19 379 ; CHECK-LE: xxlandc 34, 34, 35 380 ; CHECK-LE: blr 381 } 382 383 define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { 384 entry: 385 %m = icmp eq <4 x i32> %c, %d 386 %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b 387 ret <4 x i32> %v 388 389 ; CHECK-REG-LABEL: @test20 390 ; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5 391 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} 392 ; CHECK-REG: blr 393 394 ; CHECK-FISL-LABEL: @test20 395 ; CHECK-FISL: vcmpequw {{[0-9]+}}, 4, 5 396 ; CHECK-FISL: xxsel 34, 35, 34, {{[0-9]+}} 397 ; CHECK-FISL: blr 398 399 ; CHECK-LE-LABEL: @test20 400 ; CHECK-LE: vcmpequw {{[0-9]+}}, 4, 5 401 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} 402 ; CHECK-LE: blr 403 } 404 405 define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { 406 entry: 407 %m = fcmp oeq <4 x float> %c, %d 408 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b 409 ret <4 x float> %v 410 411 ; CHECK-REG-LABEL: @test21 412 ; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37 413 ; CHECK-REG: xxsel 34, 35, 34, [[V1]] 414 ; CHECK-REG: blr 415 416 ; CHECK-FISL-LABEL: @test21 417 ; CHECK-FISL: xvcmpeqsp [[V1:[0-9]+]], 36, 37 418 ; CHECK-FISL: xxsel 34, 35, 34, [[V1]] 419 ; CHECK-FISL: blr 420 421 ; CHECK-LE-LABEL: @test21 422 ; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37 423 ; CHECK-LE: xxsel 34, 35, 34, [[V1]] 424 ; CHECK-LE: blr 425 } 426 427 define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { 428 entry: 429 %m = fcmp ueq <4 x float> %c, %d 430 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b 431 ret <4 x float> %v 432 433 ; CHECK-REG-LABEL: @test22 434 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 435 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 436 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 437 ; CHECK-REG-DAG: xxlnor 438 ; CHECK-REG-DAG: xxlnor 439 ; CHECK-REG-DAG: xxlor 440 ; CHECK-REG-DAG: xxlor 441 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} 442 ; CHECK-REG: blr 443 444 ; CHECK-FISL-LABEL: @test22 445 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 446 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 447 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 448 ; CHECK-FISL-DAG: xxlnor 449 ; CHECK-FISL-DAG: xxlnor 450 ; CHECK-FISL-DAG: xxlor 451 ; CHECK-FISL-DAG: xxlor 452 ; CHECK-FISL: xxsel 34, 35, 34, {{[0-9]+}} 453 ; CHECK-FISL: blr 454 455 ; CHECK-LE-LABEL: @test22 456 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 457 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 458 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 459 ; CHECK-LE-DAG: xxlnor 460 ; CHECK-LE-DAG: xxlnor 461 ; CHECK-LE-DAG: xxlor 462 ; CHECK-LE-DAG: xxlor 463 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} 464 ; CHECK-LE: blr 465 } 466 467 define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { 468 entry: 469 %m = icmp eq <8 x i16> %c, %d 470 %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b 471 ret <8 x i16> %v 472 473 ; CHECK-REG-LABEL: @test23 474 ; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5 475 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} 476 ; CHECK-REG: blr 477 478 ; CHECK-FISL-LABEL: @test23 479 ; CHECK-FISL: vcmpequh 4, 4, 5 480 ; CHECK-FISL: xxsel 34, 35, 34, 36 481 ; CHECK-FISL: blr 482 483 ; CHECK-LE-LABEL: @test23 484 ; CHECK-LE: vcmpequh {{[0-9]+}}, 4, 5 485 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} 486 ; CHECK-LE: blr 487 } 488 489 define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { 490 entry: 491 %m = icmp eq <16 x i8> %c, %d 492 %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b 493 ret <16 x i8> %v 494 495 ; CHECK-REG-LABEL: @test24 496 ; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5 497 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} 498 ; CHECK-REG: blr 499 500 ; CHECK-FISL-LABEL: @test24 501 ; CHECK-FISL: vcmpequb 4, 4, 5 502 ; CHECK-FISL: xxsel 34, 35, 34, 36 503 ; CHECK-FISL: blr 504 505 ; CHECK-LE-LABEL: @test24 506 ; CHECK-LE: vcmpequb {{[0-9]+}}, 4, 5 507 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} 508 ; CHECK-LE: blr 509 } 510 511 define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) { 512 entry: 513 %m = fcmp oeq <2 x double> %c, %d 514 %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b 515 ret <2 x double> %v 516 517 ; CHECK-LABEL: @test25 518 ; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37 519 ; CHECK: xxsel 34, 35, 34, [[V1]] 520 ; CHECK: blr 521 522 ; CHECK-LE-LABEL: @test25 523 ; CHECK-LE: xvcmpeqdp [[V1:[0-9]+]], 36, 37 524 ; CHECK-LE: xxsel 34, 35, 34, [[V1]] 525 ; CHECK-LE: blr 526 } 527 528 define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) { 529 %v = add <2 x i64> %a, %b 530 ret <2 x i64> %v 531 532 ; CHECK-LABEL: @test26 533 534 ; Make sure we use only two stores (one for each operand). 535 ; CHECK: stxvd2x 35, 536 ; CHECK: stxvd2x 34, 537 ; CHECK-NOT: stxvd2x 538 539 ; FIXME: The code quality here is not good; just make sure we do something for now. 540 ; CHECK: add 541 ; CHECK: add 542 ; CHECK: blr 543 544 ; CHECK-LE: vaddudm 2, 2, 3 545 ; CHECK-LE: blr 546 } 547 548 define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) { 549 %v = and <2 x i64> %a, %b 550 ret <2 x i64> %v 551 552 ; CHECK-LABEL: @test27 553 ; CHECK: xxland 34, 34, 35 554 ; CHECK: blr 555 556 ; CHECK-LE-LABEL: @test27 557 ; CHECK-LE: xxland 34, 34, 35 558 ; CHECK-LE: blr 559 } 560 561 define <2 x double> @test28(<2 x double>* %a) { 562 %v = load <2 x double>, <2 x double>* %a, align 16 563 ret <2 x double> %v 564 565 ; CHECK-LABEL: @test28 566 ; CHECK: lxvd2x 34, 0, 3 567 ; CHECK: blr 568 569 ; CHECK-LE-LABEL: @test28 570 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 571 ; CHECK-LE: xxswapd 34, [[V1]] 572 ; CHECK-LE: blr 573 } 574 575 define void @test29(<2 x double>* %a, <2 x double> %b) { 576 store <2 x double> %b, <2 x double>* %a, align 16 577 ret void 578 579 ; CHECK-LABEL: @test29 580 ; CHECK: stxvd2x 34, 0, 3 581 ; CHECK: blr 582 583 ; CHECK-LE-LABEL: @test29 584 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 585 ; CHECK-LE: stxvd2x [[V1]], 0, 3 586 ; CHECK-LE: blr 587 } 588 589 define <2 x double> @test28u(<2 x double>* %a) { 590 %v = load <2 x double>, <2 x double>* %a, align 8 591 ret <2 x double> %v 592 593 ; CHECK-LABEL: @test28u 594 ; CHECK: lxvd2x 34, 0, 3 595 ; CHECK: blr 596 597 ; CHECK-LE-LABEL: @test28u 598 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 599 ; CHECK-LE: xxswapd 34, [[V1]] 600 ; CHECK-LE: blr 601 } 602 603 define void @test29u(<2 x double>* %a, <2 x double> %b) { 604 store <2 x double> %b, <2 x double>* %a, align 8 605 ret void 606 607 ; CHECK-LABEL: @test29u 608 ; CHECK: stxvd2x 34, 0, 3 609 ; CHECK: blr 610 611 ; CHECK-LE-LABEL: @test29u 612 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 613 ; CHECK-LE: stxvd2x [[V1]], 0, 3 614 ; CHECK-LE: blr 615 } 616 617 define <2 x i64> @test30(<2 x i64>* %a) { 618 %v = load <2 x i64>, <2 x i64>* %a, align 16 619 ret <2 x i64> %v 620 621 ; CHECK-REG-LABEL: @test30 622 ; CHECK-REG: lxvd2x 34, 0, 3 623 ; CHECK-REG: blr 624 625 ; CHECK-FISL-LABEL: @test30 626 ; CHECK-FISL: lxvd2x 0, 0, 3 627 ; CHECK-FISL: xxlor 34, 0, 0 628 ; CHECK-FISL: blr 629 630 ; CHECK-LE-LABEL: @test30 631 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 632 ; CHECK-LE: xxswapd 34, [[V1]] 633 ; CHECK-LE: blr 634 } 635 636 define void @test31(<2 x i64>* %a, <2 x i64> %b) { 637 store <2 x i64> %b, <2 x i64>* %a, align 16 638 ret void 639 640 ; CHECK-LABEL: @test31 641 ; CHECK: stxvd2x 34, 0, 3 642 ; CHECK: blr 643 644 ; CHECK-LE-LABEL: @test31 645 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 646 ; CHECK-LE: stxvd2x [[V1]], 0, 3 647 ; CHECK-LE: blr 648 } 649 650 define <4 x float> @test32(<4 x float>* %a) { 651 %v = load <4 x float>, <4 x float>* %a, align 16 652 ret <4 x float> %v 653 654 ; CHECK-REG-LABEL: @test32 655 ; CHECK-REG: lxvw4x 34, 0, 3 656 ; CHECK-REG: blr 657 658 ; CHECK-FISL-LABEL: @test32 659 ; CHECK-FISL: lxvw4x 34, 0, 3 660 ; CHECK-FISL: blr 661 662 ; CHECK-LE-LABEL: @test32 663 ; CHECK-LE: lvx 2, 0, 3 664 ; CHECK-LE-NOT: xxswapd 665 ; CHECK-LE: blr 666 } 667 668 define void @test33(<4 x float>* %a, <4 x float> %b) { 669 store <4 x float> %b, <4 x float>* %a, align 16 670 ret void 671 672 ; CHECK-REG-LABEL: @test33 673 ; CHECK-REG: stxvw4x 34, 0, 3 674 ; CHECK-REG: blr 675 676 ; CHECK-FISL-LABEL: @test33 677 ; CHECK-FISL: stxvw4x 34, 0, 3 678 ; CHECK-FISL: blr 679 680 ; CHECK-LE-LABEL: @test33 681 ; CHECK-LE-NOT: xxswapd 682 ; CHECK-LE: stvx 2, 0, 3 683 ; CHECK-LE: blr 684 } 685 686 define <4 x float> @test32u(<4 x float>* %a) { 687 %v = load <4 x float>, <4 x float>* %a, align 8 688 ret <4 x float> %v 689 690 ; CHECK-LABEL: @test32u 691 ; CHECK-DAG: lvsl 692 ; CHECK-DAG: lvx 693 ; CHECK-DAG: lvx 694 ; CHECK: vperm 2, 695 ; CHECK: blr 696 697 ; CHECK-LE-LABEL: @test32u 698 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 699 ; CHECK-LE: xxswapd 34, [[V1]] 700 ; CHECK-LE: blr 701 } 702 703 define void @test33u(<4 x float>* %a, <4 x float> %b) { 704 store <4 x float> %b, <4 x float>* %a, align 8 705 ret void 706 707 ; CHECK-REG-LABEL: @test33u 708 ; CHECK-REG: stxvw4x 34, 0, 3 709 ; CHECK-REG: blr 710 711 ; CHECK-FISL-LABEL: @test33u 712 ; CHECK-FISL: stxvw4x 34, 0, 3 713 ; CHECK-FISL: blr 714 715 ; CHECK-LE-LABEL: @test33u 716 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 717 ; CHECK-LE: stxvd2x [[V1]], 0, 3 718 ; CHECK-LE: blr 719 } 720 721 define <4 x i32> @test34(<4 x i32>* %a) { 722 %v = load <4 x i32>, <4 x i32>* %a, align 16 723 ret <4 x i32> %v 724 725 ; CHECK-REG-LABEL: @test34 726 ; CHECK-REG: lxvw4x 34, 0, 3 727 ; CHECK-REG: blr 728 729 ; CHECK-FISL-LABEL: @test34 730 ; CHECK-FISL: lxvw4x 34, 0, 3 731 ; CHECK-FISL: blr 732 733 ; CHECK-LE-LABEL: @test34 734 ; CHECK-LE: lvx 2, 0, 3 735 ; CHECK-LE-NOT: xxswapd 736 ; CHECK-LE: blr 737 } 738 739 define void @test35(<4 x i32>* %a, <4 x i32> %b) { 740 store <4 x i32> %b, <4 x i32>* %a, align 16 741 ret void 742 743 ; CHECK-REG-LABEL: @test35 744 ; CHECK-REG: stxvw4x 34, 0, 3 745 ; CHECK-REG: blr 746 747 ; CHECK-FISL-LABEL: @test35 748 ; CHECK-FISL: stxvw4x 34, 0, 3 749 ; CHECK-FISL: blr 750 751 ; CHECK-LE-LABEL: @test35 752 ; CHECK-LE-NOT: xxswapd 753 ; CHECK-LE: stvx 2, 0, 3 754 ; CHECK-LE: blr 755 } 756 757 define <2 x double> @test40(<2 x i64> %a) { 758 %v = uitofp <2 x i64> %a to <2 x double> 759 ret <2 x double> %v 760 761 ; CHECK-LABEL: @test40 762 ; CHECK: xvcvuxddp 34, 34 763 ; CHECK: blr 764 765 ; CHECK-LE-LABEL: @test40 766 ; CHECK-LE: xvcvuxddp 34, 34 767 ; CHECK-LE: blr 768 } 769 770 define <2 x double> @test41(<2 x i64> %a) { 771 %v = sitofp <2 x i64> %a to <2 x double> 772 ret <2 x double> %v 773 774 ; CHECK-LABEL: @test41 775 ; CHECK: xvcvsxddp 34, 34 776 ; CHECK: blr 777 778 ; CHECK-LE-LABEL: @test41 779 ; CHECK-LE: xvcvsxddp 34, 34 780 ; CHECK-LE: blr 781 } 782 783 define <2 x i64> @test42(<2 x double> %a) { 784 %v = fptoui <2 x double> %a to <2 x i64> 785 ret <2 x i64> %v 786 787 ; CHECK-LABEL: @test42 788 ; CHECK: xvcvdpuxds 34, 34 789 ; CHECK: blr 790 791 ; CHECK-LE-LABEL: @test42 792 ; CHECK-LE: xvcvdpuxds 34, 34 793 ; CHECK-LE: blr 794 } 795 796 define <2 x i64> @test43(<2 x double> %a) { 797 %v = fptosi <2 x double> %a to <2 x i64> 798 ret <2 x i64> %v 799 800 ; CHECK-LABEL: @test43 801 ; CHECK: xvcvdpsxds 34, 34 802 ; CHECK: blr 803 804 ; CHECK-LE-LABEL: @test43 805 ; CHECK-LE: xvcvdpsxds 34, 34 806 ; CHECK-LE: blr 807 } 808 809 define <2 x float> @test44(<2 x i64> %a) { 810 %v = uitofp <2 x i64> %a to <2 x float> 811 ret <2 x float> %v 812 813 ; CHECK-LABEL: @test44 814 ; FIXME: The code quality here looks pretty bad. 815 ; CHECK: blr 816 } 817 818 define <2 x float> @test45(<2 x i64> %a) { 819 %v = sitofp <2 x i64> %a to <2 x float> 820 ret <2 x float> %v 821 822 ; CHECK-LABEL: @test45 823 ; FIXME: The code quality here looks pretty bad. 824 ; CHECK: blr 825 } 826 827 define <2 x i64> @test46(<2 x float> %a) { 828 %v = fptoui <2 x float> %a to <2 x i64> 829 ret <2 x i64> %v 830 831 ; CHECK-LABEL: @test46 832 ; FIXME: The code quality here looks pretty bad. 833 ; CHECK: blr 834 } 835 836 define <2 x i64> @test47(<2 x float> %a) { 837 %v = fptosi <2 x float> %a to <2 x i64> 838 ret <2 x i64> %v 839 840 ; CHECK-LABEL: @test47 841 ; FIXME: The code quality here looks pretty bad. 842 ; CHECK: blr 843 } 844 845 define <2 x double> @test50(double* %a) { 846 %v = load double, double* %a, align 8 847 %w = insertelement <2 x double> undef, double %v, i32 0 848 %x = insertelement <2 x double> %w, double %v, i32 1 849 ret <2 x double> %x 850 851 ; CHECK-LABEL: @test50 852 ; CHECK: lxvdsx 34, 0, 3 853 ; CHECK: blr 854 855 ; CHECK-LE-LABEL: @test50 856 ; CHECK-LE: lxvdsx 34, 0, 3 857 ; CHECK-LE: blr 858 } 859 860 define <2 x double> @test51(<2 x double> %a, <2 x double> %b) { 861 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0> 862 ret <2 x double> %v 863 864 ; CHECK-LABEL: @test51 865 ; CHECK: xxspltd 34, 34, 0 866 ; CHECK: blr 867 868 ; CHECK-LE-LABEL: @test51 869 ; CHECK-LE: xxspltd 34, 34, 1 870 ; CHECK-LE: blr 871 } 872 873 define <2 x double> @test52(<2 x double> %a, <2 x double> %b) { 874 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2> 875 ret <2 x double> %v 876 877 ; CHECK-LABEL: @test52 878 ; CHECK: xxmrghd 34, 34, 35 879 ; CHECK: blr 880 881 ; CHECK-LE-LABEL: @test52 882 ; CHECK-LE: xxmrgld 34, 35, 34 883 ; CHECK-LE: blr 884 } 885 886 define <2 x double> @test53(<2 x double> %a, <2 x double> %b) { 887 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0> 888 ret <2 x double> %v 889 890 ; CHECK-LABEL: @test53 891 ; CHECK: xxmrghd 34, 35, 34 892 ; CHECK: blr 893 894 ; CHECK-LE-LABEL: @test53 895 ; CHECK-LE: xxmrgld 34, 34, 35 896 ; CHECK-LE: blr 897 } 898 899 define <2 x double> @test54(<2 x double> %a, <2 x double> %b) { 900 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2> 901 ret <2 x double> %v 902 903 ; CHECK-LABEL: @test54 904 ; CHECK: xxpermdi 34, 34, 35, 2 905 ; CHECK: blr 906 907 ; CHECK-LE-LABEL: @test54 908 ; CHECK-LE: xxpermdi 34, 35, 34, 2 909 ; CHECK-LE: blr 910 } 911 912 define <2 x double> @test55(<2 x double> %a, <2 x double> %b) { 913 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3> 914 ret <2 x double> %v 915 916 ; CHECK-LABEL: @test55 917 ; CHECK: xxmrgld 34, 34, 35 918 ; CHECK: blr 919 920 ; CHECK-LE-LABEL: @test55 921 ; CHECK-LE: xxmrghd 34, 35, 34 922 ; CHECK-LE: blr 923 } 924 925 define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) { 926 %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3> 927 ret <2 x i64> %v 928 929 ; CHECK-LABEL: @test56 930 ; CHECK: xxmrgld 34, 34, 35 931 ; CHECK: blr 932 933 ; CHECK-LE-LABEL: @test56 934 ; CHECK-LE: xxmrghd 34, 35, 34 935 ; CHECK-LE: blr 936 } 937 938 define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) { 939 %v = shl <2 x i64> %a, %b 940 ret <2 x i64> %v 941 942 ; CHECK-LABEL: @test60 943 ; This should scalarize, and the current code quality is not good. 944 ; CHECK: stxvd2x 945 ; CHECK: stxvd2x 946 ; CHECK: sld 947 ; CHECK: sld 948 ; CHECK: lxvd2x 949 ; CHECK: blr 950 } 951 952 define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) { 953 %v = lshr <2 x i64> %a, %b 954 ret <2 x i64> %v 955 956 ; CHECK-LABEL: @test61 957 ; This should scalarize, and the current code quality is not good. 958 ; CHECK: stxvd2x 959 ; CHECK: stxvd2x 960 ; CHECK: srd 961 ; CHECK: srd 962 ; CHECK: lxvd2x 963 ; CHECK: blr 964 } 965 966 define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) { 967 %v = ashr <2 x i64> %a, %b 968 ret <2 x i64> %v 969 970 ; CHECK-LABEL: @test62 971 ; This should scalarize, and the current code quality is not good. 972 ; CHECK: stxvd2x 973 ; CHECK: stxvd2x 974 ; CHECK: srad 975 ; CHECK: srad 976 ; CHECK: lxvd2x 977 ; CHECK: blr 978 } 979 980 define double @test63(<2 x double> %a) { 981 %v = extractelement <2 x double> %a, i32 0 982 ret double %v 983 984 ; CHECK-REG-LABEL: @test63 985 ; CHECK-REG: xxlor 1, 34, 34 986 ; CHECK-REG: blr 987 988 ; CHECK-FISL-LABEL: @test63 989 ; CHECK-FISL: xxlor 0, 34, 34 990 ; CHECK-FISL: fmr 1, 0 991 ; CHECK-FISL: blr 992 993 ; CHECK-LE-LABEL: @test63 994 ; CHECK-LE: xxswapd 1, 34 995 ; CHECK-LE: blr 996 } 997 998 define double @test64(<2 x double> %a) { 999 %v = extractelement <2 x double> %a, i32 1 1000 ret double %v 1001 1002 ; CHECK-REG-LABEL: @test64 1003 ; CHECK-REG: xxswapd 1, 34 1004 ; CHECK-REG: blr 1005 1006 ; CHECK-FISL-LABEL: @test64 1007 ; CHECK-FISL: xxswapd 34, 34 1008 ; CHECK-FISL: xxlor 0, 34, 34 1009 ; CHECK-FISL: fmr 1, 0 1010 ; CHECK-FISL: blr 1011 1012 ; CHECK-LE-LABEL: @test64 1013 ; CHECK-LE: xxlor 1, 34, 34 1014 } 1015 1016 define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) { 1017 %w = icmp eq <2 x i64> %a, %b 1018 ret <2 x i1> %w 1019 1020 ; CHECK-REG-LABEL: @test65 1021 ; CHECK-REG: vcmpequw 2, 2, 3 1022 ; CHECK-REG: blr 1023 1024 ; CHECK-FISL-LABEL: @test65 1025 ; CHECK-FISL: vcmpequw 2, 2, 3 1026 ; CHECK-FISL: blr 1027 1028 ; CHECK-LE-LABEL: @test65 1029 ; CHECK-LE: vcmpequd 2, 2, 3 1030 ; CHECK-LE: blr 1031 } 1032 1033 define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) { 1034 %w = icmp ne <2 x i64> %a, %b 1035 ret <2 x i1> %w 1036 1037 ; CHECK-REG-LABEL: @test66 1038 ; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3 1039 ; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} 1040 ; CHECK-REG: blr 1041 1042 ; CHECK-FISL-LABEL: @test66 1043 ; CHECK-FISL: vcmpequw 2, 2, 3 1044 ; CHECK-FISL: xxlnor 34, 34, 34 1045 ; CHECK-FISL: blr 1046 1047 ; CHECK-LE-LABEL: @test66 1048 ; CHECK-LE: vcmpequd {{[0-9]+}}, 2, 3 1049 ; CHECK-LE: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} 1050 ; CHECK-LE: blr 1051 } 1052 1053 define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) { 1054 %w = icmp ult <2 x i64> %a, %b 1055 ret <2 x i1> %w 1056 1057 ; CHECK-LABEL: @test67 1058 ; This should scalarize, and the current code quality is not good. 1059 ; CHECK: stxvd2x 1060 ; CHECK: stxvd2x 1061 ; CHECK: cmpld 1062 ; CHECK: cmpld 1063 ; CHECK: lxvd2x 1064 ; CHECK: blr 1065 1066 ; CHECK-LE-LABEL: @test67 1067 ; CHECK-LE: vcmpgtud 2, 3, 2 1068 ; CHECK-LE: blr 1069 } 1070 1071 define <2 x double> @test68(<2 x i32> %a) { 1072 %w = sitofp <2 x i32> %a to <2 x double> 1073 ret <2 x double> %w 1074 1075 ; CHECK-LABEL: @test68 1076 ; CHECK: xxmrghw [[V1:[0-9]+]] 1077 ; CHECK: xvcvsxwdp 34, [[V1]] 1078 ; CHECK: blr 1079 1080 ; CHECK-LE-LABEL: @test68 1081 ; CHECK-LE: xxmrglw [[V1:[0-9]+]], 34, 34 1082 ; CHECK-LE: xvcvsxwdp 34, [[V1]] 1083 ; CHECK-LE: blr 1084 } 1085 1086 ; This gets scalarized so the code isn't great 1087 define <2 x double> @test69(<2 x i16> %a) { 1088 %w = sitofp <2 x i16> %a to <2 x double> 1089 ret <2 x double> %w 1090 1091 ; CHECK-LABEL: @test69 1092 ; CHECK-DAG: lfiwax 1093 ; CHECK-DAG: lfiwax 1094 ; CHECK-DAG: xscvsxddp 1095 ; CHECK-DAG: xscvsxddp 1096 ; CHECK: xxmrghd 1097 ; CHECK: blr 1098 1099 ; CHECK-LE-LABEL: @test69 1100 ; CHECK-LE: mfvsrd 1101 ; CHECK-LE: mtvsrwa 1102 ; CHECK-LE: mtvsrwa 1103 ; CHECK-LE: xscvsxddp 1104 ; CHECK-LE: xscvsxddp 1105 ; CHECK-LE: xxmrghd 1106 ; CHECK-LE: blr 1107 } 1108 1109 ; This gets scalarized so the code isn't great 1110 define <2 x double> @test70(<2 x i8> %a) { 1111 %w = sitofp <2 x i8> %a to <2 x double> 1112 ret <2 x double> %w 1113 1114 ; CHECK-LABEL: @test70 1115 ; CHECK-DAG: lfiwax 1116 ; CHECK-DAG: lfiwax 1117 ; CHECK-DAG: xscvsxddp 1118 ; CHECK-DAG: xscvsxddp 1119 ; CHECK: xxmrghd 1120 ; CHECK: blr 1121 1122 ; CHECK-LE-LABEL: @test70 1123 ; CHECK-LE: mfvsrd 1124 ; CHECK-LE: mtvsrwa 1125 ; CHECK-LE: mtvsrwa 1126 ; CHECK-LE: xscvsxddp 1127 ; CHECK-LE: xscvsxddp 1128 ; CHECK-LE: xxmrghd 1129 ; CHECK-LE: blr 1130 } 1131 1132 ; This gets scalarized so the code isn't great 1133 define <2 x i32> @test80(i32 %v) { 1134 %b1 = insertelement <2 x i32> undef, i32 %v, i32 0 1135 %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer 1136 %i = add <2 x i32> %b2, <i32 2, i32 3> 1137 ret <2 x i32> %i 1138 1139 ; CHECK-REG-LABEL: @test80 1140 ; CHECK-REG-DAG: stw 3, -16(1) 1141 ; CHECK-REG-DAG: addi [[R1:[0-9]+]], 1, -16 1142 ; CHECK-REG: addis [[R2:[0-9]+]] 1143 ; CHECK-REG-DAG: addi [[R2]], [[R2]] 1144 ; CHECK-REG-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]] 1145 ; CHECK-REG-DAG: lxvw4x 35, 0, [[R2]] 1146 ; CHECK-REG: xxspltw 34, [[VS1]], 0 1147 ; CHECK-REG: vadduwm 2, 2, 3 1148 ; CHECK-REG-NOT: stxvw4x 1149 ; CHECK-REG: blr 1150 1151 ; CHECK-FISL-LABEL: @test80 1152 ; CHECK-FISL: mr 4, 3 1153 ; CHECK-FISL: stw 4, -16(1) 1154 ; CHECK-FISL: addi [[R1:[0-9]+]], 1, -16 1155 ; CHECK-FISL-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]] 1156 ; CHECK-FISL-DAG: xxspltw {{[0-9]+}}, [[VS1]], 0 1157 ; CHECK-FISL: addis [[R2:[0-9]+]] 1158 ; CHECK-FISL: addi [[R2]], [[R2]] 1159 ; CHECK-FISL-DAG: lxvw4x {{[0-9]+}}, 0, [[R2]] 1160 ; CHECK-FISL: vadduwm 1161 ; CHECK-FISL-NOT: stxvw4x 1162 ; CHECK-FISL: blr 1163 1164 ; CHECK-LE-LABEL: @test80 1165 ; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3 1166 ; CHECK-LE-DAG: xxswapd [[V1:[0-9]+]], [[R1]] 1167 ; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI 1168 ; CHECK-LE-DAG: lvx 3, 0, [[R2]] 1169 ; CHECK-LE-DAG: xxspltw 34, [[V1]] 1170 ; CHECK-LE-NOT: xxswapd 35, [[V2]] 1171 ; CHECK-LE: vadduwm 2, 2, 3 1172 ; CHECK-LE: blr 1173 } 1174 1175 define <2 x double> @test81(<4 x float> %b) { 1176 %w = bitcast <4 x float> %b to <2 x double> 1177 ret <2 x double> %w 1178 1179 ; CHECK-LABEL: @test81 1180 ; CHECK: blr 1181 1182 ; CHECK-LE-LABEL: @test81 1183 ; CHECK-LE: blr 1184 } 1185 1186 define double @test82(double %a, double %b, double %c, double %d) { 1187 entry: 1188 %m = fcmp oeq double %c, %d 1189 %v = select i1 %m, double %a, double %b 1190 ret double %v 1191 1192 ; CHECK-REG-LABEL: @test82 1193 ; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4 1194 ; CHECK-REG: beqlr [[REG]] 1195 1196 ; CHECK-FISL-LABEL: @test82 1197 ; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4 1198 ; CHECK-FISL: beq [[REG]], {{.*}} 1199 1200 ; CHECK-LE-LABEL: @test82 1201 ; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4 1202 ; CHECK-LE: beqlr [[REG]] 1203 } 1204 1205 ; Function Attrs: nounwind readnone 1206 define <4 x i32> @test83(i8* %a) { 1207 entry: 1208 %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %a) 1209 ret <4 x i32> %0 1210 ; CHECK-LABEL: test83 1211 ; CHECK: lxvw4x 34, 0, 3 1212 ; CHECK: blr 1213 } 1214 ; Function Attrs: nounwind readnone 1215 declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*) 1216 1217 ; Function Attrs: nounwind readnone 1218 define <2 x double> @test84(i8* %a) { 1219 entry: 1220 %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %a) 1221 ret <2 x double> %0 1222 ; CHECK-LABEL: test84 1223 ; CHECK: lxvd2x 34, 0, 3 1224 ; CHECK: blr 1225 } 1226 ; Function Attrs: nounwind readnone 1227 declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*) 1228 1229 ; Function Attrs: nounwind readnone 1230 define void @test85(<4 x i32> %a, i8* %b) { 1231 entry: 1232 tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, i8* %b) 1233 ret void 1234 ; CHECK-LABEL: test85 1235 ; CHECK: stxvw4x 34, 0, 5 1236 ; CHECK: blr 1237 } 1238 ; Function Attrs: nounwind readnone 1239 declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, i8*) 1240 1241 ; Function Attrs: nounwind readnone 1242 define void @test86(<2 x double> %a, i8* %b) { 1243 entry: 1244 tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, i8* %b) 1245 ret void 1246 ; CHECK-LABEL: test86 1247 ; CHECK: stxvd2x 34, 0, 5 1248 ; CHECK: blr 1249 } 1250 ; Function Attrs: nounwind readnone 1251 declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*) 1252
