1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ 3 ; RUN: | FileCheck -check-prefix=RV32IFD %s 4 5 define i32 @fcmp_false(double %a, double %b) nounwind { 6 ; RV32IFD-LABEL: fcmp_false: 7 ; RV32IFD: # %bb.0: 8 ; RV32IFD-NEXT: mv a0, zero 9 ; RV32IFD-NEXT: ret 10 %1 = fcmp false double %a, %b 11 %2 = zext i1 %1 to i32 12 ret i32 %2 13 } 14 15 define i32 @fcmp_oeq(double %a, double %b) nounwind { 16 ; RV32IFD-LABEL: fcmp_oeq: 17 ; RV32IFD: # %bb.0: 18 ; RV32IFD-NEXT: addi sp, sp, -16 19 ; RV32IFD-NEXT: sw a2, 8(sp) 20 ; RV32IFD-NEXT: sw a3, 12(sp) 21 ; RV32IFD-NEXT: fld ft0, 8(sp) 22 ; RV32IFD-NEXT: sw a0, 8(sp) 23 ; RV32IFD-NEXT: sw a1, 12(sp) 24 ; RV32IFD-NEXT: fld ft1, 8(sp) 25 ; RV32IFD-NEXT: feq.d a0, ft1, ft0 26 ; RV32IFD-NEXT: addi sp, sp, 16 27 ; RV32IFD-NEXT: ret 28 %1 = fcmp oeq double %a, %b 29 %2 = zext i1 %1 to i32 30 ret i32 %2 31 } 32 33 define i32 @fcmp_ogt(double %a, double %b) nounwind { 34 ; RV32IFD-LABEL: fcmp_ogt: 35 ; RV32IFD: # %bb.0: 36 ; RV32IFD-NEXT: addi sp, sp, -16 37 ; RV32IFD-NEXT: sw a0, 8(sp) 38 ; RV32IFD-NEXT: sw a1, 12(sp) 39 ; RV32IFD-NEXT: fld ft0, 8(sp) 40 ; RV32IFD-NEXT: sw a2, 8(sp) 41 ; RV32IFD-NEXT: sw a3, 12(sp) 42 ; RV32IFD-NEXT: fld ft1, 8(sp) 43 ; RV32IFD-NEXT: flt.d a0, ft1, ft0 44 ; RV32IFD-NEXT: addi sp, sp, 16 45 ; RV32IFD-NEXT: ret 46 %1 = fcmp ogt double %a, %b 47 %2 = zext i1 %1 to i32 48 ret i32 %2 49 } 50 51 define i32 @fcmp_oge(double %a, double %b) nounwind { 52 ; RV32IFD-LABEL: fcmp_oge: 53 ; RV32IFD: # %bb.0: 54 ; RV32IFD-NEXT: addi sp, sp, -16 55 ; RV32IFD-NEXT: sw a0, 8(sp) 56 ; RV32IFD-NEXT: sw a1, 12(sp) 57 ; RV32IFD-NEXT: fld ft0, 8(sp) 58 ; RV32IFD-NEXT: sw a2, 8(sp) 59 ; RV32IFD-NEXT: sw a3, 12(sp) 60 ; RV32IFD-NEXT: fld ft1, 8(sp) 61 ; RV32IFD-NEXT: fle.d a0, ft1, ft0 62 ; RV32IFD-NEXT: addi sp, sp, 16 63 ; RV32IFD-NEXT: ret 64 %1 = fcmp oge double %a, %b 65 %2 = zext i1 %1 to i32 66 ret i32 %2 67 } 68 69 define i32 @fcmp_olt(double %a, double %b) nounwind { 70 ; RV32IFD-LABEL: fcmp_olt: 71 ; RV32IFD: # %bb.0: 72 ; RV32IFD-NEXT: addi sp, sp, -16 73 ; RV32IFD-NEXT: sw a2, 8(sp) 74 ; RV32IFD-NEXT: sw a3, 12(sp) 75 ; RV32IFD-NEXT: fld ft0, 8(sp) 76 ; RV32IFD-NEXT: sw a0, 8(sp) 77 ; RV32IFD-NEXT: sw a1, 12(sp) 78 ; RV32IFD-NEXT: fld ft1, 8(sp) 79 ; RV32IFD-NEXT: flt.d a0, ft1, ft0 80 ; RV32IFD-NEXT: addi sp, sp, 16 81 ; RV32IFD-NEXT: ret 82 %1 = fcmp olt double %a, %b 83 %2 = zext i1 %1 to i32 84 ret i32 %2 85 } 86 87 define i32 @fcmp_ole(double %a, double %b) nounwind { 88 ; RV32IFD-LABEL: fcmp_ole: 89 ; RV32IFD: # %bb.0: 90 ; RV32IFD-NEXT: addi sp, sp, -16 91 ; RV32IFD-NEXT: sw a2, 8(sp) 92 ; RV32IFD-NEXT: sw a3, 12(sp) 93 ; RV32IFD-NEXT: fld ft0, 8(sp) 94 ; RV32IFD-NEXT: sw a0, 8(sp) 95 ; RV32IFD-NEXT: sw a1, 12(sp) 96 ; RV32IFD-NEXT: fld ft1, 8(sp) 97 ; RV32IFD-NEXT: fle.d a0, ft1, ft0 98 ; RV32IFD-NEXT: addi sp, sp, 16 99 ; RV32IFD-NEXT: ret 100 %1 = fcmp ole double %a, %b 101 %2 = zext i1 %1 to i32 102 ret i32 %2 103 } 104 105 define i32 @fcmp_one(double %a, double %b) nounwind { 106 ; RV32IFD-LABEL: fcmp_one: 107 ; RV32IFD: # %bb.0: 108 ; RV32IFD-NEXT: addi sp, sp, -16 109 ; RV32IFD-NEXT: sw a0, 8(sp) 110 ; RV32IFD-NEXT: sw a1, 12(sp) 111 ; RV32IFD-NEXT: fld ft0, 8(sp) 112 ; RV32IFD-NEXT: sw a2, 8(sp) 113 ; RV32IFD-NEXT: sw a3, 12(sp) 114 ; RV32IFD-NEXT: fld ft1, 8(sp) 115 ; RV32IFD-NEXT: feq.d a0, ft1, ft1 116 ; RV32IFD-NEXT: feq.d a1, ft0, ft0 117 ; RV32IFD-NEXT: and a0, a1, a0 118 ; RV32IFD-NEXT: feq.d a1, ft0, ft1 119 ; RV32IFD-NEXT: not a1, a1 120 ; RV32IFD-NEXT: seqz a0, a0 121 ; RV32IFD-NEXT: xori a0, a0, 1 122 ; RV32IFD-NEXT: and a0, a1, a0 123 ; RV32IFD-NEXT: addi sp, sp, 16 124 ; RV32IFD-NEXT: ret 125 %1 = fcmp one double %a, %b 126 %2 = zext i1 %1 to i32 127 ret i32 %2 128 } 129 130 define i32 @fcmp_ord(double %a, double %b) nounwind { 131 ; RV32IFD-LABEL: fcmp_ord: 132 ; RV32IFD: # %bb.0: 133 ; RV32IFD-NEXT: addi sp, sp, -16 134 ; RV32IFD-NEXT: sw a0, 8(sp) 135 ; RV32IFD-NEXT: sw a1, 12(sp) 136 ; RV32IFD-NEXT: fld ft0, 8(sp) 137 ; RV32IFD-NEXT: sw a2, 8(sp) 138 ; RV32IFD-NEXT: sw a3, 12(sp) 139 ; RV32IFD-NEXT: fld ft1, 8(sp) 140 ; RV32IFD-NEXT: feq.d a0, ft1, ft1 141 ; RV32IFD-NEXT: feq.d a1, ft0, ft0 142 ; RV32IFD-NEXT: and a0, a1, a0 143 ; RV32IFD-NEXT: seqz a0, a0 144 ; RV32IFD-NEXT: xori a0, a0, 1 145 ; RV32IFD-NEXT: addi sp, sp, 16 146 ; RV32IFD-NEXT: ret 147 %1 = fcmp ord double %a, %b 148 %2 = zext i1 %1 to i32 149 ret i32 %2 150 } 151 152 define i32 @fcmp_ueq(double %a, double %b) nounwind { 153 ; RV32IFD-LABEL: fcmp_ueq: 154 ; RV32IFD: # %bb.0: 155 ; RV32IFD-NEXT: addi sp, sp, -16 156 ; RV32IFD-NEXT: sw a2, 8(sp) 157 ; RV32IFD-NEXT: sw a3, 12(sp) 158 ; RV32IFD-NEXT: fld ft0, 8(sp) 159 ; RV32IFD-NEXT: sw a0, 8(sp) 160 ; RV32IFD-NEXT: sw a1, 12(sp) 161 ; RV32IFD-NEXT: fld ft1, 8(sp) 162 ; RV32IFD-NEXT: feq.d a0, ft1, ft0 163 ; RV32IFD-NEXT: feq.d a1, ft0, ft0 164 ; RV32IFD-NEXT: feq.d a2, ft1, ft1 165 ; RV32IFD-NEXT: and a1, a2, a1 166 ; RV32IFD-NEXT: seqz a1, a1 167 ; RV32IFD-NEXT: or a0, a0, a1 168 ; RV32IFD-NEXT: addi sp, sp, 16 169 ; RV32IFD-NEXT: ret 170 %1 = fcmp ueq double %a, %b 171 %2 = zext i1 %1 to i32 172 ret i32 %2 173 } 174 175 define i32 @fcmp_ugt(double %a, double %b) nounwind { 176 ; RV32IFD-LABEL: fcmp_ugt: 177 ; RV32IFD: # %bb.0: 178 ; RV32IFD-NEXT: addi sp, sp, -16 179 ; RV32IFD-NEXT: sw a2, 8(sp) 180 ; RV32IFD-NEXT: sw a3, 12(sp) 181 ; RV32IFD-NEXT: fld ft0, 8(sp) 182 ; RV32IFD-NEXT: sw a0, 8(sp) 183 ; RV32IFD-NEXT: sw a1, 12(sp) 184 ; RV32IFD-NEXT: fld ft1, 8(sp) 185 ; RV32IFD-NEXT: fle.d a0, ft1, ft0 186 ; RV32IFD-NEXT: xori a0, a0, 1 187 ; RV32IFD-NEXT: addi sp, sp, 16 188 ; RV32IFD-NEXT: ret 189 %1 = fcmp ugt double %a, %b 190 %2 = zext i1 %1 to i32 191 ret i32 %2 192 } 193 194 define i32 @fcmp_uge(double %a, double %b) nounwind { 195 ; RV32IFD-LABEL: fcmp_uge: 196 ; RV32IFD: # %bb.0: 197 ; RV32IFD-NEXT: addi sp, sp, -16 198 ; RV32IFD-NEXT: sw a2, 8(sp) 199 ; RV32IFD-NEXT: sw a3, 12(sp) 200 ; RV32IFD-NEXT: fld ft0, 8(sp) 201 ; RV32IFD-NEXT: sw a0, 8(sp) 202 ; RV32IFD-NEXT: sw a1, 12(sp) 203 ; RV32IFD-NEXT: fld ft1, 8(sp) 204 ; RV32IFD-NEXT: flt.d a0, ft1, ft0 205 ; RV32IFD-NEXT: xori a0, a0, 1 206 ; RV32IFD-NEXT: addi sp, sp, 16 207 ; RV32IFD-NEXT: ret 208 %1 = fcmp uge double %a, %b 209 %2 = zext i1 %1 to i32 210 ret i32 %2 211 } 212 213 define i32 @fcmp_ult(double %a, double %b) nounwind { 214 ; RV32IFD-LABEL: fcmp_ult: 215 ; RV32IFD: # %bb.0: 216 ; RV32IFD-NEXT: addi sp, sp, -16 217 ; RV32IFD-NEXT: sw a0, 8(sp) 218 ; RV32IFD-NEXT: sw a1, 12(sp) 219 ; RV32IFD-NEXT: fld ft0, 8(sp) 220 ; RV32IFD-NEXT: sw a2, 8(sp) 221 ; RV32IFD-NEXT: sw a3, 12(sp) 222 ; RV32IFD-NEXT: fld ft1, 8(sp) 223 ; RV32IFD-NEXT: fle.d a0, ft1, ft0 224 ; RV32IFD-NEXT: xori a0, a0, 1 225 ; RV32IFD-NEXT: addi sp, sp, 16 226 ; RV32IFD-NEXT: ret 227 %1 = fcmp ult double %a, %b 228 %2 = zext i1 %1 to i32 229 ret i32 %2 230 } 231 232 define i32 @fcmp_ule(double %a, double %b) nounwind { 233 ; RV32IFD-LABEL: fcmp_ule: 234 ; RV32IFD: # %bb.0: 235 ; RV32IFD-NEXT: addi sp, sp, -16 236 ; RV32IFD-NEXT: sw a0, 8(sp) 237 ; RV32IFD-NEXT: sw a1, 12(sp) 238 ; RV32IFD-NEXT: fld ft0, 8(sp) 239 ; RV32IFD-NEXT: sw a2, 8(sp) 240 ; RV32IFD-NEXT: sw a3, 12(sp) 241 ; RV32IFD-NEXT: fld ft1, 8(sp) 242 ; RV32IFD-NEXT: flt.d a0, ft1, ft0 243 ; RV32IFD-NEXT: xori a0, a0, 1 244 ; RV32IFD-NEXT: addi sp, sp, 16 245 ; RV32IFD-NEXT: ret 246 %1 = fcmp ule double %a, %b 247 %2 = zext i1 %1 to i32 248 ret i32 %2 249 } 250 251 define i32 @fcmp_une(double %a, double %b) nounwind { 252 ; RV32IFD-LABEL: fcmp_une: 253 ; RV32IFD: # %bb.0: 254 ; RV32IFD-NEXT: addi sp, sp, -16 255 ; RV32IFD-NEXT: sw a2, 8(sp) 256 ; RV32IFD-NEXT: sw a3, 12(sp) 257 ; RV32IFD-NEXT: fld ft0, 8(sp) 258 ; RV32IFD-NEXT: sw a0, 8(sp) 259 ; RV32IFD-NEXT: sw a1, 12(sp) 260 ; RV32IFD-NEXT: fld ft1, 8(sp) 261 ; RV32IFD-NEXT: feq.d a0, ft1, ft0 262 ; RV32IFD-NEXT: xori a0, a0, 1 263 ; RV32IFD-NEXT: addi sp, sp, 16 264 ; RV32IFD-NEXT: ret 265 %1 = fcmp une double %a, %b 266 %2 = zext i1 %1 to i32 267 ret i32 %2 268 } 269 270 define i32 @fcmp_uno(double %a, double %b) nounwind { 271 ; RV32IFD-LABEL: fcmp_uno: 272 ; RV32IFD: # %bb.0: 273 ; RV32IFD-NEXT: addi sp, sp, -16 274 ; RV32IFD-NEXT: sw a0, 8(sp) 275 ; RV32IFD-NEXT: sw a1, 12(sp) 276 ; RV32IFD-NEXT: fld ft0, 8(sp) 277 ; RV32IFD-NEXT: sw a2, 8(sp) 278 ; RV32IFD-NEXT: sw a3, 12(sp) 279 ; RV32IFD-NEXT: fld ft1, 8(sp) 280 ; RV32IFD-NEXT: feq.d a0, ft1, ft1 281 ; RV32IFD-NEXT: feq.d a1, ft0, ft0 282 ; RV32IFD-NEXT: and a0, a1, a0 283 ; RV32IFD-NEXT: seqz a0, a0 284 ; RV32IFD-NEXT: addi sp, sp, 16 285 ; RV32IFD-NEXT: ret 286 %1 = fcmp uno double %a, %b 287 %2 = zext i1 %1 to i32 288 ret i32 %2 289 } 290 291 define i32 @fcmp_true(double %a, double %b) nounwind { 292 ; RV32IFD-LABEL: fcmp_true: 293 ; RV32IFD: # %bb.0: 294 ; RV32IFD-NEXT: addi a0, zero, 1 295 ; RV32IFD-NEXT: ret 296 %1 = fcmp true double %a, %b 297 %2 = zext i1 %1 to i32 298 ret i32 %2 299 } 300
