1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3 ; RUN: | FileCheck -check-prefix=RV32I %s 4 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ 5 ; RUN: | FileCheck -check-prefix=RV32IM %s 6 7 define i32 @urem(i32 %a, i32 %b) nounwind { 8 ; RV32I-LABEL: urem: 9 ; RV32I: # %bb.0: 10 ; RV32I-NEXT: addi sp, sp, -16 11 ; RV32I-NEXT: sw ra, 12(sp) 12 ; RV32I-NEXT: call __umodsi3 13 ; RV32I-NEXT: lw ra, 12(sp) 14 ; RV32I-NEXT: addi sp, sp, 16 15 ; RV32I-NEXT: ret 16 ; 17 ; RV32IM-LABEL: urem: 18 ; RV32IM: # %bb.0: 19 ; RV32IM-NEXT: remu a0, a0, a1 20 ; RV32IM-NEXT: ret 21 %1 = urem i32 %a, %b 22 ret i32 %1 23 } 24 25 define i32 @srem(i32 %a, i32 %b) nounwind { 26 ; RV32I-LABEL: srem: 27 ; RV32I: # %bb.0: 28 ; RV32I-NEXT: addi sp, sp, -16 29 ; RV32I-NEXT: sw ra, 12(sp) 30 ; RV32I-NEXT: call __modsi3 31 ; RV32I-NEXT: lw ra, 12(sp) 32 ; RV32I-NEXT: addi sp, sp, 16 33 ; RV32I-NEXT: ret 34 ; 35 ; RV32IM-LABEL: srem: 36 ; RV32IM: # %bb.0: 37 ; RV32IM-NEXT: rem a0, a0, a1 38 ; RV32IM-NEXT: ret 39 %1 = srem i32 %a, %b 40 ret i32 %1 41 } 42
