1 # RUN: llc -run-pass arm-cp-islands %s -o - | FileCheck %s 2 3 --- | 4 ; ModuleID = '<stdin>' 5 source_filename = "<stdin>" 6 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 7 target triple = "thumbv6m--none-eabi" 8 9 declare void @exit0() 10 11 declare void @exit1(i32) 12 13 declare void @exit2() 14 15 declare void @exit3() 16 17 declare void @exit4() 18 19 define void @jump_table(i32 %val, i32 %arg2, i32 %arg3, i32 %arg4) { 20 entry: 21 switch i32 %val, label %default [ 22 i32 1, label %lab1 23 i32 2, label %lab2 24 i32 3, label %lab3 25 i32 4, label %lab4 26 ] 27 28 default: ; preds = %entry 29 tail call void @exit0() 30 ret void 31 32 lab1: ; preds = %entry 33 %b = sub i32 %val, 1 34 %a = shl i32 %b, 2 35 tail call void @exit1(i32 %a) 36 ret void 37 38 lab2: ; preds = %entry 39 tail call void @exit2() 40 ret void 41 42 lab3: ; preds = %entry 43 tail call void @exit3() 44 ret void 45 46 lab4: ; preds = %entry 47 tail call void @exit4() 48 ret void 49 } 50 51 ; Function Attrs: nounwind 52 declare void @llvm.stackprotector(i8*, i8**) #0 53 54 attributes #0 = { nounwind } 55 56 ... 57 --- 58 name: jump_table 59 alignment: 1 60 exposesReturnsTwice: false 61 legalized: false 62 regBankSelected: false 63 selected: false 64 tracksRegLiveness: true 65 liveins: 66 - { reg: '$r0' } 67 calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13', 68 '$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4', 69 '$r5', '$r6', '$r7', '$r8', '$r9', '$r10', '$r11', 70 '$s16', '$s17', '$s18', '$s19', '$s20', '$s21', 71 '$s22', '$s23', '$s24', '$s25', '$s26', '$s27', 72 '$s28', '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11', 73 '$d10_d12', '$d11_d13', '$d12_d14', '$d13_d15', 74 '$q4_q5', '$q5_q6', '$q6_q7', '$q4_q5_q6_q7', '$r4_r5', 75 '$r6_r7', '$r8_r9', '$r10_r11', '$d8_d9_d10', '$d9_d10_d11', 76 '$d10_d11_d12', '$d11_d12_d13', '$d12_d13_d14', 77 '$d13_d14_d15', '$d8_d10_d12', '$d9_d11_d13', '$d10_d12_d14', 78 '$d11_d13_d15', '$d8_d10_d12_d14', '$d9_d11_d13_d15', 79 '$d9_d10', '$d11_d12', '$d13_d14', '$d9_d10_d11_d12', 80 '$d11_d12_d13_d14' ] 81 frameInfo: 82 isFrameAddressTaken: false 83 isReturnAddressTaken: false 84 hasStackMap: false 85 hasPatchPoint: false 86 stackSize: 8 87 offsetAdjustment: 0 88 maxAlignment: 4 89 adjustsStack: true 90 hasCalls: true 91 maxCallFrameSize: 0 92 hasOpaqueSPAdjustment: false 93 hasVAStart: false 94 hasMustTailInVarArgFunc: false 95 stack: 96 - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false } 97 - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7' } 98 jumpTable: 99 kind: inline 100 entries: 101 - id: 0 102 blocks: [ '%bb.3.lab1', '%bb.4.lab2', '%bb.5.lab3', '%bb.6.lab4' ] 103 # r1 is redefined in the middle of the recognizable jump sequence - it shouldn't be clobbered! 104 # CHECK-NOT: tTBB_JT 105 106 body: | 107 bb.0.entry: 108 successors: %bb.2.default(0x19999998), %bb.1.entry(0x66666668) 109 liveins: $r0, $r7, $lr 110 111 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 112 frame-setup CFI_INSTRUCTION def_cfa_offset 8 113 frame-setup CFI_INSTRUCTION offset $lr, -4 114 frame-setup CFI_INSTRUCTION offset $r7, -8 115 $r1, dead $cpsr = tSUBi3 $r0, 1, 14, $noreg 116 tCMPi8 $r1, 3, 14, $noreg, implicit-def $cpsr 117 tBcc %bb.2.default, 8, killed $cpsr 118 119 bb.1.entry: 120 successors: %bb.3.lab1(0x20000000), %bb.4.lab2(0x20000000), %bb.5.lab3(0x20000000), %bb.6.lab4(0x20000000) 121 liveins: $r0, $r1 122 123 $r1, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg 124 $r2 = tLEApcrelJT %jump-table.0, 14, $noreg 125 $r2 = tLDRr killed $r1, killed $r2, 14, $noreg :: (load 4 from jump-table) 126 $r1, dead $cpsr = tLSLri $r2, 2, 14, $noreg 127 tBR_JTr killed $r2, %jump-table.0 128 129 bb.2.default: 130 tBL 14, $noreg, @exit0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp 131 tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp 132 133 bb.3.lab1: 134 liveins: $r0,$r1 135 136 tBL 14, $noreg, @exit1, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp 137 tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp 138 139 bb.4.lab2: 140 tBL 14, $noreg, @exit2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp 141 tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp 142 143 bb.5.lab3: 144 tBL 14, $noreg, @exit3, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp 145 tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp 146 147 bb.6.lab4: 148 tBL 14, $noreg, @exit4, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp 149 tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp 150 151 ... 152
