1 ; RUN: llc -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs < %s 2 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" 3 target triple = "x86_64-apple-darwin" 4 5 ; This test causes a virtual FP register to be redefined while it is live: 6 ;%bb.5.bb10: 7 ; successors: %bb.5 8 ; Predecessors according to CFG: %bb.4 %bb.5 9 ; %reg1024 = MOV_Fp8080 %reg1034 10 ; %reg1025 = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool] 11 ; %reg1034 = MOV_Fp8080 %reg1025 12 ; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6 13 ; JMP_4 <%bb.5> 14 ; 15 ; The X86FP pass needs good kill flags, like on %fp0 representing %reg1034: 16 ;%bb.5.bb10: 17 ; successors: %bb.5 18 ; Predecessors according to CFG: %bb.4 %bb.5 19 ; %fp0 = LD_Fp80m %stack.3, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4) 20 ; %fp1 = MOV_Fp8080 killed %fp0 21 ; %fp2 = MUL_Fp80m32 %fp1, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool] 22 ; %fp0 = MOV_Fp8080 %fp2 23 ; ST_FpP80m %stack.3, 1, %reg0, 0, %reg0, killed %fp0; mem:ST10[FixedStack3](align=4) 24 ; ST_FpP80m %stack.4, 1, %reg0, 0, %reg0, killed %fp1; mem:ST10[FixedStack4](align=4) 25 ; ST_FpP80m %stack.5, 1, %reg0, 0, %reg0, killed %fp2; mem:ST10[FixedStack5](align=4) 26 ; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6 27 ; JMP_4 <%bb.5> 28 29 define fastcc i32 @sqlite3AtoF(i8* %z, double* nocapture %pResult) nounwind ssp { 30 entry: 31 br i1 undef, label %bb2, label %bb1.i.i 32 33 bb1.i.i: ; preds = %entry 34 unreachable 35 36 bb2: ; preds = %entry 37 br i1 undef, label %isdigit339.exit11.preheader, label %bb13 38 39 isdigit339.exit11.preheader: ; preds = %bb2 40 br i1 undef, label %bb12, label %bb10 41 42 bb10: ; preds = %bb10, %isdigit339.exit11.preheader 43 %divisor.041 = phi x86_fp80 [ %0, %bb10 ], [ 0xK3FFF8000000000000000, %isdigit339.exit11.preheader ] ; <x86_fp80> [#uses=1] 44 %0 = fmul x86_fp80 %divisor.041, 0xK4002A000000000000000 ; <x86_fp80> [#uses=2] 45 br i1 false, label %bb12, label %bb10 46 47 bb12: ; preds = %bb10, %isdigit339.exit11.preheader 48 %divisor.0.lcssa = phi x86_fp80 [ 0xK3FFF8000000000000000, %isdigit339.exit11.preheader ], [ %0, %bb10 ] ; <x86_fp80> [#uses=0] 49 br label %bb13 50 51 bb13: ; preds = %bb12, %bb2 52 br i1 undef, label %bb34, label %bb36 53 54 bb34: ; preds = %bb13 55 br label %bb36 56 57 bb36: ; preds = %bb34, %bb13 58 ret i32 undef 59 } 60
