1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s 3 4 ; These tests use adc/sbb in place of set+add/sub. Should this transform 5 ; be enabled by micro-architecture rather than as part of generic lowering/isel? 6 7 ; <rdar://problem/8449754> 8 9 define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp { 10 ; CHECK-LABEL: test1: 11 ; CHECK: # %bb.0: 12 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx 13 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 14 ; CHECK-NEXT: movl %eax, %edx 15 ; CHECK-NEXT: addl %ecx, %edx 16 ; CHECK-NEXT: adcl %ecx, %eax 17 ; CHECK-NEXT: retl 18 %add4 = add i32 %x, %sum 19 %cmp = icmp ult i32 %add4, %x 20 %inc = zext i1 %cmp to i32 21 %z.0 = add i32 %add4, %inc 22 ret i32 %z.0 23 } 24 25 ; <rdar://problem/12579915> 26 27 define i32 @test2(i32 %x, i32 %y, i32 %res) nounwind uwtable readnone ssp { 28 ; CHECK-LABEL: test2: 29 ; CHECK: # %bb.0: 30 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 31 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx 32 ; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %ecx 33 ; CHECK-NEXT: sbbl $0, %eax 34 ; CHECK-NEXT: retl 35 %cmp = icmp ugt i32 %x, %y 36 %dec = sext i1 %cmp to i32 37 %dec.res = add nsw i32 %dec, %res 38 ret i32 %dec.res 39 } 40 41
