1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc -mtriple=i386-apple-darwin < %s | FileCheck %s 3 4 ; PR30841: https://llvm.org/bugs/show_bug.cgi?id=30841 5 ; Demanded bits analysis must disable nsw/nuw when it makes a 6 ; simplification to add/sub such as in this case. 7 8 define i8 @PR30841(i64 %argc) { 9 ; CHECK-LABEL: PR30841: 10 ; CHECK: ## %bb.0: ## %entry 11 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 12 ; CHECK-NEXT: negl %eax 13 ; CHECK-NEXT: ## kill: def $al killed $al killed $eax 14 ; CHECK-NEXT: retl 15 entry: 16 %or = or i64 %argc, -4294967296 17 br label %end 18 19 end: 20 %neg = sub nuw nsw i64 -4294967296, %argc 21 %trunc = trunc i64 %neg to i8 22 ret i8 %trunc 23 } 24 25
