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      1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin                  -disable-fp-elim | FileCheck %s
      2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7     -disable-fp-elim | FileCheck --check-prefix=SSE %s
      3 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -disable-fp-elim | FileCheck --check-prefix=AVX %s
      4 
      5 
      6 ; Stackmap Header: no constants - 6 callsites
      7 ; CHECK-LABEL:  .section __LLVM_STACKMAPS,__llvm_stackmaps
      8 ; CHECK-NEXT:   __LLVM_StackMaps:
      9 ; Header
     10 ; CHECK-NEXT:   .byte 3
     11 ; CHECK-NEXT:   .byte 0
     12 ; CHECK-NEXT:   .short 0
     13 ; Num Functions
     14 ; CHECK-NEXT:   .long 8
     15 ; Num Constants
     16 ; CHECK-NEXT:   .long 0
     17 ; Num Callsites
     18 ; CHECK-NEXT:   .long 8
     19 
     20 ; Functions and stack size
     21 ; CHECK-NEXT:   .quad _test
     22 ; CHECK-NEXT:   .quad 8
     23 ; CHECK-NEXT:   .quad 1
     24 ; CHECK-NEXT:   .quad _property_access1
     25 ; CHECK-NEXT:   .quad 8
     26 ; CHECK-NEXT:   .quad 1
     27 ; CHECK-NEXT:   .quad _property_access2
     28 ; CHECK-NEXT:   .quad 24
     29 ; CHECK-NEXT:   .quad 1
     30 ; CHECK-NEXT:   .quad _property_access3
     31 ; CHECK-NEXT:   .quad 24
     32 ; CHECK-NEXT:   .quad 1
     33 ; CHECK-NEXT:   .quad _anyreg_test1
     34 ; CHECK-NEXT:   .quad 56
     35 ; CHECK-NEXT:   .quad 1
     36 ; CHECK-NEXT:   .quad _anyreg_test2
     37 ; CHECK-NEXT:   .quad 8
     38 ; CHECK-NEXT:   .quad 1
     39 ; CHECK-NEXT:   .quad _patchpoint_spilldef
     40 ; CHECK-NEXT:   .quad 56
     41 ; CHECK-NEXT:   .quad 1
     42 ; CHECK-NEXT:   .quad _patchpoint_spillargs
     43 ; CHECK-NEXT:   .quad 88
     44 ; CHECK-NEXT:   .quad 1
     45 
     46 ; No constants
     47 
     48 ; Callsites
     49 ; test
     50 ; CHECK-LABEL:  .long   L{{.*}}-_test
     51 ; CHECK-NEXT:   .short  0
     52 ; 3 locations
     53 ; CHECK-NEXT:   .short  3
     54 ; Loc 0: Register
     55 ; CHECK-NEXT:   .byte 1
     56 ; CHECK-NEXT:   .byte 0
     57 ; CHECK-NEXT:   .short 4
     58 ; CHECK-NEXT:   .short {{[0-9]+}}
     59 ; CHECK-NEXT:   .short 0
     60 ; CHECK-NEXT:   .long 0
     61 ; Loc 1: Register
     62 ; CHECK-NEXT:   .byte 1
     63 ; CHECK-NEXT:   .byte 0
     64 ; CHECK-NEXT:   .short 4
     65 ; CHECK-NEXT:   .short {{[0-9]+}}
     66 ; CHECK-NEXT:   .short 0
     67 ; CHECK-NEXT:   .long 0
     68 ; Loc 2: Constant 3
     69 ; CHECK-NEXT:   .byte 4
     70 ; CHECK-NEXT:   .byte 0
     71 ; CHECK-NEXT:   .short 8
     72 ; CHECK-NEXT:   .short  0
     73 ; CHECK-NEXT:   .short 0
     74 ; CHECK-NEXT:   .long 3
     75 define i64 @test() nounwind ssp uwtable {
     76 entry:
     77   call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 15, i8* null, i32 2, i32 1, i32 2, i64 3)
     78   ret i64 0
     79 }
     80 
     81 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
     82 ; CHECK-LABEL:  .long   L{{.*}}-_property_access1
     83 ; CHECK-NEXT:   .short  0
     84 ; 2 locations
     85 ; CHECK-NEXT:   .short  2
     86 ; Loc 0: Register <-- this is the return register
     87 ; CHECK-NEXT:   .byte 1
     88 ; CHECK-NEXT:   .byte 0
     89 ; CHECK-NEXT:   .short 8
     90 ; CHECK-NEXT:   .short {{[0-9]+}}
     91 ; CHECK-NEXT:   .short 0
     92 ; CHECK-NEXT:   .long 0
     93 ; Loc 1: Register
     94 ; CHECK-NEXT:   .byte 1
     95 ; CHECK-NEXT:   .byte 0
     96 ; CHECK-NEXT:   .short 8
     97 ; CHECK-NEXT:   .short {{[0-9]+}}
     98 ; CHECK-NEXT:   .short 0
     99 ; CHECK-NEXT:   .long 0
    100 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
    101 entry:
    102   %f = inttoptr i64 12297829382473034410 to i8*
    103   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 15, i8* %f, i32 1, i8* %obj)
    104   ret i64 %ret
    105 }
    106 
    107 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
    108 ; CHECK-LABEL:  .long   L{{.*}}-_property_access2
    109 ; CHECK-NEXT:   .short  0
    110 ; 2 locations
    111 ; CHECK-NEXT:   .short  2
    112 ; Loc 0: Register <-- this is the return register
    113 ; CHECK-NEXT:   .byte 1
    114 ; CHECK-NEXT:   .byte 0
    115 ; CHECK-NEXT:   .short 8
    116 ; CHECK-NEXT:   .short {{[0-9]+}}
    117 ; CHECK-NEXT:   .short 0
    118 ; CHECK-NEXT:   .long 0
    119 ; Loc 1: Register
    120 ; CHECK-NEXT:   .byte 1
    121 ; CHECK-NEXT:   .byte 0
    122 ; CHECK-NEXT:   .short 8
    123 ; CHECK-NEXT:   .short {{[0-9]+}}
    124 ; CHECK-NEXT:   .short 0
    125 ; CHECK-NEXT:   .long 0
    126 define i64 @property_access2() nounwind ssp uwtable {
    127 entry:
    128   %obj = alloca i64, align 8
    129   %f = inttoptr i64 12297829382473034410 to i8*
    130   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %f, i32 1, i64* %obj)
    131   ret i64 %ret
    132 }
    133 
    134 ; property access 3 - %obj is a frame index
    135 ; CHECK-LABEL:  .long   L{{.*}}-_property_access3
    136 ; CHECK-NEXT:   .short  0
    137 ; 2 locations
    138 ; CHECK-NEXT:   .short  2
    139 ; Loc 0: Register <-- this is the return register
    140 ; CHECK-NEXT:   .byte 1
    141 ; CHECK-NEXT:   .byte 0
    142 ; CHECK-NEXT:   .short 8
    143 ; CHECK-NEXT:   .short {{[0-9]+}}
    144 ; CHECK-NEXT:   .short 0
    145 ; CHECK-NEXT:   .long 0
    146 ; Loc 1: Direct RBP - ofs
    147 ; CHECK-NEXT:   .byte 2
    148 ; CHECK-NEXT:   .byte 0
    149 ; CHECK-NEXT:   .short 8
    150 ; CHECK-NEXT:   .short 6
    151 ; CHECK-NEXT:   .short 0
    152 ; CHECK-NEXT:   .long
    153 define i64 @property_access3() nounwind ssp uwtable {
    154 entry:
    155   %obj = alloca i64, align 8
    156   %f = inttoptr i64 12297829382473034410 to i8*
    157   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 15, i8* %f, i32 0, i64* %obj)
    158   ret i64 %ret
    159 }
    160 
    161 ; anyreg_test1
    162 ; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test1
    163 ; CHECK-NEXT:   .short  0
    164 ; 14 locations
    165 ; CHECK-NEXT:   .short  14
    166 ; Loc 0: Register <-- this is the return register
    167 ; CHECK-NEXT:   .byte 1
    168 ; CHECK-NEXT:   .byte 0
    169 ; CHECK-NEXT:   .short 8
    170 ; CHECK-NEXT:   .short {{[0-9]+}}
    171 ; CHECK-NEXT:   .short 0
    172 ; CHECK-NEXT:   .long 0
    173 ; Loc 1: Register
    174 ; CHECK-NEXT:   .byte 1
    175 ; CHECK-NEXT:   .byte 0
    176 ; CHECK-NEXT:   .short 8
    177 ; CHECK-NEXT:   .short {{[0-9]+}}
    178 ; CHECK-NEXT:   .short 0
    179 ; CHECK-NEXT:   .long 0
    180 ; Loc 2: Register
    181 ; CHECK-NEXT:   .byte 1
    182 ; CHECK-NEXT:   .byte 0
    183 ; CHECK-NEXT:   .short 8
    184 ; CHECK-NEXT:   .short {{[0-9]+}}
    185 ; CHECK-NEXT:   .short 0
    186 ; CHECK-NEXT:   .long 0
    187 ; Loc 3: Register
    188 ; CHECK-NEXT:   .byte 1
    189 ; CHECK-NEXT:   .byte 0
    190 ; CHECK-NEXT:   .short 8
    191 ; CHECK-NEXT:   .short {{[0-9]+}}
    192 ; CHECK-NEXT:   .short 0
    193 ; CHECK-NEXT:   .long 0
    194 ; Loc 4: Register
    195 ; CHECK-NEXT:   .byte 1
    196 ; CHECK-NEXT:   .byte 0
    197 ; CHECK-NEXT:   .short 8
    198 ; CHECK-NEXT:   .short {{[0-9]+}}
    199 ; CHECK-NEXT:   .short 0
    200 ; CHECK-NEXT:   .long 0
    201 ; Loc 5: Register
    202 ; CHECK-NEXT:   .byte 1
    203 ; CHECK-NEXT:   .byte 0
    204 ; CHECK-NEXT:   .short 8
    205 ; CHECK-NEXT:   .short {{[0-9]+}}
    206 ; CHECK-NEXT:   .short 0
    207 ; CHECK-NEXT:   .long 0
    208 ; Loc 6: Register
    209 ; CHECK-NEXT:   .byte 1
    210 ; CHECK-NEXT:   .byte 0
    211 ; CHECK-NEXT:   .short 8
    212 ; CHECK-NEXT:   .short {{[0-9]+}}
    213 ; CHECK-NEXT:   .short 0
    214 ; CHECK-NEXT:   .long 0
    215 ; Loc 7: Register
    216 ; CHECK-NEXT:   .byte 1
    217 ; CHECK-NEXT:   .byte 0
    218 ; CHECK-NEXT:   .short 8
    219 ; CHECK-NEXT:   .short {{[0-9]+}}
    220 ; CHECK-NEXT:   .short 0
    221 ; CHECK-NEXT:   .long 0
    222 ; Loc 8: Register
    223 ; CHECK-NEXT:   .byte 1
    224 ; CHECK-NEXT:   .byte 0
    225 ; CHECK-NEXT:   .short 8
    226 ; CHECK-NEXT:   .short {{[0-9]+}}
    227 ; CHECK-NEXT:   .short 0
    228 ; CHECK-NEXT:   .long 0
    229 ; Loc 9: Register
    230 ; CHECK-NEXT:   .byte 1
    231 ; CHECK-NEXT:   .byte 0
    232 ; CHECK-NEXT:   .short 8
    233 ; CHECK-NEXT:   .short {{[0-9]+}}
    234 ; CHECK-NEXT:   .short 0
    235 ; CHECK-NEXT:   .long 0
    236 ; Loc 10: Register
    237 ; CHECK-NEXT:   .byte 1
    238 ; CHECK-NEXT:   .byte 0
    239 ; CHECK-NEXT:   .short 8
    240 ; CHECK-NEXT:   .short {{[0-9]+}}
    241 ; CHECK-NEXT:   .short 0
    242 ; CHECK-NEXT:   .long 0
    243 ; Loc 11: Register
    244 ; CHECK-NEXT:   .byte 1
    245 ; CHECK-NEXT:   .byte 0
    246 ; CHECK-NEXT:   .short 8
    247 ; CHECK-NEXT:   .short {{[0-9]+}}
    248 ; CHECK-NEXT:   .short 0
    249 ; CHECK-NEXT:   .long 0
    250 ; Loc 12: Register
    251 ; CHECK-NEXT:   .byte 1
    252 ; CHECK-NEXT:   .byte 0
    253 ; CHECK-NEXT:   .short 8
    254 ; CHECK-NEXT:   .short {{[0-9]+}}
    255 ; CHECK-NEXT:   .short 0
    256 ; CHECK-NEXT:   .long 0
    257 ; Loc 13: Register
    258 ; CHECK-NEXT:   .byte 1
    259 ; CHECK-NEXT:   .byte 0
    260 ; CHECK-NEXT:   .short 8
    261 ; CHECK-NEXT:   .short {{[0-9]+}}
    262 ; CHECK-NEXT:   .short 0
    263 ; CHECK-NEXT:   .long 0
    264 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
    265 entry:
    266   %f = inttoptr i64 12297829382473034410 to i8*
    267   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 15, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
    268   ret i64 %ret
    269 }
    270 
    271 ; anyreg_test2
    272 ; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test2
    273 ; CHECK-NEXT:   .short  0
    274 ; 14 locations
    275 ; CHECK-NEXT:   .short  14
    276 ; Loc 0: Register <-- this is the return register
    277 ; CHECK-NEXT:   .byte 1
    278 ; CHECK-NEXT:   .byte 0
    279 ; CHECK-NEXT:   .short 8
    280 ; CHECK-NEXT:   .short {{[0-9]+}}
    281 ; CHECK-NEXT:   .short 0
    282 ; CHECK-NEXT:   .long 0
    283 ; Loc 1: Register
    284 ; CHECK-NEXT:   .byte 1
    285 ; CHECK-NEXT:   .byte 0
    286 ; CHECK-NEXT:   .short 8
    287 ; CHECK-NEXT:   .short {{[0-9]+}}
    288 ; CHECK-NEXT:   .short 0
    289 ; CHECK-NEXT:   .long 0
    290 ; Loc 2: Register
    291 ; CHECK-NEXT:   .byte 1
    292 ; CHECK-NEXT:   .byte 0
    293 ; CHECK-NEXT:   .short 8
    294 ; CHECK-NEXT:   .short {{[0-9]+}}
    295 ; CHECK-NEXT:   .short 0
    296 ; CHECK-NEXT:   .long 0
    297 ; Loc 3: Register
    298 ; CHECK-NEXT:   .byte 1
    299 ; CHECK-NEXT:   .byte 0
    300 ; CHECK-NEXT:   .short 8
    301 ; CHECK-NEXT:   .short {{[0-9]+}}
    302 ; CHECK-NEXT:   .short 0
    303 ; CHECK-NEXT:   .long 0
    304 ; Loc 4: Register
    305 ; CHECK-NEXT:   .byte 1
    306 ; CHECK-NEXT:   .byte 0
    307 ; CHECK-NEXT:   .short 8
    308 ; CHECK-NEXT:   .short {{[0-9]+}}
    309 ; CHECK-NEXT:   .short 0
    310 ; CHECK-NEXT:   .long 0
    311 ; Loc 5: Register
    312 ; CHECK-NEXT:   .byte 1
    313 ; CHECK-NEXT:   .byte 0
    314 ; CHECK-NEXT:   .short 8
    315 ; CHECK-NEXT:   .short {{[0-9]+}}
    316 ; CHECK-NEXT:   .short 0
    317 ; CHECK-NEXT:   .long 0
    318 ; Loc 6: Register
    319 ; CHECK-NEXT:   .byte 1
    320 ; CHECK-NEXT:   .byte 0
    321 ; CHECK-NEXT:   .short 8
    322 ; CHECK-NEXT:   .short {{[0-9]+}}
    323 ; CHECK-NEXT:   .short 0
    324 ; CHECK-NEXT:   .long 0
    325 ; Loc 7: Register
    326 ; CHECK-NEXT:   .byte 1
    327 ; CHECK-NEXT:   .byte 0
    328 ; CHECK-NEXT:   .short 8
    329 ; CHECK-NEXT:   .short {{[0-9]+}}
    330 ; CHECK-NEXT:   .short 0
    331 ; CHECK-NEXT:   .long 0
    332 ; Loc 8: Register
    333 ; CHECK-NEXT:   .byte 1
    334 ; CHECK-NEXT:   .byte 0
    335 ; CHECK-NEXT:   .short 8
    336 ; CHECK-NEXT:   .short {{[0-9]+}}
    337 ; CHECK-NEXT:   .short 0
    338 ; CHECK-NEXT:   .long 0
    339 ; Loc 9: Argument, still on stack
    340 ; CHECK-NEXT: .byte  3
    341 ; CHECK-NEXT: .byte  0
    342 ; CHECK-NEXT: .short  8
    343 ; CHECK-NEXT: .short 6
    344 ; CHECK-NEXT: .short 0
    345 ; CHECK-NEXT: .long
    346 ; Loc 10: Argument, still on stack
    347 ; CHECK-NEXT: .byte  3
    348 ; CHECK-NEXT: .byte  0
    349 ; CHECK-NEXT: .short  8
    350 ; CHECK-NEXT: .short 6
    351 ; CHECK-NEXT: .short 0
    352 ; CHECK-NEXT: .long
    353 ; Loc 11: Argument, still on stack
    354 ; CHECK-NEXT: .byte  3
    355 ; CHECK-NEXT: .byte  0
    356 ; CHECK-NEXT: .short  8
    357 ; CHECK-NEXT: .short 6
    358 ; CHECK-NEXT: .short 0
    359 ; CHECK-NEXT: .long
    360 ; Loc 12: Argument, still on stack
    361 ; CHECK-NEXT: .byte  3
    362 ; CHECK-NEXT: .byte  0
    363 ; CHECK-NEXT: .short  8
    364 ; CHECK-NEXT: .short 6
    365 ; CHECK-NEXT: .short 0
    366 ; CHECK-NEXT: .long
    367 ; Loc 13: Argument, still on stack
    368 ; CHECK-NEXT: .byte  3
    369 ; CHECK-NEXT: .byte  0
    370 ; CHECK-NEXT: .short  8
    371 ; CHECK-NEXT: .short 6
    372 ; CHECK-NEXT: .short 0
    373 ; CHECK-NEXT: .long
    374 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
    375 entry:
    376   %f = inttoptr i64 12297829382473034410 to i8*
    377   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
    378   ret i64 %ret
    379 }
    380 
    381 ; Test spilling the return value of an anyregcc call.
    382 ;
    383 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
    384 ;
    385 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
    386 ; CHECK-NEXT: .short 0
    387 ; CHECK-NEXT: .short 3
    388 ; Loc 0: Register (some register that will be spilled to the stack)
    389 ; CHECK-NEXT: .byte  1
    390 ; CHECK-NEXT: .byte  0
    391 ; CHECK-NEXT: .short  8
    392 ; CHECK-NEXT: .short {{[0-9]+}}
    393 ; CHECK-NEXT: .short 0
    394 ; CHECK-NEXT: .long  0
    395 ; Loc 1: Register RDI
    396 ; CHECK-NEXT: .byte  1
    397 ; CHECK-NEXT: .byte  0
    398 ; CHECK-NEXT: .short  8
    399 ; CHECK-NEXT: .short 5
    400 ; CHECK-NEXT: .short 0
    401 ; CHECK-NEXT: .long  0
    402 ; Loc 1: Register RSI
    403 ; CHECK-NEXT: .byte  1
    404 ; CHECK-NEXT: .byte  0
    405 ; CHECK-NEXT: .short  8
    406 ; CHECK-NEXT: .short 4
    407 ; CHECK-NEXT: .short 0
    408 ; CHECK-NEXT: .long  0
    409 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
    410 entry:
    411   %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
    412   tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
    413   ret i64 %result
    414 }
    415 
    416 ; Test spilling the arguments of an anyregcc call.
    417 ;
    418 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
    419 ;
    420 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
    421 ; CHECK-NEXT: .short 0
    422 ; CHECK-NEXT: .short 5
    423 ; Loc 0: Return a register
    424 ; CHECK-NEXT: .byte  1
    425 ; CHECK-NEXT: .byte  0
    426 ; CHECK-NEXT: .short  8
    427 ; CHECK-NEXT: .short {{[0-9]+}}
    428 ; CHECK-NEXT: .short 0
    429 ; CHECK-NEXT: .long  0
    430 ; Loc 1: Arg0 in a Register
    431 ; CHECK-NEXT: .byte  1
    432 ; CHECK-NEXT: .byte  0
    433 ; CHECK-NEXT: .short  8
    434 ; CHECK-NEXT: .short {{[0-9]+}}
    435 ; CHECK-NEXT: .short 0
    436 ; CHECK-NEXT: .long  0
    437 ; Loc 2: Arg1 in a Register
    438 ; CHECK-NEXT: .byte  1
    439 ; CHECK-NEXT: .byte  0
    440 ; CHECK-NEXT: .short  8
    441 ; CHECK-NEXT: .short {{[0-9]+}}
    442 ; CHECK-NEXT: .short 0
    443 ; CHECK-NEXT: .long  0
    444 ; Loc 3: Arg2 spilled to RBP +
    445 ; CHECK-NEXT: .byte  3
    446 ; CHECK-NEXT: .byte  0
    447 ; CHECK-NEXT: .short  8
    448 ; CHECK-NEXT: .short 6
    449 ; CHECK-NEXT: .short 0
    450 ; CHECK-NEXT: .long
    451 ; Loc 4: Arg3 spilled to RBP +
    452 ; CHECK-NEXT: .byte  3
    453 ; CHECK-NEXT: .byte  0
    454 ; CHECK-NEXT: .short  8
    455 ; CHECK-NEXT: .short 6
    456 ; CHECK-NEXT: .short 0
    457 ; CHECK-NEXT: .long
    458 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
    459 entry:
    460   tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
    461   %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
    462   ret i64 %result
    463 }
    464 
    465 ; Make sure all regs are spilled
    466 define anyregcc void @anyregcc1() {
    467 entry:
    468 ;SSE-LABEL: anyregcc1
    469 ;SSE:      pushq %rbp
    470 ;SSE:      pushq %rax
    471 ;SSE:      pushq %r15
    472 ;SSE:      pushq %r14
    473 ;SSE:      pushq %r13
    474 ;SSE:      pushq %r12
    475 ;SSE:      pushq %r11
    476 ;SSE:      pushq %r10
    477 ;SSE:      pushq %r9
    478 ;SSE:      pushq %r8
    479 ;SSE:      pushq %rdi
    480 ;SSE:      pushq %rsi
    481 ;SSE:      pushq %rdx
    482 ;SSE:      pushq %rcx
    483 ;SSE:      pushq %rbx
    484 ;SSE:      movaps %xmm15
    485 ;SSE-NEXT: movaps %xmm14
    486 ;SSE-NEXT: movaps %xmm13
    487 ;SSE-NEXT: movaps %xmm12
    488 ;SSE-NEXT: movaps %xmm11
    489 ;SSE-NEXT: movaps %xmm10
    490 ;SSE-NEXT: movaps %xmm9
    491 ;SSE-NEXT: movaps %xmm8
    492 ;SSE-NEXT: movaps %xmm7
    493 ;SSE-NEXT: movaps %xmm6
    494 ;SSE-NEXT: movaps %xmm5
    495 ;SSE-NEXT: movaps %xmm4
    496 ;SSE-NEXT: movaps %xmm3
    497 ;SSE-NEXT: movaps %xmm2
    498 ;SSE-NEXT: movaps %xmm1
    499 ;SSE-NEXT: movaps %xmm0
    500 ;AVX-LABEL:anyregcc1
    501 ;AVX:      pushq %rbp
    502 ;AVX:      pushq %rax
    503 ;AVX:      pushq %r15
    504 ;AVX:      pushq %r14
    505 ;AVX:      pushq %r13
    506 ;AVX:      pushq %r12
    507 ;AVX:      pushq %r11
    508 ;AVX:      pushq %r10
    509 ;AVX:      pushq %r9
    510 ;AVX:      pushq %r8
    511 ;AVX:      pushq %rdi
    512 ;AVX:      pushq %rsi
    513 ;AVX:      pushq %rdx
    514 ;AVX:      pushq %rcx
    515 ;AVX:      pushq %rbx
    516 ;AVX:      vmovaps %ymm15
    517 ;AVX-NEXT: vmovaps %ymm14
    518 ;AVX-NEXT: vmovaps %ymm13
    519 ;AVX-NEXT: vmovaps %ymm12
    520 ;AVX-NEXT: vmovaps %ymm11
    521 ;AVX-NEXT: vmovaps %ymm10
    522 ;AVX-NEXT: vmovaps %ymm9
    523 ;AVX-NEXT: vmovaps %ymm8
    524 ;AVX-NEXT: vmovaps %ymm7
    525 ;AVX-NEXT: vmovaps %ymm6
    526 ;AVX-NEXT: vmovaps %ymm5
    527 ;AVX-NEXT: vmovaps %ymm4
    528 ;AVX-NEXT: vmovaps %ymm3
    529 ;AVX-NEXT: vmovaps %ymm2
    530 ;AVX-NEXT: vmovaps %ymm1
    531 ;AVX-NEXT: vmovaps %ymm0
    532   call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{rbp},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15}"()
    533   ret void
    534 }
    535 
    536 ; Make sure we don't spill any XMMs/YMMs
    537 declare anyregcc void @foo()
    538 define void @anyregcc2() {
    539 entry:
    540 ;SSE-LABEL: anyregcc2
    541 ;SSE-NOT: movaps %xmm
    542 ;AVX-LABEL: anyregcc2
    543 ;AVX-NOT: vmovups %ymm
    544   %a0 = call <2 x double> asm sideeffect "", "={xmm0}"() nounwind
    545   %a1 = call <2 x double> asm sideeffect "", "={xmm1}"() nounwind
    546   %a2 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
    547   %a3 = call <2 x double> asm sideeffect "", "={xmm3}"() nounwind
    548   %a4 = call <2 x double> asm sideeffect "", "={xmm4}"() nounwind
    549   %a5 = call <2 x double> asm sideeffect "", "={xmm5}"() nounwind
    550   %a6 = call <2 x double> asm sideeffect "", "={xmm6}"() nounwind
    551   %a7 = call <2 x double> asm sideeffect "", "={xmm7}"() nounwind
    552   %a8 = call <2 x double> asm sideeffect "", "={xmm8}"() nounwind
    553   %a9 = call <2 x double> asm sideeffect "", "={xmm9}"() nounwind
    554   %a10 = call <2 x double> asm sideeffect "", "={xmm10}"() nounwind
    555   %a11 = call <2 x double> asm sideeffect "", "={xmm11}"() nounwind
    556   %a12 = call <2 x double> asm sideeffect "", "={xmm12}"() nounwind
    557   %a13 = call <2 x double> asm sideeffect "", "={xmm13}"() nounwind
    558   %a14 = call <2 x double> asm sideeffect "", "={xmm14}"() nounwind
    559   %a15 = call <2 x double> asm sideeffect "", "={xmm15}"() nounwind
    560   call anyregcc void @foo()
    561   call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},{xmm8},{xmm9},{xmm10},{xmm11},{xmm12},{xmm13},{xmm14},{xmm15}"(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3, <2 x double> %a4, <2 x double> %a5, <2 x double> %a6, <2 x double> %a7, <2 x double> %a8, <2 x double> %a9, <2 x double> %a10, <2 x double> %a11, <2 x double> %a12, <2 x double> %a13, <2 x double> %a14, <2 x double> %a15)
    562   ret void
    563 }
    564 
    565 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
    566 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
    567