1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s --check-prefixes=AVX,AVX1 3 ; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f,avx512vl | FileCheck %s --check-prefixes=AVX,AVX512 4 5 ; PR37751 - https://bugs.llvm.org/show_bug.cgi?id=37751 6 ; We can't combine into 'round' instructions because the behavior is different for out-of-range values. 7 8 declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) 9 declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) 10 11 define <8 x float> @float_to_int_to_float_mem_v8f32(<8 x float>* %p) #0 { 12 ; AVX-LABEL: float_to_int_to_float_mem_v8f32: 13 ; AVX: # %bb.0: 14 ; AVX-NEXT: vcvttps2dq (%rdi), %ymm0 15 ; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0 16 ; AVX-NEXT: retq 17 %x = load <8 x float>, <8 x float>* %p, align 16 18 %fptosi = tail call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %x) 19 %sitofp = sitofp <8 x i32> %fptosi to <8 x float> 20 ret <8 x float> %sitofp 21 } 22 23 define <8 x float> @float_to_int_to_float_reg_v8f32(<8 x float> %x) #0 { 24 ; AVX-LABEL: float_to_int_to_float_reg_v8f32: 25 ; AVX: # %bb.0: 26 ; AVX-NEXT: vcvttps2dq %ymm0, %ymm0 27 ; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0 28 ; AVX-NEXT: retq 29 %fptosi = tail call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %x) 30 %sitofp = sitofp <8 x i32> %fptosi to <8 x float> 31 ret <8 x float> %sitofp 32 } 33 34 define <4 x double> @float_to_int_to_float_mem_v4f64(<4 x double>* %p) #0 { 35 ; AVX-LABEL: float_to_int_to_float_mem_v4f64: 36 ; AVX: # %bb.0: 37 ; AVX-NEXT: vcvttpd2dqy (%rdi), %xmm0 38 ; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 39 ; AVX-NEXT: retq 40 %x = load <4 x double>, <4 x double>* %p, align 16 41 %fptosi = tail call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %x) 42 %sitofp = sitofp <4 x i32> %fptosi to <4 x double> 43 ret <4 x double> %sitofp 44 } 45 46 define <4 x double> @float_to_int_to_float_reg_v4f64(<4 x double> %x) #0 { 47 ; AVX-LABEL: float_to_int_to_float_reg_v4f64: 48 ; AVX: # %bb.0: 49 ; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0 50 ; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 51 ; AVX-NEXT: retq 52 %fptosi = tail call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %x) 53 %sitofp = sitofp <4 x i32> %fptosi to <4 x double> 54 ret <4 x double> %sitofp 55 } 56 57 attributes #0 = { "no-signed-zeros-fp-math"="true" } 58 59
