1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -disable-peephole -mtriple=i686-apple-darwin -mattr=+avx512f,avx512bw | FileCheck %s --check-prefix=X32 3 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,avx512bw | FileCheck %s --check-prefix=X64 4 5 define <32 x i16> @test_llvm_x86_avx512_pmovsxbw(<32 x i8>* %a) { 6 ; X32-LABEL: test_llvm_x86_avx512_pmovsxbw: 7 ; X32: ## %bb.0: 8 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 9 ; X32-NEXT: vpmovsxbw (%eax), %zmm0 10 ; X32-NEXT: retl 11 ; 12 ; X64-LABEL: test_llvm_x86_avx512_pmovsxbw: 13 ; X64: ## %bb.0: 14 ; X64-NEXT: vpmovsxbw (%rdi), %zmm0 15 ; X64-NEXT: retq 16 %1 = load <32 x i8>, <32 x i8>* %a, align 1 17 %2 = sext <32 x i8> %1 to <32 x i16> 18 ret <32 x i16> %2 19 } 20 21 define <16 x i32> @test_llvm_x86_avx512_pmovsxbd(<16 x i8>* %a) { 22 ; X32-LABEL: test_llvm_x86_avx512_pmovsxbd: 23 ; X32: ## %bb.0: 24 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 25 ; X32-NEXT: vpmovsxbd (%eax), %zmm0 26 ; X32-NEXT: retl 27 ; 28 ; X64-LABEL: test_llvm_x86_avx512_pmovsxbd: 29 ; X64: ## %bb.0: 30 ; X64-NEXT: vpmovsxbd (%rdi), %zmm0 31 ; X64-NEXT: retq 32 %1 = load <16 x i8>, <16 x i8>* %a, align 1 33 %2 = sext <16 x i8> %1 to <16 x i32> 34 ret <16 x i32> %2 35 } 36 37 define <8 x i64> @test_llvm_x86_avx512_pmovsxbq(<16 x i8>* %a) { 38 ; X32-LABEL: test_llvm_x86_avx512_pmovsxbq: 39 ; X32: ## %bb.0: 40 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 41 ; X32-NEXT: vpmovsxbq (%eax), %zmm0 42 ; X32-NEXT: retl 43 ; 44 ; X64-LABEL: test_llvm_x86_avx512_pmovsxbq: 45 ; X64: ## %bb.0: 46 ; X64-NEXT: vpmovsxbq (%rdi), %zmm0 47 ; X64-NEXT: retq 48 %1 = load <16 x i8>, <16 x i8>* %a, align 1 49 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 50 %3 = sext <8 x i8> %2 to <8 x i64> 51 ret <8 x i64> %3 52 } 53 54 define <16 x i32> @test_llvm_x86_avx512_pmovsxwd(<16 x i16>* %a) { 55 ; X32-LABEL: test_llvm_x86_avx512_pmovsxwd: 56 ; X32: ## %bb.0: 57 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 58 ; X32-NEXT: vpmovsxwd (%eax), %zmm0 59 ; X32-NEXT: retl 60 ; 61 ; X64-LABEL: test_llvm_x86_avx512_pmovsxwd: 62 ; X64: ## %bb.0: 63 ; X64-NEXT: vpmovsxwd (%rdi), %zmm0 64 ; X64-NEXT: retq 65 %1 = load <16 x i16>, <16 x i16>* %a, align 1 66 %2 = sext <16 x i16> %1 to <16 x i32> 67 ret <16 x i32> %2 68 } 69 70 define <8 x i64> @test_llvm_x86_avx512_pmovsxwq(<8 x i16>* %a) { 71 ; X32-LABEL: test_llvm_x86_avx512_pmovsxwq: 72 ; X32: ## %bb.0: 73 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 74 ; X32-NEXT: vpmovsxwq (%eax), %zmm0 75 ; X32-NEXT: retl 76 ; 77 ; X64-LABEL: test_llvm_x86_avx512_pmovsxwq: 78 ; X64: ## %bb.0: 79 ; X64-NEXT: vpmovsxwq (%rdi), %zmm0 80 ; X64-NEXT: retq 81 %1 = load <8 x i16>, <8 x i16>* %a, align 1 82 %2 = sext <8 x i16> %1 to <8 x i64> 83 ret <8 x i64> %2 84 } 85 86 define <8 x i64> @test_llvm_x86_avx512_pmovsxdq(<8 x i32>* %a) { 87 ; X32-LABEL: test_llvm_x86_avx512_pmovsxdq: 88 ; X32: ## %bb.0: 89 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 90 ; X32-NEXT: vpmovsxdq (%eax), %zmm0 91 ; X32-NEXT: retl 92 ; 93 ; X64-LABEL: test_llvm_x86_avx512_pmovsxdq: 94 ; X64: ## %bb.0: 95 ; X64-NEXT: vpmovsxdq (%rdi), %zmm0 96 ; X64-NEXT: retq 97 %1 = load <8 x i32>, <8 x i32>* %a, align 1 98 %2 = sext <8 x i32> %1 to <8 x i64> 99 ret <8 x i64> %2 100 } 101 102 define <32 x i16> @test_llvm_x86_avx512_pmovzxbw(<32 x i8>* %a) { 103 ; X32-LABEL: test_llvm_x86_avx512_pmovzxbw: 104 ; X32: ## %bb.0: 105 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 106 ; X32-NEXT: vpmovzxbw {{.*#+}} zmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero,mem[16],zero,mem[17],zero,mem[18],zero,mem[19],zero,mem[20],zero,mem[21],zero,mem[22],zero,mem[23],zero,mem[24],zero,mem[25],zero,mem[26],zero,mem[27],zero,mem[28],zero,mem[29],zero,mem[30],zero,mem[31],zero 107 ; X32-NEXT: retl 108 ; 109 ; X64-LABEL: test_llvm_x86_avx512_pmovzxbw: 110 ; X64: ## %bb.0: 111 ; X64-NEXT: vpmovzxbw {{.*#+}} zmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero,mem[16],zero,mem[17],zero,mem[18],zero,mem[19],zero,mem[20],zero,mem[21],zero,mem[22],zero,mem[23],zero,mem[24],zero,mem[25],zero,mem[26],zero,mem[27],zero,mem[28],zero,mem[29],zero,mem[30],zero,mem[31],zero 112 ; X64-NEXT: retq 113 %1 = load <32 x i8>, <32 x i8>* %a, align 1 114 %2 = zext <32 x i8> %1 to <32 x i16> 115 ret <32 x i16> %2 116 } 117 118 define <16 x i32> @test_llvm_x86_avx512_pmovzxbd(<16 x i8>* %a) { 119 ; X32-LABEL: test_llvm_x86_avx512_pmovzxbd: 120 ; X32: ## %bb.0: 121 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 122 ; X32-NEXT: vpmovzxbd {{.*#+}} zmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero,mem[8],zero,zero,zero,mem[9],zero,zero,zero,mem[10],zero,zero,zero,mem[11],zero,zero,zero,mem[12],zero,zero,zero,mem[13],zero,zero,zero,mem[14],zero,zero,zero,mem[15],zero,zero,zero 123 ; X32-NEXT: retl 124 ; 125 ; X64-LABEL: test_llvm_x86_avx512_pmovzxbd: 126 ; X64: ## %bb.0: 127 ; X64-NEXT: vpmovzxbd {{.*#+}} zmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero,mem[8],zero,zero,zero,mem[9],zero,zero,zero,mem[10],zero,zero,zero,mem[11],zero,zero,zero,mem[12],zero,zero,zero,mem[13],zero,zero,zero,mem[14],zero,zero,zero,mem[15],zero,zero,zero 128 ; X64-NEXT: retq 129 %1 = load <16 x i8>, <16 x i8>* %a, align 1 130 %2 = zext <16 x i8> %1 to <16 x i32> 131 ret <16 x i32> %2 132 } 133 134 define <8 x i64> @test_llvm_x86_avx512_pmovzxbq(<16 x i8>* %a) { 135 ; X32-LABEL: test_llvm_x86_avx512_pmovzxbq: 136 ; X32: ## %bb.0: 137 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 138 ; X32-NEXT: vpmovzxbq {{.*#+}} zmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero,mem[4],zero,zero,zero,zero,zero,zero,zero,mem[5],zero,zero,zero,zero,zero,zero,zero,mem[6],zero,zero,zero,zero,zero,zero,zero,mem[7],zero,zero,zero,zero,zero,zero,zero 139 ; X32-NEXT: retl 140 ; 141 ; X64-LABEL: test_llvm_x86_avx512_pmovzxbq: 142 ; X64: ## %bb.0: 143 ; X64-NEXT: vpmovzxbq {{.*#+}} zmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero,mem[4],zero,zero,zero,zero,zero,zero,zero,mem[5],zero,zero,zero,zero,zero,zero,zero,mem[6],zero,zero,zero,zero,zero,zero,zero,mem[7],zero,zero,zero,zero,zero,zero,zero 144 ; X64-NEXT: retq 145 %1 = load <16 x i8>, <16 x i8>* %a, align 1 146 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 147 %3 = zext <8 x i8> %2 to <8 x i64> 148 ret <8 x i64> %3 149 } 150 151 define <16 x i32> @test_llvm_x86_avx512_pmovzxwd(<16 x i16>* %a) { 152 ; X32-LABEL: test_llvm_x86_avx512_pmovzxwd: 153 ; X32: ## %bb.0: 154 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 155 ; X32-NEXT: vpmovzxwd {{.*#+}} zmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero 156 ; X32-NEXT: retl 157 ; 158 ; X64-LABEL: test_llvm_x86_avx512_pmovzxwd: 159 ; X64: ## %bb.0: 160 ; X64-NEXT: vpmovzxwd {{.*#+}} zmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero 161 ; X64-NEXT: retq 162 %1 = load <16 x i16>, <16 x i16>* %a, align 1 163 %2 = zext <16 x i16> %1 to <16 x i32> 164 ret <16 x i32> %2 165 } 166 167 define <8 x i64> @test_llvm_x86_avx512_pmovzxwq(<8 x i16>* %a) { 168 ; X32-LABEL: test_llvm_x86_avx512_pmovzxwq: 169 ; X32: ## %bb.0: 170 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 171 ; X32-NEXT: vpmovzxwq {{.*#+}} zmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero 172 ; X32-NEXT: retl 173 ; 174 ; X64-LABEL: test_llvm_x86_avx512_pmovzxwq: 175 ; X64: ## %bb.0: 176 ; X64-NEXT: vpmovzxwq {{.*#+}} zmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero 177 ; X64-NEXT: retq 178 %1 = load <8 x i16>, <8 x i16>* %a, align 1 179 %2 = zext <8 x i16> %1 to <8 x i64> 180 ret <8 x i64> %2 181 } 182 183 define <8 x i64> @test_llvm_x86_avx512_pmovzxdq(<8 x i32>* %a) { 184 ; X32-LABEL: test_llvm_x86_avx512_pmovzxdq: 185 ; X32: ## %bb.0: 186 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 187 ; X32-NEXT: vpmovzxdq {{.*#+}} zmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero 188 ; X32-NEXT: retl 189 ; 190 ; X64-LABEL: test_llvm_x86_avx512_pmovzxdq: 191 ; X64: ## %bb.0: 192 ; X64-NEXT: vpmovzxdq {{.*#+}} zmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero 193 ; X64-NEXT: retq 194 %1 = load <8 x i32>, <8 x i32>* %a, align 1 195 %2 = zext <8 x i32> %1 to <8 x i64> 196 ret <8 x i64> %2 197 } 198
