1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -fast-isel -mtriple=i686-unknown -mattr=+avx512cd | FileCheck %s --check-prefixes=CHECK,X86 3 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown -mattr=+avx512cd | FileCheck %s --check-prefixes=CHECK,X64 4 5 define <8 x i64> @test_mm512_broadcastmb_epi64(<8 x i64> %a, <8 x i64> %b) { 6 ; X86-LABEL: test_mm512_broadcastmb_epi64: 7 ; X86: # %bb.0: # %entry 8 ; X86-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 9 ; X86-NEXT: kmovw %k0, %eax 10 ; X86-NEXT: movzbl %al, %eax 11 ; X86-NEXT: vmovd %eax, %xmm0 12 ; X86-NEXT: vpbroadcastq %xmm0, %zmm0 13 ; X86-NEXT: retl 14 ; 15 ; X64-LABEL: test_mm512_broadcastmb_epi64: 16 ; X64: # %bb.0: # %entry 17 ; X64-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 18 ; X64-NEXT: vpbroadcastmb2q %k0, %zmm0 19 ; X64-NEXT: retq 20 entry: 21 %0 = icmp eq <8 x i64> %a, %b 22 %1 = bitcast <8 x i1> %0 to i8 23 %conv.i = zext i8 %1 to i64 24 %vecinit.i.i = insertelement <8 x i64> undef, i64 %conv.i, i32 0 25 %vecinit7.i.i = shufflevector <8 x i64> %vecinit.i.i, <8 x i64> undef, <8 x i32> zeroinitializer 26 ret <8 x i64> %vecinit7.i.i 27 } 28 29 define <8 x i64> @test_mm512_broadcastmw_epi32(<8 x i64> %a, <8 x i64> %b) { 30 ; CHECK-LABEL: test_mm512_broadcastmw_epi32: 31 ; CHECK: # %bb.0: # %entry 32 ; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 33 ; CHECK-NEXT: vpbroadcastmw2d %k0, %zmm0 34 ; CHECK-NEXT: ret{{[l|q]}} 35 entry: 36 %0 = bitcast <8 x i64> %a to <16 x i32> 37 %1 = bitcast <8 x i64> %b to <16 x i32> 38 %2 = icmp eq <16 x i32> %0, %1 39 %3 = bitcast <16 x i1> %2 to i16 40 %conv.i = zext i16 %3 to i32 41 %vecinit.i.i = insertelement <16 x i32> undef, i32 %conv.i, i32 0 42 %vecinit15.i.i = shufflevector <16 x i32> %vecinit.i.i, <16 x i32> undef, <16 x i32> zeroinitializer 43 %4 = bitcast <16 x i32> %vecinit15.i.i to <8 x i64> 44 ret <8 x i64> %4 45 } 46 47 48
