1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s --check-prefixes=CHECK,X86 3 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s --check-prefixes=CHECK,X64 4 5 define <2 x i64> @test_mm_broadcastmb_epi64(<2 x i64> %a, <2 x i64> %b) { 6 ; X86-LABEL: test_mm_broadcastmb_epi64: 7 ; X86: # %bb.0: # %entry 8 ; X86-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 9 ; X86-NEXT: kmovw %k0, %eax 10 ; X86-NEXT: movzbl %al, %eax 11 ; X86-NEXT: vmovd %eax, %xmm0 12 ; X86-NEXT: vpbroadcastq %xmm0, %xmm0 13 ; X86-NEXT: retl 14 ; 15 ; X64-LABEL: test_mm_broadcastmb_epi64: 16 ; X64: # %bb.0: # %entry 17 ; X64-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 18 ; X64-NEXT: vpbroadcastmb2q %k0, %xmm0 19 ; X64-NEXT: retq 20 entry: 21 %0 = bitcast <2 x i64> %a to <4 x i32> 22 %1 = bitcast <2 x i64> %b to <4 x i32> 23 %2 = icmp eq <4 x i32> %0, %1 24 %3 = shufflevector <4 x i1> %2, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 25 %4 = bitcast <8 x i1> %3 to i8 26 %conv.i = zext i8 %4 to i64 27 %vecinit.i.i = insertelement <2 x i64> undef, i64 %conv.i, i32 0 28 %vecinit1.i.i = shufflevector <2 x i64> %vecinit.i.i, <2 x i64> undef, <2 x i32> zeroinitializer 29 ret <2 x i64> %vecinit1.i.i 30 } 31 32 define <4 x i64> @test_mm256_broadcastmb_epi64(<4 x i64> %a, <4 x i64> %b) { 33 ; X86-LABEL: test_mm256_broadcastmb_epi64: 34 ; X86: # %bb.0: # %entry 35 ; X86-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 36 ; X86-NEXT: kmovw %k0, %eax 37 ; X86-NEXT: movzbl %al, %eax 38 ; X86-NEXT: vmovd %eax, %xmm0 39 ; X86-NEXT: vpbroadcastq %xmm0, %ymm0 40 ; X86-NEXT: retl 41 ; 42 ; X64-LABEL: test_mm256_broadcastmb_epi64: 43 ; X64: # %bb.0: # %entry 44 ; X64-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 45 ; X64-NEXT: vpbroadcastmb2q %k0, %ymm0 46 ; X64-NEXT: retq 47 entry: 48 %0 = icmp eq <4 x i64> %a, %b 49 %1 = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 50 %2 = bitcast <8 x i1> %1 to i8 51 %conv.i = zext i8 %2 to i64 52 %vecinit.i.i = insertelement <4 x i64> undef, i64 %conv.i, i32 0 53 %vecinit3.i.i = shufflevector <4 x i64> %vecinit.i.i, <4 x i64> undef, <4 x i32> zeroinitializer 54 ret <4 x i64> %vecinit3.i.i 55 } 56 57 define <2 x i64> @test_mm_broadcastmw_epi32(<8 x i64> %a, <8 x i64> %b) { 58 ; CHECK-LABEL: test_mm_broadcastmw_epi32: 59 ; CHECK: # %bb.0: # %entry 60 ; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 61 ; CHECK-NEXT: vpbroadcastmw2d %k0, %xmm0 62 ; CHECK-NEXT: vzeroupper 63 ; CHECK-NEXT: ret{{[l|q]}} 64 entry: 65 %0 = bitcast <8 x i64> %a to <16 x i32> 66 %1 = bitcast <8 x i64> %b to <16 x i32> 67 %2 = icmp eq <16 x i32> %0, %1 68 %3 = bitcast <16 x i1> %2 to i16 69 %conv.i = zext i16 %3 to i32 70 %vecinit.i.i = insertelement <4 x i32> undef, i32 %conv.i, i32 0 71 %vecinit3.i.i = shufflevector <4 x i32> %vecinit.i.i, <4 x i32> undef, <4 x i32> zeroinitializer 72 %4 = bitcast <4 x i32> %vecinit3.i.i to <2 x i64> 73 ret <2 x i64> %4 74 } 75 76 define <4 x i64> @test_mm256_broadcastmw_epi32(<8 x i64> %a, <8 x i64> %b) { 77 ; CHECK-LABEL: test_mm256_broadcastmw_epi32: 78 ; CHECK: # %bb.0: # %entry 79 ; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 80 ; CHECK-NEXT: vpbroadcastmw2d %k0, %ymm0 81 ; CHECK-NEXT: ret{{[l|q]}} 82 entry: 83 %0 = bitcast <8 x i64> %a to <16 x i32> 84 %1 = bitcast <8 x i64> %b to <16 x i32> 85 %2 = icmp eq <16 x i32> %0, %1 86 %3 = bitcast <16 x i1> %2 to i16 87 %conv.i = zext i16 %3 to i32 88 %vecinit.i.i = insertelement <8 x i32> undef, i32 %conv.i, i32 0 89 %vecinit7.i.i = shufflevector <8 x i32> %vecinit.i.i, <8 x i32> undef, <8 x i32> zeroinitializer 90 %4 = bitcast <8 x i32> %vecinit7.i.i to <4 x i64> 91 ret <4 x i64> %4 92 } 93 94 95
