1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86 3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64 4 5 define i32 @t0(i64 %x) nounwind { 6 ; X86-LABEL: t0: 7 ; X86: # %bb.0: # %entry 8 ; X86-NEXT: pshufw $238, {{[0-9]+}}(%esp), %mm0 # mm0 = mem[2,3,2,3] 9 ; X86-NEXT: movd %mm0, %eax 10 ; X86-NEXT: retl 11 ; 12 ; X64-LABEL: t0: 13 ; X64: # %bb.0: # %entry 14 ; X64-NEXT: movq %rdi, %mm0 15 ; X64-NEXT: pshufw $238, %mm0, %mm0 # mm0 = mm0[2,3,2,3] 16 ; X64-NEXT: movd %mm0, %eax 17 ; X64-NEXT: retq 18 entry: 19 %0 = bitcast i64 %x to <4 x i16> 20 %1 = bitcast <4 x i16> %0 to x86_mmx 21 %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -18) 22 %3 = bitcast x86_mmx %2 to <4 x i16> 23 %4 = bitcast <4 x i16> %3 to <1 x i64> 24 %5 = extractelement <1 x i64> %4, i32 0 25 %6 = bitcast i64 %5 to <2 x i32> 26 %7 = extractelement <2 x i32> %6, i32 0 27 ret i32 %7 28 } 29 30 define i64 @t1(i64 %x, i32 %n) nounwind { 31 ; X86-LABEL: t1: 32 ; X86: # %bb.0: # %entry 33 ; X86-NEXT: pushl %ebp 34 ; X86-NEXT: movl %esp, %ebp 35 ; X86-NEXT: andl $-8, %esp 36 ; X86-NEXT: subl $8, %esp 37 ; X86-NEXT: movd 16(%ebp), %mm0 38 ; X86-NEXT: movq 8(%ebp), %mm1 39 ; X86-NEXT: psllq %mm0, %mm1 40 ; X86-NEXT: movq %mm1, (%esp) 41 ; X86-NEXT: movl (%esp), %eax 42 ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx 43 ; X86-NEXT: movl %ebp, %esp 44 ; X86-NEXT: popl %ebp 45 ; X86-NEXT: retl 46 ; 47 ; X64-LABEL: t1: 48 ; X64: # %bb.0: # %entry 49 ; X64-NEXT: movd %esi, %mm0 50 ; X64-NEXT: movq %rdi, %mm1 51 ; X64-NEXT: psllq %mm0, %mm1 52 ; X64-NEXT: movq %mm1, %rax 53 ; X64-NEXT: retq 54 entry: 55 %0 = bitcast i64 %x to x86_mmx 56 %1 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %0, i32 %n) 57 %2 = bitcast x86_mmx %1 to i64 58 ret i64 %2 59 } 60 61 define i64 @t2(i64 %x, i32 %n, i32 %w) nounwind { 62 ; X86-LABEL: t2: 63 ; X86: # %bb.0: # %entry 64 ; X86-NEXT: pushl %ebp 65 ; X86-NEXT: movl %esp, %ebp 66 ; X86-NEXT: andl $-8, %esp 67 ; X86-NEXT: subl $8, %esp 68 ; X86-NEXT: movd 16(%ebp), %mm0 69 ; X86-NEXT: movd 20(%ebp), %mm1 70 ; X86-NEXT: psllq %mm0, %mm1 71 ; X86-NEXT: por 8(%ebp), %mm1 72 ; X86-NEXT: movq %mm1, (%esp) 73 ; X86-NEXT: movl (%esp), %eax 74 ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx 75 ; X86-NEXT: movl %ebp, %esp 76 ; X86-NEXT: popl %ebp 77 ; X86-NEXT: retl 78 ; 79 ; X64-LABEL: t2: 80 ; X64: # %bb.0: # %entry 81 ; X64-NEXT: movd %esi, %mm0 82 ; X64-NEXT: movd %edx, %mm1 83 ; X64-NEXT: psllq %mm0, %mm1 84 ; X64-NEXT: movq %rdi, %mm0 85 ; X64-NEXT: por %mm1, %mm0 86 ; X64-NEXT: movq %mm0, %rax 87 ; X64-NEXT: retq 88 entry: 89 %0 = insertelement <2 x i32> undef, i32 %w, i32 0 90 %1 = insertelement <2 x i32> %0, i32 0, i32 1 91 %2 = bitcast <2 x i32> %1 to x86_mmx 92 %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %2, i32 %n) 93 %4 = bitcast i64 %x to x86_mmx 94 %5 = tail call x86_mmx @llvm.x86.mmx.por(x86_mmx %4, x86_mmx %3) 95 %6 = bitcast x86_mmx %5 to i64 96 ret i64 %6 97 } 98 99 define i64 @t3(<1 x i64>* %y, i32* %n) nounwind { 100 ; X86-LABEL: t3: 101 ; X86: # %bb.0: # %entry 102 ; X86-NEXT: pushl %ebp 103 ; X86-NEXT: movl %esp, %ebp 104 ; X86-NEXT: andl $-8, %esp 105 ; X86-NEXT: subl $8, %esp 106 ; X86-NEXT: movl 12(%ebp), %eax 107 ; X86-NEXT: movl 8(%ebp), %ecx 108 ; X86-NEXT: movq (%ecx), %mm0 109 ; X86-NEXT: movd (%eax), %mm1 110 ; X86-NEXT: psllq %mm1, %mm0 111 ; X86-NEXT: movq %mm0, (%esp) 112 ; X86-NEXT: movl (%esp), %eax 113 ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx 114 ; X86-NEXT: movl %ebp, %esp 115 ; X86-NEXT: popl %ebp 116 ; X86-NEXT: retl 117 ; 118 ; X64-LABEL: t3: 119 ; X64: # %bb.0: # %entry 120 ; X64-NEXT: movq (%rdi), %mm0 121 ; X64-NEXT: movd (%rsi), %mm1 122 ; X64-NEXT: psllq %mm1, %mm0 123 ; X64-NEXT: movq %mm0, %rax 124 ; X64-NEXT: retq 125 entry: 126 %0 = bitcast <1 x i64>* %y to x86_mmx* 127 %1 = load x86_mmx, x86_mmx* %0, align 8 128 %2 = load i32, i32* %n, align 4 129 %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2) 130 %4 = bitcast x86_mmx %3 to i64 131 ret i64 %4 132 } 133 134 declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8) 135 declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) 136 declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx) 137 138
