1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX 4 5 ; fold sextinreg(zext) -> sext 6 define <4 x i64> @sextinreg_zext_v16i8_4i64(<16 x i8> %a0) { 7 ; SSE-LABEL: sextinreg_zext_v16i8_4i64: 8 ; SSE: # %bb.0: 9 ; SSE-NEXT: pmovsxbq %xmm0, %xmm2 10 ; SSE-NEXT: psrld $16, %xmm0 11 ; SSE-NEXT: pmovsxbq %xmm0, %xmm1 12 ; SSE-NEXT: movdqa %xmm2, %xmm0 13 ; SSE-NEXT: retq 14 ; 15 ; AVX-LABEL: sextinreg_zext_v16i8_4i64: 16 ; AVX: # %bb.0: 17 ; AVX-NEXT: vpmovsxbq %xmm0, %ymm0 18 ; AVX-NEXT: retq 19 %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 20 %2 = zext <4 x i8> %1 to <4 x i64> 21 %3 = shl <4 x i64> %2, <i64 56, i64 56, i64 56, i64 56> 22 %4 = ashr <4 x i64> %3, <i64 56, i64 56, i64 56, i64 56> 23 ret <4 x i64> %4 24 } 25 26 ; fold sextinreg(zext(sext)) -> sext 27 define <4 x i64> @sextinreg_zext_sext_v16i8_4i64(<16 x i8> %a0) { 28 ; SSE-LABEL: sextinreg_zext_sext_v16i8_4i64: 29 ; SSE: # %bb.0: 30 ; SSE-NEXT: pmovsxbq %xmm0, %xmm2 31 ; SSE-NEXT: psrld $16, %xmm0 32 ; SSE-NEXT: pmovsxbq %xmm0, %xmm1 33 ; SSE-NEXT: movdqa %xmm2, %xmm0 34 ; SSE-NEXT: retq 35 ; 36 ; AVX-LABEL: sextinreg_zext_sext_v16i8_4i64: 37 ; AVX: # %bb.0: 38 ; AVX-NEXT: vpmovsxbq %xmm0, %ymm0 39 ; AVX-NEXT: retq 40 %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 41 %2 = sext <4 x i8> %1 to <4 x i32> 42 %3 = zext <4 x i32> %2 to <4 x i64> 43 %4 = shl <4 x i64> %3, <i64 32, i64 32, i64 32, i64 32> 44 %5 = ashr <4 x i64> %4, <i64 32, i64 32, i64 32, i64 32> 45 ret <4 x i64> %5 46 } 47
