1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx,+f16c -show-mc-encoding -disable-peephole | FileCheck %s --check-prefix=X32 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c -show-mc-encoding -disable-peephole | FileCheck %s --check-prefix=X64 4 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vl -show-mc-encoding -disable-peephole | FileCheck %s --check-prefix=X32-AVX512VL 5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl -show-mc-encoding -disable-peephole | FileCheck %s --check-prefix=X64-AVX512VL 6 7 define <4 x float> @test_x86_vcvtph2ps_128(<8 x i16> %a0) { 8 ; X32-LABEL: test_x86_vcvtph2ps_128: 9 ; X32: # %bb.0: 10 ; X32-NEXT: vcvtph2ps %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x13,0xc0] 11 ; X32-NEXT: retl # encoding: [0xc3] 12 ; 13 ; X64-LABEL: test_x86_vcvtph2ps_128: 14 ; X64: # %bb.0: 15 ; X64-NEXT: vcvtph2ps %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x13,0xc0] 16 ; X64-NEXT: retq # encoding: [0xc3] 17 ; 18 ; X32-AVX512VL-LABEL: test_x86_vcvtph2ps_128: 19 ; X32-AVX512VL: # %bb.0: 20 ; X32-AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0xc0] 21 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 22 ; 23 ; X64-AVX512VL-LABEL: test_x86_vcvtph2ps_128: 24 ; X64-AVX512VL: # %bb.0: 25 ; X64-AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0xc0] 26 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 27 %res = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %a0) ; <<4 x float>> [#uses=1] 28 ret <4 x float> %res 29 } 30 declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) nounwind readonly 31 32 define <4 x float> @test_x86_vcvtph2ps_128_m(<8 x i16>* nocapture %a) { 33 ; X32-LABEL: test_x86_vcvtph2ps_128_m: 34 ; X32: # %bb.0: 35 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 36 ; X32-NEXT: vcvtph2ps (%eax), %xmm0 # encoding: [0xc4,0xe2,0x79,0x13,0x00] 37 ; X32-NEXT: retl # encoding: [0xc3] 38 ; 39 ; X64-LABEL: test_x86_vcvtph2ps_128_m: 40 ; X64: # %bb.0: 41 ; X64-NEXT: vcvtph2ps (%rdi), %xmm0 # encoding: [0xc4,0xe2,0x79,0x13,0x07] 42 ; X64-NEXT: retq # encoding: [0xc3] 43 ; 44 ; X32-AVX512VL-LABEL: test_x86_vcvtph2ps_128_m: 45 ; X32-AVX512VL: # %bb.0: 46 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 47 ; X32-AVX512VL-NEXT: vcvtph2ps (%eax), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x00] 48 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 49 ; 50 ; X64-AVX512VL-LABEL: test_x86_vcvtph2ps_128_m: 51 ; X64-AVX512VL: # %bb.0: 52 ; X64-AVX512VL-NEXT: vcvtph2ps (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x07] 53 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 54 %load = load <8 x i16>, <8 x i16>* %a 55 %res = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %load) ; <<4 x float>> [#uses=1] 56 ret <4 x float> %res 57 } 58 59 define <8 x float> @test_x86_vcvtph2ps_256(<8 x i16> %a0) { 60 ; X32-LABEL: test_x86_vcvtph2ps_256: 61 ; X32: # %bb.0: 62 ; X32-NEXT: vcvtph2ps %xmm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x13,0xc0] 63 ; X32-NEXT: retl # encoding: [0xc3] 64 ; 65 ; X64-LABEL: test_x86_vcvtph2ps_256: 66 ; X64: # %bb.0: 67 ; X64-NEXT: vcvtph2ps %xmm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x13,0xc0] 68 ; X64-NEXT: retq # encoding: [0xc3] 69 ; 70 ; X32-AVX512VL-LABEL: test_x86_vcvtph2ps_256: 71 ; X32-AVX512VL: # %bb.0: 72 ; X32-AVX512VL-NEXT: vcvtph2ps %xmm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x13,0xc0] 73 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 74 ; 75 ; X64-AVX512VL-LABEL: test_x86_vcvtph2ps_256: 76 ; X64-AVX512VL: # %bb.0: 77 ; X64-AVX512VL-NEXT: vcvtph2ps %xmm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x13,0xc0] 78 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 79 %res = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %a0) ; <<8 x float>> [#uses=1] 80 ret <8 x float> %res 81 } 82 declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readonly 83 84 define <8 x float> @test_x86_vcvtph2ps_256_m(<8 x i16>* nocapture %a) nounwind { 85 ; X32-LABEL: test_x86_vcvtph2ps_256_m: 86 ; X32: # %bb.0: 87 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 88 ; X32-NEXT: vcvtph2ps (%eax), %ymm0 # encoding: [0xc4,0xe2,0x7d,0x13,0x00] 89 ; X32-NEXT: retl # encoding: [0xc3] 90 ; 91 ; X64-LABEL: test_x86_vcvtph2ps_256_m: 92 ; X64: # %bb.0: 93 ; X64-NEXT: vcvtph2ps (%rdi), %ymm0 # encoding: [0xc4,0xe2,0x7d,0x13,0x07] 94 ; X64-NEXT: retq # encoding: [0xc3] 95 ; 96 ; X32-AVX512VL-LABEL: test_x86_vcvtph2ps_256_m: 97 ; X32-AVX512VL: # %bb.0: 98 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 99 ; X32-AVX512VL-NEXT: vcvtph2ps (%eax), %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x13,0x00] 100 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 101 ; 102 ; X64-AVX512VL-LABEL: test_x86_vcvtph2ps_256_m: 103 ; X64-AVX512VL: # %bb.0: 104 ; X64-AVX512VL-NEXT: vcvtph2ps (%rdi), %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x13,0x07] 105 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 106 %load = load <8 x i16>, <8 x i16>* %a 107 %res = tail call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %load) 108 ret <8 x float> %res 109 } 110 111 define <8 x i16> @test_x86_vcvtps2ph_128(<4 x float> %a0) { 112 ; X32-LABEL: test_x86_vcvtps2ph_128: 113 ; X32: # %bb.0: 114 ; X32-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x1d,0xc0,0x00] 115 ; X32-NEXT: retl # encoding: [0xc3] 116 ; 117 ; X64-LABEL: test_x86_vcvtps2ph_128: 118 ; X64: # %bb.0: 119 ; X64-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x1d,0xc0,0x00] 120 ; X64-NEXT: retq # encoding: [0xc3] 121 ; 122 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_128: 123 ; X32-AVX512VL: # %bb.0: 124 ; X32-AVX512VL-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0xc0,0x00] 125 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 126 ; 127 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_128: 128 ; X64-AVX512VL: # %bb.0: 129 ; X64-AVX512VL-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0xc0,0x00] 130 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 131 %res = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1] 132 ret <8 x i16> %res 133 } 134 declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32) nounwind readonly 135 136 define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0) { 137 ; X32-LABEL: test_x86_vcvtps2ph_256: 138 ; X32: # %bb.0: 139 ; X32-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # encoding: [0xc4,0xe3,0x7d,0x1d,0xc0,0x00] 140 ; X32-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 141 ; X32-NEXT: retl # encoding: [0xc3] 142 ; 143 ; X64-LABEL: test_x86_vcvtps2ph_256: 144 ; X64: # %bb.0: 145 ; X64-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # encoding: [0xc4,0xe3,0x7d,0x1d,0xc0,0x00] 146 ; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 147 ; X64-NEXT: retq # encoding: [0xc3] 148 ; 149 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_256: 150 ; X32-AVX512VL: # %bb.0: 151 ; X32-AVX512VL-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x1d,0xc0,0x00] 152 ; X32-AVX512VL-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 153 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 154 ; 155 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_256: 156 ; X64-AVX512VL: # %bb.0: 157 ; X64-AVX512VL-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x1d,0xc0,0x00] 158 ; X64-AVX512VL-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 159 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 160 %res = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1] 161 ret <8 x i16> %res 162 } 163 declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly 164 165 define <4 x float> @test_x86_vcvtps2ph_128_scalar(i64* %ptr) { 166 ; X32-LABEL: test_x86_vcvtps2ph_128_scalar: 167 ; X32: # %bb.0: 168 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 169 ; X32-NEXT: vcvtph2ps (%eax), %xmm0 # encoding: [0xc4,0xe2,0x79,0x13,0x00] 170 ; X32-NEXT: retl # encoding: [0xc3] 171 ; 172 ; X64-LABEL: test_x86_vcvtps2ph_128_scalar: 173 ; X64: # %bb.0: 174 ; X64-NEXT: vcvtph2ps (%rdi), %xmm0 # encoding: [0xc4,0xe2,0x79,0x13,0x07] 175 ; X64-NEXT: retq # encoding: [0xc3] 176 ; 177 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_128_scalar: 178 ; X32-AVX512VL: # %bb.0: 179 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 180 ; X32-AVX512VL-NEXT: vcvtph2ps (%eax), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x00] 181 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 182 ; 183 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_128_scalar: 184 ; X64-AVX512VL: # %bb.0: 185 ; X64-AVX512VL-NEXT: vcvtph2ps (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x07] 186 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 187 %load = load i64, i64* %ptr 188 %ins1 = insertelement <2 x i64> undef, i64 %load, i32 0 189 %ins2 = insertelement <2 x i64> %ins1, i64 0, i32 1 190 %bc = bitcast <2 x i64> %ins2 to <8 x i16> 191 %res = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %bc) #2 192 ret <4 x float> %res 193 } 194 195 define <4 x float> @test_x86_vcvtps2ph_128_scalar2(i64* %ptr) { 196 ; X32-LABEL: test_x86_vcvtps2ph_128_scalar2: 197 ; X32: # %bb.0: 198 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 199 ; X32-NEXT: vcvtph2ps (%eax), %xmm0 # encoding: [0xc4,0xe2,0x79,0x13,0x00] 200 ; X32-NEXT: retl # encoding: [0xc3] 201 ; 202 ; X64-LABEL: test_x86_vcvtps2ph_128_scalar2: 203 ; X64: # %bb.0: 204 ; X64-NEXT: vcvtph2ps (%rdi), %xmm0 # encoding: [0xc4,0xe2,0x79,0x13,0x07] 205 ; X64-NEXT: retq # encoding: [0xc3] 206 ; 207 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_128_scalar2: 208 ; X32-AVX512VL: # %bb.0: 209 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 210 ; X32-AVX512VL-NEXT: vcvtph2ps (%eax), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x00] 211 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 212 ; 213 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_128_scalar2: 214 ; X64-AVX512VL: # %bb.0: 215 ; X64-AVX512VL-NEXT: vcvtph2ps (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x07] 216 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 217 %load = load i64, i64* %ptr 218 %ins = insertelement <2 x i64> undef, i64 %load, i32 0 219 %bc = bitcast <2 x i64> %ins to <8 x i16> 220 %res = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %bc) 221 ret <4 x float> %res 222 } 223 224 define void @test_x86_vcvtps2ph_256_m(<8 x i16>* nocapture %d, <8 x float> %a) nounwind { 225 ; X32-LABEL: test_x86_vcvtps2ph_256_m: 226 ; X32: # %bb.0: # %entry 227 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 228 ; X32-NEXT: vcvtps2ph $3, %ymm0, (%eax) # encoding: [0xc4,0xe3,0x7d,0x1d,0x00,0x03] 229 ; X32-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 230 ; X32-NEXT: retl # encoding: [0xc3] 231 ; 232 ; X64-LABEL: test_x86_vcvtps2ph_256_m: 233 ; X64: # %bb.0: # %entry 234 ; X64-NEXT: vcvtps2ph $3, %ymm0, (%rdi) # encoding: [0xc4,0xe3,0x7d,0x1d,0x07,0x03] 235 ; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 236 ; X64-NEXT: retq # encoding: [0xc3] 237 ; 238 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_256_m: 239 ; X32-AVX512VL: # %bb.0: # %entry 240 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 241 ; X32-AVX512VL-NEXT: vcvtps2ph $3, %ymm0, (%eax) # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x1d,0x00,0x03] 242 ; X32-AVX512VL-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 243 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 244 ; 245 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_256_m: 246 ; X64-AVX512VL: # %bb.0: # %entry 247 ; X64-AVX512VL-NEXT: vcvtps2ph $3, %ymm0, (%rdi) # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x1d,0x07,0x03] 248 ; X64-AVX512VL-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 249 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 250 entry: 251 %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a, i32 3) 252 store <8 x i16> %0, <8 x i16>* %d, align 16 253 ret void 254 } 255 256 define void @test_x86_vcvtps2ph_128_m(<4 x i16>* nocapture %d, <4 x float> %a) nounwind { 257 ; X32-LABEL: test_x86_vcvtps2ph_128_m: 258 ; X32: # %bb.0: # %entry 259 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 260 ; X32-NEXT: vcvtps2ph $3, %xmm0, (%eax) # encoding: [0xc4,0xe3,0x79,0x1d,0x00,0x03] 261 ; X32-NEXT: retl # encoding: [0xc3] 262 ; 263 ; X64-LABEL: test_x86_vcvtps2ph_128_m: 264 ; X64: # %bb.0: # %entry 265 ; X64-NEXT: vcvtps2ph $3, %xmm0, (%rdi) # encoding: [0xc4,0xe3,0x79,0x1d,0x07,0x03] 266 ; X64-NEXT: retq # encoding: [0xc3] 267 ; 268 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_128_m: 269 ; X32-AVX512VL: # %bb.0: # %entry 270 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 271 ; X32-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0xc0,0x03] 272 ; X32-AVX512VL-NEXT: vpmovzxwd %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x33,0xc0] 273 ; X32-AVX512VL-NEXT: # xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 274 ; X32-AVX512VL-NEXT: vpmovdw %xmm0, (%eax) # encoding: [0x62,0xf2,0x7e,0x08,0x33,0x00] 275 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 276 ; 277 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_128_m: 278 ; X64-AVX512VL: # %bb.0: # %entry 279 ; X64-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0xc0,0x03] 280 ; X64-AVX512VL-NEXT: vpmovzxwd %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x33,0xc0] 281 ; X64-AVX512VL-NEXT: # xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 282 ; X64-AVX512VL-NEXT: vpmovdw %xmm0, (%rdi) # encoding: [0x62,0xf2,0x7e,0x08,0x33,0x07] 283 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 284 entry: 285 %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a, i32 3) 286 %1 = shufflevector <8 x i16> %0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 287 store <4 x i16> %1, <4 x i16>* %d, align 8 288 ret void 289 } 290 291 define void @test_x86_vcvtps2ph_128_m2(double* nocapture %hf4x16, <4 x float> %f4x32) #0 { 292 ; X32-LABEL: test_x86_vcvtps2ph_128_m2: 293 ; X32: # %bb.0: # %entry 294 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 295 ; X32-NEXT: vcvtps2ph $3, %xmm0, (%eax) # encoding: [0xc4,0xe3,0x79,0x1d,0x00,0x03] 296 ; X32-NEXT: retl # encoding: [0xc3] 297 ; 298 ; X64-LABEL: test_x86_vcvtps2ph_128_m2: 299 ; X64: # %bb.0: # %entry 300 ; X64-NEXT: vcvtps2ph $3, %xmm0, (%rdi) # encoding: [0xc4,0xe3,0x79,0x1d,0x07,0x03] 301 ; X64-NEXT: retq # encoding: [0xc3] 302 ; 303 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_128_m2: 304 ; X32-AVX512VL: # %bb.0: # %entry 305 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 306 ; X32-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, (%eax) # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0x00,0x03] 307 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 308 ; 309 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_128_m2: 310 ; X64-AVX512VL: # %bb.0: # %entry 311 ; X64-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, (%rdi) # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0x07,0x03] 312 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 313 entry: 314 %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4x32, i32 3) 315 %1 = bitcast <8 x i16> %0 to <2 x double> 316 %vecext = extractelement <2 x double> %1, i32 0 317 store double %vecext, double* %hf4x16, align 8 318 ret void 319 } 320 321 define void @test_x86_vcvtps2ph_128_m3(i64* nocapture %hf4x16, <4 x float> %f4x32) #0 { 322 ; X32-LABEL: test_x86_vcvtps2ph_128_m3: 323 ; X32: # %bb.0: # %entry 324 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 325 ; X32-NEXT: vcvtps2ph $3, %xmm0, (%eax) # encoding: [0xc4,0xe3,0x79,0x1d,0x00,0x03] 326 ; X32-NEXT: retl # encoding: [0xc3] 327 ; 328 ; X64-LABEL: test_x86_vcvtps2ph_128_m3: 329 ; X64: # %bb.0: # %entry 330 ; X64-NEXT: vcvtps2ph $3, %xmm0, (%rdi) # encoding: [0xc4,0xe3,0x79,0x1d,0x07,0x03] 331 ; X64-NEXT: retq # encoding: [0xc3] 332 ; 333 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_128_m3: 334 ; X32-AVX512VL: # %bb.0: # %entry 335 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] 336 ; X32-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, (%eax) # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0x00,0x03] 337 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3] 338 ; 339 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_128_m3: 340 ; X64-AVX512VL: # %bb.0: # %entry 341 ; X64-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, (%rdi) # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0x07,0x03] 342 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] 343 entry: 344 %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4x32, i32 3) 345 %1 = bitcast <8 x i16> %0 to <2 x i64> 346 %vecext = extractelement <2 x i64> %1, i32 0 347 store i64 %vecext, i64* %hf4x16, align 8 348 ret void 349 } 350
