1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE 3 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE 4 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX 5 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX 6 7 8 define float @select_fcmp_one_f32(float %a, float %b, float %c, float %d) { 9 ; SSE-LABEL: select_fcmp_one_f32: 10 ; SSE: ## %bb.0: 11 ; SSE-NEXT: ucomiss %xmm1, %xmm0 12 ; SSE-NEXT: jne LBB0_2 13 ; SSE-NEXT: ## %bb.1: 14 ; SSE-NEXT: movaps %xmm3, %xmm2 15 ; SSE-NEXT: LBB0_2: 16 ; SSE-NEXT: movaps %xmm2, %xmm0 17 ; SSE-NEXT: retq 18 ; 19 ; AVX-LABEL: select_fcmp_one_f32: 20 ; AVX: ## %bb.0: 21 ; AVX-NEXT: vcmpneq_oqss %xmm1, %xmm0, %xmm0 22 ; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 23 ; AVX-NEXT: retq 24 %1 = fcmp one float %a, %b 25 %2 = select i1 %1, float %c, float %d 26 ret float %2 27 } 28 29 define double @select_fcmp_one_f64(double %a, double %b, double %c, double %d) { 30 ; SSE-LABEL: select_fcmp_one_f64: 31 ; SSE: ## %bb.0: 32 ; SSE-NEXT: ucomisd %xmm1, %xmm0 33 ; SSE-NEXT: jne LBB1_2 34 ; SSE-NEXT: ## %bb.1: 35 ; SSE-NEXT: movaps %xmm3, %xmm2 36 ; SSE-NEXT: LBB1_2: 37 ; SSE-NEXT: movaps %xmm2, %xmm0 38 ; SSE-NEXT: retq 39 ; 40 ; AVX-LABEL: select_fcmp_one_f64: 41 ; AVX: ## %bb.0: 42 ; AVX-NEXT: vcmpneq_oqsd %xmm1, %xmm0, %xmm0 43 ; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0 44 ; AVX-NEXT: retq 45 %1 = fcmp one double %a, %b 46 %2 = select i1 %1, double %c, double %d 47 ret double %2 48 } 49 50 define float @select_icmp_eq_f32(i64 %a, i64 %b, float %c, float %d) { 51 ; SSE-LABEL: select_icmp_eq_f32: 52 ; SSE: ## %bb.0: 53 ; SSE-NEXT: cmpq %rsi, %rdi 54 ; SSE-NEXT: je LBB2_2 55 ; SSE-NEXT: ## %bb.1: 56 ; SSE-NEXT: movaps %xmm1, %xmm0 57 ; SSE-NEXT: LBB2_2: 58 ; SSE-NEXT: retq 59 ; 60 ; AVX-LABEL: select_icmp_eq_f32: 61 ; AVX: ## %bb.0: 62 ; AVX-NEXT: cmpq %rsi, %rdi 63 ; AVX-NEXT: je LBB2_2 64 ; AVX-NEXT: ## %bb.1: 65 ; AVX-NEXT: vmovaps %xmm1, %xmm0 66 ; AVX-NEXT: LBB2_2: 67 ; AVX-NEXT: retq 68 %1 = icmp eq i64 %a, %b 69 %2 = select i1 %1, float %c, float %d 70 ret float %2 71 } 72 73 define float @select_icmp_ne_f32(i64 %a, i64 %b, float %c, float %d) { 74 ; SSE-LABEL: select_icmp_ne_f32: 75 ; SSE: ## %bb.0: 76 ; SSE-NEXT: cmpq %rsi, %rdi 77 ; SSE-NEXT: jne LBB3_2 78 ; SSE-NEXT: ## %bb.1: 79 ; SSE-NEXT: movaps %xmm1, %xmm0 80 ; SSE-NEXT: LBB3_2: 81 ; SSE-NEXT: retq 82 ; 83 ; AVX-LABEL: select_icmp_ne_f32: 84 ; AVX: ## %bb.0: 85 ; AVX-NEXT: cmpq %rsi, %rdi 86 ; AVX-NEXT: jne LBB3_2 87 ; AVX-NEXT: ## %bb.1: 88 ; AVX-NEXT: vmovaps %xmm1, %xmm0 89 ; AVX-NEXT: LBB3_2: 90 ; AVX-NEXT: retq 91 %1 = icmp ne i64 %a, %b 92 %2 = select i1 %1, float %c, float %d 93 ret float %2 94 } 95 96 define float @select_icmp_ugt_f32(i64 %a, i64 %b, float %c, float %d) { 97 ; SSE-LABEL: select_icmp_ugt_f32: 98 ; SSE: ## %bb.0: 99 ; SSE-NEXT: cmpq %rsi, %rdi 100 ; SSE-NEXT: ja LBB4_2 101 ; SSE-NEXT: ## %bb.1: 102 ; SSE-NEXT: movaps %xmm1, %xmm0 103 ; SSE-NEXT: LBB4_2: 104 ; SSE-NEXT: retq 105 ; 106 ; AVX-LABEL: select_icmp_ugt_f32: 107 ; AVX: ## %bb.0: 108 ; AVX-NEXT: cmpq %rsi, %rdi 109 ; AVX-NEXT: ja LBB4_2 110 ; AVX-NEXT: ## %bb.1: 111 ; AVX-NEXT: vmovaps %xmm1, %xmm0 112 ; AVX-NEXT: LBB4_2: 113 ; AVX-NEXT: retq 114 %1 = icmp ugt i64 %a, %b 115 %2 = select i1 %1, float %c, float %d 116 ret float %2 117 } 118 119 define float @select_icmp_uge_f32(i64 %a, i64 %b, float %c, float %d) { 120 ; SSE-LABEL: select_icmp_uge_f32: 121 ; SSE: ## %bb.0: 122 ; SSE-NEXT: cmpq %rsi, %rdi 123 ; SSE-NEXT: jae LBB5_2 124 ; SSE-NEXT: ## %bb.1: 125 ; SSE-NEXT: movaps %xmm1, %xmm0 126 ; SSE-NEXT: LBB5_2: 127 ; SSE-NEXT: retq 128 ; 129 ; AVX-LABEL: select_icmp_uge_f32: 130 ; AVX: ## %bb.0: 131 ; AVX-NEXT: cmpq %rsi, %rdi 132 ; AVX-NEXT: jae LBB5_2 133 ; AVX-NEXT: ## %bb.1: 134 ; AVX-NEXT: vmovaps %xmm1, %xmm0 135 ; AVX-NEXT: LBB5_2: 136 ; AVX-NEXT: retq 137 %1 = icmp uge i64 %a, %b 138 %2 = select i1 %1, float %c, float %d 139 ret float %2 140 } 141 142 define float @select_icmp_ult_f32(i64 %a, i64 %b, float %c, float %d) { 143 ; SSE-LABEL: select_icmp_ult_f32: 144 ; SSE: ## %bb.0: 145 ; SSE-NEXT: cmpq %rsi, %rdi 146 ; SSE-NEXT: jb LBB6_2 147 ; SSE-NEXT: ## %bb.1: 148 ; SSE-NEXT: movaps %xmm1, %xmm0 149 ; SSE-NEXT: LBB6_2: 150 ; SSE-NEXT: retq 151 ; 152 ; AVX-LABEL: select_icmp_ult_f32: 153 ; AVX: ## %bb.0: 154 ; AVX-NEXT: cmpq %rsi, %rdi 155 ; AVX-NEXT: jb LBB6_2 156 ; AVX-NEXT: ## %bb.1: 157 ; AVX-NEXT: vmovaps %xmm1, %xmm0 158 ; AVX-NEXT: LBB6_2: 159 ; AVX-NEXT: retq 160 %1 = icmp ult i64 %a, %b 161 %2 = select i1 %1, float %c, float %d 162 ret float %2 163 } 164 165 define float @select_icmp_ule_f32(i64 %a, i64 %b, float %c, float %d) { 166 ; SSE-LABEL: select_icmp_ule_f32: 167 ; SSE: ## %bb.0: 168 ; SSE-NEXT: cmpq %rsi, %rdi 169 ; SSE-NEXT: jbe LBB7_2 170 ; SSE-NEXT: ## %bb.1: 171 ; SSE-NEXT: movaps %xmm1, %xmm0 172 ; SSE-NEXT: LBB7_2: 173 ; SSE-NEXT: retq 174 ; 175 ; AVX-LABEL: select_icmp_ule_f32: 176 ; AVX: ## %bb.0: 177 ; AVX-NEXT: cmpq %rsi, %rdi 178 ; AVX-NEXT: jbe LBB7_2 179 ; AVX-NEXT: ## %bb.1: 180 ; AVX-NEXT: vmovaps %xmm1, %xmm0 181 ; AVX-NEXT: LBB7_2: 182 ; AVX-NEXT: retq 183 %1 = icmp ule i64 %a, %b 184 %2 = select i1 %1, float %c, float %d 185 ret float %2 186 } 187 188 define float @select_icmp_sgt_f32(i64 %a, i64 %b, float %c, float %d) { 189 ; SSE-LABEL: select_icmp_sgt_f32: 190 ; SSE: ## %bb.0: 191 ; SSE-NEXT: cmpq %rsi, %rdi 192 ; SSE-NEXT: jg LBB8_2 193 ; SSE-NEXT: ## %bb.1: 194 ; SSE-NEXT: movaps %xmm1, %xmm0 195 ; SSE-NEXT: LBB8_2: 196 ; SSE-NEXT: retq 197 ; 198 ; AVX-LABEL: select_icmp_sgt_f32: 199 ; AVX: ## %bb.0: 200 ; AVX-NEXT: cmpq %rsi, %rdi 201 ; AVX-NEXT: jg LBB8_2 202 ; AVX-NEXT: ## %bb.1: 203 ; AVX-NEXT: vmovaps %xmm1, %xmm0 204 ; AVX-NEXT: LBB8_2: 205 ; AVX-NEXT: retq 206 %1 = icmp sgt i64 %a, %b 207 %2 = select i1 %1, float %c, float %d 208 ret float %2 209 } 210 211 define float @select_icmp_sge_f32(i64 %a, i64 %b, float %c, float %d) { 212 ; SSE-LABEL: select_icmp_sge_f32: 213 ; SSE: ## %bb.0: 214 ; SSE-NEXT: cmpq %rsi, %rdi 215 ; SSE-NEXT: jge LBB9_2 216 ; SSE-NEXT: ## %bb.1: 217 ; SSE-NEXT: movaps %xmm1, %xmm0 218 ; SSE-NEXT: LBB9_2: 219 ; SSE-NEXT: retq 220 ; 221 ; AVX-LABEL: select_icmp_sge_f32: 222 ; AVX: ## %bb.0: 223 ; AVX-NEXT: cmpq %rsi, %rdi 224 ; AVX-NEXT: jge LBB9_2 225 ; AVX-NEXT: ## %bb.1: 226 ; AVX-NEXT: vmovaps %xmm1, %xmm0 227 ; AVX-NEXT: LBB9_2: 228 ; AVX-NEXT: retq 229 %1 = icmp sge i64 %a, %b 230 %2 = select i1 %1, float %c, float %d 231 ret float %2 232 } 233 234 define float @select_icmp_slt_f32(i64 %a, i64 %b, float %c, float %d) { 235 ; SSE-LABEL: select_icmp_slt_f32: 236 ; SSE: ## %bb.0: 237 ; SSE-NEXT: cmpq %rsi, %rdi 238 ; SSE-NEXT: jl LBB10_2 239 ; SSE-NEXT: ## %bb.1: 240 ; SSE-NEXT: movaps %xmm1, %xmm0 241 ; SSE-NEXT: LBB10_2: 242 ; SSE-NEXT: retq 243 ; 244 ; AVX-LABEL: select_icmp_slt_f32: 245 ; AVX: ## %bb.0: 246 ; AVX-NEXT: cmpq %rsi, %rdi 247 ; AVX-NEXT: jl LBB10_2 248 ; AVX-NEXT: ## %bb.1: 249 ; AVX-NEXT: vmovaps %xmm1, %xmm0 250 ; AVX-NEXT: LBB10_2: 251 ; AVX-NEXT: retq 252 %1 = icmp slt i64 %a, %b 253 %2 = select i1 %1, float %c, float %d 254 ret float %2 255 } 256 257 define float @select_icmp_sle_f32(i64 %a, i64 %b, float %c, float %d) { 258 ; SSE-LABEL: select_icmp_sle_f32: 259 ; SSE: ## %bb.0: 260 ; SSE-NEXT: cmpq %rsi, %rdi 261 ; SSE-NEXT: jle LBB11_2 262 ; SSE-NEXT: ## %bb.1: 263 ; SSE-NEXT: movaps %xmm1, %xmm0 264 ; SSE-NEXT: LBB11_2: 265 ; SSE-NEXT: retq 266 ; 267 ; AVX-LABEL: select_icmp_sle_f32: 268 ; AVX: ## %bb.0: 269 ; AVX-NEXT: cmpq %rsi, %rdi 270 ; AVX-NEXT: jle LBB11_2 271 ; AVX-NEXT: ## %bb.1: 272 ; AVX-NEXT: vmovaps %xmm1, %xmm0 273 ; AVX-NEXT: LBB11_2: 274 ; AVX-NEXT: retq 275 %1 = icmp sle i64 %a, %b 276 %2 = select i1 %1, float %c, float %d 277 ret float %2 278 } 279 280 define i8 @select_icmp_sle_i8(i64 %a, i64 %b, i8 %c, i8 %d) { 281 ; CHECK-LABEL: select_icmp_sle_i8: 282 ; CHECK: ## %bb.0: 283 ; CHECK-NEXT: cmpq %rsi, %rdi 284 ; CHECK-NEXT: jle LBB12_2 285 ; CHECK-NEXT: ## %bb.1: 286 ; CHECK-NEXT: movl %ecx, %edx 287 ; CHECK-NEXT: LBB12_2: 288 ; CHECK-NEXT: movl %edx, %eax 289 ; CHECK-NEXT: retq 290 %1 = icmp sle i64 %a, %b 291 %2 = select i1 %1, i8 %c, i8 %d 292 ret i8 %2 293 } 294
