1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 5 6 define <4 x float> @shuffle_v4f32_0z27(<4 x float> %x, <4 x float> %a) { 7 ; SSE-LABEL: shuffle_v4f32_0z27: 8 ; SSE: # %bb.0: 9 ; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[2] 10 ; SSE-NEXT: retq 11 ; 12 ; AVX-LABEL: shuffle_v4f32_0z27: 13 ; AVX: # %bb.0: 14 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[2] 15 ; AVX-NEXT: retq 16 %vecext = extractelement <4 x float> %x, i32 0 17 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0 18 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1 19 %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 6, i32 undef> 20 %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6> 21 ret <4 x float> %vecinit5 22 } 23 24 define <4 x float> @shuffle_v4f32_0zz4(<4 x float> %xyzw, <4 x float> %abcd) { 25 ; SSE-LABEL: shuffle_v4f32_0zz4: 26 ; SSE: # %bb.0: 27 ; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0] 28 ; SSE-NEXT: retq 29 ; 30 ; AVX-LABEL: shuffle_v4f32_0zz4: 31 ; AVX: # %bb.0: 32 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0] 33 ; AVX-NEXT: retq 34 %vecext = extractelement <4 x float> %xyzw, i32 0 35 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0 36 %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1 37 %vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 2 38 %vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4> 39 ret <4 x float> %vecinit4 40 } 41 42 define <4 x float> @shuffle_v4f32_0z24(<4 x float> %xyzw, <4 x float> %abcd) { 43 ; SSE-LABEL: shuffle_v4f32_0z24: 44 ; SSE: # %bb.0: 45 ; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0] 46 ; SSE-NEXT: retq 47 ; 48 ; AVX-LABEL: shuffle_v4f32_0z24: 49 ; AVX: # %bb.0: 50 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0] 51 ; AVX-NEXT: retq 52 %vecext = extractelement <4 x float> %xyzw, i32 0 53 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0 54 %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1 55 %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %xyzw, <4 x i32> <i32 0, i32 1, i32 6, i32 undef> 56 %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4> 57 ret <4 x float> %vecinit5 58 } 59 60 define <4 x float> @shuffle_v4f32_0zz0(float %a) { 61 ; SSE-LABEL: shuffle_v4f32_0zz0: 62 ; SSE: # %bb.0: 63 ; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm0[0] 64 ; SSE-NEXT: retq 65 ; 66 ; AVX-LABEL: shuffle_v4f32_0zz0: 67 ; AVX: # %bb.0: 68 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm0[0] 69 ; AVX-NEXT: retq 70 %vecinit = insertelement <4 x float> undef, float %a, i32 0 71 %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1 72 %vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 2 73 %vecinit3 = insertelement <4 x float> %vecinit2, float %a, i32 3 74 ret <4 x float> %vecinit3 75 } 76 77 define <4 x float> @shuffle_v4f32_0z6z(<4 x float> %A, <4 x float> %B) { 78 ; SSE-LABEL: shuffle_v4f32_0z6z: 79 ; SSE: # %bb.0: 80 ; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero 81 ; SSE-NEXT: retq 82 ; 83 ; AVX-LABEL: shuffle_v4f32_0z6z: 84 ; AVX: # %bb.0: 85 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero 86 ; AVX-NEXT: retq 87 %vecext = extractelement <4 x float> %A, i32 0 88 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0 89 %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1 90 %vecext2 = extractelement <4 x float> %B, i32 2 91 %vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2 92 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3 93 ret <4 x float> %vecinit4 94 } 95 96 define <4 x float> @shuffle_v4f32_z06z(<4 x float> %a, <4 x float> %b) { 97 ; SSE-LABEL: shuffle_v4f32_z06z: 98 ; SSE: # %bb.0: 99 ; SSE-NEXT: insertps {{.*#+}} xmm1 = zero,xmm0[0],xmm1[2],zero 100 ; SSE-NEXT: movaps %xmm1, %xmm0 101 ; SSE-NEXT: retq 102 ; 103 ; AVX-LABEL: shuffle_v4f32_z06z: 104 ; AVX: # %bb.0: 105 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[0],xmm1[2],zero 106 ; AVX-NEXT: retq 107 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 undef, i32 0, i32 6, i32 undef> 108 %shuffle1 = shufflevector <4 x float> %shuffle, <4 x float> <float 0.000000e+00, float undef, float undef, float 0.000000e+00>, <4 x i32> <i32 4, i32 1, i32 2, i32 7> 109 ret <4 x float> %shuffle1 110 } 111 112 define <4 x float> @shuffle_v4f32_05zz(<4 x float> %a, <4 x float> %b) { 113 ; SSE-LABEL: shuffle_v4f32_05zz: 114 ; SSE: # %bb.0: 115 ; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero 116 ; SSE-NEXT: retq 117 ; 118 ; AVX-LABEL: shuffle_v4f32_05zz: 119 ; AVX: # %bb.0: 120 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero 121 ; AVX-NEXT: retq 122 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> 123 %shuffle1 = shufflevector <4 x float> %shuffle, <4 x float> <float undef, float undef, float 0.000000e+00, float 0.000000e+00>, <4 x i32> <i32 0, i32 1, i32 6, i32 7> 124 ret <4 x float> %shuffle1 125 } 126 127 define <4 x float> @insertps_undef_input0(<4 x float> %a0, <4 x float> %a1) { 128 ; SSE-LABEL: insertps_undef_input0: 129 ; SSE: # %bb.0: 130 ; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm1[0],zero,zero 131 ; SSE-NEXT: retq 132 ; 133 ; AVX-LABEL: insertps_undef_input0: 134 ; AVX: # %bb.0: 135 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm1[0],zero,zero 136 ; AVX-NEXT: retq 137 %res0 = fadd <4 x float> %a0, <float 1.0, float 1.0, float 1.0, float 1.0> 138 %res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %res0, <4 x float> %a1, i8 21) 139 %res2 = shufflevector <4 x float> %res1, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7> 140 ret <4 x float> %res2 141 } 142 143 define <4 x float> @insertps_undef_input1(<4 x float> %a0, <4 x float> %a1) { 144 ; SSE-LABEL: insertps_undef_input1: 145 ; SSE: # %bb.0: 146 ; SSE-NEXT: xorps %xmm1, %xmm1 147 ; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3] 148 ; SSE-NEXT: retq 149 ; 150 ; AVX-LABEL: insertps_undef_input1: 151 ; AVX: # %bb.0: 152 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 153 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3] 154 ; AVX-NEXT: retq 155 %res0 = fadd <4 x float> %a1, <float 1.0, float 1.0, float 1.0, float 1.0> 156 %res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %res0, i8 21) 157 %res2 = shufflevector <4 x float> %res1, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 3> 158 ret <4 x float> %res2 159 } 160 161 define <4 x float> @insertps_zero_from_v2f64(<4 x float> %a0, <2 x double>* %a1) nounwind { 162 ; SSE-LABEL: insertps_zero_from_v2f64: 163 ; SSE: # %bb.0: 164 ; SSE-NEXT: movapd (%rdi), %xmm1 165 ; SSE-NEXT: addpd {{.*}}(%rip), %xmm1 166 ; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3] 167 ; SSE-NEXT: movapd %xmm1, (%rdi) 168 ; SSE-NEXT: retq 169 ; 170 ; AVX-LABEL: insertps_zero_from_v2f64: 171 ; AVX: # %bb.0: 172 ; AVX-NEXT: vmovapd (%rdi), %xmm1 173 ; AVX-NEXT: vaddpd {{.*}}(%rip), %xmm1, %xmm1 174 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3] 175 ; AVX-NEXT: vmovapd %xmm1, (%rdi) 176 ; AVX-NEXT: retq 177 %1 = load <2 x double>, <2 x double>* %a1 178 %2 = bitcast <2 x double> <double 1.0, double 2.0> to <4 x float> 179 %3 = fadd <2 x double> %1, <double 1.0, double 2.0> 180 %4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 6, i32 2, i32 2, i32 3> 181 store <2 x double> %3, <2 x double> *%a1 182 ret <4 x float> %4 183 } 184 185 define <4 x float> @insertps_zero_from_v2i64(<4 x float> %a0, <2 x i64>* %a1) nounwind { 186 ; SSE-LABEL: insertps_zero_from_v2i64: 187 ; SSE: # %bb.0: 188 ; SSE-NEXT: movdqa (%rdi), %xmm1 189 ; SSE-NEXT: paddq {{.*}}(%rip), %xmm1 190 ; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3] 191 ; SSE-NEXT: movdqa %xmm1, (%rdi) 192 ; SSE-NEXT: retq 193 ; 194 ; AVX-LABEL: insertps_zero_from_v2i64: 195 ; AVX: # %bb.0: 196 ; AVX-NEXT: vmovdqa (%rdi), %xmm1 197 ; AVX-NEXT: vpaddq {{.*}}(%rip), %xmm1, %xmm1 198 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3] 199 ; AVX-NEXT: vmovdqa %xmm1, (%rdi) 200 ; AVX-NEXT: retq 201 %1 = load <2 x i64>, <2 x i64>* %a1 202 %2 = bitcast <2 x i64> <i64 1, i64 -2> to <4 x float> 203 %3 = add <2 x i64> %1, <i64 1, i64 -2> 204 %4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 5, i32 2, i32 2, i32 3> 205 store <2 x i64> %3, <2 x i64> *%a1 206 ret <4 x float> %4 207 } 208 209 define <4 x float> @insertps_zero_from_v8i16(<4 x float> %a0, <8 x i16>* %a1) nounwind { 210 ; SSE-LABEL: insertps_zero_from_v8i16: 211 ; SSE: # %bb.0: 212 ; SSE-NEXT: movdqa (%rdi), %xmm1 213 ; SSE-NEXT: paddw {{.*}}(%rip), %xmm1 214 ; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3] 215 ; SSE-NEXT: movdqa %xmm1, (%rdi) 216 ; SSE-NEXT: retq 217 ; 218 ; AVX-LABEL: insertps_zero_from_v8i16: 219 ; AVX: # %bb.0: 220 ; AVX-NEXT: vmovdqa (%rdi), %xmm1 221 ; AVX-NEXT: vpaddw {{.*}}(%rip), %xmm1, %xmm1 222 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3] 223 ; AVX-NEXT: vmovdqa %xmm1, (%rdi) 224 ; AVX-NEXT: retq 225 %1 = load <8 x i16>, <8 x i16>* %a1 226 %2 = bitcast <8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 2, i16 2, i16 3, i16 3> to <4 x float> 227 %3 = add <8 x i16> %1, <i16 0, i16 0, i16 1, i16 1, i16 2, i16 2, i16 3, i16 3> 228 %4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 4, i32 2, i32 2, i32 3> 229 store <8 x i16> %3, <8 x i16> *%a1 230 ret <4 x float> %4 231 } 232 233 define <4 x float> @consecutive_load_insertps_04zz(float* %p) { 234 ; SSE-LABEL: consecutive_load_insertps_04zz: 235 ; SSE: # %bb.0: 236 ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero 237 ; SSE-NEXT: retq 238 ; 239 ; AVX-LABEL: consecutive_load_insertps_04zz: 240 ; AVX: # %bb.0: 241 ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero 242 ; AVX-NEXT: retq 243 %p0 = getelementptr inbounds float, float* %p, i64 1 244 %p1 = getelementptr inbounds float, float* %p, i64 2 245 %s0 = load float, float* %p0 246 %s1 = load float, float* %p1 247 %v0 = insertelement <4 x float> undef, float %s0, i32 0 248 %v1 = insertelement <4 x float> undef, float %s1, i32 0 249 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v0, <4 x float> %v1, i8 28) 250 ret <4 x float> %res 251 } 252 253 define float @extract_zero_insertps_z0z7(<4 x float> %a0, <4 x float> %a1) { 254 ; SSE-LABEL: extract_zero_insertps_z0z7: 255 ; SSE: # %bb.0: 256 ; SSE-NEXT: xorps %xmm0, %xmm0 257 ; SSE-NEXT: retq 258 ; 259 ; AVX-LABEL: extract_zero_insertps_z0z7: 260 ; AVX: # %bb.0: 261 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 262 ; AVX-NEXT: retq 263 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 21) 264 %ext = extractelement <4 x float> %res, i32 0 265 ret float %ext 266 } 267 268 define float @extract_lane_insertps_5123(<4 x float> %a0, <4 x float> *%p1) { 269 ; SSE-LABEL: extract_lane_insertps_5123: 270 ; SSE: # %bb.0: 271 ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 272 ; SSE-NEXT: retq 273 ; 274 ; AVX-LABEL: extract_lane_insertps_5123: 275 ; AVX: # %bb.0: 276 ; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero 277 ; AVX-NEXT: retq 278 %a1 = load <4 x float>, <4 x float> *%p1 279 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 128) 280 %ext = extractelement <4 x float> %res, i32 0 281 ret float %ext 282 } 283 284 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone 285
