1 ; REQUIRES: asserts 2 ; RUN: llc < %s -verify-machineinstrs -mtriple=i686-- -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 3 ; 4 ; Test scheduling of copy instructions. 5 ; 6 ; Argument copies should be hoisted to the top of the block. 7 ; Return copies should be sunk to the end. 8 ; MUL_HiLo PhysReg use copies should be just above the mul. 9 ; MUL_HiLo PhysReg def copies should be just below the mul. 10 ; 11 ; CHECK: *** Final schedule for %bb.1 *** 12 ; CHECK: $eax = COPY 13 ; CHECK-NEXT: MUL32r %{{[0-9]+}}:gr32, implicit-def $eax, implicit-def $edx, implicit-def dead $eflags, implicit $eax 14 ; CHECK-NEXT: COPY $e{{[ad]}}x 15 ; CHECK-NEXT: COPY $e{{[ad]}}x 16 ; CHECK: DIVSSrm 17 define i64 @mulhoist(i32 %a, i32 %b) #0 { 18 entry: 19 br label %body 20 21 body: 22 %convb = sitofp i32 %b to float 23 ; Generates an iMUL64r to legalize types. 24 %aa = zext i32 %a to i64 25 %mul = mul i64 %aa, 74383 26 ; Do some dependent long latency stuff. 27 %trunc = trunc i64 %mul to i32 28 %convm = sitofp i32 %trunc to float 29 %divm = fdiv float %convm, 0.75 30 ;%addmb = fadd float %divm, %convb 31 ;%divmb = fdiv float %addmb, 0.125 32 ; Do some independent long latency stuff. 33 %conva = sitofp i32 %a to float 34 %diva = fdiv float %conva, 0.75 35 %addab = fadd float %diva, %convb 36 %divab = fdiv float %addab, 0.125 37 br label %end 38 39 end: 40 %val = fptosi float %divab to i64 41 %add = add i64 %mul, %val 42 ret i64 %add 43 } 44 45 attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 46 47 !0 = !{!"float", !1} 48 !1 = !{!"omnipotent char", !2} 49 !2 = !{!"Simple C/C++ TBAA"} 50
