1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7 | FileCheck %s 3 ; RUN: opt -instsimplify -disable-output < %s 4 5 define <8 x i32*> @SHUFF0(<4 x i32*> %ptrv) nounwind { 6 ; CHECK-LABEL: SHUFF0: 7 ; CHECK: # %bb.0: # %entry 8 ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,1,2] 9 ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,1] 10 ; CHECK-NEXT: movdqa %xmm2, %xmm0 11 ; CHECK-NEXT: retl 12 entry: 13 %G = shufflevector <4 x i32*> %ptrv, <4 x i32*> %ptrv, <8 x i32> <i32 2, i32 7, i32 1, i32 2, i32 4, i32 5, i32 1, i32 1> 14 ret <8 x i32*> %G 15 } 16 17 define <4 x i32*> @SHUFF1(<4 x i32*> %ptrv) nounwind { 18 ; CHECK-LABEL: SHUFF1: 19 ; CHECK: # %bb.0: # %entry 20 ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,3,2] 21 ; CHECK-NEXT: retl 22 entry: 23 %G = shufflevector <4 x i32*> %ptrv, <4 x i32*> %ptrv, <4 x i32> <i32 2, i32 7, i32 7, i32 2> 24 ret <4 x i32*> %G 25 } 26 27 define <4 x i8*> @SHUFF3(<4 x i8*> %ptrv) nounwind { 28 ; CHECK-LABEL: SHUFF3: 29 ; CHECK: # %bb.0: # %entry 30 ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,1,2] 31 ; CHECK-NEXT: retl 32 entry: 33 %G = shufflevector <4 x i8*> %ptrv, <4 x i8*> undef, <4 x i32> <i32 2, i32 7, i32 1, i32 2> 34 ret <4 x i8*> %G 35 } 36 37 define <4 x i8*> @LOAD0(<4 x i8*>* %p) nounwind { 38 ; CHECK-LABEL: LOAD0: 39 ; CHECK: # %bb.0: # %entry 40 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 41 ; CHECK-NEXT: movaps (%eax), %xmm0 42 ; CHECK-NEXT: retl 43 entry: 44 %G = load <4 x i8*>, <4 x i8*>* %p 45 ret <4 x i8*> %G 46 } 47 48 define <4 x i8*> @LOAD1(<4 x i8*>* %p) nounwind { 49 ; CHECK-LABEL: LOAD1: 50 ; CHECK: # %bb.0: # %entry 51 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 52 ; CHECK-NEXT: movdqa (%eax), %xmm0 53 ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,0,3] 54 ; CHECK-NEXT: movdqa %xmm1, (%eax) 55 ; CHECK-NEXT: retl 56 entry: 57 %G = load <4 x i8*>, <4 x i8*>* %p 58 %T = shufflevector <4 x i8*> %G, <4 x i8*> %G, <4 x i32> <i32 7, i32 1, i32 4, i32 3> 59 store <4 x i8*> %T, <4 x i8*>* %p 60 ret <4 x i8*> %G 61 } 62 63 define <4 x i8*> @LOAD2(<4 x i8*>* %p) nounwind { 64 ; CHECK-LABEL: LOAD2: 65 ; CHECK: # %bb.0: # %entry 66 ; CHECK-NEXT: subl $28, %esp 67 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 68 ; CHECK-NEXT: movaps (%eax), %xmm0 69 ; CHECK-NEXT: movaps %xmm0, (%esp) 70 ; CHECK-NEXT: addl $28, %esp 71 ; CHECK-NEXT: retl 72 entry: 73 %I = alloca <4 x i8*> 74 %G = load <4 x i8*>, <4 x i8*>* %p 75 store <4 x i8*> %G, <4 x i8*>* %I 76 %Z = load <4 x i8*>, <4 x i8*>* %I 77 ret <4 x i8*> %Z 78 } 79 80 define <4 x i32> @INT2PTR0(<4 x i8*>* %p) nounwind { 81 ; CHECK-LABEL: INT2PTR0: 82 ; CHECK: # %bb.0: # %entry 83 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 84 ; CHECK-NEXT: movaps (%eax), %xmm0 85 ; CHECK-NEXT: retl 86 entry: 87 %G = load <4 x i8*>, <4 x i8*>* %p 88 %K = ptrtoint <4 x i8*> %G to <4 x i32> 89 ret <4 x i32> %K 90 } 91 92 define <4 x i32*> @INT2PTR1(<4 x i8>* %p) nounwind { 93 ; CHECK-LABEL: INT2PTR1: 94 ; CHECK: # %bb.0: # %entry 95 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 96 ; CHECK-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 97 ; CHECK-NEXT: retl 98 entry: 99 %G = load <4 x i8>, <4 x i8>* %p 100 %K = inttoptr <4 x i8> %G to <4 x i32*> 101 ret <4 x i32*> %K 102 } 103 104 define <4 x i32*> @BITCAST0(<4 x i8*>* %p) nounwind { 105 ; CHECK-LABEL: BITCAST0: 106 ; CHECK: # %bb.0: # %entry 107 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 108 ; CHECK-NEXT: movaps (%eax), %xmm0 109 ; CHECK-NEXT: retl 110 entry: 111 %G = load <4 x i8*>, <4 x i8*>* %p 112 %T = bitcast <4 x i8*> %G to <4 x i32*> 113 ret <4 x i32*> %T 114 } 115 116 define <2 x i32*> @BITCAST1(<2 x i8*>* %p) nounwind { 117 ; CHECK-LABEL: BITCAST1: 118 ; CHECK: # %bb.0: # %entry 119 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 120 ; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero 121 ; CHECK-NEXT: retl 122 entry: 123 %G = load <2 x i8*>, <2 x i8*>* %p 124 %T = bitcast <2 x i8*> %G to <2 x i32*> 125 ret <2 x i32*> %T 126 } 127 128 define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind { 129 ; CHECK-LABEL: ICMP0: 130 ; CHECK: # %bb.0: # %entry 131 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 132 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx 133 ; CHECK-NEXT: movdqa (%ecx), %xmm0 134 ; CHECK-NEXT: pcmpgtd (%eax), %xmm0 135 ; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6] 136 ; CHECK-NEXT: blendvps %xmm0, {{\.LCPI.*}}, %xmm1 137 ; CHECK-NEXT: movaps %xmm1, %xmm0 138 ; CHECK-NEXT: retl 139 entry: 140 %g0 = load <4 x i8*>, <4 x i8*>* %p0 141 %g1 = load <4 x i8*>, <4 x i8*>* %p1 142 %k = icmp sgt <4 x i8*> %g0, %g1 143 %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6> 144 ret <4 x i32> %j 145 } 146 147 define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind { 148 ; CHECK-LABEL: ICMP1: 149 ; CHECK: # %bb.0: # %entry 150 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 151 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx 152 ; CHECK-NEXT: movdqa (%ecx), %xmm0 153 ; CHECK-NEXT: pcmpeqd (%eax), %xmm0 154 ; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6] 155 ; CHECK-NEXT: blendvps %xmm0, {{\.LCPI.*}}, %xmm1 156 ; CHECK-NEXT: movaps %xmm1, %xmm0 157 ; CHECK-NEXT: retl 158 entry: 159 %g0 = load <4 x i8*>, <4 x i8*>* %p0 160 %g1 = load <4 x i8*>, <4 x i8*>* %p1 161 %k = icmp eq <4 x i8*> %g0, %g1 162 %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6> 163 ret <4 x i32> %j 164 } 165 166
