1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc -o - %s | FileCheck %s 3 4 target triple = "i386-unknown-linux-gnu" 5 6 @a = external global i32, align 4 7 @d = external global i32*, align 4 8 @k = external global i32**, align 4 9 @j = external global i32***, align 4 10 @h = external global i32, align 4 11 @c = external global i32, align 4 12 @i = external global i32, align 4 13 @b = external global i32, align 4 14 @f = external global i64, align 8 15 @e = external global i64, align 8 16 @g = external global i32, align 4 17 18 declare i32 @fn1(i32 returned) optsize readnone 19 20 declare i32 @main() optsize 21 22 declare i32 @putchar(i32) nounwind 23 24 define void @fn2() nounwind optsize { 25 ; CHECK-LABEL: fn2: 26 ; CHECK: # %bb.0: # %entry 27 ; CHECK-NEXT: pushl %ebx 28 ; CHECK-NEXT: subl $8, %esp 29 ; CHECK-NEXT: movl $48, (%esp) 30 ; CHECK-NEXT: calll putchar 31 ; CHECK-NEXT: movl h, %eax 32 ; CHECK-NEXT: movl c, %ecx 33 ; CHECK-NEXT: movl j, %edx 34 ; CHECK-NEXT: movl (%edx), %edx 35 ; CHECK-NEXT: movl (%edx), %edx 36 ; CHECK-NEXT: xorl %ebx, %ebx 37 ; CHECK-NEXT: cmpl (%edx), %ecx 38 ; CHECK-NEXT: setg %bl 39 ; CHECK-NEXT: xorl %ecx, %ecx 40 ; CHECK-NEXT: cmpl %ebx, i 41 ; CHECK-NEXT: setg %cl 42 ; CHECK-NEXT: movl %ecx, b 43 ; CHECK-NEXT: xorl %edx, %edx 44 ; CHECK-NEXT: cmpl %ecx, %eax 45 ; CHECK-NEXT: setg %dl 46 ; CHECK-NEXT: xorl %edx, a 47 ; CHECK-NEXT: movl d, %eax 48 ; CHECK-NEXT: movl (%eax), %eax 49 ; CHECK-NEXT: andl %eax, e 50 ; CHECK-NEXT: sarl $31, %eax 51 ; CHECK-NEXT: andl %eax, e+4 52 ; CHECK-NEXT: decl g 53 ; CHECK-NEXT: addl $1, f 54 ; CHECK-NEXT: adcl $0, f+4 55 ; CHECK-NEXT: addl $8, %esp 56 ; CHECK-NEXT: popl %ebx 57 ; CHECK-NEXT: retl 58 entry: 59 %putchar = tail call i32 @putchar(i32 48) 60 %0 = load volatile i32, i32* @h, align 4 61 %1 = load i32, i32* @c, align 4, !tbaa !1 62 %2 = load i32***, i32**** @j, align 4 63 %3 = load i32**, i32*** %2, align 4 64 %4 = load i32*, i32** %3, align 4 65 %5 = load i32, i32* %4, align 4 66 %cmp = icmp sgt i32 %1, %5 67 %conv = zext i1 %cmp to i32 68 %6 = load i32, i32* @i, align 4 69 %cmp1 = icmp sgt i32 %6, %conv 70 %conv2 = zext i1 %cmp1 to i32 71 store i32 %conv2, i32* @b, align 4 72 %cmp3 = icmp sgt i32 %0, %conv2 73 %conv4 = zext i1 %cmp3 to i32 74 %7 = load i32, i32* @a, align 4 75 %or = xor i32 %7, %conv4 76 store i32 %or, i32* @a, align 4 77 %8 = load i32*, i32** @d, align 4 78 %9 = load i32, i32* %8, align 4 79 %conv6 = sext i32 %9 to i64 80 %10 = load i64, i64* @e, align 8 81 %and = and i64 %10, %conv6 82 store i64 %and, i64* @e, align 8 83 %11 = load i32, i32* @g, align 4 84 %dec = add nsw i32 %11, -1 85 store i32 %dec, i32* @g, align 4 86 %12 = load i64, i64* @f, align 8 87 %inc = add nsw i64 %12, 1 88 store i64 %inc, i64* @f, align 8 89 ret void 90 } 91 92 !0 = !{i32 1, !"NumRegisterParameters", i32 0} 93 !1 = !{!2, !2, i64 0} 94 !2 = !{!"int", !3, i64 0} 95 !3 = !{!"omnipotent char", !4, i64 0} 96 !4 = !{!"Simple C/C++ TBAA"} 97 !5 = !{!6, !6, i64 0} 98 !6 = !{!"any pointer", !3, i64 0} 99 !7 = !{!8, !8, i64 0} 100 !8 = !{!"long long", !3, i64 0} 101
