1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=CHECK,SSE 3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=CHECK,AVX512 4 5 ; This test makes sure that a vector that needs to be promoted that is bitcasted to fp16 is legalized correctly without causing a width mismatch. 6 define void @constant_fold_vector_to_half() { 7 ; CHECK-LABEL: constant_fold_vector_to_half: 8 ; CHECK: # %bb.0: 9 ; CHECK-NEXT: movw $16384, (%rax) # imm = 0x4000 10 ; CHECK-NEXT: retq 11 store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), half* undef 12 ret void 13 } 14 15 ; Similarly this makes sure that the opposite bitcast of the above is also legalized without crashing. 16 define void @pr38533_2(half %x) { 17 ; SSE-LABEL: pr38533_2: 18 ; SSE: # %bb.0: 19 ; SSE-NEXT: pushq %rax 20 ; SSE-NEXT: .cfi_def_cfa_offset 16 21 ; SSE-NEXT: callq __gnu_f2h_ieee 22 ; SSE-NEXT: movw %ax, {{[0-9]+}}(%rsp) 23 ; SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax 24 ; SSE-NEXT: movw %ax, (%rax) 25 ; SSE-NEXT: popq %rax 26 ; SSE-NEXT: .cfi_def_cfa_offset 8 27 ; SSE-NEXT: retq 28 ; 29 ; AVX512-LABEL: pr38533_2: 30 ; AVX512: # %bb.0: 31 ; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 32 ; AVX512-NEXT: vmovd %xmm0, %eax 33 ; AVX512-NEXT: movw %ax, -{{[0-9]+}}(%rsp) 34 ; AVX512-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax 35 ; AVX512-NEXT: movw %ax, (%rax) 36 ; AVX512-NEXT: retq 37 %a = bitcast half %x to <4 x i4> 38 store volatile <4 x i4> %a, <4 x i4>* undef 39 ret void 40 } 41 42 ; This case is a bitcast from fp16 to a 16-bit wide legal vector type. In this case the result type is legal when the bitcast gets type legalized. 43 define void @pr38533_3(half %x) { 44 ; SSE-LABEL: pr38533_3: 45 ; SSE: # %bb.0: 46 ; SSE-NEXT: pushq %rax 47 ; SSE-NEXT: .cfi_def_cfa_offset 16 48 ; SSE-NEXT: callq __gnu_f2h_ieee 49 ; SSE-NEXT: movw %ax, (%rsp) 50 ; SSE-NEXT: movzwl (%rsp), %eax 51 ; SSE-NEXT: movw %ax, (%rax) 52 ; SSE-NEXT: popq %rax 53 ; SSE-NEXT: .cfi_def_cfa_offset 8 54 ; SSE-NEXT: retq 55 ; 56 ; AVX512-LABEL: pr38533_3: 57 ; AVX512: # %bb.0: 58 ; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 59 ; AVX512-NEXT: vmovd %xmm0, %eax 60 ; AVX512-NEXT: movw %ax, (%rax) 61 ; AVX512-NEXT: retq 62 %a = bitcast half %x to <16 x i1> 63 store volatile <16 x i1> %a, <16 x i1>* undef 64 ret void 65 } 66
