1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s 3 4 define i32 @test1(i32 %X) { 5 ; CHECK-LABEL: test1: 6 ; CHECK: # %bb.0: 7 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx 8 ; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081 9 ; CHECK-NEXT: movl %ecx, %eax 10 ; CHECK-NEXT: imull %edx 11 ; CHECK-NEXT: addl %ecx, %edx 12 ; CHECK-NEXT: movl %edx, %eax 13 ; CHECK-NEXT: shrl $31, %eax 14 ; CHECK-NEXT: sarl $7, %edx 15 ; CHECK-NEXT: addl %eax, %edx 16 ; CHECK-NEXT: movl %edx, %eax 17 ; CHECK-NEXT: shll $8, %eax 18 ; CHECK-NEXT: subl %eax, %edx 19 ; CHECK-NEXT: addl %edx, %ecx 20 ; CHECK-NEXT: movl %ecx, %eax 21 ; CHECK-NEXT: retl 22 %tmp1 = srem i32 %X, 255 23 ret i32 %tmp1 24 } 25 26 define i32 @test2(i32 %X) { 27 ; CHECK-LABEL: test2: 28 ; CHECK: # %bb.0: 29 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 30 ; CHECK-NEXT: movl %eax, %ecx 31 ; CHECK-NEXT: sarl $31, %ecx 32 ; CHECK-NEXT: shrl $24, %ecx 33 ; CHECK-NEXT: addl %eax, %ecx 34 ; CHECK-NEXT: andl $-256, %ecx 35 ; CHECK-NEXT: subl %ecx, %eax 36 ; CHECK-NEXT: retl 37 %tmp1 = srem i32 %X, 256 38 ret i32 %tmp1 39 } 40 41 define i32 @test3(i32 %X) { 42 ; CHECK-LABEL: test3: 43 ; CHECK: # %bb.0: 44 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx 45 ; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081 46 ; CHECK-NEXT: movl %ecx, %eax 47 ; CHECK-NEXT: mull %edx 48 ; CHECK-NEXT: shrl $7, %edx 49 ; CHECK-NEXT: movl %edx, %eax 50 ; CHECK-NEXT: shll $8, %eax 51 ; CHECK-NEXT: subl %eax, %edx 52 ; CHECK-NEXT: addl %edx, %ecx 53 ; CHECK-NEXT: movl %ecx, %eax 54 ; CHECK-NEXT: retl 55 %tmp1 = urem i32 %X, 255 56 ret i32 %tmp1 57 } 58 59 define i32 @test4(i32 %X) { 60 ; CHECK-LABEL: test4: 61 ; CHECK: # %bb.0: 62 ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax 63 ; CHECK-NEXT: retl 64 %tmp1 = urem i32 %X, 256 65 ret i32 %tmp1 66 } 67 68 define i32 @test5(i32 %X) nounwind readnone { 69 ; CHECK-LABEL: test5: 70 ; CHECK: # %bb.0: # %entry 71 ; CHECK-NEXT: movl $41, %eax 72 ; CHECK-NEXT: xorl %edx, %edx 73 ; CHECK-NEXT: idivl {{[0-9]+}}(%esp) 74 ; CHECK-NEXT: movl %edx, %eax 75 ; CHECK-NEXT: retl 76 entry: 77 %0 = srem i32 41, %X 78 ret i32 %0 79 } 80 81
