1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s 3 4 define <4 x i32> @rot_v4i32_splat(<4 x i32> %x) { 5 ; CHECK-LABEL: rot_v4i32_splat: 6 ; CHECK: # %bb.0: 7 ; CHECK-NEXT: vprotd $31, %xmm0, %xmm0 8 ; CHECK-NEXT: retq 9 %1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1> 10 %2 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> 11 %3 = or <4 x i32> %1, %2 12 ret <4 x i32> %3 13 } 14 15 define <4 x i32> @rot_v4i32_non_splat(<4 x i32> %x) { 16 ; CHECK-LABEL: rot_v4i32_non_splat: 17 ; CHECK: # %bb.0: 18 ; CHECK-NEXT: vprotd {{.*}}(%rip), %xmm0, %xmm0 19 ; CHECK-NEXT: retq 20 %1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4> 21 %2 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28> 22 %3 = or <4 x i32> %1, %2 23 ret <4 x i32> %3 24 } 25 26 define <4 x i32> @rot_v4i32_splat_2masks(<4 x i32> %x) { 27 ; CHECK-LABEL: rot_v4i32_splat_2masks: 28 ; CHECK: # %bb.0: 29 ; CHECK-NEXT: vprotd $31, %xmm0, %xmm0 30 ; CHECK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 31 ; CHECK-NEXT: retq 32 %1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1> 33 %2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760> 34 35 %3 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> 36 %4 = and <4 x i32> %3, <i32 0, i32 4294901760, i32 0, i32 4294901760> 37 %5 = or <4 x i32> %2, %4 38 ret <4 x i32> %5 39 } 40 41 define <4 x i32> @rot_v4i32_non_splat_2masks(<4 x i32> %x) { 42 ; CHECK-LABEL: rot_v4i32_non_splat_2masks: 43 ; CHECK: # %bb.0: 44 ; CHECK-NEXT: vprotd {{.*}}(%rip), %xmm0, %xmm0 45 ; CHECK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 46 ; CHECK-NEXT: retq 47 %1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4> 48 %2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760> 49 50 %3 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28> 51 %4 = and <4 x i32> %3, <i32 0, i32 4294901760, i32 0, i32 4294901760> 52 %5 = or <4 x i32> %2, %4 53 ret <4 x i32> %5 54 } 55
