1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s 3 4 define i32 @shl48sar47(i64 %a) #0 { 5 ; CHECK-LABEL: shl48sar47: 6 ; CHECK: # %bb.0: 7 ; CHECK-NEXT: movswq %di, %rax 8 ; CHECK-NEXT: addl %eax, %eax 9 ; CHECK-NEXT: # kill: def $eax killed $eax killed $rax 10 ; CHECK-NEXT: retq 11 %1 = shl i64 %a, 48 12 %2 = ashr exact i64 %1, 47 13 %3 = trunc i64 %2 to i32 14 ret i32 %3 15 } 16 17 define i32 @shl48sar49(i64 %a) #0 { 18 ; CHECK-LABEL: shl48sar49: 19 ; CHECK: # %bb.0: 20 ; CHECK-NEXT: movswq %di, %rax 21 ; CHECK-NEXT: shrq %rax 22 ; CHECK-NEXT: # kill: def $eax killed $eax killed $rax 23 ; CHECK-NEXT: retq 24 %1 = shl i64 %a, 48 25 %2 = ashr exact i64 %1, 49 26 %3 = trunc i64 %2 to i32 27 ret i32 %3 28 } 29 30 define i32 @shl56sar55(i64 %a) #0 { 31 ; CHECK-LABEL: shl56sar55: 32 ; CHECK: # %bb.0: 33 ; CHECK-NEXT: movsbq %dil, %rax 34 ; CHECK-NEXT: addl %eax, %eax 35 ; CHECK-NEXT: # kill: def $eax killed $eax killed $rax 36 ; CHECK-NEXT: retq 37 %1 = shl i64 %a, 56 38 %2 = ashr exact i64 %1, 55 39 %3 = trunc i64 %2 to i32 40 ret i32 %3 41 } 42 43 define i32 @shl56sar57(i64 %a) #0 { 44 ; CHECK-LABEL: shl56sar57: 45 ; CHECK: # %bb.0: 46 ; CHECK-NEXT: movsbq %dil, %rax 47 ; CHECK-NEXT: shrq %rax 48 ; CHECK-NEXT: # kill: def $eax killed $eax killed $rax 49 ; CHECK-NEXT: retq 50 %1 = shl i64 %a, 56 51 %2 = ashr exact i64 %1, 57 52 %3 = trunc i64 %2 to i32 53 ret i32 %3 54 } 55 56 define i8 @all_sign_bit_ashr(i8 %x) { 57 ; CHECK-LABEL: all_sign_bit_ashr: 58 ; CHECK: # %bb.0: 59 ; CHECK-NEXT: andb $1, %dil 60 ; CHECK-NEXT: negb %dil 61 ; CHECK-NEXT: movl %edi, %eax 62 ; CHECK-NEXT: retq 63 %and = and i8 %x, 1 64 %neg = sub i8 0, %and 65 %sar = ashr i8 %neg, 6 66 ret i8 %sar 67 } 68 69 define <4 x i32> @all_sign_bit_ashr_vec(<4 x i32> %x) { 70 ; CHECK-LABEL: all_sign_bit_ashr_vec: 71 ; CHECK: # %bb.0: 72 ; CHECK-NEXT: pand {{.*}}(%rip), %xmm0 73 ; CHECK-NEXT: pxor %xmm1, %xmm1 74 ; CHECK-NEXT: psubd %xmm0, %xmm1 75 ; CHECK-NEXT: movdqa %xmm1, %xmm0 76 ; CHECK-NEXT: retq 77 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> 78 %neg = sub <4 x i32> zeroinitializer, %and 79 %sar = ashr <4 x i32> %neg, <i32 1, i32 31, i32 5, i32 0> 80 ret <4 x i32> %sar 81 } 82 83 attributes #0 = { nounwind } 84
