1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s 3 4 define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) nounwind { 5 ; CHECK-LABEL: all_bits_clear: 6 ; CHECK: # %bb.0: 7 ; CHECK-NEXT: orl %esi, %edi 8 ; CHECK-NEXT: sete %al 9 ; CHECK-NEXT: retq 10 %a = icmp eq i32 %P, 0 11 %b = icmp eq i32 %Q, 0 12 %c = and i1 %a, %b 13 ret i1 %c 14 } 15 16 define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) nounwind { 17 ; CHECK-LABEL: all_sign_bits_clear: 18 ; CHECK: # %bb.0: 19 ; CHECK-NEXT: orl %esi, %edi 20 ; CHECK-NEXT: setns %al 21 ; CHECK-NEXT: retq 22 %a = icmp sgt i32 %P, -1 23 %b = icmp sgt i32 %Q, -1 24 %c = and i1 %a, %b 25 ret i1 %c 26 } 27 28 define zeroext i1 @all_bits_set(i32 %P, i32 %Q) nounwind { 29 ; CHECK-LABEL: all_bits_set: 30 ; CHECK: # %bb.0: 31 ; CHECK-NEXT: andl %esi, %edi 32 ; CHECK-NEXT: cmpl $-1, %edi 33 ; CHECK-NEXT: sete %al 34 ; CHECK-NEXT: retq 35 %a = icmp eq i32 %P, -1 36 %b = icmp eq i32 %Q, -1 37 %c = and i1 %a, %b 38 ret i1 %c 39 } 40 41 define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) nounwind { 42 ; CHECK-LABEL: all_sign_bits_set: 43 ; CHECK: # %bb.0: 44 ; CHECK-NEXT: andl %esi, %edi 45 ; CHECK-NEXT: shrl $31, %edi 46 ; CHECK-NEXT: movl %edi, %eax 47 ; CHECK-NEXT: retq 48 %a = icmp slt i32 %P, 0 49 %b = icmp slt i32 %Q, 0 50 %c = and i1 %a, %b 51 ret i1 %c 52 } 53 54 define zeroext i1 @any_bits_set(i32 %P, i32 %Q) nounwind { 55 ; CHECK-LABEL: any_bits_set: 56 ; CHECK: # %bb.0: 57 ; CHECK-NEXT: orl %esi, %edi 58 ; CHECK-NEXT: setne %al 59 ; CHECK-NEXT: retq 60 %a = icmp ne i32 %P, 0 61 %b = icmp ne i32 %Q, 0 62 %c = or i1 %a, %b 63 ret i1 %c 64 } 65 66 define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) nounwind { 67 ; CHECK-LABEL: any_sign_bits_set: 68 ; CHECK: # %bb.0: 69 ; CHECK-NEXT: orl %esi, %edi 70 ; CHECK-NEXT: shrl $31, %edi 71 ; CHECK-NEXT: movl %edi, %eax 72 ; CHECK-NEXT: retq 73 %a = icmp slt i32 %P, 0 74 %b = icmp slt i32 %Q, 0 75 %c = or i1 %a, %b 76 ret i1 %c 77 } 78 79 define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) nounwind { 80 ; CHECK-LABEL: any_bits_clear: 81 ; CHECK: # %bb.0: 82 ; CHECK-NEXT: andl %esi, %edi 83 ; CHECK-NEXT: cmpl $-1, %edi 84 ; CHECK-NEXT: setne %al 85 ; CHECK-NEXT: retq 86 %a = icmp ne i32 %P, -1 87 %b = icmp ne i32 %Q, -1 88 %c = or i1 %a, %b 89 ret i1 %c 90 } 91 92 define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) nounwind { 93 ; CHECK-LABEL: any_sign_bits_clear: 94 ; CHECK: # %bb.0: 95 ; CHECK-NEXT: testl %esi, %edi 96 ; CHECK-NEXT: setns %al 97 ; CHECK-NEXT: retq 98 %a = icmp sgt i32 %P, -1 99 %b = icmp sgt i32 %Q, -1 100 %c = or i1 %a, %b 101 ret i1 %c 102 } 103 104 ; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0 105 define i32 @all_bits_clear_branch(i32* %P, i32* %Q) nounwind { 106 ; CHECK-LABEL: all_bits_clear_branch: 107 ; CHECK: # %bb.0: # %entry 108 ; CHECK-NEXT: orq %rsi, %rdi 109 ; CHECK-NEXT: jne .LBB8_2 110 ; CHECK-NEXT: # %bb.1: # %bb1 111 ; CHECK-NEXT: movl $4, %eax 112 ; CHECK-NEXT: retq 113 ; CHECK-NEXT: .LBB8_2: # %return 114 ; CHECK-NEXT: movl $192, %eax 115 ; CHECK-NEXT: retq 116 entry: 117 %a = icmp eq i32* %P, null 118 %b = icmp eq i32* %Q, null 119 %c = and i1 %a, %b 120 br i1 %c, label %bb1, label %return 121 122 bb1: 123 ret i32 4 124 125 return: 126 ret i32 192 127 } 128 129 define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) nounwind { 130 ; CHECK-LABEL: all_sign_bits_clear_branch: 131 ; CHECK: # %bb.0: # %entry 132 ; CHECK-NEXT: testl %edi, %edi 133 ; CHECK-NEXT: js .LBB9_3 134 ; CHECK-NEXT: # %bb.1: # %entry 135 ; CHECK-NEXT: testl %esi, %esi 136 ; CHECK-NEXT: js .LBB9_3 137 ; CHECK-NEXT: # %bb.2: # %bb1 138 ; CHECK-NEXT: movl $4, %eax 139 ; CHECK-NEXT: retq 140 ; CHECK-NEXT: .LBB9_3: # %return 141 ; CHECK-NEXT: movl $192, %eax 142 ; CHECK-NEXT: retq 143 entry: 144 %a = icmp sgt i32 %P, -1 145 %b = icmp sgt i32 %Q, -1 146 %c = and i1 %a, %b 147 br i1 %c, label %bb1, label %return 148 149 bb1: 150 ret i32 4 151 152 return: 153 ret i32 192 154 } 155 156 define i32 @all_bits_set_branch(i32 %P, i32 %Q) nounwind { 157 ; CHECK-LABEL: all_bits_set_branch: 158 ; CHECK: # %bb.0: # %entry 159 ; CHECK-NEXT: cmpl $-1, %edi 160 ; CHECK-NEXT: jne .LBB10_3 161 ; CHECK-NEXT: # %bb.1: # %entry 162 ; CHECK-NEXT: cmpl $-1, %esi 163 ; CHECK-NEXT: jne .LBB10_3 164 ; CHECK-NEXT: # %bb.2: # %bb1 165 ; CHECK-NEXT: movl $4, %eax 166 ; CHECK-NEXT: retq 167 ; CHECK-NEXT: .LBB10_3: # %return 168 ; CHECK-NEXT: movl $192, %eax 169 ; CHECK-NEXT: retq 170 entry: 171 %a = icmp eq i32 %P, -1 172 %b = icmp eq i32 %Q, -1 173 %c = and i1 %a, %b 174 br i1 %c, label %bb1, label %return 175 176 bb1: 177 ret i32 4 178 179 return: 180 ret i32 192 181 } 182 183 define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) nounwind { 184 ; CHECK-LABEL: all_sign_bits_set_branch: 185 ; CHECK: # %bb.0: # %entry 186 ; CHECK-NEXT: testl %edi, %edi 187 ; CHECK-NEXT: jns .LBB11_3 188 ; CHECK-NEXT: # %bb.1: # %entry 189 ; CHECK-NEXT: testl %esi, %esi 190 ; CHECK-NEXT: jns .LBB11_3 191 ; CHECK-NEXT: # %bb.2: # %bb1 192 ; CHECK-NEXT: movl $4, %eax 193 ; CHECK-NEXT: retq 194 ; CHECK-NEXT: .LBB11_3: # %return 195 ; CHECK-NEXT: movl $192, %eax 196 ; CHECK-NEXT: retq 197 entry: 198 %a = icmp slt i32 %P, 0 199 %b = icmp slt i32 %Q, 0 200 %c = and i1 %a, %b 201 br i1 %c, label %bb1, label %return 202 203 bb1: 204 ret i32 4 205 206 return: 207 ret i32 192 208 } 209 210 ; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0 211 define i32 @any_bits_set_branch(i32* %P, i32* %Q) nounwind { 212 ; CHECK-LABEL: any_bits_set_branch: 213 ; CHECK: # %bb.0: # %entry 214 ; CHECK-NEXT: orq %rsi, %rdi 215 ; CHECK-NEXT: je .LBB12_2 216 ; CHECK-NEXT: # %bb.1: # %bb1 217 ; CHECK-NEXT: movl $4, %eax 218 ; CHECK-NEXT: retq 219 ; CHECK-NEXT: .LBB12_2: # %return 220 ; CHECK-NEXT: movl $192, %eax 221 ; CHECK-NEXT: retq 222 entry: 223 %a = icmp ne i32* %P, null 224 %b = icmp ne i32* %Q, null 225 %c = or i1 %a, %b 226 br i1 %c, label %bb1, label %return 227 228 bb1: 229 ret i32 4 230 231 return: 232 ret i32 192 233 } 234 235 define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) nounwind { 236 ; CHECK-LABEL: any_sign_bits_set_branch: 237 ; CHECK: # %bb.0: # %entry 238 ; CHECK-NEXT: testl %edi, %edi 239 ; CHECK-NEXT: js .LBB13_2 240 ; CHECK-NEXT: # %bb.1: # %entry 241 ; CHECK-NEXT: testl %esi, %esi 242 ; CHECK-NEXT: js .LBB13_2 243 ; CHECK-NEXT: # %bb.3: # %return 244 ; CHECK-NEXT: movl $192, %eax 245 ; CHECK-NEXT: retq 246 ; CHECK-NEXT: .LBB13_2: # %bb1 247 ; CHECK-NEXT: movl $4, %eax 248 ; CHECK-NEXT: retq 249 entry: 250 %a = icmp slt i32 %P, 0 251 %b = icmp slt i32 %Q, 0 252 %c = or i1 %a, %b 253 br i1 %c, label %bb1, label %return 254 255 bb1: 256 ret i32 4 257 258 return: 259 ret i32 192 260 } 261 262 define i32 @any_bits_clear_branch(i32 %P, i32 %Q) nounwind { 263 ; CHECK-LABEL: any_bits_clear_branch: 264 ; CHECK: # %bb.0: # %entry 265 ; CHECK-NEXT: cmpl $-1, %edi 266 ; CHECK-NEXT: jne .LBB14_2 267 ; CHECK-NEXT: # %bb.1: # %entry 268 ; CHECK-NEXT: cmpl $-1, %esi 269 ; CHECK-NEXT: jne .LBB14_2 270 ; CHECK-NEXT: # %bb.3: # %return 271 ; CHECK-NEXT: movl $192, %eax 272 ; CHECK-NEXT: retq 273 ; CHECK-NEXT: .LBB14_2: # %bb1 274 ; CHECK-NEXT: movl $4, %eax 275 ; CHECK-NEXT: retq 276 entry: 277 %a = icmp ne i32 %P, -1 278 %b = icmp ne i32 %Q, -1 279 %c = or i1 %a, %b 280 br i1 %c, label %bb1, label %return 281 282 bb1: 283 ret i32 4 284 285 return: 286 ret i32 192 287 } 288 289 define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) nounwind { 290 ; CHECK-LABEL: any_sign_bits_clear_branch: 291 ; CHECK: # %bb.0: # %entry 292 ; CHECK-NEXT: testl %edi, %edi 293 ; CHECK-NEXT: jns .LBB15_2 294 ; CHECK-NEXT: # %bb.1: # %entry 295 ; CHECK-NEXT: testl %esi, %esi 296 ; CHECK-NEXT: jns .LBB15_2 297 ; CHECK-NEXT: # %bb.3: # %return 298 ; CHECK-NEXT: movl $192, %eax 299 ; CHECK-NEXT: retq 300 ; CHECK-NEXT: .LBB15_2: # %bb1 301 ; CHECK-NEXT: movl $4, %eax 302 ; CHECK-NEXT: retq 303 entry: 304 %a = icmp sgt i32 %P, -1 305 %b = icmp sgt i32 %Q, -1 306 %c = or i1 %a, %b 307 br i1 %c, label %bb1, label %return 308 309 bb1: 310 ret i32 4 311 312 return: 313 ret i32 192 314 } 315 316 define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind { 317 ; CHECK-LABEL: all_bits_clear_vec: 318 ; CHECK: # %bb.0: 319 ; CHECK-NEXT: por %xmm1, %xmm0 320 ; CHECK-NEXT: pxor %xmm1, %xmm1 321 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 322 ; CHECK-NEXT: retq 323 %a = icmp eq <4 x i32> %P, zeroinitializer 324 %b = icmp eq <4 x i32> %Q, zeroinitializer 325 %c = and <4 x i1> %a, %b 326 ret <4 x i1> %c 327 } 328 329 define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind { 330 ; CHECK-LABEL: all_sign_bits_clear_vec: 331 ; CHECK: # %bb.0: 332 ; CHECK-NEXT: por %xmm1, %xmm0 333 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 334 ; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 335 ; CHECK-NEXT: retq 336 %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> 337 %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> 338 %c = and <4 x i1> %a, %b 339 ret <4 x i1> %c 340 } 341 342 define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind { 343 ; CHECK-LABEL: all_bits_set_vec: 344 ; CHECK: # %bb.0: 345 ; CHECK-NEXT: pand %xmm1, %xmm0 346 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 347 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 348 ; CHECK-NEXT: retq 349 %a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> 350 %b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> 351 %c = and <4 x i1> %a, %b 352 ret <4 x i1> %c 353 } 354 355 define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind { 356 ; CHECK-LABEL: all_sign_bits_set_vec: 357 ; CHECK: # %bb.0: 358 ; CHECK-NEXT: pand %xmm1, %xmm0 359 ; CHECK-NEXT: pxor %xmm1, %xmm1 360 ; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 361 ; CHECK-NEXT: movdqa %xmm1, %xmm0 362 ; CHECK-NEXT: retq 363 %a = icmp slt <4 x i32> %P, zeroinitializer 364 %b = icmp slt <4 x i32> %Q, zeroinitializer 365 %c = and <4 x i1> %a, %b 366 ret <4 x i1> %c 367 } 368 369 define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind { 370 ; CHECK-LABEL: any_bits_set_vec: 371 ; CHECK: # %bb.0: 372 ; CHECK-NEXT: por %xmm1, %xmm0 373 ; CHECK-NEXT: pxor %xmm1, %xmm1 374 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 375 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 376 ; CHECK-NEXT: pxor %xmm1, %xmm0 377 ; CHECK-NEXT: retq 378 %a = icmp ne <4 x i32> %P, zeroinitializer 379 %b = icmp ne <4 x i32> %Q, zeroinitializer 380 %c = or <4 x i1> %a, %b 381 ret <4 x i1> %c 382 } 383 384 define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind { 385 ; CHECK-LABEL: any_sign_bits_set_vec: 386 ; CHECK: # %bb.0: 387 ; CHECK-NEXT: por %xmm1, %xmm0 388 ; CHECK-NEXT: pxor %xmm1, %xmm1 389 ; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 390 ; CHECK-NEXT: movdqa %xmm1, %xmm0 391 ; CHECK-NEXT: retq 392 %a = icmp slt <4 x i32> %P, zeroinitializer 393 %b = icmp slt <4 x i32> %Q, zeroinitializer 394 %c = or <4 x i1> %a, %b 395 ret <4 x i1> %c 396 } 397 398 define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind { 399 ; CHECK-LABEL: any_bits_clear_vec: 400 ; CHECK: # %bb.0: 401 ; CHECK-NEXT: pand %xmm1, %xmm0 402 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 403 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 404 ; CHECK-NEXT: pxor %xmm1, %xmm0 405 ; CHECK-NEXT: retq 406 %a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> 407 %b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> 408 %c = or <4 x i1> %a, %b 409 ret <4 x i1> %c 410 } 411 412 define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind { 413 ; CHECK-LABEL: any_sign_bits_clear_vec: 414 ; CHECK: # %bb.0: 415 ; CHECK-NEXT: pand %xmm1, %xmm0 416 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 417 ; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 418 ; CHECK-NEXT: retq 419 %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> 420 %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> 421 %c = or <4 x i1> %a, %b 422 ret <4 x i1> %c 423 } 424 425 define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) nounwind { 426 ; CHECK-LABEL: ne_neg1_and_ne_zero: 427 ; CHECK: # %bb.0: 428 ; CHECK-NEXT: incq %rdi 429 ; CHECK-NEXT: cmpq $1, %rdi 430 ; CHECK-NEXT: seta %al 431 ; CHECK-NEXT: retq 432 %cmp1 = icmp ne i64 %x, -1 433 %cmp2 = icmp ne i64 %x, 0 434 %and = and i1 %cmp1, %cmp2 435 ret i1 %and 436 } 437 438 ; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401 439 440 define zeroext i1 @and_eq(i8 %a, i8 %b, i8 %c, i8 %d) nounwind { 441 ; CHECK-LABEL: and_eq: 442 ; CHECK: # %bb.0: 443 ; CHECK-NEXT: xorl %esi, %edi 444 ; CHECK-NEXT: xorl %ecx, %edx 445 ; CHECK-NEXT: orb %dl, %dil 446 ; CHECK-NEXT: sete %al 447 ; CHECK-NEXT: retq 448 %cmp1 = icmp eq i8 %a, %b 449 %cmp2 = icmp eq i8 %c, %d 450 %and = and i1 %cmp1, %cmp2 451 ret i1 %and 452 } 453 454 define zeroext i1 @or_ne(i8 %a, i8 %b, i8 %c, i8 %d) nounwind { 455 ; CHECK-LABEL: or_ne: 456 ; CHECK: # %bb.0: 457 ; CHECK-NEXT: xorl %esi, %edi 458 ; CHECK-NEXT: xorl %ecx, %edx 459 ; CHECK-NEXT: orb %dl, %dil 460 ; CHECK-NEXT: setne %al 461 ; CHECK-NEXT: retq 462 %cmp1 = icmp ne i8 %a, %b 463 %cmp2 = icmp ne i8 %c, %d 464 %or = or i1 %cmp1, %cmp2 465 ret i1 %or 466 } 467 468 ; This should not be transformed because vector compares + bitwise logic are faster. 469 470 define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) nounwind { 471 ; CHECK-LABEL: and_eq_vec: 472 ; CHECK: # %bb.0: 473 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 474 ; CHECK-NEXT: pcmpeqd %xmm3, %xmm2 475 ; CHECK-NEXT: pand %xmm2, %xmm0 476 ; CHECK-NEXT: retq 477 %cmp1 = icmp eq <4 x i32> %a, %b 478 %cmp2 = icmp eq <4 x i32> %c, %d 479 %and = and <4 x i1> %cmp1, %cmp2 480 ret <4 x i1> %and 481 } 482 483
