1 ; RUN: llc < %s -mtriple=i686-- 2 ; RUN: llc < %s -mtriple=x86_64-- 3 4 ; 5 ; Scalars 6 ; 7 8 define void @test_lshr_i128(i128 %x, i128 %a, i128* nocapture %r) nounwind { 9 entry: 10 %0 = lshr i128 %x, %a 11 store i128 %0, i128* %r, align 16 12 ret void 13 } 14 15 define void @test_ashr_i128(i128 %x, i128 %a, i128* nocapture %r) nounwind { 16 entry: 17 %0 = ashr i128 %x, %a 18 store i128 %0, i128* %r, align 16 19 ret void 20 } 21 22 define void @test_shl_i128(i128 %x, i128 %a, i128* nocapture %r) nounwind { 23 entry: 24 %0 = shl i128 %x, %a 25 store i128 %0, i128* %r, align 16 26 ret void 27 } 28 29 define void @test_lshr_i128_outofrange(i128 %x, i128* nocapture %r) nounwind { 30 entry: 31 %0 = lshr i128 %x, -1 32 store i128 %0, i128* %r, align 16 33 ret void 34 } 35 36 define void @test_ashr_i128_outofrange(i128 %x, i128* nocapture %r) nounwind { 37 entry: 38 %0 = ashr i128 %x, -1 39 store i128 %0, i128* %r, align 16 40 ret void 41 } 42 43 define void @test_shl_i128_outofrange(i128 %x, i128* nocapture %r) nounwind { 44 entry: 45 %0 = shl i128 %x, -1 46 store i128 %0, i128* %r, align 16 47 ret void 48 } 49 50 ; 51 ; Vectors 52 ; 53 54 define void @test_lshr_v2i128(<2 x i128> %x, <2 x i128> %a, <2 x i128>* nocapture %r) nounwind { 55 entry: 56 %0 = lshr <2 x i128> %x, %a 57 store <2 x i128> %0, <2 x i128>* %r, align 16 58 ret void 59 } 60 61 define void @test_ashr_v2i128(<2 x i128> %x, <2 x i128> %a, <2 x i128>* nocapture %r) nounwind { 62 entry: 63 %0 = ashr <2 x i128> %x, %a 64 store <2 x i128> %0, <2 x i128>* %r, align 16 65 ret void 66 } 67 68 define void @test_shl_v2i128(<2 x i128> %x, <2 x i128> %a, <2 x i128>* nocapture %r) nounwind { 69 entry: 70 %0 = shl <2 x i128> %x, %a 71 store <2 x i128> %0, <2 x i128>* %r, align 16 72 ret void 73 } 74 75 define void @test_lshr_v2i128_outofrange(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { 76 entry: 77 %0 = lshr <2 x i128> %x, <i128 -1, i128 -1> 78 store <2 x i128> %0, <2 x i128>* %r, align 16 79 ret void 80 } 81 82 define void @test_ashr_v2i128_outofrange(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { 83 entry: 84 %0 = ashr <2 x i128> %x, <i128 -1, i128 -1> 85 store <2 x i128> %0, <2 x i128>* %r, align 16 86 ret void 87 } 88 89 define void @test_shl_v2i128_outofrange(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { 90 entry: 91 %0 = shl <2 x i128> %x, <i128 -1, i128 -1> 92 store <2 x i128> %0, <2 x i128>* %r, align 16 93 ret void 94 } 95 96 define void @test_lshr_v2i128_outofrange_sum(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { 97 entry: 98 %0 = lshr <2 x i128> %x, <i128 -1, i128 -1> 99 %1 = lshr <2 x i128> %0, <i128 1, i128 1> 100 store <2 x i128> %1, <2 x i128>* %r, align 16 101 ret void 102 } 103 104 define void @test_ashr_v2i128_outofrange_sum(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { 105 entry: 106 %0 = ashr <2 x i128> %x, <i128 -1, i128 -1> 107 %1 = ashr <2 x i128> %0, <i128 1, i128 1> 108 store <2 x i128> %1, <2 x i128>* %r, align 16 109 ret void 110 } 111 112 define void @test_shl_v2i128_outofrange_sum(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { 113 entry: 114 %0 = shl <2 x i128> %x, <i128 -1, i128 -1> 115 %1 = shl <2 x i128> %0, <i128 1, i128 1> 116 store <2 x i128> %1, <2 x i128>* %r, align 16 117 ret void 118 } 119 120 ; 121 ; Combines 122 ; 123 124 define <2 x i256> @shl_sext_shl_outofrange(<2 x i128> %a0) { 125 %1 = shl <2 x i128> %a0, <i128 -1, i128 -1> 126 %2 = sext <2 x i128> %1 to <2 x i256> 127 %3 = shl <2 x i256> %2, <i256 128, i256 128> 128 ret <2 x i256> %3 129 } 130 131 define <2 x i256> @shl_zext_shl_outofrange(<2 x i128> %a0) { 132 %1 = shl <2 x i128> %a0, <i128 -1, i128 -1> 133 %2 = zext <2 x i128> %1 to <2 x i256> 134 %3 = shl <2 x i256> %2, <i256 128, i256 128> 135 ret <2 x i256> %3 136 } 137 138 define <2 x i256> @shl_zext_lshr_outofrange(<2 x i128> %a0) { 139 %1 = lshr <2 x i128> %a0, <i128 -1, i128 -1> 140 %2 = zext <2 x i128> %1 to <2 x i256> 141 %3 = shl <2 x i256> %2, <i256 128, i256 128> 142 ret <2 x i256> %3 143 } 144 145 define i128 @lshr_shl_mask(i128 %a0) { 146 %1 = shl i128 %a0, 1 147 %2 = lshr i128 %1, 1 148 ret i128 %2 149 } 150
