1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse | FileCheck %s --check-prefixes=CHECK,SSE 3 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1 4 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX,AVX512 5 6 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse-builtins.c 7 8 define <4 x float> @test_mm_cvtsi64_ss(<4 x float> %a0, i64 %a1) nounwind { 9 ; SSE-LABEL: test_mm_cvtsi64_ss: 10 ; SSE: # %bb.0: 11 ; SSE-NEXT: cvtsi2ssq %rdi, %xmm0 12 ; SSE-NEXT: retq 13 ; 14 ; AVX-LABEL: test_mm_cvtsi64_ss: 15 ; AVX: # %bb.0: 16 ; AVX-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0 17 ; AVX-NEXT: retq 18 %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) 19 ret <4 x float> %res 20 } 21 declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone 22 23 define i64 @test_mm_cvtss_si64(<4 x float> %a0) nounwind { 24 ; SSE-LABEL: test_mm_cvtss_si64: 25 ; SSE: # %bb.0: 26 ; SSE-NEXT: cvtss2si %xmm0, %rax 27 ; SSE-NEXT: retq 28 ; 29 ; AVX-LABEL: test_mm_cvtss_si64: 30 ; AVX: # %bb.0: 31 ; AVX-NEXT: vcvtss2si %xmm0, %rax 32 ; AVX-NEXT: retq 33 %res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0) 34 ret i64 %res 35 } 36 declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone 37 38 define i64 @test_mm_cvttss_si64(<4 x float> %a0) nounwind { 39 ; SSE-LABEL: test_mm_cvttss_si64: 40 ; SSE: # %bb.0: 41 ; SSE-NEXT: cvttss2si %xmm0, %rax 42 ; SSE-NEXT: retq 43 ; 44 ; AVX-LABEL: test_mm_cvttss_si64: 45 ; AVX: # %bb.0: 46 ; AVX-NEXT: vcvttss2si %xmm0, %rax 47 ; AVX-NEXT: retq 48 %res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0) 49 ret i64 %res 50 } 51 declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone 52
