1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE 3 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1 4 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX,AVX512 5 6 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse42-builtins.c 7 8 define i64 @test_mm_crc64_u8(i64 %a0, i8 %a1) nounwind{ 9 ; CHECK-LABEL: test_mm_crc64_u8: 10 ; CHECK: # %bb.0: 11 ; CHECK-NEXT: crc32b %sil, %edi 12 ; CHECK-NEXT: movl %edi, %eax 13 ; CHECK-NEXT: retq 14 %res = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a0, i8 %a1) 15 ret i64 %res 16 } 17 declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind readnone 18 19 define i64 @test_mm_crc64_u64(i64 %a0, i64 %a1) nounwind{ 20 ; CHECK-LABEL: test_mm_crc64_u64: 21 ; CHECK: # %bb.0: 22 ; CHECK-NEXT: crc32q %rsi, %rdi 23 ; CHECK-NEXT: movq %rdi, %rax 24 ; CHECK-NEXT: retq 25 %res = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a0, i64 %a1) 26 ret i64 %res 27 } 28 declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind readnone 29
