1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s 2 ; 3 ; Note: Print verbose stackmaps using -debug-only=stackmaps. 4 5 ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps 6 ; CHECK-NEXT: __LLVM_StackMaps: 7 ; Header 8 ; CHECK-NEXT: .byte 3 9 ; CHECK-NEXT: .byte 0 10 ; CHECK-NEXT: .short 0 11 ; Num Functions 12 ; CHECK-NEXT: .long 16 13 ; Num LargeConstants 14 ; CHECK-NEXT: .long 3 15 ; Num Callsites 16 ; CHECK-NEXT: .long 20 17 18 ; Functions and stack size 19 ; CHECK-NEXT: .quad _constantargs 20 ; CHECK-NEXT: .quad 8 21 ; CHECK-NEXT: .quad 1 22 ; CHECK-NEXT: .quad _osrinline 23 ; CHECK-NEXT: .quad 24 24 ; CHECK-NEXT: .quad 1 25 ; CHECK-NEXT: .quad _osrcold 26 ; CHECK-NEXT: .quad 8 27 ; CHECK-NEXT: .quad 1 28 ; CHECK-NEXT: .quad _propertyRead 29 ; CHECK-NEXT: .quad 8 30 ; CHECK-NEXT: .quad 1 31 ; CHECK-NEXT: .quad _propertyWrite 32 ; CHECK-NEXT: .quad 8 33 ; CHECK-NEXT: .quad 1 34 ; CHECK-NEXT: .quad _jsVoidCall 35 ; CHECK-NEXT: .quad 8 36 ; CHECK-NEXT: .quad 1 37 ; CHECK-NEXT: .quad _jsIntCall 38 ; CHECK-NEXT: .quad 8 39 ; CHECK-NEXT: .quad 1 40 ; CHECK-NEXT: .quad _spilledValue 41 ; CHECK-NEXT: .quad 8 42 ; CHECK-NEXT: .quad 1 43 ; CHECK-NEXT: .quad _spilledStackMapValue 44 ; CHECK-NEXT: .quad 8 45 ; CHECK-NEXT: .quad 1 46 ; CHECK-NEXT: .quad _spillSubReg 47 ; CHECK-NEXT: .quad 56 48 ; CHECK-NEXT: .quad 1 49 ; CHECK-NEXT: .quad _subRegOffset 50 ; CHECK-NEXT: .quad 56 51 ; CHECK-NEXT: .quad 1 52 ; CHECK-NEXT: .quad _liveConstant 53 ; CHECK-NEXT: .quad 8 54 ; CHECK-NEXT: .quad 1 55 ; CHECK-NEXT: .quad _directFrameIdx 56 ; CHECK-NEXT: .quad 56 57 ; CHECK-NEXT: .quad 2 58 ; CHECK-NEXT: .quad _longid 59 ; CHECK-NEXT: .quad 8 60 ; CHECK-NEXT: .quad 4 61 ; CHECK-NEXT: .quad _clobberScratch 62 ; CHECK-NEXT: .quad 56 63 ; CHECK-NEXT: .quad 1 64 ; CHECK-NEXT: .quad _needsStackRealignment 65 ; CHECK-NEXT: .quad -1 66 ; CHECK-NEXT: .quad 1 67 68 ; Large Constants 69 ; CHECK-NEXT: .quad 2147483648 70 ; CHECK-NEXT: .quad 4294967295 71 ; CHECK-NEXT: .quad 4294967296 72 73 ; Callsites 74 ; Constant arguments 75 ; 76 ; CHECK-NEXT: .quad 1 77 ; CHECK-NEXT: .long L{{.*}}-_constantargs 78 ; CHECK-NEXT: .short 0 79 ; CHECK-NEXT: .short 12 80 ; SmallConstant 81 ; CHECK-NEXT: .byte 4 82 ; CHECK-NEXT: .byte 0 83 ; CHECK-NEXT: .short 8 84 ; CHECK-NEXT: .short 0 85 ; CHECK-NEXT: .short 0 86 ; CHECK-NEXT: .long -1 87 ; SmallConstant 88 ; CHECK-NEXT: .byte 4 89 ; CHECK-NEXT: .byte 0 90 ; CHECK-NEXT: .short 8 91 ; CHECK-NEXT: .short 0 92 ; CHECK-NEXT: .short 0 93 ; CHECK-NEXT: .long -1 94 ; SmallConstant 95 ; CHECK-NEXT: .byte 4 96 ; CHECK-NEXT: .byte 0 97 ; CHECK-NEXT: .short 8 98 ; CHECK-NEXT: .short 0 99 ; CHECK-NEXT: .short 0 100 ; CHECK-NEXT: .long 65536 101 ; SmallConstant 102 ; CHECK-NEXT: .byte 4 103 ; CHECK-NEXT: .byte 0 104 ; CHECK-NEXT: .short 8 105 ; CHECK-NEXT: .short 0 106 ; CHECK-NEXT: .short 0 107 ; CHECK-NEXT: .long 2000000000 108 ; SmallConstant 109 ; CHECK-NEXT: .byte 4 110 ; CHECK-NEXT: .byte 0 111 ; CHECK-NEXT: .short 8 112 ; CHECK-NEXT: .short 0 113 ; CHECK-NEXT: .short 0 114 ; CHECK-NEXT: .long 2147483647 115 ; SmallConstant 116 ; CHECK-NEXT: .byte 4 117 ; CHECK-NEXT: .byte 0 118 ; CHECK-NEXT: .short 8 119 ; CHECK-NEXT: .short 0 120 ; CHECK-NEXT: .short 0 121 ; CHECK-NEXT: .long -1 122 ; SmallConstant 123 ; CHECK-NEXT: .byte 4 124 ; CHECK-NEXT: .byte 0 125 ; CHECK-NEXT: .short 8 126 ; CHECK-NEXT: .short 0 127 ; CHECK-NEXT: .short 0 128 ; CHECK-NEXT: .long -1 129 ; SmallConstant 130 ; CHECK-NEXT: .byte 4 131 ; CHECK-NEXT: .byte 0 132 ; CHECK-NEXT: .short 8 133 ; CHECK-NEXT: .short 0 134 ; CHECK-NEXT: .short 0 135 ; CHECK-NEXT: .long 0 136 ; LargeConstant at index 0 137 ; CHECK-NEXT: .byte 5 138 ; CHECK-NEXT: .byte 0 139 ; CHECK-NEXT: .short 8 140 ; CHECK-NEXT: .short 0 141 ; CHECK-NEXT: .short 0 142 ; CHECK-NEXT: .long 0 143 ; LargeConstant at index 1 144 ; CHECK-NEXT: .byte 5 145 ; CHECK-NEXT: .byte 0 146 ; CHECK-NEXT: .short 8 147 ; CHECK-NEXT: .short 0 148 ; CHECK-NEXT: .short 0 149 ; CHECK-NEXT: .long 1 150 ; LargeConstant at index 2 151 ; CHECK-NEXT: .byte 5 152 ; CHECK-NEXT: .byte 0 153 ; CHECK-NEXT: .short 8 154 ; CHECK-NEXT: .short 0 155 ; CHECK-NEXT: .short 0 156 ; CHECK-NEXT: .long 2 157 ; SmallConstant 158 ; CHECK-NEXT: .byte 4 159 ; CHECK-NEXT: .byte 0 160 ; CHECK-NEXT: .short 8 161 ; CHECK-NEXT: .short 0 162 ; CHECK-NEXT: .short 0 163 ; CHECK-NEXT: .long -1 164 165 define void @constantargs() { 166 entry: 167 %0 = inttoptr i64 12345 to i8* 168 tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 15, i8* %0, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1) 169 ret void 170 } 171 172 ; Inline OSR Exit 173 ; 174 ; CHECK-LABEL: .long L{{.*}}-_osrinline 175 ; CHECK-NEXT: .short 0 176 ; CHECK-NEXT: .short 2 177 ; CHECK-NEXT: .byte 1 178 ; CHECK-NEXT: .byte 0 179 ; CHECK-NEXT: .short 8 180 ; CHECK-NEXT: .short {{[0-9]+}} 181 ; CHECK-NEXT: .short 0 182 ; CHECK-NEXT: .long 0 183 ; CHECK-NEXT: .byte 1 184 ; CHECK-NEXT: .byte 0 185 ; CHECK-NEXT: .short 8 186 ; CHECK-NEXT: .short {{[0-9]+}} 187 ; CHECK-NEXT: .short 0 188 ; CHECK-NEXT: .long 0 189 define void @osrinline(i64 %a, i64 %b) { 190 entry: 191 ; Runtime void->void call. 192 call void inttoptr (i64 -559038737 to void ()*)() 193 ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars. 194 call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b) 195 ret void 196 } 197 198 ; Cold OSR Exit 199 ; 200 ; 2 live variables in register. 201 ; 202 ; CHECK-LABEL: .long L{{.*}}-_osrcold 203 ; CHECK-NEXT: .short 0 204 ; CHECK-NEXT: .short 2 205 ; CHECK-NEXT: .byte 1 206 ; CHECK-NEXT: .byte 0 207 ; CHECK-NEXT: .short 8 208 ; CHECK-NEXT: .short {{[0-9]+}} 209 ; CHECK-NEXT: .short 0 210 ; CHECK-NEXT: .long 0 211 ; CHECK-NEXT: .byte 1 212 ; CHECK-NEXT: .byte 0 213 ; CHECK-NEXT: .short 8 214 ; CHECK-NEXT: .short {{[0-9]+}} 215 ; CHECK-NEXT: .short 0 216 ; CHECK-NEXT: .long 0 217 define void @osrcold(i64 %a, i64 %b) { 218 entry: 219 %test = icmp slt i64 %a, %b 220 br i1 %test, label %ret, label %cold 221 cold: 222 ; OSR patchpoint with 12-byte nop-slide and 2 live vars. 223 %thunk = inttoptr i64 -559038737 to i8* 224 call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 15, i8* %thunk, i32 0, i64 %a, i64 %b) 225 unreachable 226 ret: 227 ret void 228 } 229 230 ; Property Read 231 ; CHECK-LABEL: .long L{{.*}}-_propertyRead 232 ; CHECK-NEXT: .short 0 233 ; CHECK-NEXT: .short 2 234 ; CHECK-NEXT: .byte 1 235 ; CHECK-NEXT: .byte 0 236 ; CHECK-NEXT: .short 8 237 ; CHECK-NEXT: .short {{[0-9]+}} 238 ; CHECK-NEXT: .short 0 239 ; CHECK-NEXT: .long 0 240 ; CHECK-NEXT: .byte 1 241 ; CHECK-NEXT: .byte 0 242 ; CHECK-NEXT: .short 8 243 ; CHECK-NEXT: .short {{[0-9]+}} 244 ; CHECK-NEXT: .short 0 245 ; CHECK-NEXT: .long 0 246 define i64 @propertyRead(i64* %obj) { 247 entry: 248 %resolveRead = inttoptr i64 -559038737 to i8* 249 %result = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveRead, i32 1, i64* %obj) 250 %add = add i64 %result, 3 251 ret i64 %add 252 } 253 254 ; Property Write 255 ; CHECK-LABEL: .long L{{.*}}-_propertyWrite 256 ; CHECK-NEXT: .short 0 257 ; CHECK-NEXT: .short 2 258 ; CHECK-NEXT: .byte 1 259 ; CHECK-NEXT: .byte 0 260 ; CHECK-NEXT: .short 8 261 ; CHECK-NEXT: .short {{[0-9]+}} 262 ; CHECK-NEXT: .short 0 263 ; CHECK-NEXT: .long 0 264 ; CHECK-NEXT: .byte 1 265 ; CHECK-NEXT: .byte 0 266 ; CHECK-NEXT: .short 8 267 ; CHECK-NEXT: .short {{[0-9]+}} 268 ; CHECK-NEXT: .short 0 269 ; CHECK-NEXT: .long 0 270 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) { 271 entry: 272 %resolveWrite = inttoptr i64 -559038737 to i8* 273 call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 15, i8* %resolveWrite, i32 2, i64* %obj, i64 %a) 274 ret void 275 } 276 277 ; Void JS Call 278 ; 279 ; 2 live variables in registers. 280 ; 281 ; CHECK-LABEL: .long L{{.*}}-_jsVoidCall 282 ; CHECK-NEXT: .short 0 283 ; CHECK-NEXT: .short 2 284 ; CHECK-NEXT: .byte 1 285 ; CHECK-NEXT: .byte 0 286 ; CHECK-NEXT: .short 8 287 ; CHECK-NEXT: .short {{[0-9]+}} 288 ; CHECK-NEXT: .short 0 289 ; CHECK-NEXT: .long 0 290 ; CHECK-NEXT: .byte 1 291 ; CHECK-NEXT: .byte 0 292 ; CHECK-NEXT: .short 8 293 ; CHECK-NEXT: .short {{[0-9]+}} 294 ; CHECK-NEXT: .short 0 295 ; CHECK-NEXT: .long 0 296 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { 297 entry: 298 %resolveCall = inttoptr i64 -559038737 to i8* 299 call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) 300 ret void 301 } 302 303 ; i64 JS Call 304 ; 305 ; 2 live variables in registers. 306 ; 307 ; CHECK-LABEL: .long L{{.*}}-_jsIntCall 308 ; CHECK-NEXT: .short 0 309 ; CHECK-NEXT: .short 2 310 ; CHECK-NEXT: .byte 1 311 ; CHECK-NEXT: .byte 0 312 ; CHECK-NEXT: .short 8 313 ; CHECK-NEXT: .short {{[0-9]+}} 314 ; CHECK-NEXT: .short 0 315 ; CHECK-NEXT: .long 0 316 ; CHECK-NEXT: .byte 1 317 ; CHECK-NEXT: .byte 0 318 ; CHECK-NEXT: .short 8 319 ; CHECK-NEXT: .short {{[0-9]+}} 320 ; CHECK-NEXT: .short 0 321 ; CHECK-NEXT: .long 0 322 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { 323 entry: 324 %resolveCall = inttoptr i64 -559038737 to i8* 325 %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) 326 %add = add i64 %result, 3 327 ret i64 %add 328 } 329 330 ; Spilled stack map values. 331 ; 332 ; Verify 17 stack map entries. 333 ; 334 ; CHECK-LABEL: .long L{{.*}}-_spilledValue 335 ; CHECK-NEXT: .short 0 336 ; CHECK-NEXT: .short 17 337 ; 338 ; Check that at least one is a spilled entry from RBP. 339 ; Location: Indirect RBP + ... 340 ; CHECK: .byte 3 341 ; CHECK-NEXT: .byte 0 342 ; CHECK-NEXT: .short 8 343 ; CHECK-NEXT: .short 6 344 ; CHECK-NEXT: .short 0 345 ; CHECK-NEXT: .long 346 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) { 347 entry: 348 call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 15, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) 349 ret void 350 } 351 352 ; Spilled stack map values. 353 ; 354 ; Verify 17 stack map entries. 355 ; 356 ; CHECK-LABEL: .long L{{.*}}-_spilledStackMapValue 357 ; CHECK-NEXT: .short 0 358 ; CHECK-NEXT: .short 17 359 ; 360 ; Check that at least one is a spilled entry from RBP. 361 ; Location: Indirect RBP + ... 362 ; CHECK: .byte 3 363 ; CHECK-NEXT: .byte 0 364 ; CHECK-NEXT: .short 8 365 ; CHECK-NEXT: .short 6 366 ; CHECK-NEXT: .short 0 367 ; CHECK-NEXT: .long 368 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) { 369 entry: 370 call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 15, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) 371 ret void 372 } 373 374 ; Spill a subregister stackmap operand. 375 ; 376 ; CHECK-LABEL: .long L{{.*}}-_spillSubReg 377 ; CHECK-NEXT: .short 0 378 ; 4 locations 379 ; CHECK-NEXT: .short 1 380 ; 381 ; Check that the subregister operand is a 4-byte spill. 382 ; Location: Indirect, 4-byte, RBP + ... 383 ; CHECK: .byte 3 384 ; CHECK-NEXT: .byte 0 385 ; CHECK-NEXT: .short 4 386 ; CHECK-NEXT: .short 6 387 ; CHECK-NEXT: .short 0 388 ; CHECK-NEXT: .long 389 define void @spillSubReg(i64 %arg) #0 { 390 bb: 391 br i1 undef, label %bb1, label %bb2 392 393 bb1: 394 unreachable 395 396 bb2: 397 %tmp = load i64, i64* inttoptr (i64 140685446136880 to i64*) 398 br i1 undef, label %bb16, label %bb17 399 400 bb16: 401 unreachable 402 403 bb17: 404 %tmp32 = trunc i64 %tmp to i32 405 br i1 undef, label %bb60, label %bb61 406 407 bb60: 408 tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind 409 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 13, i32 5, i32 %tmp32) 410 unreachable 411 412 bb61: 413 unreachable 414 } 415 416 ; Map a single byte subregister. There is no DWARF register number, so 417 ; we expect the register to be encoded with the proper size and spill offset. We don't know which 418 ; 419 ; CHECK-LABEL: .long L{{.*}}-_subRegOffset 420 ; CHECK-NEXT: .short 0 421 ; 2 locations 422 ; CHECK-NEXT: .short 2 423 ; 424 ; Check that the subregister operands are 1-byte spills. 425 ; Location 0: Register, 4-byte, AL 426 ; CHECK-NEXT: .byte 1 427 ; CHECK-NEXT: .byte 0 428 ; CHECK-NEXT: .short 1 429 ; CHECK-NEXT: .short 0 430 ; CHECK-NEXT: .short 0 431 ; CHECK-NEXT: .long 0 432 ; 433 ; Location 1: Register, 4-byte, BL 434 ; CHECK-NEXT: .byte 1 435 ; CHECK-NEXT: .byte 0 436 ; CHECK-NEXT: .short 1 437 ; CHECK-NEXT: .short 3 438 ; CHECK-NEXT: .short 0 439 ; CHECK-NEXT: .long 0 440 define void @subRegOffset(i16 %arg) { 441 %v = mul i16 %arg, 5 442 %a0 = trunc i16 %v to i8 443 tail call void asm sideeffect "nop", "~{bx}"() nounwind 444 %arghi = lshr i16 %v, 8 445 %a1 = trunc i16 %arghi to i8 446 tail call void asm sideeffect "nop", "~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind 447 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 5, i8 %a0, i8 %a1) 448 ret void 449 } 450 451 ; Map a constant value. 452 ; 453 ; CHECK-LABEL: .long L{{.*}}-_liveConstant 454 ; CHECK-NEXT: .short 0 455 ; 1 location 456 ; CHECK-NEXT: .short 1 457 ; Loc 0: SmallConstant 458 ; CHECK-NEXT: .byte 4 459 ; CHECK-NEXT: .byte 0 460 ; CHECK-NEXT: .short 8 461 ; CHECK-NEXT: .short 0 462 ; CHECK-NEXT: .short 0 463 ; CHECK-NEXT: .long 33 464 465 define void @liveConstant() { 466 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 5, i32 33) 467 ret void 468 } 469 470 ; Directly map an alloca's address. 471 ; 472 ; Callsite 16 473 ; CHECK-LABEL: .long L{{.*}}-_directFrameIdx 474 ; CHECK-NEXT: .short 0 475 ; 1 location 476 ; CHECK-NEXT: .short 1 477 ; Loc 0: Direct RBP - ofs 478 ; CHECK-NEXT: .byte 2 479 ; CHECK-NEXT: .byte 0 480 ; CHECK-NEXT: .short 8 481 ; CHECK-NEXT: .short 6 482 ; CHECK-NEXT: .short 0 483 ; CHECK-NEXT: .long 484 485 ; Callsite 17 486 ; CHECK-LABEL: .long L{{.*}}-_directFrameIdx 487 ; CHECK-NEXT: .short 0 488 ; 2 locations 489 ; CHECK-NEXT: .short 2 490 ; Loc 0: Direct RBP - ofs 491 ; CHECK-NEXT: .byte 2 492 ; CHECK-NEXT: .byte 0 493 ; CHECK-NEXT: .short 8 494 ; CHECK-NEXT: .short 6 495 ; CHECK-NEXT: .short 0 496 ; CHECK-NEXT: .long 497 ; Loc 1: Direct RBP - ofs 498 ; CHECK-NEXT: .byte 2 499 ; CHECK-NEXT: .byte 0 500 ; CHECK-NEXT: .short 8 501 ; CHECK-NEXT: .short 6 502 ; CHECK-NEXT: .short 0 503 ; CHECK-NEXT: .long 504 define void @directFrameIdx() { 505 entry: 506 %metadata1 = alloca i64, i32 3, align 8 507 store i64 11, i64* %metadata1 508 store i64 12, i64* %metadata1 509 store i64 13, i64* %metadata1 510 call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 0, i64* %metadata1) 511 %metadata2 = alloca i8, i32 4, align 8 512 %metadata3 = alloca i16, i32 4, align 8 513 call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 17, i32 5, i8* null, i32 0, i8* %metadata2, i16* %metadata3) 514 ret void 515 } 516 517 ; Test a 64-bit ID. 518 ; 519 ; CHECK: .quad 4294967295 520 ; CHECK-LABEL: .long L{{.*}}-_longid 521 ; CHECK: .quad 4294967296 522 ; CHECK-LABEL: .long L{{.*}}-_longid 523 ; CHECK: .quad 9223372036854775807 524 ; CHECK-LABEL: .long L{{.*}}-_longid 525 ; CHECK: .quad -1 526 ; CHECK-LABEL: .long L{{.*}}-_longid 527 define void @longid() { 528 entry: 529 tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967295, i32 0, i8* null, i32 0) 530 tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967296, i32 0, i8* null, i32 0) 531 tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 9223372036854775807, i32 0, i8* null, i32 0) 532 tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 -1, i32 0, i8* null, i32 0) 533 ret void 534 } 535 536 ; Map a value when R11 is the only free register. 537 ; The scratch register should not be used for a live stackmap value. 538 ; 539 ; CHECK-LABEL: .long L{{.*}}-_clobberScratch 540 ; CHECK-NEXT: .short 0 541 ; 1 location 542 ; CHECK-NEXT: .short 1 543 ; Loc 0: Indirect fp - offset 544 ; CHECK-NEXT: .byte 3 545 ; CHECK-NEXT: .byte 0 546 ; CHECK-NEXT: .short 4 547 ; CHECK-NEXT: .short 6 548 ; CHECK-NEXT: .short 0 549 ; CHECK-NEXT: .long -{{[0-9]+}} 550 define void @clobberScratch(i32 %a) { 551 tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r12},~{r13},~{r14},~{r15}"() nounwind 552 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 8, i32 %a) 553 ret void 554 } 555 556 ; A stack frame which needs to be realigned at runtime (to meet alignment 557 ; criteria for values on the stack) does not have a fixed frame size. 558 ; CHECK-LABEL: .long L{{.*}}-_needsStackRealignment 559 ; CHECK-NEXT: .short 0 560 ; 0 locations 561 ; CHECK-NEXT: .short 0 562 define void @needsStackRealignment() { 563 %val = alloca i64, i32 3, align 128 564 tail call void (...) @escape_values(i64* %val) 565 ; Note: Adding any non-constant to the stackmap would fail because we 566 ; expected to be able to address off the frame pointer. In a realigned 567 ; frame, we must use the stack pointer instead. This is a separate bug. 568 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 0) 569 ret void 570 } 571 declare void @escape_values(...) 572 573 declare void @llvm.experimental.stackmap(i64, i32, ...) 574 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) 575 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...) 576
