1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F 6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW 7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512DQ 8 9 ; AVX1 has support for 256-bit bitwise logic because the FP variants were included. 10 ; If using those ops requires extra insert/extract though, it's probably not worth it. 11 12 define <8 x i32> @PR32790(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) { 13 ; SSE-LABEL: PR32790: 14 ; SSE: # %bb.0: 15 ; SSE-NEXT: paddd %xmm2, %xmm0 16 ; SSE-NEXT: paddd %xmm3, %xmm1 17 ; SSE-NEXT: pand %xmm5, %xmm1 18 ; SSE-NEXT: pand %xmm4, %xmm0 19 ; SSE-NEXT: psubd %xmm6, %xmm0 20 ; SSE-NEXT: psubd %xmm7, %xmm1 21 ; SSE-NEXT: retq 22 ; 23 ; AVX1-LABEL: PR32790: 24 ; AVX1: # %bb.0: 25 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm4 26 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 27 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 28 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 29 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm1 30 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 31 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm1 32 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 33 ; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm1 34 ; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1 35 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 36 ; AVX1-NEXT: retq 37 ; 38 ; AVX2-LABEL: PR32790: 39 ; AVX2: # %bb.0: 40 ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0 41 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0 42 ; AVX2-NEXT: vpsubd %ymm3, %ymm0, %ymm0 43 ; AVX2-NEXT: retq 44 ; 45 ; AVX512-LABEL: PR32790: 46 ; AVX512: # %bb.0: 47 ; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0 48 ; AVX512-NEXT: vpand %ymm2, %ymm0, %ymm0 49 ; AVX512-NEXT: vpsubd %ymm3, %ymm0, %ymm0 50 ; AVX512-NEXT: retq 51 %add = add <8 x i32> %a, %b 52 %and = and <8 x i32> %add, %c 53 %sub = sub <8 x i32> %and, %d 54 ret <8 x i32> %sub 55 } 56 57 ; In a more extreme case, even the later AVX targets should avoid extract/insert just 58 ; because 256-bit ops are supported. 59 60 define <4 x i32> @do_not_use_256bit_op(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { 61 ; SSE-LABEL: do_not_use_256bit_op: 62 ; SSE: # %bb.0: 63 ; SSE-NEXT: pand %xmm2, %xmm0 64 ; SSE-NEXT: pand %xmm3, %xmm1 65 ; SSE-NEXT: psubd %xmm1, %xmm0 66 ; SSE-NEXT: retq 67 ; 68 ; AVX-LABEL: do_not_use_256bit_op: 69 ; AVX: # %bb.0: 70 ; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0 71 ; AVX-NEXT: vpand %xmm3, %xmm1, %xmm1 72 ; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0 73 ; AVX-NEXT: retq 74 %concat1 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 75 %concat2 = shufflevector <4 x i32> %c, <4 x i32> %d, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 76 %and = and <8 x i32> %concat1, %concat2 77 %extract1 = shufflevector <8 x i32> %and, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 78 %extract2 = shufflevector <8 x i32> %and, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 79 %sub = sub <4 x i32> %extract1, %extract2 80 ret <4 x i32> %sub 81 } 82 83
