1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42 4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 6 7 ; PR28925 8 9 define <4 x i32> @test1(<4 x i1> %cond, <4 x i32> %x) { 10 ; SSE-LABEL: test1: 11 ; SSE: # %bb.0: 12 ; SSE-NEXT: pslld $31, %xmm0 13 ; SSE-NEXT: psrad $31, %xmm0 14 ; SSE-NEXT: pandn %xmm1, %xmm0 15 ; SSE-NEXT: retq 16 ; 17 ; AVX-LABEL: test1: 18 ; AVX: # %bb.0: 19 ; AVX-NEXT: vpslld $31, %xmm0, %xmm0 20 ; AVX-NEXT: vpsrad $31, %xmm0, %xmm0 21 ; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm0 22 ; AVX-NEXT: retq 23 %r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x 24 ret <4 x i32> %r 25 } 26 27 define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %x) { 28 ; SSE-LABEL: test2: 29 ; SSE: # %bb.0: 30 ; SSE-NEXT: cmpneqps %xmm1, %xmm0 31 ; SSE-NEXT: andps %xmm2, %xmm0 32 ; SSE-NEXT: retq 33 ; 34 ; AVX-LABEL: test2: 35 ; AVX: # %bb.0: 36 ; AVX-NEXT: vcmpneqps %xmm1, %xmm0, %xmm0 37 ; AVX-NEXT: vandps %xmm2, %xmm0, %xmm0 38 ; AVX-NEXT: retq 39 %cond = fcmp oeq <4 x float> %a, %b 40 %r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x 41 ret <4 x i32> %r 42 } 43 44 define float @fsel(float %a, float %b, float %x) { 45 ; SSE-LABEL: fsel: 46 ; SSE: # %bb.0: 47 ; SSE-NEXT: cmpeqss %xmm1, %xmm0 48 ; SSE-NEXT: andnps %xmm2, %xmm0 49 ; SSE-NEXT: retq 50 ; 51 ; AVX-LABEL: fsel: 52 ; AVX: # %bb.0: 53 ; AVX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 54 ; AVX-NEXT: vandnps %xmm2, %xmm0, %xmm0 55 ; AVX-NEXT: retq 56 %cond = fcmp oeq float %a, %b 57 %sel = select i1 %cond, float 0.0, float %x 58 ret float %sel 59 } 60
