1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE42 3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE42 4 5 ; 6 ; AND/XOR/OR i32 as v4i8 7 ; 8 9 define i32 @and_i32_as_v4i8(i32 %a, i32 %b) nounwind { 10 ; X32-SSE-LABEL: and_i32_as_v4i8: 11 ; X32-SSE: # %bb.0: 12 ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax 13 ; X32-SSE-NEXT: andl {{[0-9]+}}(%esp), %eax 14 ; X32-SSE-NEXT: retl 15 ; 16 ; X64-SSE-LABEL: and_i32_as_v4i8: 17 ; X64-SSE: # %bb.0: 18 ; X64-SSE-NEXT: andl %esi, %edi 19 ; X64-SSE-NEXT: movl %edi, %eax 20 ; X64-SSE-NEXT: retq 21 %1 = bitcast i32 %a to <4 x i8> 22 %2 = bitcast i32 %b to <4 x i8> 23 %3 = and <4 x i8> %1, %2 24 %4 = bitcast <4 x i8> %3 to i32 25 ret i32 %4 26 } 27 28 define i32 @xor_i32_as_v4i8(i32 %a, i32 %b) nounwind { 29 ; X32-SSE-LABEL: xor_i32_as_v4i8: 30 ; X32-SSE: # %bb.0: 31 ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax 32 ; X32-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax 33 ; X32-SSE-NEXT: retl 34 ; 35 ; X64-SSE-LABEL: xor_i32_as_v4i8: 36 ; X64-SSE: # %bb.0: 37 ; X64-SSE-NEXT: xorl %esi, %edi 38 ; X64-SSE-NEXT: movl %edi, %eax 39 ; X64-SSE-NEXT: retq 40 %1 = bitcast i32 %a to <4 x i8> 41 %2 = bitcast i32 %b to <4 x i8> 42 %3 = xor <4 x i8> %1, %2 43 %4 = bitcast <4 x i8> %3 to i32 44 ret i32 %4 45 } 46 47 define i32 @or_i32_as_v4i8(i32 %a, i32 %b) nounwind { 48 ; X32-SSE-LABEL: or_i32_as_v4i8: 49 ; X32-SSE: # %bb.0: 50 ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax 51 ; X32-SSE-NEXT: orl {{[0-9]+}}(%esp), %eax 52 ; X32-SSE-NEXT: retl 53 ; 54 ; X64-SSE-LABEL: or_i32_as_v4i8: 55 ; X64-SSE: # %bb.0: 56 ; X64-SSE-NEXT: orl %esi, %edi 57 ; X64-SSE-NEXT: movl %edi, %eax 58 ; X64-SSE-NEXT: retq 59 %1 = bitcast i32 %a to <4 x i8> 60 %2 = bitcast i32 %b to <4 x i8> 61 %3 = or <4 x i8> %1, %2 62 %4 = bitcast <4 x i8> %3 to i32 63 ret i32 %4 64 } 65 66 ; 67 ; AND/XOR/OR i32 as v8i4 68 ; 69 70 define i32 @and_i32_as_v8i4(i32 %a, i32 %b) nounwind { 71 ; X32-SSE-LABEL: and_i32_as_v8i4: 72 ; X32-SSE: # %bb.0: 73 ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax 74 ; X32-SSE-NEXT: andl {{[0-9]+}}(%esp), %eax 75 ; X32-SSE-NEXT: retl 76 ; 77 ; X64-SSE-LABEL: and_i32_as_v8i4: 78 ; X64-SSE: # %bb.0: 79 ; X64-SSE-NEXT: andl %esi, %edi 80 ; X64-SSE-NEXT: movl %edi, %eax 81 ; X64-SSE-NEXT: retq 82 %1 = bitcast i32 %a to <8 x i4> 83 %2 = bitcast i32 %b to <8 x i4> 84 %3 = and <8 x i4> %1, %2 85 %4 = bitcast <8 x i4> %3 to i32 86 ret i32 %4 87 } 88 89 define i32 @xor_i32_as_v8i4(i32 %a, i32 %b) nounwind { 90 ; X32-SSE-LABEL: xor_i32_as_v8i4: 91 ; X32-SSE: # %bb.0: 92 ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax 93 ; X32-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax 94 ; X32-SSE-NEXT: retl 95 ; 96 ; X64-SSE-LABEL: xor_i32_as_v8i4: 97 ; X64-SSE: # %bb.0: 98 ; X64-SSE-NEXT: xorl %esi, %edi 99 ; X64-SSE-NEXT: movl %edi, %eax 100 ; X64-SSE-NEXT: retq 101 %1 = bitcast i32 %a to <8 x i4> 102 %2 = bitcast i32 %b to <8 x i4> 103 %3 = xor <8 x i4> %1, %2 104 %4 = bitcast <8 x i4> %3 to i32 105 ret i32 %4 106 } 107 108 define i32 @or_i32_as_v8i4(i32 %a, i32 %b) nounwind { 109 ; X32-SSE-LABEL: or_i32_as_v8i4: 110 ; X32-SSE: # %bb.0: 111 ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax 112 ; X32-SSE-NEXT: orl {{[0-9]+}}(%esp), %eax 113 ; X32-SSE-NEXT: retl 114 ; 115 ; X64-SSE-LABEL: or_i32_as_v8i4: 116 ; X64-SSE: # %bb.0: 117 ; X64-SSE-NEXT: orl %esi, %edi 118 ; X64-SSE-NEXT: movl %edi, %eax 119 ; X64-SSE-NEXT: retq 120 %1 = bitcast i32 %a to <8 x i4> 121 %2 = bitcast i32 %b to <8 x i4> 122 %3 = or <8 x i4> %1, %2 123 %4 = bitcast <8 x i4> %3 to i32 124 ret i32 %4 125 } 126 127 ; 128 ; AND/XOR/OR v4i8 as i32 129 ; 130 131 define <4 x i8> @and_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind { 132 ; X32-SSE-LABEL: and_v4i8_as_i32: 133 ; X32-SSE: # %bb.0: 134 ; X32-SSE-NEXT: andps %xmm1, %xmm0 135 ; X32-SSE-NEXT: retl 136 ; 137 ; X64-SSE-LABEL: and_v4i8_as_i32: 138 ; X64-SSE: # %bb.0: 139 ; X64-SSE-NEXT: andps %xmm1, %xmm0 140 ; X64-SSE-NEXT: retq 141 %1 = bitcast <4 x i8> %a to i32 142 %2 = bitcast <4 x i8> %b to i32 143 %3 = and i32 %1, %2 144 %4 = bitcast i32 %3 to <4 x i8> 145 ret <4 x i8> %4 146 } 147 148 define <4 x i8> @xor_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind { 149 ; X32-SSE-LABEL: xor_v4i8_as_i32: 150 ; X32-SSE: # %bb.0: 151 ; X32-SSE-NEXT: xorps %xmm1, %xmm0 152 ; X32-SSE-NEXT: retl 153 ; 154 ; X64-SSE-LABEL: xor_v4i8_as_i32: 155 ; X64-SSE: # %bb.0: 156 ; X64-SSE-NEXT: xorps %xmm1, %xmm0 157 ; X64-SSE-NEXT: retq 158 %1 = bitcast <4 x i8> %a to i32 159 %2 = bitcast <4 x i8> %b to i32 160 %3 = xor i32 %1, %2 161 %4 = bitcast i32 %3 to <4 x i8> 162 ret <4 x i8> %4 163 } 164 165 define <4 x i8> @or_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind { 166 ; X32-SSE-LABEL: or_v4i8_as_i32: 167 ; X32-SSE: # %bb.0: 168 ; X32-SSE-NEXT: orps %xmm1, %xmm0 169 ; X32-SSE-NEXT: retl 170 ; 171 ; X64-SSE-LABEL: or_v4i8_as_i32: 172 ; X64-SSE: # %bb.0: 173 ; X64-SSE-NEXT: orps %xmm1, %xmm0 174 ; X64-SSE-NEXT: retq 175 %1 = bitcast <4 x i8> %a to i32 176 %2 = bitcast <4 x i8> %b to i32 177 %3 = or i32 %1, %2 178 %4 = bitcast i32 %3 to <4 x i8> 179 ret <4 x i8> %4 180 } 181 182 ; 183 ; AND/XOR/OR v8i4 as i32 184 ; 185 186 define <8 x i4> @and_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind { 187 ; X32-SSE-LABEL: and_v8i4_as_i32: 188 ; X32-SSE: # %bb.0: 189 ; X32-SSE-NEXT: andps %xmm1, %xmm0 190 ; X32-SSE-NEXT: retl 191 ; 192 ; X64-SSE-LABEL: and_v8i4_as_i32: 193 ; X64-SSE: # %bb.0: 194 ; X64-SSE-NEXT: andps %xmm1, %xmm0 195 ; X64-SSE-NEXT: retq 196 %1 = bitcast <8 x i4> %a to i32 197 %2 = bitcast <8 x i4> %b to i32 198 %3 = and i32 %1, %2 199 %4 = bitcast i32 %3 to <8 x i4> 200 ret <8 x i4> %4 201 } 202 203 define <8 x i4> @xor_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind { 204 ; X32-SSE-LABEL: xor_v8i4_as_i32: 205 ; X32-SSE: # %bb.0: 206 ; X32-SSE-NEXT: xorps %xmm1, %xmm0 207 ; X32-SSE-NEXT: retl 208 ; 209 ; X64-SSE-LABEL: xor_v8i4_as_i32: 210 ; X64-SSE: # %bb.0: 211 ; X64-SSE-NEXT: xorps %xmm1, %xmm0 212 ; X64-SSE-NEXT: retq 213 %1 = bitcast <8 x i4> %a to i32 214 %2 = bitcast <8 x i4> %b to i32 215 %3 = xor i32 %1, %2 216 %4 = bitcast i32 %3 to <8 x i4> 217 ret <8 x i4> %4 218 } 219 220 define <8 x i4> @or_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind { 221 ; X32-SSE-LABEL: or_v8i4_as_i32: 222 ; X32-SSE: # %bb.0: 223 ; X32-SSE-NEXT: orps %xmm1, %xmm0 224 ; X32-SSE-NEXT: retl 225 ; 226 ; X64-SSE-LABEL: or_v8i4_as_i32: 227 ; X64-SSE: # %bb.0: 228 ; X64-SSE-NEXT: orps %xmm1, %xmm0 229 ; X64-SSE-NEXT: retq 230 %1 = bitcast <8 x i4> %a to i32 231 %2 = bitcast <8 x i4> %b to i32 232 %3 = or i32 %1, %2 233 %4 = bitcast i32 %3 to <8 x i4> 234 ret <8 x i4> %4 235 } 236
