1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE2 3 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE42 4 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE2 5 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE42 6 7 ; sign to float v2i16 to v2f32 8 9 define void @convert_v2i16_to_v2f32(<2 x float>* %dst.addr, <2 x i16> %src) nounwind { 10 ; X86-SSE2-LABEL: convert_v2i16_to_v2f32: 11 ; X86-SSE2: # %bb.0: # %entry 12 ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax 13 ; X86-SSE2-NEXT: psllq $48, %xmm0 14 ; X86-SSE2-NEXT: psrad $16, %xmm0 15 ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3] 16 ; X86-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 17 ; X86-SSE2-NEXT: movss %xmm0, (%eax) 18 ; X86-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3] 19 ; X86-SSE2-NEXT: movss %xmm0, 4(%eax) 20 ; X86-SSE2-NEXT: retl 21 ; 22 ; X86-SSE42-LABEL: convert_v2i16_to_v2f32: 23 ; X86-SSE42: # %bb.0: # %entry 24 ; X86-SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax 25 ; X86-SSE42-NEXT: psllq $48, %xmm0 26 ; X86-SSE42-NEXT: psrad $16, %xmm0 27 ; X86-SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3] 28 ; X86-SSE42-NEXT: cvtdq2ps %xmm0, %xmm0 29 ; X86-SSE42-NEXT: extractps $1, %xmm0, 4(%eax) 30 ; X86-SSE42-NEXT: movss %xmm0, (%eax) 31 ; X86-SSE42-NEXT: retl 32 ; 33 ; X64-LABEL: convert_v2i16_to_v2f32: 34 ; X64: # %bb.0: # %entry 35 ; X64-NEXT: psllq $48, %xmm0 36 ; X64-NEXT: psrad $16, %xmm0 37 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3] 38 ; X64-NEXT: cvtdq2ps %xmm0, %xmm0 39 ; X64-NEXT: movlps %xmm0, (%rdi) 40 ; X64-NEXT: retq 41 entry: 42 %val = sitofp <2 x i16> %src to <2 x float> 43 store <2 x float> %val, <2 x float>* %dst.addr, align 4 44 ret void 45 } 46 47 ; sign to float v3i8 to v3f32 48 49 define void @convert_v3i8_to_v3f32(<3 x float>* %dst.addr, <3 x i8>* %src.addr) nounwind { 50 ; X86-SSE2-LABEL: convert_v3i8_to_v3f32: 51 ; X86-SSE2: # %bb.0: # %entry 52 ; X86-SSE2-NEXT: pushl %ebp 53 ; X86-SSE2-NEXT: movl %esp, %ebp 54 ; X86-SSE2-NEXT: pushl %esi 55 ; X86-SSE2-NEXT: andl $-16, %esp 56 ; X86-SSE2-NEXT: subl $32, %esp 57 ; X86-SSE2-NEXT: movl 8(%ebp), %eax 58 ; X86-SSE2-NEXT: movl 12(%ebp), %ecx 59 ; X86-SSE2-NEXT: movzwl (%ecx), %edx 60 ; X86-SSE2-NEXT: movd %edx, %xmm0 61 ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 62 ; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 63 ; X86-SSE2-NEXT: movzbl 2(%ecx), %ecx 64 ; X86-SSE2-NEXT: movdqa %xmm0, (%esp) 65 ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx 66 ; X86-SSE2-NEXT: shll $8, %edx 67 ; X86-SSE2-NEXT: movzbl (%esp), %esi 68 ; X86-SSE2-NEXT: orl %edx, %esi 69 ; X86-SSE2-NEXT: movd %esi, %xmm0 70 ; X86-SSE2-NEXT: pinsrw $1, %ecx, %xmm0 71 ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 72 ; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 73 ; X86-SSE2-NEXT: psrad $24, %xmm0 74 ; X86-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 75 ; X86-SSE2-NEXT: movss %xmm0, (%eax) 76 ; X86-SSE2-NEXT: movaps %xmm0, %xmm1 77 ; X86-SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1] 78 ; X86-SSE2-NEXT: movss %xmm1, 8(%eax) 79 ; X86-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3] 80 ; X86-SSE2-NEXT: movss %xmm0, 4(%eax) 81 ; X86-SSE2-NEXT: leal -4(%ebp), %esp 82 ; X86-SSE2-NEXT: popl %esi 83 ; X86-SSE2-NEXT: popl %ebp 84 ; X86-SSE2-NEXT: retl 85 ; 86 ; X86-SSE42-LABEL: convert_v3i8_to_v3f32: 87 ; X86-SSE42: # %bb.0: # %entry 88 ; X86-SSE42-NEXT: pushl %eax 89 ; X86-SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax 90 ; X86-SSE42-NEXT: movl {{[0-9]+}}(%esp), %ecx 91 ; X86-SSE42-NEXT: movzbl 2(%ecx), %edx 92 ; X86-SSE42-NEXT: movzwl (%ecx), %ecx 93 ; X86-SSE42-NEXT: movd %ecx, %xmm0 94 ; X86-SSE42-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 95 ; X86-SSE42-NEXT: pinsrd $2, %edx, %xmm0 96 ; X86-SSE42-NEXT: pslld $24, %xmm0 97 ; X86-SSE42-NEXT: psrad $24, %xmm0 98 ; X86-SSE42-NEXT: cvtdq2ps %xmm0, %xmm0 99 ; X86-SSE42-NEXT: extractps $2, %xmm0, 8(%eax) 100 ; X86-SSE42-NEXT: extractps $1, %xmm0, 4(%eax) 101 ; X86-SSE42-NEXT: movss %xmm0, (%eax) 102 ; X86-SSE42-NEXT: popl %eax 103 ; X86-SSE42-NEXT: retl 104 ; 105 ; X64-SSE2-LABEL: convert_v3i8_to_v3f32: 106 ; X64-SSE2: # %bb.0: # %entry 107 ; X64-SSE2-NEXT: movzwl (%rsi), %eax 108 ; X64-SSE2-NEXT: movq %rax, %xmm0 109 ; X64-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 110 ; X64-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 111 ; X64-SSE2-NEXT: movzbl 2(%rsi), %eax 112 ; X64-SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) 113 ; X64-SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %ecx 114 ; X64-SSE2-NEXT: shll $8, %ecx 115 ; X64-SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx 116 ; X64-SSE2-NEXT: orl %ecx, %edx 117 ; X64-SSE2-NEXT: movd %edx, %xmm0 118 ; X64-SSE2-NEXT: pinsrw $1, %eax, %xmm0 119 ; X64-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 120 ; X64-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 121 ; X64-SSE2-NEXT: psrad $24, %xmm0 122 ; X64-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 123 ; X64-SSE2-NEXT: movlps %xmm0, (%rdi) 124 ; X64-SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] 125 ; X64-SSE2-NEXT: movss %xmm0, 8(%rdi) 126 ; X64-SSE2-NEXT: retq 127 ; 128 ; X64-SSE42-LABEL: convert_v3i8_to_v3f32: 129 ; X64-SSE42: # %bb.0: # %entry 130 ; X64-SSE42-NEXT: movzbl 2(%rsi), %eax 131 ; X64-SSE42-NEXT: movzwl (%rsi), %ecx 132 ; X64-SSE42-NEXT: movq %rcx, %xmm0 133 ; X64-SSE42-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 134 ; X64-SSE42-NEXT: pinsrd $2, %eax, %xmm0 135 ; X64-SSE42-NEXT: pslld $24, %xmm0 136 ; X64-SSE42-NEXT: psrad $24, %xmm0 137 ; X64-SSE42-NEXT: cvtdq2ps %xmm0, %xmm0 138 ; X64-SSE42-NEXT: extractps $2, %xmm0, 8(%rdi) 139 ; X64-SSE42-NEXT: movlps %xmm0, (%rdi) 140 ; X64-SSE42-NEXT: retq 141 entry: 142 %load = load <3 x i8>, <3 x i8>* %src.addr, align 1 143 %cvt = sitofp <3 x i8> %load to <3 x float> 144 store <3 x float> %cvt, <3 x float>* %dst.addr, align 4 145 ret void 146 } 147
