1 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s 2 ; RUN: llc -mtriple=x86_64-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0 3 4 %struct.interrupt_frame = type { i64, i64, i64, i64, i64 } 5 6 @llvm.used = appending global [4 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_clobbers to i8*), i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_x87 to i8*)], section "llvm.metadata" 7 8 ; Spills rax, putting original esp at +8. 9 ; No stack adjustment if declared with no error code 10 define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) { 11 ; CHECK-LABEL: test_isr_no_ecode: 12 ; CHECK: pushq %rax 13 ; CHECK: movq 24(%rsp), %rax 14 ; CHECK: popq %rax 15 ; CHECK: iretq 16 ; CHECK0-LABEL: test_isr_no_ecode: 17 ; CHECK0: pushq %rax 18 ; CHECK0: leaq 8(%rsp), %rax 19 ; CHECK0: movq 16(%rax), %rax 20 ; CHECK0: popq %rax 21 ; CHECK0: iretq 22 %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2 23 %flags = load i64, i64* %pflags, align 4 24 call void asm sideeffect "", "r"(i64 %flags) 25 ret void 26 } 27 28 ; Spills rax and rcx, putting original rsp at +16. Stack is adjusted up another 8 bytes 29 ; before return, popping the error code. 30 define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i64 %ecode) { 31 ; CHECK-LABEL: test_isr_ecode 32 ; CHECK: pushq %rax 33 ; CHECK: pushq %rax 34 ; CHECK: pushq %rcx 35 ; CHECK: movq 24(%rsp), %rax 36 ; CHECK: movq 48(%rsp), %rcx 37 ; CHECK: popq %rcx 38 ; CHECK: popq %rax 39 ; CHECK: addq $16, %rsp 40 ; CHECK: iretq 41 ; CHECK0-LABEL: test_isr_ecode 42 ; CHECK0: pushq %rax 43 ; CHECK0: pushq %rax 44 ; CHECK0: pushq %rcx 45 ; CHECK0: movq 24(%rsp), %rax 46 ; CHECK0: leaq 32(%rsp), %rcx 47 ; CHECK0: movq 16(%rcx), %rcx 48 ; CHECK0: popq %rcx 49 ; CHECK0: popq %rax 50 ; CHECK0: addq $16, %rsp 51 ; CHECK0: iretq 52 %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2 53 %flags = load i64, i64* %pflags, align 4 54 call void asm sideeffect "", "r,r"(i64 %flags, i64 %ecode) 55 ret void 56 } 57 58 ; All clobbered registers must be saved 59 define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) { 60 call void asm sideeffect "", "~{rax},~{rbx},~{rbp},~{r11},~{xmm0}"() 61 ; CHECK-LABEL: test_isr_clobbers 62 63 ; CHECK: pushq %rax 64 ; CHECK: pushq %rbp 65 ; CHECK: pushq %r11 66 ; CHECK: pushq %rbx 67 ; CHECK: movaps %xmm0 68 ; CHECK: movaps {{.*}}, %xmm0 69 ; CHECK: popq %rbx 70 ; CHECK: popq %r11 71 ; CHECK: popq %rbp 72 ; CHECK: popq %rax 73 ; CHECK: addq $16, %rsp 74 ; CHECK: iretq 75 ; CHECK0-LABEL: test_isr_clobbers 76 77 ; CHECK0: pushq %rax 78 ; CHECK0: pushq %rbp 79 ; CHECK0: pushq %r11 80 ; CHECK0: pushq %rbx 81 ; CHECK0: movaps %xmm0 82 ; CHECK0: movaps {{.*}}, %xmm0 83 ; CHECK0: popq %rbx 84 ; CHECK0: popq %r11 85 ; CHECK0: popq %rbp 86 ; CHECK0: popq %rax 87 ; CHECK0: addq $16, %rsp 88 ; CHECK0: iretq 89 ret void 90 } 91 92 @f80 = common global x86_fp80 0xK00000000000000000000, align 4 93 94 ; Test that the presence of x87 does not crash the FP stackifier 95 define x86_intrcc void @test_isr_x87(%struct.interrupt_frame* %frame) { 96 ; CHECK-LABEL: test_isr_x87 97 ; CHECK-DAG: fldt f80 98 ; CHECK-DAG: fld1 99 ; CHECK: faddp 100 ; CHECK-NEXT: fstpt f80 101 ; CHECK-NEXT: iretq 102 entry: 103 %ld = load x86_fp80, x86_fp80* @f80, align 4 104 %add = fadd x86_fp80 %ld, 0xK3FFF8000000000000000 105 store x86_fp80 %add, x86_fp80* @f80, align 4 106 ret void 107 } 108
