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      1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
      2 
      3 
      4 // ------------------------------------------------------------------------- //
      5 // Invalid predicate
      6 
      7 fmla z0.h, p8/m, z1.h, z2.h
      8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
      9 // CHECK-NEXT: fmla z0.h, p8/m, z1.h, z2.h
     10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     11 
     12 
     13 // ------------------------------------------------------------------------- //
     14 // Invalid element width
     15 
     16 fmla z0.s, p7/m, z1.h, z2.h
     17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
     18 // CHECK-NEXT: fmla z0.s, p7/m, z1.h, z2.h
     19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     20 
     21 
     22 // ------------------------------------------------------------------------- //
     23 // z register out of range for index
     24 
     25 fmla z0.h, z1.h, z8.h[0]
     26 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
     27 // CHECK-NEXT: fmla z0.h, z1.h, z8.h[0]
     28 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     29 
     30 fmla z0.s, z1.s, z8.s[0]
     31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s
     32 // CHECK-NEXT: fmla z0.s, z1.s, z8.s[0]
     33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     34 
     35 fmla z0.d, z1.d, z16.s[0]
     36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
     37 // CHECK-NEXT: fmla z0.d, z1.d, z16.s[0]
     38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     39 
     40 
     41 // ------------------------------------------------------------------------- //
     42 // Invalid element index
     43 
     44 fmla z0.h, z1.h, z2.h[-1]
     45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
     46 // CHECK-NEXT: fmla z0.h, z1.h, z2.h[-1]
     47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     48 
     49 fmla z0.h, z1.h, z2.h[8]
     50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
     51 // CHECK-NEXT: fmla z0.h, z1.h, z2.h[8]
     52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     53 
     54 fmla z0.s, z1.s, z2.s[-1]
     55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
     56 // CHECK-NEXT: fmla z0.s, z1.s, z2.s[-1]
     57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     58 
     59 fmla z0.s, z1.s, z2.s[4]
     60 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
     61 // CHECK-NEXT: fmla z0.s, z1.s, z2.s[4]
     62 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     63 
     64 fmla z0.d, z1.d, z2.d[-1]
     65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
     66 // CHECK-NEXT: fmla z0.d, z1.d, z2.d[-1]
     67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     68 
     69 fmla z0.d, z1.d, z2.d[2]
     70 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
     71 // CHECK-NEXT: fmla z0.d, z1.d, z2.d[2]
     72 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     73 
     74 
     75 // --------------------------------------------------------------------------//
     76 // Negative tests for instructions that are incompatible with movprfx
     77 
     78 movprfx z0.d, p0/z, z7.d
     79 fmla z0.d, z1.d, z7.d[1]
     80 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
     81 // CHECK-NEXT: fmla z0.d, z1.d, z7.d[1]
     82 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
     83