1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s 2 3 // --------------------------------------------------------------------------// 4 // Immediate out of lower bound [-8, 7]. 5 6 ld1d z28.d, p2/z, [x28, #-9, MUL VL] 7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. 8 // CHECK-NEXT: ld1d z28.d, p2/z, [x28, #-9, MUL VL] 9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 10 11 ld1d z27.d, p1/z, [x26, #8, MUL VL] 12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. 13 // CHECK-NEXT: ld1d z27.d, p1/z, [x26, #8, MUL VL] 14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 15 16 17 // --------------------------------------------------------------------------// 18 // restricted predicate has range [0, 7]. 19 20 ld1d z4.d, p8/z, [x11, #1, MUL VL] 21 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. 22 // CHECK-NEXT: ld1d z4.d, p8/z, [x11, #1, MUL VL] 23 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 24 25 26 // --------------------------------------------------------------------------// 27 // Invalid vector list. 28 29 ld1d { }, p0/z, [x1, #1, MUL VL] 30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected 31 // CHECK-NEXT: ld1d { }, p0/z, [x1, #1, MUL VL] 32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 33 34 ld1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL] 35 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 36 // CHECK-NEXT: ld1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL] 37 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 38 39 ld1d { v0.2d }, p0/z, [x1, #1, MUL VL] 40 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 41 // CHECK-NEXT: ld1d { v0.2d }, p0/z, [x1, #1, MUL VL] 42 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 43 44 45 // --------------------------------------------------------------------------// 46 // Invalid scalar + scalar addressing modes 47 48 ld1d z0.d, p0/z, [x0, x0] 49 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' 50 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0] 51 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 52 53 ld1d z0.d, p0/z, [x0, xzr] 54 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' 55 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, xzr] 56 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 57 58 ld1d z0.d, p0/z, [x0, x0, lsl #2] 59 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' 60 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0, lsl #2] 61 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 62 63 ld1d z0.d, p0/z, [x0, w0] 64 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' 65 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0] 66 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 67 68 ld1d z0.d, p0/z, [x0, w0, uxtw] 69 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' 70 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0, uxtw] 71 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 72 73 74 // --------------------------------------------------------------------------// 75 // Invalid scalar + vector addressing modes 76 77 ld1d z0.d, p0/z, [x0, z0.s] 78 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 79 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.s] 80 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 81 82 ld1d z0.d, p0/z, [x0, z0.d, uxtw #2] 83 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' 84 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, uxtw #2] 85 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 86 87 ld1d z0.d, p0/z, [x0, z0.d, lsl #2] 88 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' 89 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl #2] 90 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 91 92 ld1d z0.d, p0/z, [x0, z0.d, lsl] 93 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier 94 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl] 95 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 96 97 98 // --------------------------------------------------------------------------// 99 // Invalid vector + immediate addressing modes 100 101 ld1d z0.s, p0/z, [z0.s] 102 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 103 // CHECK-NEXT: ld1d z0.s, p0/z, [z0.s] 104 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 105 106 ld1d z0.s, p0/z, [z0.s, #8] 107 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 108 // CHECK-NEXT: ld1d z0.s, p0/z, [z0.s, #8] 109 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 110 111 ld1d z0.d, p0/z, [z0.d, #-8] 112 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. 113 // CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #-8] 114 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 115 116 ld1d z0.d, p0/z, [z0.d, #-1] 117 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. 118 // CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #-1] 119 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 120 121 ld1d z0.d, p0/z, [z0.d, #249] 122 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. 123 // CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #249] 124 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 125 126 ld1d z0.d, p0/z, [z0.d, #256] 127 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. 128 // CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #256] 129 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 130 131 ld1d z0.d, p0/z, [z0.d, #3] 132 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. 133 // CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #3] 134 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 135 136 137 // --------------------------------------------------------------------------// 138 // Negative tests for instructions that are incompatible with movprfx 139 140 movprfx z0.d, p0/z, z7.d 141 ld1d { z0.d }, p0/z, [z0.d] 142 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 143 // CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d] 144 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 145 146 movprfx z0, z7 147 ld1d { z0.d }, p0/z, [z0.d] 148 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 149 // CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d] 150 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 151
