1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s 2 3 // --------------------------------------------------------------------------// 4 // Immediate out of lower bound [-128, 112]. 5 6 ld1rqb z0.b, p0/z, [x0, #-144] 7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112]. 8 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, #-144] 9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 10 11 ld1rqb z0.b, p0/z, [x0, #-129] 12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112]. 13 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, #-129] 14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 15 16 ld1rqb z0.b, p0/z, [x0, #113] 17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112]. 18 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, #113] 19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 20 21 ld1rqb z0.b, p0/z, [x0, #128] 22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112]. 23 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, #128] 24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 25 26 ld1rqb z0.b, p0/z, [x0, #12] 27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112]. 28 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, #12] 29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 30 31 32 // --------------------------------------------------------------------------// 33 // Invalid immediate suffix 34 35 ld1rqb z0.b, p0/z, [x0, #16, MUL VL] 36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 37 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, #16, MUL VL] 38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 39 40 41 // --------------------------------------------------------------------------// 42 // Invalid destination register width. 43 44 ld1rqb z0.h, p0/z, [x0] 45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 46 // CHECK-NEXT: ld1rqb z0.h, p0/z, [x0] 47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 48 49 ld1rqb z0.s, p0/z, [x0] 50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 51 // CHECK-NEXT: ld1rqb z0.s, p0/z, [x0] 52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 53 54 ld1rqb z0.d, p0/z, [x0] 55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 56 // CHECK-NEXT: ld1rqb z0.d, p0/z, [x0] 57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 58 59 60 // --------------------------------------------------------------------------// 61 // Invalid scalar + scalar addressing modes 62 63 ld1rqb z0.b, p0/z, [x0, xzr] 64 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift 65 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, xzr] 66 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 67 68 ld1rqb z0.b, p0/z, [x0, x1, lsl #1] 69 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift 70 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, x1, lsl #1] 71 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 72 73 ld1rqb z0.b, p0/z, [x0, w1] 74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift 75 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, w1] 76 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 77 78 ld1rqb z0.b, p0/z, [x0, w1, uxtw] 79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift 80 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, w1, uxtw] 81 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 82 83 84 // --------------------------------------------------------------------------// 85 // Negative tests for instructions that are incompatible with movprfx 86 87 movprfx z21.b, p5/z, z28.b 88 ld1rqb { z21.b }, p5/z, [x10, #112] 89 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 90 // CHECK-NEXT: ld1rqb { z21.b }, p5/z, [x10, #112] 91 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 92 93 movprfx z21, z28 94 ld1rqb { z21.b }, p5/z, [x10, #112] 95 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 96 // CHECK-NEXT: ld1rqb { z21.b }, p5/z, [x10, #112] 97 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 98
