1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s 2 3 // --------------------------------------------------------------------------// 4 // Immediate out of lower bound [-8, 7]. 5 6 st1d z25.d, p4, [x16, #-9, MUL VL] 7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. 8 // CHECK-NEXT: st1d z25.d, p4, [x16, #-9, MUL VL] 9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 10 11 // Immediate out of upper bound [-8, 7]. 12 st1d z16.d, p4, [x2, #8, MUL VL] 13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. 14 // CHECK-NEXT: st1d z16.d, p4, [x2, #8, MUL VL] 15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 16 17 // --------------------------------------------------------------------------// 18 // Restricted predicate has range [0, 7]. 19 20 st1d z12.d, p8, [x4, #14, MUL VL] 21 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. 22 // CHECK-NEXT: st1d z12.d, p8, [x4, #14, MUL VL] 23 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 24 25 // --------------------------------------------------------------------------// 26 // Invalid vector list 27 28 st1d { }, p0, [x0] 29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected 30 // CHECK-NEXT: st1d { }, p0, [x0] 31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 32 33 st1d { z1.d, z2.d }, p0, [x0] 34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 35 // CHECK-NEXT: st1d { z1.d, z2.d }, p0, [x0] 36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 37 38 st1d { v0.2d }, p0, [x0] 39 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 40 // CHECK-NEXT: st1d { v0.2d }, p0, [x0] 41 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 42 43 44 // --------------------------------------------------------------------------// 45 // Invalid scalar + scalar addressing modes 46 47 st1d z0.d, p0, [x0, x0] 48 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' 49 // CHECK-NEXT: st1d z0.d, p0, [x0, x0] 50 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 51 52 st1d z0.d, p0, [x0, xzr] 53 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' 54 // CHECK-NEXT: st1d z0.d, p0, [x0, xzr] 55 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 56 57 st1d z0.d, p0, [x0, x0, lsl #2] 58 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' 59 // CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2] 60 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 61 62 st1d z0.d, p0, [x0, w0] 63 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' 64 // CHECK-NEXT: st1d z0.d, p0, [x0, w0] 65 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 66 67 st1d z0.d, p0, [x0, w0, uxtw] 68 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' 69 // CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw] 70 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 71 72 73 // --------------------------------------------------------------------------// 74 // Invalid scalar + vector addressing modes 75 76 st1d z0.d, p0, [x0, z0.s] 77 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 78 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.s] 79 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 80 81 st1d z0.d, p0, [x0, z0.d, uxtw #2] 82 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' 83 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, uxtw #2] 84 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 85 86 st1d z0.d, p0, [x0, z0.d, lsl #2] 87 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' 88 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl #2] 89 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 90 91 st1d z0.d, p0, [x0, z0.d, lsl] 92 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier 93 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl] 94 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 95 96 97 // --------------------------------------------------------------------------// 98 // Invalid vector + immediate addressing modes 99 100 st1d z0.s, p0, [z0.s] 101 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 102 // CHECK-NEXT: st1d z0.s, p0, [z0.s] 103 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 104 105 st1d z0.s, p0, [z0.s, #8] 106 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 107 // CHECK-NEXT: st1d z0.s, p0, [z0.s, #8] 108 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 109 110 st1d z0.d, p0, [z0.d, #-1] 111 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. 112 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #-1] 113 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 114 115 st1d z0.d, p0, [z0.d, #-8] 116 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. 117 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #-8] 118 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 119 120 st1d z0.d, p0, [z0.d, #249] 121 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. 122 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #249] 123 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 124 125 st1d z0.d, p0, [z0.d, #256] 126 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. 127 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #256] 128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 129 130 st1d z0.d, p0, [z0.d, #3] 131 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. 132 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #3] 133 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 134 135 136 // --------------------------------------------------------------------------// 137 // Negative tests for instructions that are incompatible with movprfx 138 139 movprfx z31.d, p7/z, z6.d 140 st1d { z31.d }, p7, [z31.d, #248] 141 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 142 // CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248] 143 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 144 145 movprfx z31, z6 146 st1d { z31.d }, p7, [z31.d, #248] 147 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 148 // CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248] 149 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 150
