1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s 2 3 4 // --------------------------------------------------------------------------// 5 // Immediate out of lower bound [-32, 28]. 6 7 st4b {z12.b, z13.b, z14.b, z15.b}, p4, [x12, #-36, MUL VL] 8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. 9 // CHECK-NEXT: st4b {z12.b, z13.b, z14.b, z15.b}, p4, [x12, #-36, MUL VL] 10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 11 12 st4b {z7.b, z8.b, z9.b, z10.b}, p3, [x1, #32, MUL VL] 13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. 14 // CHECK-NEXT: st4b {z7.b, z8.b, z9.b, z10.b}, p3, [x1, #32, MUL VL] 15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 16 17 18 // --------------------------------------------------------------------------// 19 // Immediate not a multiple of four. 20 21 st4b {z12.b, z13.b, z14.b, z15.b}, p4, [x12, #-7, MUL VL] 22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. 23 // CHECK-NEXT: st4b {z12.b, z13.b, z14.b, z15.b}, p4, [x12, #-7, MUL VL] 24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 25 26 st4b {z7.b, z8.b, z9.b, z10.b}, p3, [x1, #5, MUL VL] 27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. 28 // CHECK-NEXT: st4b {z7.b, z8.b, z9.b, z10.b}, p3, [x1, #5, MUL VL] 29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 30 31 32 // --------------------------------------------------------------------------// 33 // Invalid scalar + scalar addressing modes 34 35 st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, xzr] 36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift 37 // CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, xzr] 38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 39 40 st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0, lsl #1] 41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift 42 // CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0, lsl #1] 43 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 44 45 st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0] 46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift 47 // CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0] 48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 49 50 st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0, uxtw] 51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift 52 // CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0, uxtw] 53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 54 55 56 // --------------------------------------------------------------------------// 57 // error: restricted predicate has range [0, 7]. 58 59 st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL] 60 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. 61 // CHECK-NEXT: st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL] 62 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 63 64 65 // --------------------------------------------------------------------------// 66 // Invalid vector list. 67 68 st4b { }, p0, [x0] 69 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected 70 // CHECK-NEXT: st4b { }, p0, [x0] 71 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 72 73 st4b { z0.b, z1.b, z2.b, z3.b, z4.b }, p0, [x0] 74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors 75 // CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b, z4.b }, p0, [x0] 76 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 77 78 st4b { z0.b, z1.b, z2.b, z3.h }, p0, [x0] 79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix 80 // CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.h }, p0, [x0] 81 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 82 83 st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0] 84 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential 85 // CHECK-NEXT: st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0] 86 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 87 88 st4b { v0.16b, v1.16b, v2.16b }, p0, [x0] 89 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 90 // CHECK-NEXT: st4b { v0.16b, v1.16b, v2.16b }, p0, [x0] 91 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 92 93 94 // --------------------------------------------------------------------------// 95 // Negative tests for instructions that are incompatible with movprfx 96 97 movprfx z21.b, p5/z, z28.b 98 st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] 99 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 100 // CHECK-NEXT: st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] 101 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 102 103 movprfx z21, z28 104 st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] 105 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 106 // CHECK-NEXT: st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] 107 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 108
