1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s 2 3 4 // --------------------------------------------------------------------------// 5 // Immediate out of lower bound [-32, 28]. 6 7 st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-36, MUL VL] 8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. 9 // CHECK-NEXT: st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-36, MUL VL] 10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 11 12 st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #32, MUL VL] 13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. 14 // CHECK-NEXT: st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #32, MUL VL] 15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 16 17 18 // --------------------------------------------------------------------------// 19 // Immediate not a multiple of four. 20 21 st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-7, MUL VL] 22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. 23 // CHECK-NEXT: st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-7, MUL VL] 24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 25 26 st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #5, MUL VL] 27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. 28 // CHECK-NEXT: st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #5, MUL VL] 29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 30 31 32 // --------------------------------------------------------------------------// 33 // Invalid scalar + scalar addressing modes 34 35 st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0] 36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' 37 // CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0] 38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 39 40 st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, xzr] 41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' 42 // CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, xzr] 43 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 44 45 st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #2] 46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' 47 // CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #2] 48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 49 50 st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0] 51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' 52 // CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0] 53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 54 55 st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw] 56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' 57 // CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw] 58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 59 60 61 // --------------------------------------------------------------------------// 62 // error: restricted predicate has range [0, 7]. 63 64 st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL] 65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. 66 // CHECK-NEXT: st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL] 67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 68 69 70 // --------------------------------------------------------------------------// 71 // Invalid vector list. 72 73 st4h { }, p0, [x0] 74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected 75 // CHECK-NEXT: st4h { }, p0, [x0] 76 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 77 78 st4h { z0.h, z1.h, z2.h, z3.h, z4.h }, p0, [x0] 79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors 80 // CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h, z4.h }, p0, [x0] 81 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 82 83 st4h { z0.h, z1.h, z2.h, z3.s }, p0, [x0] 84 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix 85 // CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.s }, p0, [x0] 86 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 87 88 st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0] 89 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential 90 // CHECK-NEXT: st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0] 91 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 92 93 st4h { v0.8h, v1.8h, v2.8h }, p0, [x0] 94 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 95 // CHECK-NEXT: st4h { v0.8h, v1.8h, v2.8h }, p0, [x0] 96 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 97 98 99 // --------------------------------------------------------------------------// 100 // Negative tests for instructions that are incompatible with movprfx 101 102 movprfx z21.h, p5/z, z28.h 103 st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] 104 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 105 // CHECK-NEXT: st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] 106 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 107 108 movprfx z21, z28 109 st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] 110 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 111 // CHECK-NEXT: st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] 112 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 113
