1 # RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V62 2 # RUN: not llvm-mc -arch=hexagon -mcpu=hexagonv60 -filetype=asm %s 2>%t; FileCheck -check-prefix=CHECK-NOV62 %s < %t 3 # 4 5 # Assure that v62 added registers are understood 6 7 r0=framelimit 8 r0=framekey 9 r1:0=c17:16 10 11 # CHECK-V62: 6a10c000 { r0 = framelimit } 12 # CHECK-V62: 6a11c000 { r0 = framekey } 13 # CHECK-V62: 6810c000 { r1:0 = c17:16 } 14 # CHECK-NOV62: rror: invalid operand for instruction 15 # CHECK-NOV62: rror: invalid operand for instruction 16 # CHECK-NOV62: rror: invalid operand for instruction 17 18 r0=pktcountlo 19 r0=pktcounthi 20 r1:0=c19:18 21 r1:0=pktcount 22 23 # CHECK-V62: 6a12c000 { r0 = pktcountlo } 24 # CHECK-V62: 6a13c000 { r0 = pktcounthi } 25 # CHECK-V62: 6812c000 { r1:0 = c19:18 } 26 # CHECK-V62: 6812c000 { r1:0 = c19:18 } 27 # CHECK-NOV62: rror: invalid operand for instruction 28 # CHECK-NOV62: rror: invalid operand for instruction 29 # CHECK-NOV62: rror: invalid operand for instruction 30 # CHECK-NOV62: rror: invalid operand for instruction 31 32 r0=utimerlo 33 r0=utimerhi 34 r1:0=c31:30 35 r1:0=UTIMER 36 37 # CHECK-V62: 6a1ec000 { r0 = utimerlo } 38 # CHECK-V62: 6a1fc000 { r0 = utimerhi } 39 # CHECK-V62: 681ec000 { r1:0 = c31:30 } 40 # CHECK-V62: 681ec000 { r1:0 = c31:30 } 41 # CHECK-NOV62: rror: invalid operand for instruction 42 # CHECK-NOV62: rror: invalid operand for instruction 43 # CHECK-NOV62: rror: invalid operand for instruction 44 # CHECK-NOV62: rror: invalid operand for instruction 45
