1 // RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s 2 // Checks that tablegen correctly and completely infers subregister relations. 3 include "llvm/Target/Target.td" 4 5 class MyReg<string n, list<Register> subregs = []> 6 : Register<n> { 7 let Namespace = "Test"; 8 let SubRegs = subregs; 9 let CoveredBySubRegs = 1; 10 } 11 class MyClass<int size, list<ValueType> types, dag registers> 12 : RegisterClass<"Test", types, size, registers> { 13 let Size = size; 14 } 15 16 // Register Example: 17 // D0_D1 -- D0 (sub0) -- S0 (ssub0) 18 // \ \- S1 (ssub1) 19 // \ D1 (sub1) -- S2 (ssub2) 20 // \- S3 (ssub3) 21 22 def sub0 : SubRegIndex<32>; 23 def sub1 : SubRegIndex<32, 32>; 24 def sub2 : SubRegIndex<32, 64>; 25 26 def ssub0 : SubRegIndex<16>; 27 def ssub1 : SubRegIndex<16, 16>; 28 def ssub2 : ComposedSubRegIndex<sub1, ssub0>; 29 def ssub3 : ComposedSubRegIndex<sub1, ssub1>; 30 def ssub4 : ComposedSubRegIndex<sub2, ssub0>; 31 32 def S0 : MyReg<"s0">; 33 def S1 : MyReg<"s1">; 34 def S2 : MyReg<"s2">; 35 def S3 : MyReg<"s3">; 36 def S4 : MyReg<"s4">; 37 def S5 : MyReg<"s5">; 38 def S6 : MyReg<"s6">; 39 def S7 : MyReg<"s7">; 40 def S8 : MyReg<"s8">; 41 def S9 : MyReg<"s9">; 42 def S10 : MyReg<"s10">; 43 def S11 : MyReg<"s11">; 44 def S12 : MyReg<"s12">; 45 def S13 : MyReg<"s13">; 46 def S14 : MyReg<"s14">; 47 def S15 : MyReg<"s15">; 48 def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>; 49 50 let SubRegIndices = [ssub0, ssub1] in { 51 def D0 : MyReg<"d0", [S0, S1]>; 52 def D1 : MyReg<"d1", [S2, S3]>; 53 def D2 : MyReg<"d2", [S4, S5]>; 54 def D3 : MyReg<"d3", [S6, S7]>; 55 def D4 : MyReg<"d4", [S8, S9]>; 56 def D5 : MyReg<"d5", [S10, S11]>; 57 def D6 : MyReg<"d6", [S12, S13]>; 58 def D7 : MyReg<"d7", [S14, S15]>; 59 } 60 def DRegs : MyClass<32, [i32], (sequence "D%u", 0, 7)>; 61 62 def Dtup2regs : RegisterTuples<[sub0, sub1], 63 [(shl DRegs, 0), (shl DRegs, 1)]>; 64 def Dtup2 : MyClass<64, [untyped], (add Dtup2regs)>; 65 66 def Stup2_odds_regs : RegisterTuples<[ssub0, ssub1], 67 [(decimate (shl SRegs, 1), 2), 68 (decimate (shl SRegs, 2), 2)]>; 69 def Stup2 : MyClass<32, [untyped], (interleave DRegs, Stup2_odds_regs)>; 70 71 def Stup5 : RegisterTuples<[ssub0, ssub1, ssub2, ssub3, ssub4], [ 72 (shl SRegs, 0), 73 (shl SRegs, 1), 74 (shl SRegs, 2), 75 (shl SRegs, 3), 76 (shl SRegs, 4) 77 ]>; 78 79 80 def TestTarget : Target; 81 82 // CHECK-LABEL: RegisterClass SRegs: 83 // CHECK: CoveredBySubRegs: 1 84 // CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 85 86 // CHECK-LABEL: RegisterClass Stup2: 87 // CHECK: CoveredBySubRegs: 1 88 // CHECK: Regs: D0 D1 D2 D3 D4 D5 D6 D7 S1_S2 S3_S4 S5_S6 S7_S8 S9_S10 S11_S12 S13_S14 89 // CHECK-LABEL: RegisterClass DRegs: 90 91 // CHECK-LABEL: SubRegIndex sub0: 92 // CHECK-LABEL: SubRegIndex sub1: 93 // CHECK-LABEL: SubRegIndex sub2: 94 // Check infered indexes: 95 // CHECK: SubRegIndex ssub1_ssub2: 96 // CHECK: SubRegIndex ssub3_ssub4: 97 // CHECK: SubRegIndex ssub0_ssub1_ssub2_ssub3: 98 // CHECK: SubRegIndex ssub1_ssub2_ssub3_ssub4: 99 100 // Check that all subregs are generated on some examples 101 // CHECK-LABEL: Register D0: 102 // CHECK: HasDisjunctSubRegs: 1 103 // CHECK-NEXT: SubReg ssub0 = S0 104 // CHECK-NEXT: SubReg ssub1 = S1 105 106 // CHECK-LABEL: Register S9_S10_S11_S12_S13: 107 // CHECK: HasDisjunctSubRegs: 1 108 // CHECK-NEXT: SubReg ssub0 = S9 109 // CHECK-NEXT: SubReg ssub1 = S10 110 // CHECK-NEXT: SubReg ssub2 = S11 111 // CHECK-NEXT: SubReg ssub3 = S12 112 // CHECK-NEXT: SubReg ssub4 = S13 113 // CHECK-NEXT: SubReg sub0 = S9_S10 114 // CHECK-NEXT: SubReg sub1 = S11_S12 115 // CHECK-NEXT: SubReg ssub1_ssub2 = D5 116 // CHECK-NEXT: SubReg ssub3_ssub4 = D6 117 // CHECK-NEXT: SubReg ssub1_ssub2_ssub3_ssub4 = D5_D6 118 119 // CHECK-LABEL: Register S10_S11_S12_S13_S14: 120 // CHECK: HasDisjunctSubRegs: 1 121 // CHECK-NEXT: SubReg ssub0 = S10 122 // CHECK-NEXT: SubReg ssub1 = S11 123 // CHECK-NEXT: SubReg ssub2 = S12 124 // CHECK-NEXT: SubReg ssub3 = S13 125 // CHECK-NEXT: SubReg ssub4 = S14 126 // CHECK-NEXT: SubReg sub0 = D5 127 // CHECK-NEXT: SubReg sub1 = D6 128 // CHECK-NEXT: SubReg ssub1_ssub2 = S11_S12 129 // CHECK-NEXT: SubReg ssub3_ssub4 = S13_S14 130 // CHECK-NEXT: SubReg ssub0_ssub1_ssub2_ssub3 = D5_D6 131
