1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2 ; RUN: opt < %s -instsimplify -S | FileCheck %s 3 4 define i47 @shl_by_0(i47 %A) { 5 ; CHECK-LABEL: @shl_by_0( 6 ; CHECK-NEXT: ret i47 [[A:%.*]] 7 ; 8 %B = shl i47 %A, 0 9 ret i47 %B 10 } 11 12 define i41 @shl_0(i41 %X) { 13 ; CHECK-LABEL: @shl_0( 14 ; CHECK-NEXT: ret i41 0 15 ; 16 %B = shl i41 0, %X 17 ret i41 %B 18 } 19 20 define <2 x i41> @shl_0_vec_undef_elt(<2 x i41> %X) { 21 ; CHECK-LABEL: @shl_0_vec_undef_elt( 22 ; CHECK-NEXT: ret <2 x i41> zeroinitializer 23 ; 24 %B = shl <2 x i41> <i41 0, i41 undef>, %X 25 ret <2 x i41> %B 26 } 27 28 define i41 @ashr_by_0(i41 %A) { 29 ; CHECK-LABEL: @ashr_by_0( 30 ; CHECK-NEXT: ret i41 [[A:%.*]] 31 ; 32 %B = ashr i41 %A, 0 33 ret i41 %B 34 } 35 36 define i39 @ashr_0(i39 %X) { 37 ; CHECK-LABEL: @ashr_0( 38 ; CHECK-NEXT: ret i39 0 39 ; 40 %B = ashr i39 0, %X 41 ret i39 %B 42 } 43 44 define <2 x i141> @ashr_0_vec_undef_elt(<2 x i141> %X) { 45 ; CHECK-LABEL: @ashr_0_vec_undef_elt( 46 ; CHECK-NEXT: ret <2 x i141> zeroinitializer 47 ; 48 %B = shl <2 x i141> <i141 undef, i141 0>, %X 49 ret <2 x i141> %B 50 } 51 52 define i55 @lshr_by_bitwidth(i55 %A) { 53 ; CHECK-LABEL: @lshr_by_bitwidth( 54 ; CHECK-NEXT: ret i55 undef 55 ; 56 %B = lshr i55 %A, 55 57 ret i55 %B 58 } 59 60 define i32 @shl_by_bitwidth(i32 %A) { 61 ; CHECK-LABEL: @shl_by_bitwidth( 62 ; CHECK-NEXT: ret i32 undef 63 ; 64 %B = shl i32 %A, 32 65 ret i32 %B 66 } 67 68 define <4 x i32> @lshr_by_bitwidth_splat(<4 x i32> %A) { 69 ; CHECK-LABEL: @lshr_by_bitwidth_splat( 70 ; CHECK-NEXT: ret <4 x i32> undef 71 ; 72 %B = lshr <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out 73 ret <4 x i32> %B 74 } 75 76 define <4 x i32> @lshr_by_0_splat(<4 x i32> %A) { 77 ; CHECK-LABEL: @lshr_by_0_splat( 78 ; CHECK-NEXT: ret <4 x i32> [[A:%.*]] 79 ; 80 %B = lshr <4 x i32> %A, zeroinitializer 81 ret <4 x i32> %B 82 } 83 84 define <4 x i32> @shl_by_bitwidth_splat(<4 x i32> %A) { 85 ; CHECK-LABEL: @shl_by_bitwidth_splat( 86 ; CHECK-NEXT: ret <4 x i32> undef 87 ; 88 %B = shl <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out 89 ret <4 x i32> %B 90 } 91 92 define i32 @ashr_undef() { 93 ; CHECK-LABEL: @ashr_undef( 94 ; CHECK-NEXT: ret i32 0 95 ; 96 %B = ashr i32 undef, 2 ;; top two bits must be equal, so not undef 97 ret i32 %B 98 } 99 100 define i32 @ashr_undef_variable_shift_amount(i32 %A) { 101 ; CHECK-LABEL: @ashr_undef_variable_shift_amount( 102 ; CHECK-NEXT: ret i32 0 103 ; 104 %B = ashr i32 undef, %A ;; top %A bits must be equal, so not undef 105 ret i32 %B 106 } 107 108 define i32 @ashr_all_ones(i32 %A) { 109 ; CHECK-LABEL: @ashr_all_ones( 110 ; CHECK-NEXT: ret i32 -1 111 ; 112 %B = ashr i32 -1, %A 113 ret i32 %B 114 } 115 116 define <3 x i8> @ashr_all_ones_vec_with_undef_elts(<3 x i8> %x, <3 x i8> %y) { 117 ; CHECK-LABEL: @ashr_all_ones_vec_with_undef_elts( 118 ; CHECK-NEXT: ret <3 x i8> <i8 -1, i8 -1, i8 -1> 119 ; 120 %sh = ashr <3 x i8> <i8 undef, i8 -1, i8 undef>, %y 121 ret <3 x i8> %sh 122 } 123 124 define i8 @lshr_by_sext_bool(i1 %x, i8 %y) { 125 ; CHECK-LABEL: @lshr_by_sext_bool( 126 ; CHECK-NEXT: ret i8 [[Y:%.*]] 127 ; 128 %s = sext i1 %x to i8 129 %r = lshr i8 %y, %s 130 ret i8 %r 131 } 132 133 define <2 x i8> @lshr_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) { 134 ; CHECK-LABEL: @lshr_by_sext_bool_vec( 135 ; CHECK-NEXT: ret <2 x i8> [[Y:%.*]] 136 ; 137 %s = sext <2 x i1> %x to <2 x i8> 138 %r = lshr <2 x i8> %y, %s 139 ret <2 x i8> %r 140 } 141 142 define i8 @ashr_by_sext_bool(i1 %x, i8 %y) { 143 ; CHECK-LABEL: @ashr_by_sext_bool( 144 ; CHECK-NEXT: ret i8 [[Y:%.*]] 145 ; 146 %s = sext i1 %x to i8 147 %r = ashr i8 %y, %s 148 ret i8 %r 149 } 150 151 define <2 x i8> @ashr_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) { 152 ; CHECK-LABEL: @ashr_by_sext_bool_vec( 153 ; CHECK-NEXT: ret <2 x i8> [[Y:%.*]] 154 ; 155 %s = sext <2 x i1> %x to <2 x i8> 156 %r = ashr <2 x i8> %y, %s 157 ret <2 x i8> %r 158 } 159 160 define i8 @shl_by_sext_bool(i1 %x, i8 %y) { 161 ; CHECK-LABEL: @shl_by_sext_bool( 162 ; CHECK-NEXT: ret i8 [[Y:%.*]] 163 ; 164 %s = sext i1 %x to i8 165 %r = shl i8 %y, %s 166 ret i8 %r 167 } 168 169 define <2 x i8> @shl_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) { 170 ; CHECK-LABEL: @shl_by_sext_bool_vec( 171 ; CHECK-NEXT: ret <2 x i8> [[Y:%.*]] 172 ; 173 %s = sext <2 x i1> %x to <2 x i8> 174 %r = shl <2 x i8> %y, %s 175 ret <2 x i8> %r 176 } 177 178 define i64 @shl_or_shr(i32 %a, i32 %b) { 179 ; CHECK-LABEL: @shl_or_shr( 180 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64 181 ; CHECK-NEXT: ret i64 [[TMP1]] 182 ; 183 %tmp1 = zext i32 %a to i64 184 %tmp2 = zext i32 %b to i64 185 %tmp3 = shl nuw i64 %tmp1, 32 186 %tmp4 = or i64 %tmp2, %tmp3 187 %tmp5 = lshr i64 %tmp4, 32 188 ret i64 %tmp5 189 } 190 191 ; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated. 192 define i64 @shl_or_shr2(i32 %a, i32 %b) { 193 ; CHECK-LABEL: @shl_or_shr2( 194 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64 195 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64 196 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 31 197 ; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]] 198 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 31 199 ; CHECK-NEXT: ret i64 [[TMP5]] 200 ; 201 %tmp1 = zext i32 %a to i64 202 %tmp2 = zext i32 %b to i64 203 %tmp3 = shl nuw i64 %tmp1, 31 204 %tmp4 = or i64 %tmp2, %tmp3 205 %tmp5 = lshr i64 %tmp4, 31 206 ret i64 %tmp5 207 } 208 209 ; Unit test for vector integer 210 define <2 x i64> @shl_or_shr1v(<2 x i32> %a, <2 x i32> %b) { 211 ; CHECK-LABEL: @shl_or_shr1v( 212 ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> 213 ; CHECK-NEXT: ret <2 x i64> [[TMP1]] 214 ; 215 %tmp1 = zext <2 x i32> %a to <2 x i64> 216 %tmp2 = zext <2 x i32> %b to <2 x i64> 217 %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32> 218 %tmp4 = or <2 x i64> %tmp3, %tmp2 219 %tmp5 = lshr <2 x i64> %tmp4, <i64 32, i64 32> 220 ret <2 x i64> %tmp5 221 } 222 223 ; Negative unit test for vector integer 224 define <2 x i64> @shl_or_shr2v(<2 x i32> %a, <2 x i32> %b) { 225 ; CHECK-LABEL: @shl_or_shr2v( 226 ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> 227 ; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64> 228 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 31, i64 31> 229 ; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]] 230 ; CHECK-NEXT: [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], <i64 31, i64 31> 231 ; CHECK-NEXT: ret <2 x i64> [[TMP5]] 232 ; 233 %tmp1 = zext <2 x i32> %a to <2 x i64> 234 %tmp2 = zext <2 x i32> %b to <2 x i64> 235 %tmp3 = shl nuw <2 x i64> %tmp1, <i64 31, i64 31> 236 %tmp4 = or <2 x i64> %tmp2, %tmp3 237 %tmp5 = lshr <2 x i64> %tmp4, <i64 31, i64 31> 238 ret <2 x i64> %tmp5 239 } 240
