1 ; RUN: opt < %s -basicaa -licm -S | FileCheck %s 2 ; RUN: opt < %s -debugify -basicaa -licm -S | FileCheck %s -check-prefix=DEBUGIFY 3 4 declare i32 @strlen(i8*) readonly nounwind 5 6 declare void @foo() 7 8 ; Sink readonly function. 9 define i32 @test1(i8* %P) { 10 br label %Loop 11 12 Loop: ; preds = %Loop, %0 13 %A = call i32 @strlen( i8* %P ) readonly 14 br i1 false, label %Loop, label %Out 15 16 Out: ; preds = %Loop 17 ret i32 %A 18 ; CHECK-LABEL: @test1( 19 ; CHECK: Out: 20 ; CHECK-NEXT: call i32 @strlen 21 ; CHECK-NEXT: ret i32 %A 22 } 23 24 declare double @sin(double) readnone nounwind 25 26 ; Sink readnone function out of loop with unknown memory behavior. 27 define double @test2(double %X) { 28 br label %Loop 29 30 Loop: ; preds = %Loop, %0 31 call void @foo( ) 32 %A = call double @sin( double %X ) readnone 33 br i1 true, label %Loop, label %Out 34 35 Out: ; preds = %Loop 36 ret double %A 37 ; CHECK-LABEL: @test2( 38 ; CHECK: Out: 39 ; CHECK-NEXT: call double @sin 40 ; CHECK-NEXT: ret double %A 41 } 42 43 ; This testcase checks to make sure the sinker does not cause problems with 44 ; critical edges. 45 define void @test3() { 46 Entry: 47 br i1 false, label %Loop, label %Exit 48 Loop: 49 %X = add i32 0, 1 50 br i1 false, label %Loop, label %Exit 51 Exit: 52 %Y = phi i32 [ 0, %Entry ], [ %X, %Loop ] 53 ret void 54 55 ; CHECK-LABEL: @test3( 56 ; CHECK: Exit.loopexit: 57 ; CHECK-NEXT: %X.le = add i32 0, 1 58 ; CHECK-NEXT: br label %Exit 59 60 } 61 62 ; If the result of an instruction is only used outside of the loop, sink 63 ; the instruction to the exit blocks instead of executing it on every 64 ; iteration of the loop. 65 ; 66 define i32 @test4(i32 %N) { 67 Entry: 68 br label %Loop 69 Loop: ; preds = %Loop, %Entry 70 %N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ] 71 %tmp.6 = mul i32 %N, %N_addr.0.pn ; <i32> [#uses=1] 72 %tmp.7 = sub i32 %tmp.6, %N ; <i32> [#uses=1] 73 %dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1] 74 %tmp.1 = icmp ne i32 %N_addr.0.pn, 1 ; <i1> [#uses=1] 75 br i1 %tmp.1, label %Loop, label %Out 76 Out: ; preds = %Loop 77 ret i32 %tmp.7 78 ; CHECK-LABEL: @test4( 79 ; CHECK: Out: 80 ; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn 81 ; CHECK-NEXT: mul i32 %N, %[[LCSSAPHI]] 82 ; CHECK-NEXT: sub i32 %tmp.6.le, %N 83 ; CHECK-NEXT: ret i32 84 } 85 86 ; To reduce register pressure, if a load is hoistable out of the loop, and the 87 ; result of the load is only used outside of the loop, sink the load instead of 88 ; hoisting it! 89 ; 90 @X = global i32 5 ; <i32*> [#uses=1] 91 92 define i32 @test5(i32 %N) { 93 Entry: 94 br label %Loop 95 Loop: ; preds = %Loop, %Entry 96 %N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ] 97 %tmp.6 = load i32, i32* @X ; <i32> [#uses=1] 98 %dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1] 99 %tmp.1 = icmp ne i32 %N_addr.0.pn, 1 ; <i1> [#uses=1] 100 br i1 %tmp.1, label %Loop, label %Out 101 Out: ; preds = %Loop 102 ret i32 %tmp.6 103 ; CHECK-LABEL: @test5( 104 ; CHECK: Out: 105 ; CHECK-NEXT: %tmp.6.le = load i32, i32* @X 106 ; CHECK-NEXT: ret i32 %tmp.6.le 107 } 108 109 110 111 ; The loop sinker was running from the bottom of the loop to the top, causing 112 ; it to miss opportunities to sink instructions that depended on sinking other 113 ; instructions from the loop. Instead they got hoisted, which is better than 114 ; leaving them in the loop, but increases register pressure pointlessly. 115 116 %Ty = type { i32, i32 } 117 @X2 = external global %Ty 118 119 define i32 @test6() { 120 br label %Loop 121 Loop: 122 %dead = getelementptr %Ty, %Ty* @X2, i64 0, i32 0 123 %sunk2 = load i32, i32* %dead 124 br i1 false, label %Loop, label %Out 125 Out: ; preds = %Loop 126 ret i32 %sunk2 127 ; CHECK-LABEL: @test6( 128 ; CHECK: Out: 129 ; CHECK-NEXT: %dead.le = getelementptr %Ty, %Ty* @X2, i64 0, i32 0 130 ; CHECK-NEXT: %sunk2.le = load i32, i32* %dead.le 131 ; CHECK-NEXT: ret i32 %sunk2.le 132 } 133 134 135 136 ; This testcase ensures that we can sink instructions from loops with 137 ; multiple exits. 138 ; 139 define i32 @test7(i32 %N, i1 %C) { 140 Entry: 141 br label %Loop 142 Loop: ; preds = %ContLoop, %Entry 143 %N_addr.0.pn = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ] 144 %tmp.6 = mul i32 %N, %N_addr.0.pn 145 %tmp.7 = sub i32 %tmp.6, %N ; <i32> [#uses=2] 146 %dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1] 147 br i1 %C, label %ContLoop, label %Out1 148 ContLoop: 149 %tmp.1 = icmp ne i32 %N_addr.0.pn, 1 150 br i1 %tmp.1, label %Loop, label %Out2 151 Out1: ; preds = %Loop 152 ret i32 %tmp.7 153 Out2: ; preds = %ContLoop 154 ret i32 %tmp.7 155 ; CHECK-LABEL: @test7( 156 ; CHECK: Out1: 157 ; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn 158 ; CHECK-NEXT: mul i32 %N, %[[LCSSAPHI]] 159 ; CHECK-NEXT: sub i32 %tmp.6.le, %N 160 ; CHECK-NEXT: ret 161 ; CHECK: Out2: 162 ; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn 163 ; CHECK-NEXT: mul i32 %N, %[[LCSSAPHI]] 164 ; CHECK-NEXT: sub i32 %tmp.6.le4, %N 165 ; CHECK-NEXT: ret 166 } 167 168 169 ; This testcase checks to make sure we can sink values which are only live on 170 ; some exits out of the loop, and that we can do so without breaking dominator 171 ; info. 172 define i32 @test8(i1 %C1, i1 %C2, i32* %P, i32* %Q) { 173 Entry: 174 br label %Loop 175 Loop: ; preds = %Cont, %Entry 176 br i1 %C1, label %Cont, label %exit1 177 Cont: ; preds = %Loop 178 %X = load i32, i32* %P ; <i32> [#uses=2] 179 store i32 %X, i32* %Q 180 %V = add i32 %X, 1 ; <i32> [#uses=1] 181 br i1 %C2, label %Loop, label %exit2 182 exit1: ; preds = %Loop 183 ret i32 0 184 exit2: ; preds = %Cont 185 ret i32 %V 186 ; CHECK-LABEL: @test8( 187 ; CHECK: exit1: 188 ; CHECK-NEXT: ret i32 0 189 ; CHECK: exit2: 190 ; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %X 191 ; CHECK-NEXT: %V.le = add i32 %[[LCSSAPHI]], 1 192 ; CHECK-NEXT: ret i32 %V.le 193 } 194 195 196 define void @test9() { 197 loopentry.2.i: 198 br i1 false, label %no_exit.1.i.preheader, label %loopentry.3.i.preheader 199 no_exit.1.i.preheader: ; preds = %loopentry.2.i 200 br label %no_exit.1.i 201 no_exit.1.i: ; preds = %endif.8.i, %no_exit.1.i.preheader 202 br i1 false, label %return.i, label %endif.8.i 203 endif.8.i: ; preds = %no_exit.1.i 204 %inc.1.i = add i32 0, 1 ; <i32> [#uses=1] 205 br i1 false, label %no_exit.1.i, label %loopentry.3.i.preheader.loopexit 206 loopentry.3.i.preheader.loopexit: ; preds = %endif.8.i 207 br label %loopentry.3.i.preheader 208 loopentry.3.i.preheader: ; preds = %loopentry.3.i.preheader.loopexit, %loopentry.2.i 209 %arg_num.0.i.ph13000 = phi i32 [ 0, %loopentry.2.i ], [ %inc.1.i, %loopentry.3.i.preheader.loopexit ] ; <i32> [#uses=0] 210 ret void 211 return.i: ; preds = %no_exit.1.i 212 ret void 213 214 ; CHECK-LABEL: @test9( 215 ; CHECK: loopentry.3.i.preheader.loopexit: 216 ; CHECK-NEXT: %inc.1.i.le = add i32 0, 1 217 ; CHECK-NEXT: br label %loopentry.3.i.preheader 218 } 219 220 221 ; Potentially trapping instructions may be sunk as long as they are guaranteed 222 ; to be executed. 223 define i32 @test10(i32 %N) { 224 Entry: 225 br label %Loop 226 Loop: ; preds = %Loop, %Entry 227 %N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ] ; <i32> [#uses=3] 228 %tmp.6 = sdiv i32 %N, %N_addr.0.pn ; <i32> [#uses=1] 229 %dec = add i32 %N_addr.0.pn, -1 ; <i32> [#uses=1] 230 %tmp.1 = icmp ne i32 %N_addr.0.pn, 0 ; <i1> [#uses=1] 231 br i1 %tmp.1, label %Loop, label %Out 232 Out: ; preds = %Loop 233 ret i32 %tmp.6 234 235 ; CHECK-LABEL: @test10( 236 ; CHECK: Out: 237 ; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn 238 ; CHECK-NEXT: %tmp.6.le = sdiv i32 %N, %[[LCSSAPHI]] 239 ; CHECK-NEXT: ret i32 %tmp.6.le 240 } 241 242 ; Should delete, not sink, dead instructions. 243 define void @test11() { 244 br label %Loop 245 Loop: 246 %dead1 = getelementptr %Ty, %Ty* @X2, i64 0, i32 0 247 %dead2 = getelementptr %Ty, %Ty* @X2, i64 0, i32 1 248 br i1 false, label %Loop, label %Out 249 Out: 250 ret void 251 ; CHECK-LABEL: @test11( 252 ; CHECK: Out: 253 ; CHECK-NEXT: ret void 254 255 ; The GEP in dead1 is adding a zero offset, so the DIExpression can be kept as 256 ; a "register location". 257 ; The GEP in dead2 is adding a 4 bytes to the pointer, so the DIExpression is 258 ; turned into an "implicit location" using DW_OP_stack_value. 259 ; 260 ; DEBUGIFY-LABEL: @test11( 261 ; DEBUGIFY: call void @llvm.dbg.value(metadata %Ty* @X2, metadata {{.*}}, metadata !DIExpression()) 262 ; DEBUGIFY: call void @llvm.dbg.value(metadata %Ty* @X2, metadata {{.*}}, metadata !DIExpression(DW_OP_plus_uconst, 4, DW_OP_stack_value)) 263 } 264 265 @c = common global [1 x i32] zeroinitializer, align 4 266 267 ; Test a *many* way nested loop with multiple exit blocks both of which exit 268 ; multiple loop nests. This exercises LCSSA corner cases. 269 define i32 @PR18753(i1* %a, i1* %b, i1* %c, i1* %d) { 270 entry: 271 br label %l1.header 272 273 l1.header: 274 %iv = phi i64 [ %iv.next, %l1.latch ], [ 0, %entry ] 275 %arrayidx.i = getelementptr inbounds [1 x i32], [1 x i32]* @c, i64 0, i64 %iv 276 br label %l2.header 277 278 l2.header: 279 %x0 = load i1, i1* %c, align 4 280 br i1 %x0, label %l1.latch, label %l3.preheader 281 282 l3.preheader: 283 br label %l3.header 284 285 l3.header: 286 %x1 = load i1, i1* %d, align 4 287 br i1 %x1, label %l2.latch, label %l4.preheader 288 289 l4.preheader: 290 br label %l4.header 291 292 l4.header: 293 %x2 = load i1, i1* %a 294 br i1 %x2, label %l3.latch, label %l4.body 295 296 l4.body: 297 call void @f(i32* %arrayidx.i) 298 %x3 = load i1, i1* %b 299 %l = trunc i64 %iv to i32 300 br i1 %x3, label %l4.latch, label %exit 301 302 l4.latch: 303 call void @g() 304 %x4 = load i1, i1* %b, align 4 305 br i1 %x4, label %l4.header, label %exit 306 307 l3.latch: 308 br label %l3.header 309 310 l2.latch: 311 br label %l2.header 312 313 l1.latch: 314 %iv.next = add nsw i64 %iv, 1 315 br label %l1.header 316 317 exit: 318 %lcssa = phi i32 [ %l, %l4.latch ], [ %l, %l4.body ] 319 ; CHECK-LABEL: @PR18753( 320 ; CHECK: exit: 321 ; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i64 [ %iv, %l4.latch ], [ %iv, %l4.body ] 322 ; CHECK-NEXT: %l.le = trunc i64 %[[LCSSAPHI]] to i32 323 ; CHECK-NEXT: ret i32 %l.le 324 325 ret i32 %lcssa 326 } 327 328 ; Can't sink stores out of exit blocks containing indirectbr instructions 329 ; because loop simplify does not create dedicated exits for such blocks. Test 330 ; that by sinking the store from lab21 to lab22, but not further. 331 define void @test12() { 332 ; CHECK-LABEL: @test12 333 br label %lab4 334 335 lab4: 336 br label %lab20 337 338 lab5: 339 br label %lab20 340 341 lab6: 342 br label %lab4 343 344 lab7: 345 br i1 undef, label %lab8, label %lab13 346 347 lab8: 348 br i1 undef, label %lab13, label %lab10 349 350 lab10: 351 br label %lab7 352 353 lab13: 354 ret void 355 356 lab20: 357 br label %lab21 358 359 lab21: 360 ; CHECK: lab21: 361 ; CHECK-NOT: store 362 ; CHECK: br i1 false, label %lab21, label %lab22 363 store i32 36127957, i32* undef, align 4 364 br i1 undef, label %lab21, label %lab22 365 366 lab22: 367 ; CHECK: lab22: 368 ; CHECK: store 369 ; CHECK-NEXT: indirectbr i8* undef 370 indirectbr i8* undef, [label %lab5, label %lab6, label %lab7] 371 } 372 373 ; Test that we don't crash when trying to sink stores and there's no preheader 374 ; available (which is used for creating loads that may be used by the SSA 375 ; updater) 376 define void @test13() { 377 ; CHECK-LABEL: @test13 378 br label %lab59 379 380 lab19: 381 br i1 undef, label %lab20, label %lab38 382 383 lab20: 384 br label %lab60 385 386 lab21: 387 br i1 undef, label %lab22, label %lab38 388 389 lab22: 390 br label %lab38 391 392 lab38: 393 ret void 394 395 lab59: 396 indirectbr i8* undef, [label %lab60, label %lab38] 397 398 lab60: 399 ; CHECK: lab60: 400 ; CHECK: store 401 ; CHECK-NEXT: indirectbr 402 store i32 2145244101, i32* undef, align 4 403 indirectbr i8* undef, [label %lab21, label %lab19] 404 } 405 406 ; Check if LICM can sink a sinkable instruction the exit blocks through 407 ; a non-trivially replacable PHI node. 408 ; 409 ; CHECK-LABEL: @test14 410 ; CHECK-LABEL: Loop: 411 ; CHECK-NOT: mul 412 ; CHECK-NOT: sub 413 ; 414 ; CHECK-LABEL: Out12.split.loop.exit: 415 ; CHECK: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn, %ContLoop ] 416 ; CHECK: %[[MUL:.*]] = mul i32 %N, %[[LCSSAPHI]] 417 ; CHECK: br label %Out12 418 ; 419 ; CHECK-LABEL: Out12.split.loop.exit1: 420 ; CHECK: %[[LCSSAPHI2:.*]] = phi i32 [ %N_addr.0.pn, %Loop ] 421 ; CHECK: %[[MUL2:.*]] = mul i32 %N, %[[LCSSAPHI2]] 422 ; CHECK: %[[SUB:.*]] = sub i32 %[[MUL2]], %N 423 ; CHECK: br label %Out12 424 ; 425 ; CHECK-LABEL: Out12: 426 ; CHECK: phi i32 [ %[[MUL]], %Out12.split.loop.exit ], [ %[[SUB]], %Out12.split.loop.exit1 ] 427 define i32 @test14(i32 %N, i32 %N2, i1 %C) { 428 Entry: 429 br label %Loop 430 Loop: 431 %N_addr.0.pn = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ] 432 %sink.mul = mul i32 %N, %N_addr.0.pn 433 %sink.sub = sub i32 %sink.mul, %N 434 %dec = add i32 %N_addr.0.pn, -1 435 br i1 %C, label %ContLoop, label %Out12 436 ContLoop: 437 %tmp.1 = icmp ne i32 %N_addr.0.pn, 1 438 br i1 %tmp.1, label %Loop, label %Out12 439 Out12: 440 %tmp = phi i32 [%sink.mul, %ContLoop], [%sink.sub, %Loop] 441 ret i32 %tmp 442 } 443 444 ; In this test, splitting predecessors is not really required because the 445 ; operations of sinkable instructions (sub and mul) are same. In this case, we 446 ; can sink the same sinkable operations and modify the PHI to pass the operands 447 ; to the shared operations. As of now, we split predecessors of non-trivially 448 ; replicalbe PHIs by default in LICM because all incoming edges of a 449 ; non-trivially replacable PHI in LCSSA is critical. 450 ; 451 ; CHECK-LABEL: @test15 452 ; CHECK-LABEL: Loop: 453 ; CHECK-NOT: mul 454 ; CHECK-NOT: sub 455 ; 456 ; CHECK-LABEL: Out12.split.loop.exit: 457 ; CHECK: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn, %ContLoop ] 458 ; CHECK: %[[MUL:.*]] = mul i32 %N, %[[LCSSAPHI]] 459 ; CHECK: %[[SUB:.*]] = sub i32 %[[MUL]], %N2 460 ; CHECK: br label %Out12 461 ; 462 ; CHECK-LABEL: Out12.split.loop.exit1: 463 ; CHECK: %[[LCSSAPHI2:.*]] = phi i32 [ %N_addr.0.pn, %Loop ] 464 ; CHECK: %[[MUL2:.*]] = mul i32 %N, %[[LCSSAPHI2]] 465 ; CHECK: %[[SUB2:.*]] = sub i32 %[[MUL2]], %N 466 ; CHECK: br label %Out12 467 ; 468 ; CHECK-LABEL: Out12: 469 ; CHECK: phi i32 [ %[[SUB]], %Out12.split.loop.exit ], [ %[[SUB2]], %Out12.split.loop.exit1 ] 470 define i32 @test15(i32 %N, i32 %N2, i1 %C) { 471 Entry: 472 br label %Loop 473 Loop: 474 %N_addr.0.pn = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ] 475 %sink.mul = mul i32 %N, %N_addr.0.pn 476 %sink.sub = sub i32 %sink.mul, %N 477 %sink.sub2 = sub i32 %sink.mul, %N2 478 %dec = add i32 %N_addr.0.pn, -1 479 br i1 %C, label %ContLoop, label %Out12 480 ContLoop: 481 %tmp.1 = icmp ne i32 %N_addr.0.pn, 1 482 br i1 %tmp.1, label %Loop, label %Out12 483 Out12: 484 %tmp = phi i32 [%sink.sub2, %ContLoop], [%sink.sub, %Loop] 485 ret i32 %tmp 486 } 487 488 ; Sink through a non-trivially replacable PHI node which use the same sinkable 489 ; instruction multiple times. 490 ; 491 ; CHECK-LABEL: @test16 492 ; CHECK-LABEL: Loop: 493 ; CHECK-NOT: mul 494 ; 495 ; CHECK-LABEL: Out.split.loop.exit: 496 ; CHECK: %[[PHI:.*]] = phi i32 [ %l2, %ContLoop ] 497 ; CHECK: br label %Out 498 ; 499 ; CHECK-LABEL: Out.split.loop.exit1: 500 ; CHECK: %[[SINKABLE:.*]] = mul i32 %l2.lcssa, %t.le 501 ; CHECK: br label %Out 502 ; 503 ; CHECK-LABEL: Out: 504 ; CHECK: %idx = phi i32 [ %[[PHI]], %Out.split.loop.exit ], [ %[[SINKABLE]], %Out.split.loop.exit1 ] 505 define i32 @test16(i1 %c, i8** %P, i32* %P2, i64 %V) { 506 entry: 507 br label %loop.ph 508 loop.ph: 509 br label %Loop 510 Loop: 511 %iv = phi i64 [ 0, %loop.ph ], [ %next, %ContLoop ] 512 %l2 = call i32 @getv() 513 %t = trunc i64 %iv to i32 514 %sinkable = mul i32 %l2, %t 515 switch i32 %l2, label %ContLoop [ 516 i32 32, label %Out 517 i32 46, label %Out 518 i32 95, label %Out 519 ] 520 ContLoop: 521 %next = add nuw i64 %iv, 1 522 %c1 = call i1 @getc() 523 br i1 %c1, label %Loop, label %Out 524 Out: 525 %idx = phi i32 [ %l2, %ContLoop ], [ %sinkable, %Loop ], [ %sinkable, %Loop ], [ %sinkable, %Loop ] 526 ret i32 %idx 527 } 528 529 ; Sink a sinkable instruction through multiple non-trivially replacable PHIs in 530 ; differect exit blocks. 531 ; 532 ; CHECK-LABEL: @test17 533 ; CHECK-LABEL: Loop: 534 ; CHECK-NOT: mul 535 ; 536 ; CHECK-LABEL:OutA.split.loop.exit{{.*}}: 537 ; CHECK: %[[OP1:.*]] = phi i32 [ %N_addr.0.pn, %ContLoop1 ] 538 ; CHECK: %[[SINKABLE:.*]] = mul i32 %N, %[[OP1]] 539 ; CHECK: br label %OutA 540 ; 541 ; CHECK-LABEL:OutA: 542 ; CHECK: phi i32{{.*}}[ %[[SINKABLE]], %OutA.split.loop.exit{{.*}} ] 543 ; 544 ; CHECK-LABEL:OutB.split.loop.exit{{.*}}: 545 ; CHECK: %[[OP2:.*]] = phi i32 [ %N_addr.0.pn, %ContLoop2 ] 546 ; CHECK: %[[SINKABLE2:.*]] = mul i32 %N, %[[OP2]] 547 ; CHECK: br label %OutB 548 ; 549 ; CHECK-LABEL:OutB: 550 ; CHECK: phi i32 {{.*}}[ %[[SINKABLE2]], %OutB.split.loop.exit{{.*}} ] 551 define i32 @test17(i32 %N, i32 %N2) { 552 Entry: 553 br label %Loop 554 Loop: 555 %N_addr.0.pn = phi i32 [ %dec, %ContLoop3 ], [ %N, %Entry ] 556 %sink.mul = mul i32 %N, %N_addr.0.pn 557 %c0 = call i1 @getc() 558 br i1 %c0 , label %ContLoop1, label %OutA 559 ContLoop1: 560 %c1 = call i1 @getc() 561 br i1 %c1, label %ContLoop2, label %OutA 562 563 ContLoop2: 564 %c2 = call i1 @getc() 565 br i1 %c2, label %ContLoop3, label %OutB 566 ContLoop3: 567 %c3 = call i1 @getc() 568 %dec = add i32 %N_addr.0.pn, -1 569 br i1 %c3, label %Loop, label %OutB 570 OutA: 571 %tmp1 = phi i32 [%sink.mul, %ContLoop1], [%N2, %Loop] 572 br label %Out12 573 OutB: 574 %tmp2 = phi i32 [%sink.mul, %ContLoop2], [%dec, %ContLoop3] 575 br label %Out12 576 Out12: 577 %tmp = phi i32 [%tmp1, %OutA], [%tmp2, %OutB] 578 ret i32 %tmp 579 } 580 581 582 ; Sink a sinkable instruction through both trivially and non-trivially replacable PHIs. 583 ; 584 ; CHECK-LABEL: @test18 585 ; CHECK-LABEL: Loop: 586 ; CHECK-NOT: mul 587 ; CHECK-NOT: sub 588 ; 589 ; CHECK-LABEL:Out12.split.loop.exit: 590 ; CHECK: %[[OP:.*]] = phi i32 [ %iv, %ContLoop ] 591 ; CHECK: %[[DEC:.*]] = phi i32 [ %dec, %ContLoop ] 592 ; CHECK: %[[SINKMUL:.*]] = mul i32 %N, %[[OP]] 593 ; CHECK: %[[SINKSUB:.*]] = sub i32 %[[SINKMUL]], %N2 594 ; CHECK: br label %Out12 595 ; 596 ; CHECK-LABEL:Out12.split.loop.exit1: 597 ; CHECK: %[[OP2:.*]] = phi i32 [ %iv, %Loop ] 598 ; CHECK: %[[SINKMUL2:.*]] = mul i32 %N, %[[OP2]] 599 ; CHECK: %[[SINKSUB2:.*]] = sub i32 %[[SINKMUL2]], %N2 600 ; CHECK: br label %Out12 601 ; 602 ; CHECK-LABEL:Out12: 603 ; CHECK: %tmp1 = phi i32 [ %[[SINKSUB]], %Out12.split.loop.exit ], [ %[[SINKSUB2]], %Out12.split.loop.exit1 ] 604 ; CHECK: %tmp2 = phi i32 [ %[[DEC]], %Out12.split.loop.exit ], [ %[[SINKSUB2]], %Out12.split.loop.exit1 ] 605 ; CHECK: %add = add i32 %tmp1, %tmp2 606 define i32 @test18(i32 %N, i32 %N2) { 607 Entry: 608 br label %Loop 609 Loop: 610 %iv = phi i32 [ %dec, %ContLoop ], [ %N, %Entry ] 611 %sink.mul = mul i32 %N, %iv 612 %sink.sub = sub i32 %sink.mul, %N2 613 %c0 = call i1 @getc() 614 br i1 %c0, label %ContLoop, label %Out12 615 ContLoop: 616 %dec = add i32 %iv, -1 617 %c1 = call i1 @getc() 618 br i1 %c1, label %Loop, label %Out12 619 Out12: 620 %tmp1 = phi i32 [%sink.sub, %ContLoop], [%sink.sub, %Loop] 621 %tmp2 = phi i32 [%dec, %ContLoop], [%sink.sub, %Loop] 622 %add = add i32 %tmp1, %tmp2 623 ret i32 %add 624 } 625 626 ; Do not sink an instruction through a non-trivially replacable PHI, to avoid 627 ; assert while splitting predecessors, if the terminator of predecessor is an 628 ; indirectbr. 629 ; CHECK-LABEL: @test19 630 ; CHECK-LABEL: L0: 631 ; CHECK: %sinkable = mul 632 ; CHECK: %sinkable2 = add 633 634 define i32 @test19(i1 %cond, i1 %cond2, i8* %address, i32 %v1) nounwind { 635 entry: 636 br label %L0 637 L0: 638 %indirect.goto.dest = select i1 %cond, i8* blockaddress(@test19, %exit), i8* %address 639 %v2 = call i32 @getv() 640 %sinkable = mul i32 %v1, %v2 641 %sinkable2 = add i32 %v1, %v2 642 indirectbr i8* %indirect.goto.dest, [label %L1, label %exit] 643 644 L1: 645 %indirect.goto.dest2 = select i1 %cond2, i8* blockaddress(@test19, %exit), i8* %address 646 indirectbr i8* %indirect.goto.dest2, [label %L0, label %exit] 647 648 exit: 649 %r = phi i32 [%sinkable, %L0], [%sinkable2, %L1] 650 ret i32 %r 651 } 652 653 654 ; Do not sink through a non-trivially replacable PHI if splitting predecessors 655 ; not allowed in SplitBlockPredecessors(). 656 ; 657 ; CHECK-LABEL: @test20 658 ; CHECK-LABEL: while.cond 659 ; CHECK: %sinkable = mul 660 ; CHECK: %sinkable2 = add 661 define void @test20(i32* %s, i1 %b, i32 %v1, i32 %v2) personality i32 (...)* @__CxxFrameHandler3 { 662 entry: 663 br label %while.cond 664 while.cond: 665 %v = call i32 @getv() 666 %sinkable = mul i32 %v, %v2 667 %sinkable2 = add i32 %v, %v2 668 br i1 %b, label %try.cont, label %while.body 669 while.body: 670 invoke void @may_throw() 671 to label %while.body2 unwind label %catch.dispatch 672 while.body2: 673 invoke void @may_throw2() 674 to label %while.cond unwind label %catch.dispatch 675 catch.dispatch: 676 %.lcssa1 = phi i32 [ %sinkable, %while.body ], [ %sinkable2, %while.body2 ] 677 %cp = cleanuppad within none [] 678 store i32 %.lcssa1, i32* %s 679 cleanupret from %cp unwind to caller 680 try.cont: 681 ret void 682 } 683 684 ; The sinkable call should be sunk into an exit block split. After splitting 685 ; the exit block, BlockColor for new blocks should be added properly so 686 ; that we should be able to access valid ColorVector. 687 ; 688 ; CHECK-LABEL:@test21_pr36184 689 ; CHECK-LABEL: Loop 690 ; CHECK-NOT: %sinkableCall 691 ; CHECK-LABEL:Out.split.loop.exit 692 ; CHECK: %sinkableCall 693 define i32 @test21_pr36184(i8* %P) personality i32 (...)* @__CxxFrameHandler3 { 694 entry: 695 br label %loop.ph 696 697 loop.ph: 698 br label %Loop 699 700 Loop: 701 %sinkableCall = call i32 @strlen( i8* %P ) readonly 702 br i1 undef, label %ContLoop, label %Out 703 704 ContLoop: 705 br i1 undef, label %Loop, label %Out 706 707 Out: 708 %idx = phi i32 [ %sinkableCall, %Loop ], [0, %ContLoop ] 709 ret i32 %idx 710 } 711 712 ; We do not support splitting a landingpad block if BlockColors is not empty. 713 ; CHECK-LABEL: @test22 714 ; CHECK-LABEL: while.body2 715 ; CHECK-LABEL: %mul 716 ; CHECK-NOT: lpadBB.split{{.*}} 717 define void @test22(i1 %b, i32 %v1, i32 %v2) personality i32 (...)* @__CxxFrameHandler3 { 718 entry: 719 br label %while.cond 720 while.cond: 721 br i1 %b, label %try.cont, label %while.body 722 723 while.body: 724 invoke void @may_throw() 725 to label %while.body2 unwind label %lpadBB 726 727 while.body2: 728 %v = call i32 @getv() 729 %mul = mul i32 %v, %v2 730 invoke void @may_throw2() 731 to label %while.cond unwind label %lpadBB 732 lpadBB: 733 %.lcssa1 = phi i32 [ 0, %while.body ], [ %mul, %while.body2 ] 734 landingpad { i8*, i32 } 735 catch i8* null 736 br label %lpadBBSucc1 737 738 lpadBBSucc1: 739 ret void 740 741 try.cont: 742 ret void 743 } 744 745 declare void @may_throw() 746 declare void @may_throw2() 747 declare i32 @__CxxFrameHandler3(...) 748 declare i32 @getv() 749 declare i1 @getc() 750 declare void @f(i32*) 751 declare void @g() 752
