1 ; RUN: opt -passes='loop(unswitch),verify<loops>' -S < %s | FileCheck %s 2 3 define i32 @test(i32* %A, i1 %C) { 4 entry: 5 br label %no_exit 6 no_exit: ; preds = %no_exit.backedge, %entry 7 %i.0.0 = phi i32 [ 0, %entry ], [ %i.0.0.be, %no_exit.backedge ] ; <i32> [#uses=3] 8 %gep.upgrd.1 = zext i32 %i.0.0 to i64 ; <i64> [#uses=1] 9 %tmp.7 = getelementptr i32, i32* %A, i64 %gep.upgrd.1 ; <i32*> [#uses=4] 10 %tmp.13 = load i32, i32* %tmp.7 ; <i32> [#uses=2] 11 %tmp.14 = add i32 %tmp.13, 1 ; <i32> [#uses=1] 12 store i32 %tmp.14, i32* %tmp.7 13 br i1 %C, label %then, label %endif 14 then: ; preds = %no_exit 15 %tmp.29 = load i32, i32* %tmp.7 ; <i32> [#uses=1] 16 %tmp.30 = add i32 %tmp.29, 2 ; <i32> [#uses=1] 17 store i32 %tmp.30, i32* %tmp.7 18 %inc9 = add i32 %i.0.0, 1 ; <i32> [#uses=2] 19 %tmp.112 = icmp ult i32 %inc9, 100000 ; <i1> [#uses=1] 20 br i1 %tmp.112, label %no_exit.backedge, label %return 21 no_exit.backedge: ; preds = %endif, %then 22 %i.0.0.be = phi i32 [ %inc9, %then ], [ %inc, %endif ] ; <i32> [#uses=1] 23 br label %no_exit 24 endif: ; preds = %no_exit 25 %inc = add i32 %i.0.0, 1 ; <i32> [#uses=2] 26 %tmp.1 = icmp ult i32 %inc, 100000 ; <i1> [#uses=1] 27 br i1 %tmp.1, label %no_exit.backedge, label %return 28 return: ; preds = %endif, %then 29 ret i32 %tmp.13 30 } 31 32 ; This simple test would normally unswitch, but should be inhibited by the presence of 33 ; the noduplicate call. 34 35 ; CHECK-LABEL: @test2( 36 define i32 @test2(i32* %var) { 37 %mem = alloca i32 38 store i32 2, i32* %mem 39 %c = load i32, i32* %mem 40 41 br label %loop_begin 42 43 loop_begin: 44 45 %var_val = load i32, i32* %var 46 47 switch i32 %c, label %default [ 48 i32 1, label %inc 49 i32 2, label %dec 50 ] 51 52 inc: 53 call void @incf() noreturn nounwind 54 br label %loop_begin 55 dec: 56 ; CHECK: call void @decf() 57 ; CHECK-NOT: call void @decf() 58 call void @decf() noreturn nounwind noduplicate 59 br label %loop_begin 60 default: 61 br label %loop_exit 62 loop_exit: 63 ret i32 0 64 ; CHECK: } 65 } 66 67 ; This simple test would normally unswitch, but should be inhibited by the presence of 68 ; the convergent call that is not control-dependent on the unswitch condition. 69 70 ; CHECK-LABEL: @test3( 71 define i32 @test3(i32* %var) { 72 %mem = alloca i32 73 store i32 2, i32* %mem 74 %c = load i32, i32* %mem 75 76 br label %loop_begin 77 78 loop_begin: 79 80 %var_val = load i32, i32* %var 81 82 ; CHECK: call void @conv() 83 ; CHECK-NOT: call void @conv() 84 call void @conv() convergent 85 86 switch i32 %c, label %default [ 87 i32 1, label %inc 88 i32 2, label %dec 89 ] 90 91 inc: 92 call void @incf() noreturn nounwind 93 br label %loop_begin 94 dec: 95 call void @decf() noreturn nounwind 96 br label %loop_begin 97 default: 98 br label %loop_exit 99 loop_exit: 100 ret i32 0 101 ; CHECK: } 102 } 103 104 ; Make sure we don't unswitch, as we can not find an input value %a 105 ; that will effectively unswitch 0 or 3 out of the loop. 106 ; 107 ; CHECK: define void @and_or_i2_as_switch_input(i2 108 ; CHECK: entry: 109 ; This is an indication that the loop has NOT been unswitched. 110 ; CHECK-NOT: icmp 111 ; CHECK: br 112 define void @and_or_i2_as_switch_input(i2 %a) { 113 entry: 114 br label %for.body 115 116 for.body: 117 %i = phi i2 [ 0, %entry ], [ %inc, %for.inc ] 118 %and = and i2 %a, %i 119 %or = or i2 %and, %i 120 switch i2 %or, label %sw.default [ 121 i2 0, label %sw.bb 122 i2 3, label %sw.bb1 123 ] 124 125 sw.bb: 126 br label %sw.epilog 127 128 sw.bb1: 129 br label %sw.epilog 130 131 sw.default: 132 br label %sw.epilog 133 134 sw.epilog: 135 br label %for.inc 136 137 for.inc: 138 %inc = add nsw i2 %i, 1 139 %cmp = icmp slt i2 %inc, 3 140 br i1 %cmp, label %for.body, label %for.end 141 142 for.end: 143 ret void 144 } 145 146 ; Make sure we don't unswitch, as we can not find an input value %a 147 ; that will effectively unswitch true/false out of the loop. 148 ; 149 ; CHECK: define void @and_or_i1_as_branch_input(i1 150 ; CHECK: entry: 151 ; This is an indication that the loop has NOT been unswitched. 152 ; CHECK-NOT: icmp 153 ; CHECK: br 154 define void @and_or_i1_as_branch_input(i1 %a) { 155 entry: 156 br label %for.body 157 158 for.body: 159 %i = phi i1 [ 0, %entry ], [ %inc, %for.inc ] 160 %and = and i1 %a, %i 161 %or = or i1 %and, %i 162 br i1 %or, label %sw.bb, label %sw.bb1 163 164 sw.bb: 165 br label %sw.epilog 166 167 sw.bb1: 168 br label %sw.epilog 169 170 sw.epilog: 171 br label %for.inc 172 173 for.inc: 174 %inc = add nsw i1 %i, 1 175 %cmp = icmp slt i1 %inc, 1 176 br i1 %cmp, label %for.body, label %for.end 177 178 for.end: 179 ret void 180 } 181 182 declare void @incf() noreturn 183 declare void @decf() noreturn 184 declare void @conv() convergent 185
