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      1 //===---------------------------- Context.h ---------------------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 /// \file
     10 ///
     11 /// This file defines a class for holding ownership of various simulated
     12 /// hardware units.  A Context also provides a utility routine for constructing
     13 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
     14 /// stages).
     15 ///
     16 //===----------------------------------------------------------------------===//
     17 
     18 #ifndef LLVM_TOOLS_LLVM_MCA_CONTEXT_H
     19 #define LLVM_TOOLS_LLVM_MCA_CONTEXT_H
     20 #include "HardwareUnit.h"
     21 #include "InstrBuilder.h"
     22 #include "Pipeline.h"
     23 #include "SourceMgr.h"
     24 #include "llvm/MC/MCRegisterInfo.h"
     25 #include "llvm/MC/MCSchedule.h"
     26 #include "llvm/MC/MCSubtargetInfo.h"
     27 #include <memory>
     28 
     29 namespace mca {
     30 
     31 /// This is a convenience struct to hold the parameters necessary for creating
     32 /// the pre-built "default" out-of-order pipeline.
     33 struct PipelineOptions {
     34   PipelineOptions(unsigned DW, unsigned RFS, unsigned LQS, unsigned SQS,
     35                   bool NoAlias)
     36       : DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS),
     37         StoreQueueSize(SQS), AssumeNoAlias(NoAlias) {}
     38   unsigned DispatchWidth;
     39   unsigned RegisterFileSize;
     40   unsigned LoadQueueSize;
     41   unsigned StoreQueueSize;
     42   bool AssumeNoAlias;
     43 };
     44 
     45 class Context {
     46   llvm::SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware;
     47   const llvm::MCRegisterInfo &MRI;
     48   const llvm::MCSubtargetInfo &STI;
     49 
     50 public:
     51   Context(const llvm::MCRegisterInfo &R, const llvm::MCSubtargetInfo &S)
     52       : MRI(R), STI(S) {}
     53   Context(const Context &C) = delete;
     54   Context &operator=(const Context &C) = delete;
     55 
     56   void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
     57     Hardware.push_back(std::move(H));
     58   }
     59 
     60   /// Construct a basic pipeline for simulating an out-of-order pipeline.
     61   /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
     62   std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
     63                                                   InstrBuilder &IB,
     64                                                   SourceMgr &SrcMgr);
     65 };
     66 
     67 } // namespace mca
     68 #endif // LLVM_TOOLS_LLVM_MCA_CONTEXT_H
     69