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DartARM32/22-Oct-2020
IceASanInstrumentation.cpp22-Oct-202018.9K
IceASanInstrumentation.h22-Oct-20202.7K
IceAssembler.cpp22-Oct-20205.7K
IceAssembler.h22-Oct-202012.5K
IceAssemblerARM32.cpp22-Oct-2020159.7K
IceAssemblerARM32.h22-Oct-202034.6K
IceAssemblerMIPS32.cpp22-Oct-202040.5K
IceAssemblerMIPS32.h22-Oct-202012.4K
IceAssemblerX8632.h22-Oct-20201.3K
IceAssemblerX8664.h22-Oct-20201.3K
IceAssemblerX86Base.h22-Oct-202037K
IceAssemblerX86BaseImpl.h22-Oct-2020125.7K
IceBitVector.h22-Oct-202023K
IceBrowserCompileServer.cpp22-Oct-202011.7K
IceBrowserCompileServer.h22-Oct-20203.5K
IceBuildDefs.h22-Oct-20203.7K
IceCfg.cpp22-Oct-202067.4K
IceCfg.h22-Oct-202013K
IceCfgNode.cpp22-Oct-202057.4K
IceCfgNode.h22-Oct-20205.6K
IceClFlags.cpp22-Oct-20207K
IceClFlags.def22-Oct-202030.1K
IceClFlags.h22-Oct-20207.5K
IceCompiler.cpp22-Oct-20206.2K
IceCompiler.h22-Oct-20201.2K
IceCompileServer.cpp22-Oct-20208.9K
IceCompileServer.h22-Oct-20202.4K
IceConditionCodesARM32.h22-Oct-20201.2K
IceConditionCodesMIPS32.h22-Oct-20201.2K
IceConditionCodesX8632.h22-Oct-20201.4K
IceConditionCodesX8664.h22-Oct-20201.3K
IceConverter.cpp22-Oct-202033.4K
IceConverter.h22-Oct-20202.4K
IceDefs.h22-Oct-202014.8K
IceELFObjectWriter.cpp22-Oct-202027.8K
IceELFObjectWriter.h22-Oct-20207.7K
IceELFSection.cpp22-Oct-20208K
IceELFSection.h22-Oct-202013.7K
IceELFStreamer.h22-Oct-20202.7K
IceFixups.cpp22-Oct-20202.8K
IceFixups.h22-Oct-20203.7K
IceGlobalContext.cpp22-Oct-202040.8K
IceGlobalContext.h22-Oct-202021.8K
IceGlobalInits.cpp22-Oct-20206.5K
IceGlobalInits.h22-Oct-202018.6K
IceInst.cpp22-Oct-202032.8K
IceInst.def22-Oct-20206.4K
IceInst.h22-Oct-202044.5K
IceInstARM32.cpp22-Oct-2020107.7K
IceInstARM32.def22-Oct-20207.4K
IceInstARM32.h22-Oct-202060.7K
IceInstMIPS32.cpp22-Oct-202040.8K
IceInstMIPS32.def22-Oct-202020.9K
IceInstMIPS32.h22-Oct-202048.6K
IceInstrumentation.cpp22-Oct-20203.9K
IceInstrumentation.h22-Oct-20203.8K
IceInstVarIter.h22-Oct-20207.8K
IceInstX8632.cpp22-Oct-202011.2K
IceInstX8632.def22-Oct-202015.1K
IceInstX8632.h22-Oct-20201.2K
IceInstX8664.cpp22-Oct-202011.6K
IceInstX8664.def22-Oct-202022.7K
IceInstX8664.h22-Oct-20201.2K
IceInstX86Base.h22-Oct-2020178.3K
IceInstX86BaseImpl.h22-Oct-2020110.9K
IceIntrinsics.cpp22-Oct-202013.6K
IceIntrinsics.h22-Oct-20205.9K
IceLiveness.cpp22-Oct-20205.3K
IceLiveness.h22-Oct-20205.9K
IceLoopAnalyzer.cpp22-Oct-20209.2K
IceLoopAnalyzer.h22-Oct-2020955
IceMangling.cpp22-Oct-20207.2K
IceMangling.h22-Oct-2020729
IceMemory.cpp22-Oct-20201.7K
IceMemory.h22-Oct-20205.3K
IceOperand.cpp22-Oct-202019.9K
IceOperand.h22-Oct-202042.1K
IcePhiLoweringImpl.h22-Oct-20202.8K
IceRangeSpec.cpp22-Oct-20205.5K
IceRangeSpec.h22-Oct-20202.8K
IceRegAlloc.cpp22-Oct-202037.9K
IceRegAlloc.h22-Oct-20205.4K
IceRegistersARM32.def22-Oct-202010.3K
IceRegistersARM32.h22-Oct-20206.3K
IceRegistersMIPS32.h22-Oct-20204.8K
IceRegistersX8632.h22-Oct-20203.1K
IceRegistersX8664.h22-Oct-20202.7K
IceRegList.h22-Oct-20201.8K
IceRevision.cpp22-Oct-2020803
IceRevision.h22-Oct-20201.1K
IceRNG.cpp22-Oct-20201.9K
IceRNG.h22-Oct-20203.1K
IceStringPool.h22-Oct-20205.6K
IceSwitchLowering.cpp22-Oct-20203.8K
IceSwitchLowering.h22-Oct-20203.7K
IceTargetLowering.cpp22-Oct-202039.7K
IceTargetLowering.def22-Oct-20203.7K
IceTargetLowering.h22-Oct-202027.7K
IceTargetLoweringARM32.cpp22-Oct-2020249.1K
IceTargetLoweringARM32.def22-Oct-20203.7K
IceTargetLoweringARM32.h22-Oct-202052.6K
IceTargetLoweringMIPS32.cpp22-Oct-2020208.9K
IceTargetLoweringMIPS32.def22-Oct-2020763
IceTargetLoweringMIPS32.h22-Oct-202035.5K
IceTargetLoweringX86.cpp22-Oct-20201.9K
IceTargetLoweringX8632.cpp22-Oct-202018.4K
IceTargetLoweringX8632.def22-Oct-20202.6K
IceTargetLoweringX8632.h22-Oct-20202.6K
IceTargetLoweringX8632Traits.h22-Oct-202037.4K
IceTargetLoweringX8664.cpp22-Oct-202028.3K
IceTargetLoweringX8664.def22-Oct-20202.6K
IceTargetLoweringX8664.h22-Oct-20202.6K
IceTargetLoweringX8664Traits.h22-Oct-202040.7K
IceTargetLoweringX86Base.h22-Oct-202052.1K
IceTargetLoweringX86BaseImpl.h22-Oct-2020304.8K
IceTargetLoweringX86RegClass.h22-Oct-20201.2K
IceThreading.cpp22-Oct-20201.9K
IceThreading.h22-Oct-20208K
IceTimerTree.cpp22-Oct-202010.4K
IceTimerTree.def22-Oct-20205.2K
IceTimerTree.h22-Oct-20203.4K
IceTLS.h22-Oct-20204.6K
IceTranslator.cpp22-Oct-20202.1K
IceTranslator.h22-Oct-20202.8K
IceTypeConverter.cpp22-Oct-20202.2K
IceTypeConverter.h22-Oct-20201.9K
IceTypes.cpp22-Oct-20209K
IceTypes.def22-Oct-20204.9K
IceTypes.h22-Oct-20205.9K
IceUtils.h22-Oct-20205.9K
IceVariableSplitting.cpp22-Oct-202023.3K
IceVariableSplitting.h22-Oct-2020764
LinuxMallocProfiling.cpp22-Oct-20202.9K
LinuxMallocProfiling.h22-Oct-20201K
main.cpp22-Oct-20201.8K
Makefile22-Oct-2020294
PNaClTranslator.cpp22-Oct-2020117K
PNaClTranslator.h22-Oct-20201.6K
README.SIMD.rst22-Oct-20202.6K
SZTargets.def22-Oct-20201K
WasmTranslator.cpp22-Oct-202055K
WasmTranslator.h22-Oct-20202K

README.SIMD.rst

      1 Missing support
      2 ===============
      3 
      4 * The PNaCl LLVM backend expands shufflevector operations into sequences of
      5   insertelement and extractelement operations. For instance:
      6 
      7     define <4 x i32> @shuffle(<4 x i32> %arg1, <4 x i32> %arg2) {
      8     entry:
      9       %res = shufflevector <4 x i32> %arg1,
     10                            <4 x i32> %arg2,
     11                            <4 x i32> <i32 4, i32 5, i32 0, i32 1>
     12       ret <4 x i32> %res
     13     }
     14 
     15   gets expanded into:
     16 
     17     define <4 x i32> @shuffle(<4 x i32> %arg1, <4 x i32> %arg2) {
     18     entry:
     19       %0 = extractelement <4 x i32> %arg2, i32 0
     20       %1 = insertelement <4 x i32> undef, i32 %0, i32 0
     21       %2 = extractelement <4 x i32> %arg2, i32 1
     22       %3 = insertelement <4 x i32> %1, i32 %2, i32 1
     23       %4 = extractelement <4 x i32> %arg1, i32 0
     24       %5 = insertelement <4 x i32> %3, i32 %4, i32 2
     25       %6 = extractelement <4 x i32> %arg1, i32 1
     26       %7 = insertelement <4 x i32> %5, i32 %6, i32 3
     27       ret <4 x i32> %7
     28     }
     29 
     30   Subzero should recognize these sequences and recombine them into
     31   shuffle operations where appropriate.
     32 
     33 * Add support for vector constants in the backend. The current code
     34   materializes the vector constants it needs (eg. for performing icmp on
     35   unsigned operands) using register operations, but this should be changed to
     36   loading them from a constant pool if the register initialization is too
     37   complicated (such as in TargetX8632::makeVectorOfHighOrderBits()).
     38 
     39 * [x86 specific] llvm-mc does not allow lea to take a mem128 memory operand
     40   when assembling x86-32 code. The current InstX8632Lea::emit() code uses
     41   Variable::asType() to convert any mem128 Variables into a compatible memory
     42   operand type. However, the emit code does not do any conversions of
     43   OperandX8632Mem, so if an OperandX8632Mem is passed to lea as mem128 the
     44   resulting code will not assemble.  One way to fix this is by implementing
     45   OperandX8632Mem::asType().
     46 
     47 * [x86 specific] Lower shl with <4 x i32> using some clever float conversion:
     48 http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20100726/105087.html
     49 
     50 * [x86 specific] Add support for using aligned mov operations (movaps). This
     51   will require passing alignment information to loads and stores.
     52 
     53 x86 SIMD Diversification
     54 ========================
     55 
     56 * Vector "bitwise" operations have several variant instructions: the AND
     57   operation can be implemented with pand, andpd, or andps. This pattern also
     58   holds for ANDN, OR, and XOR.
     59 
     60 * Vector "mov" instructions can be diversified (eg. movdqu instead of movups)
     61   at the cost of a possible performance penalty.
     62 
     63 * Scalar FP arithmetic can be diversified by performing the operations with the
     64   vector version of the instructions.
     65