1 ; This is a smoke test of randomized register allocation. The output 2 ; of this test will change with changes to the random number generator 3 ; implementation. 4 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -sz-seed=1 \ 6 ; RUN: -randomize-regalloc -split-local-vars=0 \ 7 ; RUN: | FileCheck %s --check-prefix=CHECK_1 8 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -sz-seed=1 \ 9 ; RUN: -randomize-regalloc \ 10 ; RUN: | FileCheck %s --check-prefix=OPTM1_1 11 12 ; Same tests but with a different seed, just to verify randomness. 13 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -sz-seed=123 \ 14 ; RUN: -randomize-regalloc -split-local-vars=0 \ 15 ; RUN: | FileCheck %s --check-prefix=CHECK_123 16 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -sz-seed=123 \ 17 ; RUN: -randomize-regalloc \ 18 ; RUN: | FileCheck %s --check-prefix=OPTM1_123 19 20 define internal <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) { 21 entry: 22 %res = mul <4 x i32> %a, %b 23 ret <4 x i32> %res 24 ; OPTM1_1-LABEL: mul_v4i32 25 ; OPTM1_1: sub esp,0x3c 26 ; OPTM1_1-NEXT: movups XMMWORD PTR [esp+0x20],xmm0 27 ; OPTM1_1-NEXT: movups XMMWORD PTR [esp+0x10],xmm1 28 ; OPTM1_1-NEXT: movups xmm0,XMMWORD PTR [esp+0x20] 29 ; OPTM1_1-NEXT: pshufd xmm6,XMMWORD PTR [esp+0x20],0x31 30 ; OPTM1_1-NEXT: pshufd xmm2,XMMWORD PTR [esp+0x10],0x31 31 ; OPTM1_1-NEXT: pmuludq xmm0,XMMWORD PTR [esp+0x10] 32 ; OPTM1_1-NEXT: pmuludq xmm6,xmm2 33 ; OPTM1_1-NEXT: shufps xmm0,xmm6,0x88 34 ; OPTM1_1-NEXT: pshufd xmm0,xmm0,0xd8 35 ; OPTM1_1-NEXT: movups XMMWORD PTR [esp],xmm0 36 ; OPTM1_1-NEXT: movups xmm0,XMMWORD PTR [esp] 37 ; OPTM1_1-NEXT: add esp,0x3c 38 ; OPTM1_1-NEXT: ret 39 40 ; CHECK_1-LABEL: mul_v4i32 41 ; CHECK_1: movups xmm7,xmm0 42 ; CHECK_1-NEXT: pshufd xmm0,xmm0,0x31 43 ; CHECK_1-NEXT: pshufd xmm5,xmm1,0x31 44 ; CHECK_1-NEXT: pmuludq xmm7,xmm1 45 ; CHECK_1-NEXT: pmuludq xmm0,xmm5 46 ; CHECK_1-NEXT: shufps xmm7,xmm0,0x88 47 ; CHECK_1-NEXT: pshufd xmm7,xmm7,0xd8 48 ; CHECK_1-NEXT: movups xmm0,xmm7 49 ; CHECK_1-NEXT: ret 50 51 ; OPTM1_123-LABEL: mul_v4i32 52 ; OPTM1_123: sub esp,0x3c 53 ; OPTM1_123-NEXT: movups XMMWORD PTR [esp+0x20],xmm0 54 ; OPTM1_123-NEXT: movups XMMWORD PTR [esp+0x10],xmm1 55 ; OPTM1_123-NEXT: movups xmm0,XMMWORD PTR [esp+0x20] 56 ; OPTM1_123-NEXT: pshufd xmm6,XMMWORD PTR [esp+0x20],0x31 57 ; OPTM1_123-NEXT: pshufd xmm2,XMMWORD PTR [esp+0x10],0x31 58 ; OPTM1_123-NEXT: pmuludq xmm0,XMMWORD PTR [esp+0x10] 59 ; OPTM1_123-NEXT: pmuludq xmm6,xmm2 60 ; OPTM1_123-NEXT: shufps xmm0,xmm6,0x88 61 ; OPTM1_123-NEXT: pshufd xmm0,xmm0,0xd8 62 ; OPTM1_123-NEXT: movups XMMWORD PTR [esp],xmm0 63 ; OPTM1_123-NEXT: movups xmm0,XMMWORD PTR [esp] 64 ; OPTM1_123-NEXT: add esp,0x3c 65 ; OPTM1_123-NEXT: ret 66 67 ; CHECK_123-LABEL: mul_v4i32 68 ; CHECK_123: movups xmm5,xmm0 69 ; CHECK_123-NEXT: pshufd xmm0,xmm0,0x31 70 ; CHECK_123-NEXT: pshufd xmm7,xmm1,0x31 71 ; CHECK_123-NEXT: pmuludq xmm5,xmm1 72 ; CHECK_123-NEXT: pmuludq xmm0,xmm7 73 ; CHECK_123-NEXT: shufps xmm5,xmm0,0x88 74 ; CHECK_123-NEXT: pshufd xmm5,xmm5,0xd8 75 ; CHECK_123-NEXT: movups xmm0,xmm5 76 ; CHECK_123-NEXT: ret 77 } 78 79 ; ERRORS-NOT: ICE translation error 80 ; DUMP-NOT: SZ 81
