1 2 3 ###FILE: ../xed/datafiles/xed-isa.txt 4 5 #BEGIN_LEGAL 6 # 7 #Copyright (c) 2016 Intel Corporation 8 # 9 # Licensed under the Apache License, Version 2.0 (the "License"); 10 # you may not use this file except in compliance with the License. 11 # You may obtain a copy of the License at 12 # 13 # http://www.apache.org/licenses/LICENSE-2.0 14 # 15 # Unless required by applicable law or agreed to in writing, software 16 # distributed under the License is distributed on an "AS IS" BASIS, 17 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 18 # See the License for the specific language governing permissions and 19 # limitations under the License. 20 # 21 #END_LEGAL 22 23 24 INSTRUCTIONS():: 25 { 26 ICLASS : FADD 27 ATTRIBUTES: NOTSX 28 CPL : 3 29 CATEGORY : X87_ALU 30 EXTENSION : X87 31 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 32 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 33 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP 34 } 35 { 36 ICLASS : FMUL 37 ATTRIBUTES: NOTSX 38 CPL : 3 39 CATEGORY : X87_ALU 40 EXTENSION : X87 41 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 42 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 43 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP 44 } 45 { 46 ICLASS : FCOMP 47 ATTRIBUTES: NOTSX 48 CPL : 3 49 CATEGORY : X87_ALU 50 EXTENSION : X87 51 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 52 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 53 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 54 } 55 { 56 ICLASS : FSUB 57 ATTRIBUTES: NOTSX 58 CPL : 3 59 CATEGORY : X87_ALU 60 EXTENSION : X87 61 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 62 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 63 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP 64 } 65 { 66 ICLASS : FSUBR 67 ATTRIBUTES: NOTSX 68 CPL : 3 69 CATEGORY : X87_ALU 70 EXTENSION : X87 71 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 72 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 73 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP 74 } 75 { 76 ICLASS : FDIV 77 ATTRIBUTES: NOTSX 78 CPL : 3 79 CATEGORY : X87_ALU 80 EXTENSION : X87 81 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 82 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 83 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP 84 } 85 { 86 ICLASS : FDIVR 87 ATTRIBUTES: NOTSX 88 CPL : 3 89 CATEGORY : X87_ALU 90 EXTENSION : X87 91 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 92 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 93 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP 94 } 95 { 96 ICLASS : FADD 97 ATTRIBUTES: NOTSX 98 CPL : 3 99 CATEGORY : X87_ALU 100 EXTENSION : X87 101 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 102 PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b000] RM[nnn] 103 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 104 } 105 { 106 ICLASS : FMUL 107 ATTRIBUTES: NOTSX 108 CPL : 3 109 CATEGORY : X87_ALU 110 EXTENSION : X87 111 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 112 PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 113 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 114 } 115 { 116 ICLASS : FCOM 117 ATTRIBUTES: NOTSX 118 CPL : 3 119 CATEGORY : X87_ALU 120 EXTENSION : X87 121 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 122 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 123 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP 124 125 PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 126 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP 127 } 128 129 { 130 ICLASS : FCOM 131 ATTRIBUTES: NOTSX 132 CPL : 3 133 CATEGORY : X87_ALU 134 EXTENSION : X87 135 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 136 PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 137 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 138 139 COMMENT : UNDOC DC D0..D7 is an undocumented alaias (see sandpile.org) 140 PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b010] RM[nnn] 141 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 142 IFORM : FCOM_ST0_X87_DCD0 143 } 144 145 146 { 147 ICLASS : FCOMP 148 ATTRIBUTES: NOTSX 149 CPL : 3 150 CATEGORY : X87_ALU 151 EXTENSION : X87 152 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 153 PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 154 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 155 } 156 157 { 158 ICLASS : FCOMP 159 ATTRIBUTES: NOTSX 160 COMMENT : UNDOC ALIASES 161 CPL : 3 162 CATEGORY : X87_ALU 163 EXTENSION : X87 164 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 165 PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b011] RM[nnn] 166 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 167 IFORM : FCOMP_ST0_X87_DCD1 168 169 PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn] 170 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 171 IFORM : FCOMP_ST0_X87_DED0 172 } 173 174 175 { 176 ICLASS : FSUB 177 ATTRIBUTES: NOTSX 178 CPL : 3 179 CATEGORY : X87_ALU 180 EXTENSION : X87 181 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 182 PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b100] RM[nnn] 183 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 184 } 185 { 186 ICLASS : FSUBR 187 ATTRIBUTES: NOTSX 188 CPL : 3 189 CATEGORY : X87_ALU 190 EXTENSION : X87 191 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 192 PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b101] RM[nnn] 193 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 194 } 195 { 196 ICLASS : FDIV 197 ATTRIBUTES: NOTSX 198 CPL : 3 199 CATEGORY : X87_ALU 200 EXTENSION : X87 201 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 202 PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b110] RM[nnn] 203 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 204 } 205 { 206 ICLASS : FDIVR 207 ATTRIBUTES: NOTSX 208 CPL : 3 209 CATEGORY : X87_ALU 210 EXTENSION : X87 211 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 212 PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b111] RM[nnn] 213 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 214 } 215 { 216 ICLASS : FLD 217 ATTRIBUTES: NOTSX 218 CPL : 3 219 CATEGORY : X87_ALU 220 EXTENSION : X87 221 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 222 PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 223 OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 224 } 225 { 226 ICLASS : FST 227 ATTRIBUTES: NOTSX 228 CPL : 3 229 CATEGORY : X87_ALU 230 EXTENSION : X87 231 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 232 PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 233 OPERANDS : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP 234 } 235 { 236 ICLASS : FSTP 237 ATTRIBUTES: NOTSX 238 CPL : 3 239 CATEGORY : X87_ALU 240 EXTENSION : X87 241 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 242 PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 243 OPERANDS : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 244 245 PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 246 OPERANDS : MEM0:w:mem80real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 247 248 PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 249 OPERANDS : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 250 } 251 { 252 ICLASS : FSTP 253 ATTRIBUTES: NOTSX 254 CPL : 3 255 CATEGORY : X87_ALU 256 EXTENSION : X87 257 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 258 PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn] 259 OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 260 261 COMMENT : UNDOC ALIASES 262 PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn] 263 OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 264 IFORM : FSTP_X87_ST0_DFD0 265 266 PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn] 267 OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 268 IFORM : FSTP_X87_ST0_DFD1 269 } 270 271 { 272 ICLASS : FSTPNCE 273 ATTRIBUTES: NOTSX 274 CPL : 3 275 CATEGORY : X87_ALU 276 EXTENSION : X87 277 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 278 COMMENT : UNDOC ALIASES - empty top of stack behavior differs from FSTP. 279 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 280 OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 281 } 282 283 284 285 { 286 ICLASS : FLDENV 287 CPL : 3 288 CATEGORY : X87_ALU 289 EXTENSION : X87 290 ATTRIBUTES : X87_CONTROL NOTSX 291 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 292 PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ=1 MODRM() 293 OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP 294 PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ!=1 MODRM() 295 OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP 296 } 297 { 298 ICLASS : FLDCW 299 CPL : 3 300 CATEGORY : X87_ALU 301 EXTENSION : X87 302 ATTRIBUTES : X87_CONTROL NOTSX 303 FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] 304 PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 305 OPERANDS : MEM0:r:mem16 REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87STATUS:w:SUPP 306 } 307 { 308 ICLASS : FNSTENV 309 CPL : 3 310 CATEGORY : X87_ALU 311 EXTENSION : X87 312 ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX 313 FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] 314 PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ=1 MODRM() 315 OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP 316 PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ!=1 MODRM() 317 OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP 318 } 319 { 320 ICLASS : FNSTCW 321 CPL : 3 322 CATEGORY : X87_ALU 323 EXTENSION : X87 324 ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX 325 FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] 326 PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 327 OPERANDS : MEM0:w:mem16 REG0=XED_REG_X87CONTROL:r:SUPP REG1=XED_REG_X87STATUS:w:SUPP 328 } 329 { 330 ICLASS : FLD 331 ATTRIBUTES: NOTSX 332 CPL : 3 333 CATEGORY : X87_ALU 334 EXTENSION : X87 335 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 336 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] 337 OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87PUSH:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 338 } 339 { 340 ICLASS : FXCH 341 ATTRIBUTES: NOTSX 342 CPL : 3 343 CATEGORY : X87_ALU 344 EXTENSION : X87 345 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 346 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 347 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP 348 } 349 { 350 ICLASS : FXCH 351 ATTRIBUTES: NOTSX 352 CPL : 3 353 COMMENT : UNDOC ALIAS 354 CATEGORY : X87_ALU 355 EXTENSION : X87 356 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 357 PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn] 358 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP 359 IFORM : FXCH_ST0_X87_DFC1 360 361 PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn] 362 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP 363 IFORM : FXCH_ST0_X87_DDC1 364 } 365 366 367 368 { 369 ICLASS : FNOP 370 CPL : 3 371 CATEGORY : X87_ALU 372 EXTENSION : X87 373 ATTRIBUTES: NOP X87_CONTROL NOTSX 374 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000] 375 OPERANDS : 376 } 377 { 378 ICLASS : FCHS 379 ATTRIBUTES: NOTSX 380 CPL : 3 381 CATEGORY : X87_ALU 382 EXTENSION : X87 383 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 384 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000] 385 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP 386 } 387 { 388 ICLASS : FABS 389 ATTRIBUTES: NOTSX 390 CPL : 3 391 CATEGORY : X87_ALU 392 EXTENSION : X87 393 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 394 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001] 395 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP 396 } 397 { 398 ICLASS : FTST 399 ATTRIBUTES: NOTSX 400 CPL : 3 401 CATEGORY : X87_ALU 402 EXTENSION : X87 403 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 404 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100] 405 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP 406 } 407 { 408 ICLASS : FXAM 409 ATTRIBUTES: NOTSX 410 CPL : 3 411 CATEGORY : X87_ALU 412 EXTENSION : X87 413 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 414 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101] 415 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP 416 } 417 { 418 ICLASS : FLD1 419 ATTRIBUTES: NOTSX 420 CPL : 3 421 CATEGORY : X87_ALU 422 EXTENSION : X87 423 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 424 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000] 425 OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 426 } 427 { 428 ICLASS : FLDL2T 429 ATTRIBUTES: NOTSX 430 CPL : 3 431 CATEGORY : X87_ALU 432 EXTENSION : X87 433 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 434 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001] 435 OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 436 } 437 { 438 ICLASS : FLDL2E 439 ATTRIBUTES: NOTSX 440 CPL : 3 441 CATEGORY : X87_ALU 442 EXTENSION : X87 443 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 444 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010] 445 OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 446 } 447 { 448 ICLASS : FLDPI 449 ATTRIBUTES: NOTSX 450 CPL : 3 451 CATEGORY : X87_ALU 452 EXTENSION : X87 453 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 454 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011] 455 OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 456 } 457 { 458 ICLASS : FLDLG2 459 ATTRIBUTES: NOTSX 460 CPL : 3 461 CATEGORY : X87_ALU 462 EXTENSION : X87 463 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 464 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100] 465 OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 466 } 467 { 468 ICLASS : FLDLN2 469 ATTRIBUTES: NOTSX 470 CPL : 3 471 CATEGORY : X87_ALU 472 EXTENSION : X87 473 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 474 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101] 475 OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 476 } 477 { 478 ICLASS : FLDZ 479 ATTRIBUTES: NOTSX 480 CPL : 3 481 CATEGORY : X87_ALU 482 EXTENSION : X87 483 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 484 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110] 485 OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 486 } 487 { 488 ICLASS : F2XM1 489 ATTRIBUTES: NOTSX 490 CPL : 3 491 CATEGORY : X87_ALU 492 EXTENSION : X87 493 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 494 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000] 495 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP 496 } 497 { 498 ICLASS : FYL2X 499 ATTRIBUTES: NOTSX 500 CPL : 3 501 CATEGORY : X87_ALU 502 EXTENSION : X87 503 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 504 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001] 505 OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 506 } 507 { 508 ICLASS : FPTAN 509 ATTRIBUTES: NOTSX 510 CPL : 3 511 CATEGORY : X87_ALU 512 EXTENSION : X87 513 FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] 514 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010] 515 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP 516 } 517 { 518 ICLASS : FPATAN 519 ATTRIBUTES: NOTSX 520 CPL : 3 521 CATEGORY : X87_ALU 522 EXTENSION : X87 523 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 524 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011] 525 OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 526 } 527 { 528 ICLASS : FXTRACT 529 ATTRIBUTES: NOTSX 530 CPL : 3 531 CATEGORY : X87_ALU 532 EXTENSION : X87 533 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 534 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100] 535 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP 536 } 537 { 538 ICLASS : FPREM1 539 ATTRIBUTES: NOTSX 540 CPL : 3 541 CATEGORY : X87_ALU 542 EXTENSION : X87 543 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 544 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101] 545 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP 546 } 547 { 548 ICLASS : FDECSTP 549 CPL : 3 550 CATEGORY : X87_ALU 551 EXTENSION : X87 552 ATTRIBUTES: X87_CONTROL NOTSX 553 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 554 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110] 555 OPERANDS : REG0=XED_REG_X87STATUS:rw:SUPP 556 } 557 { 558 ICLASS : FINCSTP 559 CPL : 3 560 CATEGORY : X87_ALU 561 EXTENSION : X87 562 ATTRIBUTES: X87_CONTROL NOTSX 563 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 564 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111] 565 OPERANDS : REG0=XED_REG_X87STATUS:rw:SUPP 566 } 567 { 568 ICLASS : FPREM 569 ATTRIBUTES: NOTSX 570 CPL : 3 571 CATEGORY : X87_ALU 572 EXTENSION : X87 573 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 574 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000] 575 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP 576 } 577 { 578 ICLASS : FYL2XP1 579 ATTRIBUTES: NOTSX 580 CPL : 3 581 CATEGORY : X87_ALU 582 EXTENSION : X87 583 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 584 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001] 585 OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 586 } 587 { 588 ICLASS : FSQRT 589 ATTRIBUTES: NOTSX 590 CPL : 3 591 CATEGORY : X87_ALU 592 EXTENSION : X87 593 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 594 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010] 595 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP 596 } 597 { 598 ICLASS : FSINCOS 599 ATTRIBUTES: NOTSX 600 CPL : 3 601 CATEGORY : X87_ALU 602 EXTENSION : X87 603 FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] 604 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011] 605 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP 606 } 607 { 608 ICLASS : FRNDINT 609 ATTRIBUTES: NOTSX 610 CPL : 3 611 CATEGORY : X87_ALU 612 EXTENSION : X87 613 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 614 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100] 615 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP 616 } 617 { 618 ICLASS : FSCALE 619 ATTRIBUTES: NOTSX 620 CPL : 3 621 CATEGORY : X87_ALU 622 EXTENSION : X87 623 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 624 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101] 625 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP 626 } 627 { 628 ICLASS : FSIN 629 ATTRIBUTES: NOTSX 630 CPL : 3 631 CATEGORY : X87_ALU 632 EXTENSION : X87 633 FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] 634 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110] 635 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP 636 } 637 { 638 ICLASS : FCOS 639 ATTRIBUTES: NOTSX 640 CPL : 3 641 CATEGORY : X87_ALU 642 EXTENSION : X87 643 FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] 644 PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111] 645 OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP 646 } 647 { 648 ICLASS : FIADD 649 ATTRIBUTES: NOTSX 650 CPL : 3 651 CATEGORY : X87_ALU 652 EXTENSION : X87 653 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 654 PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 655 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP 656 } 657 { 658 ICLASS : FIMUL 659 ATTRIBUTES: NOTSX 660 CPL : 3 661 CATEGORY : X87_ALU 662 EXTENSION : X87 663 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 664 PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 665 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP 666 } 667 { 668 ICLASS : FICOM 669 ATTRIBUTES: NOTSX 670 CPL : 3 671 CATEGORY : X87_ALU 672 EXTENSION : X87 673 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 674 PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 675 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP 676 } 677 { 678 ICLASS : FICOMP 679 ATTRIBUTES: NOTSX 680 CPL : 3 681 CATEGORY : X87_ALU 682 EXTENSION : X87 683 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 684 PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 685 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 686 } 687 { 688 ICLASS : FISUB 689 ATTRIBUTES: NOTSX 690 CPL : 3 691 CATEGORY : X87_ALU 692 EXTENSION : X87 693 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 694 PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 695 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP 696 } 697 { 698 ICLASS : FISUBR 699 ATTRIBUTES: NOTSX 700 CPL : 3 701 CATEGORY : X87_ALU 702 EXTENSION : X87 703 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 704 PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 705 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP 706 } 707 { 708 ICLASS : FIDIV 709 ATTRIBUTES: NOTSX 710 CPL : 3 711 CATEGORY : X87_ALU 712 EXTENSION : X87 713 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 714 PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 715 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP 716 } 717 { 718 ICLASS : FIDIVR 719 ATTRIBUTES: NOTSX 720 CPL : 3 721 CATEGORY : X87_ALU 722 EXTENSION : X87 723 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 724 PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 725 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP 726 } 727 { 728 ICLASS : FCMOVB 729 ATTRIBUTES: NOTSX 730 CPL : 3 731 CATEGORY : FCMOV 732 EXTENSION : X87 733 ISA_SET : PPRO 734 FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ] 735 PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn] 736 OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 737 } 738 { 739 ICLASS : FCMOVE 740 ATTRIBUTES: NOTSX 741 CPL : 3 742 CATEGORY : FCMOV 743 EXTENSION : X87 744 ISA_SET : PPRO 745 FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ] 746 PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn] 747 OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 748 } 749 { 750 ICLASS : FCMOVBE 751 ATTRIBUTES: NOTSX 752 CPL : 3 753 CATEGORY : FCMOV 754 EXTENSION : X87 755 ISA_SET : PPRO 756 FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ] 757 PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn] 758 OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 759 } 760 { 761 ICLASS : FCMOVU 762 ATTRIBUTES: NOTSX 763 CPL : 3 764 CATEGORY : FCMOV 765 EXTENSION : X87 766 ISA_SET : PPRO 767 FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ] 768 PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn] 769 OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 770 } 771 { 772 ICLASS : FUCOMPP 773 ATTRIBUTES: NOTSX 774 CPL : 3 775 CATEGORY : X87_ALU 776 EXTENSION : X87 777 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 778 PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b101] RM[0b001] 779 OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:rw:SUPP REG3=XED_REG_X87STATUS:rw:SUPP 780 } 781 { 782 ICLASS : FILD 783 ATTRIBUTES: NOTSX 784 CPL : 3 785 CATEGORY : X87_ALU 786 EXTENSION : X87 787 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 788 PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 789 OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 790 } 791 { 792 ICLASS : FISTTP 793 ATTRIBUTES: NOTSX 794 CPL : 3 795 CATEGORY : X87_ALU 796 EXTENSION : SSE3 797 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 798 PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 799 OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 800 } 801 { 802 ICLASS : FIST 803 ATTRIBUTES: NOTSX 804 CPL : 3 805 CATEGORY : X87_ALU 806 EXTENSION : X87 807 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 808 PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 809 OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP 810 } 811 { 812 ICLASS : FISTP 813 ATTRIBUTES: NOTSX 814 CPL : 3 815 CATEGORY : X87_ALU 816 EXTENSION : X87 817 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 818 PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 819 OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 820 } 821 { 822 ICLASS : FLD 823 ATTRIBUTES: NOTSX 824 CPL : 3 825 CATEGORY : X87_ALU 826 EXTENSION : X87 827 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 828 PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 829 OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 830 } 831 { 832 ICLASS : FCMOVNB 833 ATTRIBUTES: NOTSX 834 CPL : 3 835 CATEGORY : FCMOV 836 EXTENSION : X87 837 ISA_SET : PPRO 838 FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ] 839 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn] 840 OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 841 } 842 { 843 ICLASS : FCMOVNE 844 ATTRIBUTES: NOTSX 845 CPL : 3 846 CATEGORY : FCMOV 847 EXTENSION : X87 848 ISA_SET : PPRO 849 FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ] 850 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn] 851 OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 852 } 853 { 854 ICLASS : FCMOVNBE 855 ATTRIBUTES: NOTSX 856 CPL : 3 857 CATEGORY : FCMOV 858 EXTENSION : X87 859 ISA_SET : PPRO 860 FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ] 861 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn] 862 OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 863 } 864 { 865 ICLASS : FCMOVNU 866 ATTRIBUTES: NOTSX 867 CPL : 3 868 CATEGORY : FCMOV 869 EXTENSION : X87 870 ISA_SET : PPRO 871 FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ] 872 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn] 873 OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 874 } 875 { 876 ICLASS : FNCLEX 877 CPL : 3 878 CATEGORY : X87_ALU 879 EXTENSION : X87 880 ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX 881 FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] 882 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b010] 883 OPERANDS : REG0=XED_REG_X87STATUS:w:SUPP 884 } 885 { 886 ICLASS : FNINIT 887 CPL : 3 888 ATTRIBUTES : x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX 889 CATEGORY : X87_ALU 890 EXTENSION : X87 891 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 892 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b011] 893 OPERANDS : REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87STATUS:w:SUPP 894 } 895 { 896 ICLASS : FSETPM287_NOP 897 CPL : 3 898 CATEGORY : X87_ALU 899 EXTENSION : X87 900 ATTRIBUTES: NOP NOTSX 901 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b100] 902 OPERANDS : 903 COMMENT : UNDOC 904 } 905 { 906 ICLASS : FENI8087_NOP 907 CPL : 3 908 CATEGORY : X87_ALU 909 EXTENSION : X87 910 ATTRIBUTES: NOP NOTSX 911 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b000] 912 OPERANDS : 913 COMMENT : UNDOC 914 } 915 { 916 ICLASS : FDISI8087_NOP 917 CPL : 3 918 CATEGORY : X87_ALU 919 EXTENSION : X87 920 ATTRIBUTES: NOP NOTSX 921 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b001] 922 COMMENT : UNDOC 923 OPERANDS : 924 } 925 926 927 { 928 ICLASS : FUCOMI 929 ATTRIBUTES: NOTSX 930 CPL : 3 931 CATEGORY : X87_ALU 932 EXTENSION : X87 933 ISA_SET : PPRO 934 FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] 935 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn] 936 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 937 } 938 { 939 ICLASS : FCOMI 940 ATTRIBUTES: NOTSX 941 CPL : 3 942 CATEGORY : X87_ALU 943 EXTENSION : X87 944 ISA_SET : PPRO 945 FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] 946 PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn] 947 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 948 } 949 { 950 ICLASS : FADD 951 ATTRIBUTES: NOTSX 952 CPL : 3 953 CATEGORY : X87_ALU 954 EXTENSION : X87 955 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 956 PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 957 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP 958 } 959 { 960 ICLASS : FMUL 961 ATTRIBUTES: NOTSX 962 CPL : 3 963 CATEGORY : X87_ALU 964 EXTENSION : X87 965 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 966 PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 967 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP 968 } 969 { 970 ICLASS : FCOMP 971 ATTRIBUTES: NOTSX 972 CPL : 3 973 CATEGORY : X87_ALU 974 EXTENSION : X87 975 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 976 PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 977 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 978 } 979 { 980 ICLASS : FSUB 981 ATTRIBUTES: NOTSX 982 CPL : 3 983 CATEGORY : X87_ALU 984 EXTENSION : X87 985 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 986 PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 987 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP 988 } 989 { 990 ICLASS : FSUBR 991 ATTRIBUTES: NOTSX 992 CPL : 3 993 CATEGORY : X87_ALU 994 EXTENSION : X87 995 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 996 PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 997 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP 998 } 999 { 1000 ICLASS : FDIV 1001 ATTRIBUTES: NOTSX 1002 CPL : 3 1003 CATEGORY : X87_ALU 1004 EXTENSION : X87 1005 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1006 PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 1007 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP 1008 } 1009 { 1010 ICLASS : FDIVR 1011 ATTRIBUTES: NOTSX 1012 CPL : 3 1013 CATEGORY : X87_ALU 1014 EXTENSION : X87 1015 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1016 PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 1017 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP 1018 } 1019 { 1020 ICLASS : FADD 1021 ATTRIBUTES: NOTSX 1022 CPL : 3 1023 CATEGORY : X87_ALU 1024 EXTENSION : X87 1025 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1026 PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b000] RM[nnn] 1027 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP 1028 } 1029 { 1030 ICLASS : FMUL 1031 ATTRIBUTES: NOTSX 1032 CPL : 3 1033 CATEGORY : X87_ALU 1034 EXTENSION : X87 1035 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1036 PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b001] RM[nnn] 1037 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP 1038 } 1039 { 1040 ICLASS : FSUBR 1041 ATTRIBUTES: NOTSX 1042 CPL : 3 1043 CATEGORY : X87_ALU 1044 EXTENSION : X87 1045 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1046 PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b100] RM[nnn] 1047 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP 1048 } 1049 { 1050 ICLASS : FSUB 1051 ATTRIBUTES: NOTSX 1052 CPL : 3 1053 CATEGORY : X87_ALU 1054 EXTENSION : X87 1055 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1056 PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b101] RM[nnn] 1057 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP 1058 } 1059 { 1060 ICLASS : FDIVR 1061 ATTRIBUTES: NOTSX 1062 CPL : 3 1063 CATEGORY : X87_ALU 1064 EXTENSION : X87 1065 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1066 PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b110] RM[nnn] 1067 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP 1068 } 1069 { 1070 ICLASS : FDIV 1071 ATTRIBUTES: NOTSX 1072 CPL : 3 1073 CATEGORY : X87_ALU 1074 EXTENSION : X87 1075 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1076 PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b111] RM[nnn] 1077 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP 1078 } 1079 { 1080 ICLASS : FLD 1081 ATTRIBUTES: NOTSX 1082 CPL : 3 1083 CATEGORY : X87_ALU 1084 EXTENSION : X87 1085 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1086 PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 1087 OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 1088 } 1089 { 1090 ICLASS : FISTTP 1091 CPL : 3 1092 CATEGORY : X87_ALU 1093 EXTENSION : SSE3 1094 ATTRIBUTES : NOTSX 1095 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1096 PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 1097 OPERANDS : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 1098 } 1099 { 1100 ICLASS : FST 1101 ATTRIBUTES: NOTSX 1102 CPL : 3 1103 CATEGORY : X87_ALU 1104 EXTENSION : X87 1105 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1106 PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 1107 OPERANDS : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP 1108 } 1109 { 1110 ICLASS : FRSTOR 1111 CPL : 3 1112 CATEGORY : X87_ALU 1113 EXTENSION : X87 1114 ATTRIBUTES : x87_mmx_state_w X87_CONTROL NOTSX 1115 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 1116 PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ=1 MODRM() 1117 OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP 1118 PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] EOSZ!=1 MODRM() 1119 OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP 1120 } 1121 { 1122 ICLASS : FNSAVE 1123 CPL : 3 1124 CATEGORY : X87_ALU 1125 EXTENSION : X87 1126 ATTRIBUTES : x87_mmx_state_r x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX 1127 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 1128 PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ=1 MODRM() 1129 OPERANDS : MEM0:w:mem94 \ 1130 REG0=XED_REG_X87CONTROL:rw:SUPP \ 1131 REG1=XED_REG_X87TAG:rw:SUPP \ 1132 REG3=XED_REG_X87STATUS:rw:SUPP 1133 1134 PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] EOSZ!=1 MODRM() 1135 OPERANDS : MEM0:w:mem108 \ 1136 REG0=XED_REG_X87CONTROL:rw:SUPP \ 1137 REG1=XED_REG_X87TAG:rw:SUPP \ 1138 REG3=XED_REG_X87STATUS:rw:SUPP 1139 } 1140 { 1141 ICLASS : FNSTSW 1142 CPL : 3 1143 CATEGORY : X87_ALU 1144 EXTENSION : X87 1145 ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX 1146 FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] 1147 PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 1148 OPERANDS : MEM0:w:mem16 REG0=XED_REG_X87STATUS:rw:SUPP 1149 } 1150 { 1151 ICLASS : FFREE 1152 CPL : 3 1153 CATEGORY : X87_ALU 1154 EXTENSION : X87 1155 ATTRIBUTES: X87_CONTROL NOTSX 1156 FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] 1157 PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn] 1158 OPERANDS : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP 1159 } 1160 { 1161 ICLASS : FST 1162 ATTRIBUTES: NOTSX 1163 CPL : 3 1164 CATEGORY : X87_ALU 1165 EXTENSION : X87 1166 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1167 PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn] 1168 OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP 1169 } 1170 { 1171 ICLASS : FUCOM 1172 ATTRIBUTES: NOTSX 1173 CPL : 3 1174 CATEGORY : X87_ALU 1175 EXTENSION : X87 1176 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 1177 PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn] 1178 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP 1179 } 1180 { 1181 ICLASS : FUCOMP 1182 ATTRIBUTES: NOTSX 1183 CPL : 3 1184 CATEGORY : X87_ALU 1185 EXTENSION : X87 1186 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 1187 PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn] 1188 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP 1189 } 1190 { 1191 ICLASS : FIADD 1192 ATTRIBUTES: NOTSX 1193 CPL : 3 1194 CATEGORY : X87_ALU 1195 EXTENSION : X87 1196 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1197 PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 1198 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP 1199 } 1200 { 1201 ICLASS : FIMUL 1202 ATTRIBUTES: NOTSX 1203 CPL : 3 1204 CATEGORY : X87_ALU 1205 EXTENSION : X87 1206 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1207 PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 1208 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP 1209 } 1210 { 1211 ICLASS : FICOM 1212 ATTRIBUTES: NOTSX 1213 CPL : 3 1214 CATEGORY : X87_ALU 1215 EXTENSION : X87 1216 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 1217 PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 1218 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP 1219 } 1220 { 1221 ICLASS : FICOMP 1222 ATTRIBUTES: NOTSX 1223 CPL : 3 1224 CATEGORY : X87_ALU 1225 EXTENSION : X87 1226 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 1227 PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 1228 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 1229 } 1230 { 1231 ICLASS : FISUB 1232 ATTRIBUTES: NOTSX 1233 CPL : 3 1234 CATEGORY : X87_ALU 1235 EXTENSION : X87 1236 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1237 PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 1238 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP 1239 } 1240 { 1241 ICLASS : FISUBR 1242 ATTRIBUTES: NOTSX 1243 CPL : 3 1244 CATEGORY : X87_ALU 1245 EXTENSION : X87 1246 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1247 PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 1248 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP 1249 } 1250 { 1251 ICLASS : FIDIV 1252 ATTRIBUTES: NOTSX 1253 CPL : 3 1254 CATEGORY : X87_ALU 1255 EXTENSION : X87 1256 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1257 PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 1258 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP 1259 } 1260 { 1261 ICLASS : FIDIVR 1262 ATTRIBUTES: NOTSX 1263 CPL : 3 1264 CATEGORY : X87_ALU 1265 EXTENSION : X87 1266 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1267 PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 1268 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP 1269 } 1270 { 1271 ICLASS : FADDP 1272 ATTRIBUTES: NOTSX 1273 CPL : 3 1274 CATEGORY : X87_ALU 1275 EXTENSION : X87 1276 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1277 PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn] 1278 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 1279 COMMENT : 2011-02-10: the pop essentially occurs later. faddp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. 1280 } 1281 { 1282 ICLASS : FMULP 1283 ATTRIBUTES: NOTSX 1284 CPL : 3 1285 CATEGORY : X87_ALU 1286 EXTENSION : X87 1287 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1288 PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn] 1289 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 1290 COMMENT : 2011-02-10: the pop essentially occurs later. fmulp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. 1291 } 1292 { 1293 ICLASS : FCOMPP 1294 ATTRIBUTES: NOTSX 1295 CPL : 3 1296 CATEGORY : X87_ALU 1297 EXTENSION : X87 1298 FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] 1299 PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b011] RM[0b001] 1300 OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP 1301 } 1302 { 1303 ICLASS : FSUBRP 1304 ATTRIBUTES: NOTSX 1305 CPL : 3 1306 CATEGORY : X87_ALU 1307 EXTENSION : X87 1308 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1309 PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn] 1310 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 1311 COMMENT : 2011-02-10: the pop essentially occurs later. fsubrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. 1312 1313 } 1314 { 1315 ICLASS : FSUBP 1316 ATTRIBUTES: NOTSX 1317 CPL : 3 1318 CATEGORY : X87_ALU 1319 EXTENSION : X87 1320 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1321 PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn] 1322 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 1323 COMMENT : 2011-02-10: the pop essentially occurs later. fsubp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. 1324 } 1325 { 1326 ICLASS : FDIVRP 1327 ATTRIBUTES: NOTSX 1328 CPL : 3 1329 CATEGORY : X87_ALU 1330 EXTENSION : X87 1331 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1332 PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn] 1333 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 1334 COMMENT : 2011-02-10: the pop essentially occurs later. fdivrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. 1335 1336 } 1337 { 1338 ICLASS : FDIVP 1339 ATTRIBUTES: NOTSX 1340 CPL : 3 1341 CATEGORY : X87_ALU 1342 EXTENSION : X87 1343 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1344 PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn] 1345 OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 1346 COMMENT : 2011-02-10: the pop essentially occurs later. fdivp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. 1347 } 1348 { 1349 ICLASS : FILD 1350 ATTRIBUTES: NOTSX 1351 CPL : 3 1352 CATEGORY : X87_ALU 1353 EXTENSION : X87 1354 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1355 PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 1356 OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 1357 } 1358 { 1359 ICLASS : FISTTP 1360 ATTRIBUTES: NOTSX 1361 CPL : 3 1362 CATEGORY : X87_ALU 1363 EXTENSION : SSE3 1364 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1365 PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 1366 OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 1367 } 1368 { 1369 ICLASS : FIST 1370 ATTRIBUTES: NOTSX 1371 CPL : 3 1372 CATEGORY : X87_ALU 1373 EXTENSION : X87 1374 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1375 PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 1376 OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP 1377 } 1378 { 1379 ICLASS : FISTP 1380 ATTRIBUTES: NOTSX 1381 CPL : 3 1382 CATEGORY : X87_ALU 1383 EXTENSION : X87 1384 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1385 PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 1386 OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 1387 } 1388 { 1389 ICLASS : FBLD 1390 ATTRIBUTES: NOTSX 1391 CPL : 3 1392 CATEGORY : X87_ALU 1393 EXTENSION : X87 1394 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1395 PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 1396 OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80dec REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 1397 } 1398 { 1399 ICLASS : FILD 1400 ATTRIBUTES: NOTSX 1401 CPL : 3 1402 CATEGORY : X87_ALU 1403 EXTENSION : X87 1404 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1405 PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 1406 OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 1407 } 1408 { 1409 ICLASS : FBSTP 1410 ATTRIBUTES: NOTSX 1411 CPL : 3 1412 CATEGORY : X87_ALU 1413 EXTENSION : X87 1414 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1415 PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 1416 OPERANDS : MEM0:w:mem80dec REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 1417 } 1418 { 1419 ICLASS : FISTP 1420 ATTRIBUTES: NOTSX 1421 CPL : 3 1422 CATEGORY : X87_ALU 1423 EXTENSION : X87 1424 FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] 1425 PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 1426 OPERANDS : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP 1427 } 1428 { 1429 ICLASS : FFREEP 1430 CPL : 3 1431 CATEGORY : X87_ALU 1432 EXTENSION : X87 1433 ATTRIBUTES: X87_CONTROL NOTSX 1434 FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] 1435 PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn] 1436 OPERANDS : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87POP:r:SUPP 1437 COMMENT : UNDOC 1438 } 1439 { 1440 ICLASS : FNSTSW 1441 CPL : 3 1442 CATEGORY : X87_ALU 1443 EXTENSION : X87 1444 ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX 1445 FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] 1446 PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b100] RM[0b000] 1447 OPERANDS : REG0=XED_REG_AX:w:IMPL REG1=XED_REG_X87STATUS:rw:SUPP 1448 } 1449 { 1450 ICLASS : FUCOMIP 1451 ATTRIBUTES: NOTSX 1452 CPL : 3 1453 CATEGORY : X87_ALU 1454 EXTENSION : X87 1455 ISA_SET : PPRO 1456 FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] 1457 PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn] 1458 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 1459 } 1460 { 1461 ICLASS : FCOMIP 1462 ATTRIBUTES: NOTSX 1463 CPL : 3 1464 CATEGORY : X87_ALU 1465 EXTENSION : X87 1466 ISA_SET : PPRO 1467 FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] 1468 PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn] 1469 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP 1470 } 1471 { 1472 ICLASS : ADD_LOCK 1473 DISASM : add 1474 CPL : 3 1475 CATEGORY : BINARY 1476 EXTENSION : BASE 1477 ISA_SET : I86 1478 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1479 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1480 1481 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix 1482 OPERANDS : MEM0:rw:b IMM0:r:b:i8 1483 IFORM : ADD_LOCK_MEMb_IMMb_80r0 1484 } 1485 { 1486 ICLASS : ADD 1487 CPL : 3 1488 CATEGORY : BINARY 1489 EXTENSION : BASE 1490 ISA_SET : I86 1491 ATTRIBUTES : BYTEOP LOCKABLE 1492 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1493 1494 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix 1495 OPERANDS : MEM0:rw:b IMM0:r:b:i8 1496 IFORM : ADD_MEMb_IMMb_80r0 1497 } 1498 1499 1500 1501 { 1502 ICLASS : ADD 1503 CPL : 3 1504 CATEGORY : BINARY 1505 EXTENSION : BASE 1506 ISA_SET : I86 1507 ATTRIBUTES : BYTEOP 1508 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1509 1510 PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() 1511 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 1512 IFORM : ADD_GPR8_IMMb_80r0 1513 } 1514 1515 1516 1517 { 1518 ICLASS : OR_LOCK 1519 DISASM : or 1520 CPL : 3 1521 CATEGORY : LOGICAL 1522 EXTENSION : BASE 1523 ISA_SET : I86 1524 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1525 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1526 1527 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix 1528 OPERANDS : MEM0:rw:b IMM0:r:b:i8 1529 IFORM : OR_LOCK_MEMb_IMMb_80r1 1530 } 1531 { 1532 ICLASS : OR 1533 CPL : 3 1534 CATEGORY : LOGICAL 1535 EXTENSION : BASE 1536 ISA_SET : I86 1537 ATTRIBUTES : BYTEOP LOCKABLE 1538 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1539 1540 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix 1541 OPERANDS : MEM0:rw:b IMM0:r:b:i8 1542 IFORM : OR_MEMb_IMMb_80r1 1543 } 1544 1545 1546 { 1547 ICLASS : OR 1548 CPL : 3 1549 CATEGORY : LOGICAL 1550 EXTENSION : BASE 1551 ISA_SET : I86 1552 ATTRIBUTES : BYTEOP 1553 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1554 PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() 1555 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 1556 IFORM : OR_GPR8_IMMb_80r1 1557 } 1558 1559 1560 1561 { 1562 ICLASS : ADC_LOCK 1563 DISASM : adc 1564 CPL : 3 1565 CATEGORY : BINARY 1566 EXTENSION : BASE 1567 ISA_SET : I86 1568 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1569 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 1570 1571 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix 1572 OPERANDS : MEM0:rw:b IMM0:r:b:i8 1573 IFORM : ADC_LOCK_MEMb_IMMb_80r2 1574 } 1575 { 1576 ICLASS : ADC 1577 CPL : 3 1578 CATEGORY : BINARY 1579 EXTENSION : BASE 1580 ISA_SET : I86 1581 ATTRIBUTES : BYTEOP LOCKABLE 1582 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 1583 1584 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix 1585 OPERANDS : MEM0:rw:b IMM0:r:b:i8 1586 IFORM : ADC_MEMb_IMMb_80r2 1587 } 1588 1589 { 1590 ICLASS : ADC 1591 CPL : 3 1592 CATEGORY : BINARY 1593 EXTENSION : BASE 1594 ISA_SET : I86 1595 ATTRIBUTES : BYTEOP 1596 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 1597 1598 PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8() 1599 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 1600 IFORM : ADC_GPR8_IMMb_80r2 1601 } 1602 1603 1604 { 1605 ICLASS : SBB_LOCK 1606 DISASM : sbb 1607 CPL : 3 1608 CATEGORY : BINARY 1609 EXTENSION : BASE 1610 ISA_SET : I86 1611 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1612 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 1613 1614 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix 1615 OPERANDS : MEM0:rw:b IMM0:r:b:i8 1616 IFORM : SBB_LOCK_MEMb_IMMb_80r3 1617 } 1618 { 1619 ICLASS : SBB 1620 CPL : 3 1621 CATEGORY : BINARY 1622 EXTENSION : BASE 1623 ISA_SET : I86 1624 ATTRIBUTES : BYTEOP LOCKABLE 1625 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 1626 1627 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix 1628 OPERANDS : MEM0:rw:b IMM0:r:b:i8 1629 IFORM : SBB_MEMb_IMMb_80r3 1630 } 1631 { 1632 ICLASS : SBB 1633 CPL : 3 1634 CATEGORY : BINARY 1635 EXTENSION : BASE 1636 ISA_SET : I86 1637 ATTRIBUTES : BYTEOP 1638 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 1639 1640 PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8() 1641 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 1642 IFORM : SBB_GPR8_IMMb_80r3 1643 } 1644 1645 1646 1647 { 1648 ICLASS : AND_LOCK 1649 DISASM : and 1650 CPL : 3 1651 CATEGORY : LOGICAL 1652 EXTENSION : BASE 1653 ISA_SET : I86 1654 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1655 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1656 1657 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() lock_prefix 1658 OPERANDS : MEM0:rw:b IMM0:r:b 1659 IFORM : AND_LOCK_MEMb_IMMb_80r4 1660 } 1661 { 1662 ICLASS : AND 1663 CPL : 3 1664 CATEGORY : LOGICAL 1665 EXTENSION : BASE 1666 ISA_SET : I86 1667 ATTRIBUTES : BYTEOP LOCKABLE 1668 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1669 1670 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() nolock_prefix 1671 OPERANDS : MEM0:rw:b IMM0:r:b 1672 IFORM : AND_MEMb_IMMb_80r4 1673 } 1674 { 1675 ICLASS : AND 1676 CPL : 3 1677 CATEGORY : LOGICAL 1678 EXTENSION : BASE 1679 ISA_SET : I86 1680 ATTRIBUTES : BYTEOP 1681 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1682 1683 PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 1684 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 1685 IFORM : AND_GPR8_IMMb_80r4 1686 } 1687 1688 { 1689 ICLASS : SUB_LOCK 1690 DISASM : sub 1691 CPL : 3 1692 CATEGORY : BINARY 1693 EXTENSION : BASE 1694 ISA_SET : I86 1695 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1696 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1697 1698 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix 1699 OPERANDS : MEM0:rw:b IMM0:r:b:i8 1700 IFORM : SUB_LOCK_MEMb_IMMb_80r5 1701 } 1702 { 1703 ICLASS : SUB 1704 CPL : 3 1705 CATEGORY : BINARY 1706 EXTENSION : BASE 1707 ISA_SET : I86 1708 ATTRIBUTES : BYTEOP LOCKABLE 1709 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1710 1711 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix 1712 OPERANDS : MEM0:rw:b IMM0:r:b:i8 1713 IFORM : SUB_MEMb_IMMb_80r5 1714 } 1715 { 1716 ICLASS : SUB 1717 CPL : 3 1718 CATEGORY : BINARY 1719 EXTENSION : BASE 1720 ISA_SET : I86 1721 ATTRIBUTES : BYTEOP 1722 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1723 1724 PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8() 1725 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 1726 IFORM : SUB_GPR8_IMMb_80r5 1727 } 1728 1729 1730 1731 1732 1733 { 1734 ICLASS : XOR_LOCK 1735 DISASM : xor 1736 CPL : 3 1737 CATEGORY : LOGICAL 1738 EXTENSION : BASE 1739 ISA_SET : I86 1740 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1741 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1742 1743 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix 1744 OPERANDS : MEM0:rw:b IMM0:r:b 1745 IFORM : XOR_LOCK_MEMb_IMMb_80r6 1746 } 1747 { 1748 ICLASS : XOR 1749 CPL : 3 1750 CATEGORY : LOGICAL 1751 EXTENSION : BASE 1752 ISA_SET : I86 1753 ATTRIBUTES : BYTEOP LOCKABLE 1754 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1755 1756 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix 1757 OPERANDS : MEM0:rw:b IMM0:r:b 1758 IFORM : XOR_MEMb_IMMb_80r6 1759 } 1760 { 1761 ICLASS : XOR 1762 CPL : 3 1763 CATEGORY : LOGICAL 1764 EXTENSION : BASE 1765 ISA_SET : I86 1766 ATTRIBUTES : BYTEOP 1767 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1768 1769 PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 1770 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 1771 IFORM : XOR_GPR8_IMMb_80r6 1772 } 1773 1774 { 1775 ICLASS : CMP 1776 CPL : 3 1777 CATEGORY : BINARY 1778 EXTENSION : BASE 1779 ISA_SET : I86 1780 ATTRIBUTES : BYTEOP 1781 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1782 PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8() 1783 OPERANDS : MEM0:r:b IMM0:r:b:i8 1784 IFORM : CMP_MEMb_IMMb_80r7 1785 1786 PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8() 1787 OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 1788 IFORM : CMP_GPR8_IMMb_80r7 1789 } 1790 { 1791 ICLASS : ADD_LOCK 1792 DISASM : add 1793 CPL : 3 1794 CATEGORY : BINARY 1795 EXTENSION : BASE 1796 ISA_SET : I86 1797 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1798 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1799 1800 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() lock_prefix 1801 OPERANDS : MEM0:rw:v IMM0:r:z 1802 } 1803 { 1804 ICLASS : ADD 1805 CPL : 3 1806 CATEGORY : BINARY 1807 EXTENSION : BASE 1808 ISA_SET : I86 1809 ATTRIBUTES : LOCKABLE 1810 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1811 1812 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() nolock_prefix 1813 OPERANDS : MEM0:rw:v IMM0:r:z 1814 } 1815 { 1816 ICLASS : ADD 1817 CPL : 3 1818 CATEGORY : BINARY 1819 EXTENSION : BASE 1820 ISA_SET : I86 1821 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1822 1823 PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() 1824 OPERANDS : REG0=GPRv_B():rw IMM0:r:z 1825 } 1826 1827 1828 { 1829 ICLASS : OR_LOCK 1830 DISASM : or 1831 CPL : 3 1832 CATEGORY : LOGICAL 1833 EXTENSION : BASE 1834 ISA_SET : I86 1835 ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1836 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1837 1838 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() lock_prefix 1839 OPERANDS : MEM0:rw:v IMM0:r:z 1840 } 1841 1842 { 1843 ICLASS : OR 1844 CPL : 3 1845 CATEGORY : LOGICAL 1846 EXTENSION : BASE 1847 ISA_SET : I86 1848 ATTRIBUTES: LOCKABLE 1849 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1850 1851 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() nolock_prefix 1852 OPERANDS : MEM0:rw:v IMM0:r:z 1853 } 1854 { 1855 ICLASS : OR 1856 CPL : 3 1857 CATEGORY : LOGICAL 1858 EXTENSION : BASE 1859 ISA_SET : I86 1860 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1861 PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz() 1862 OPERANDS : REG0=GPRv_B():rw IMM0:r:z 1863 } 1864 1865 1866 1867 1868 { 1869 ICLASS : ADC_LOCK 1870 DISASM : adc 1871 CPL : 3 1872 CATEGORY : BINARY 1873 EXTENSION : BASE 1874 ISA_SET : I86 1875 ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1876 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 1877 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() lock_prefix 1878 OPERANDS : MEM0:rw:v IMM0:r:z 1879 } 1880 { 1881 ICLASS : ADC 1882 CPL : 3 1883 CATEGORY : BINARY 1884 EXTENSION : BASE 1885 ISA_SET : I86 1886 ATTRIBUTES: LOCKABLE 1887 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 1888 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() nolock_prefix 1889 OPERANDS : MEM0:rw:v IMM0:r:z 1890 } 1891 { 1892 ICLASS : ADC 1893 CPL : 3 1894 CATEGORY : BINARY 1895 EXTENSION : BASE 1896 ISA_SET : I86 1897 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 1898 PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMMz() 1899 OPERANDS : REG0=GPRv_B():rw IMM0:r:z 1900 } 1901 1902 1903 { 1904 ICLASS : SBB_LOCK 1905 DISASM : sbb 1906 CPL : 3 1907 CATEGORY : BINARY 1908 EXTENSION : BASE 1909 ISA_SET : I86 1910 ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1911 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 1912 1913 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() lock_prefix 1914 OPERANDS : MEM0:rw:v IMM0:r:z 1915 } 1916 { 1917 ICLASS : SBB 1918 CPL : 3 1919 CATEGORY : BINARY 1920 EXTENSION : BASE 1921 ISA_SET : I86 1922 ATTRIBUTES: LOCKABLE 1923 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 1924 1925 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() nolock_prefix 1926 OPERANDS : MEM0:rw:v IMM0:r:z 1927 } 1928 { 1929 ICLASS : SBB 1930 CPL : 3 1931 CATEGORY : BINARY 1932 EXTENSION : BASE 1933 ISA_SET : I86 1934 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 1935 PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMMz() 1936 OPERANDS : REG0=GPRv_B():rw IMM0:r:z 1937 } 1938 1939 1940 1941 1942 { 1943 ICLASS : AND_LOCK 1944 DISASM : and 1945 CPL : 3 1946 CATEGORY : LOGICAL 1947 EXTENSION : BASE 1948 ISA_SET : I86 1949 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1950 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1951 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() lock_prefix 1952 OPERANDS : MEM0:rw:v IMM0:r:z 1953 } 1954 { 1955 ICLASS : AND 1956 CPL : 3 1957 CATEGORY : LOGICAL 1958 EXTENSION : BASE 1959 ISA_SET : I86 1960 ATTRIBUTES : LOCKABLE 1961 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1962 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() nolock_prefix 1963 OPERANDS : MEM0:rw:v IMM0:r:z 1964 } 1965 { 1966 ICLASS : AND 1967 CPL : 3 1968 CATEGORY : LOGICAL 1969 EXTENSION : BASE 1970 ISA_SET : I86 1971 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 1972 PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMMz() 1973 OPERANDS : REG0=GPRv_B():rw IMM0:r:z 1974 } 1975 1976 { 1977 ICLASS : SUB_LOCK 1978 DISASM : sub 1979 CPL : 3 1980 CATEGORY : BINARY 1981 EXTENSION : BASE 1982 ISA_SET : I86 1983 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 1984 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1985 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() lock_prefix 1986 OPERANDS : MEM0:rw:v IMM0:r:z 1987 } 1988 { 1989 ICLASS : SUB 1990 CPL : 3 1991 CATEGORY : BINARY 1992 EXTENSION : BASE 1993 ISA_SET : I86 1994 ATTRIBUTES : LOCKABLE 1995 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 1996 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() nolock_prefix 1997 OPERANDS : MEM0:rw:v IMM0:r:z 1998 } 1999 { 2000 ICLASS : SUB 2001 CPL : 3 2002 CATEGORY : BINARY 2003 EXTENSION : BASE 2004 ISA_SET : I86 2005 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2006 PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMMz() 2007 OPERANDS : REG0=GPRv_B():rw IMM0:r:z 2008 } 2009 2010 2011 2012 { 2013 ICLASS : XOR_LOCK 2014 DISASM : xor 2015 CPL : 3 2016 CATEGORY : LOGICAL 2017 EXTENSION : BASE 2018 ISA_SET : I86 2019 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2020 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2021 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() lock_prefix 2022 OPERANDS : MEM0:rw:v IMM0:r:z 2023 } 2024 { 2025 ICLASS : XOR 2026 CPL : 3 2027 CATEGORY : LOGICAL 2028 EXTENSION : BASE 2029 ISA_SET : I86 2030 ATTRIBUTES : LOCKABLE 2031 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2032 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() nolock_prefix 2033 OPERANDS : MEM0:rw:v IMM0:r:z 2034 } 2035 { 2036 ICLASS : XOR 2037 CPL : 3 2038 CATEGORY : LOGICAL 2039 EXTENSION : BASE 2040 ISA_SET : I86 2041 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2042 PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMMz() 2043 OPERANDS : REG0=GPRv_B():rw IMM0:r:z 2044 } 2045 2046 2047 2048 { 2049 ICLASS : CMP 2050 CPL : 3 2051 CATEGORY : BINARY 2052 EXTENSION : BASE 2053 ISA_SET : I86 2054 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2055 PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMMz() 2056 OPERANDS : MEM0:r:v IMM0:r:z 2057 PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMMz() 2058 OPERANDS : REG0=GPRv_B():r IMM0:r:z 2059 } 2060 2061 { 2062 ICLASS : ADD_LOCK 2063 DISASM : add 2064 CPL : 3 2065 CATEGORY : BINARY 2066 EXTENSION : BASE 2067 ISA_SET : I86 2068 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2069 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2070 2071 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() lock_prefix 2072 OPERANDS : MEM0:rw:b IMM0:r:b:i8 2073 IFORM : ADD_LOCK_MEMb_IMMb_82r0 2074 } 2075 { 2076 ICLASS : ADD 2077 CPL : 3 2078 CATEGORY : BINARY 2079 EXTENSION : BASE 2080 ISA_SET : I86 2081 ATTRIBUTES : BYTEOP LOCKABLE 2082 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2083 2084 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() nolock_prefix 2085 OPERANDS : MEM0:rw:b IMM0:r:b:i8 2086 IFORM : ADD_MEMb_IMMb_82r0 2087 } 2088 { 2089 ICLASS : ADD 2090 CPL : 3 2091 CATEGORY : BINARY 2092 EXTENSION : BASE 2093 ISA_SET : I86 2094 ATTRIBUTES : BYTEOP 2095 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2096 PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8() 2097 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 2098 IFORM : ADD_GPR8_IMMb_82r0 2099 } 2100 2101 2102 { 2103 ICLASS : OR_LOCK 2104 DISASM : or 2105 CPL : 3 2106 CATEGORY : LOGICAL 2107 EXTENSION : BASE 2108 ISA_SET : I86 2109 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2110 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2111 2112 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() lock_prefix 2113 OPERANDS : MEM0:rw:b IMM0:r:b:i8 2114 IFORM : OR_LOCK_MEMb_IMMb_82r1 2115 } 2116 { 2117 ICLASS : OR 2118 CPL : 3 2119 CATEGORY : LOGICAL 2120 EXTENSION : BASE 2121 ISA_SET : I86 2122 ATTRIBUTES : BYTEOP LOCKABLE 2123 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2124 2125 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() nolock_prefix 2126 OPERANDS : MEM0:rw:b IMM0:r:b:i8 2127 IFORM : OR_MEMb_IMMb_82r1 2128 } 2129 { 2130 ICLASS : OR 2131 CPL : 3 2132 CATEGORY : LOGICAL 2133 EXTENSION : BASE 2134 ISA_SET : I86 2135 ATTRIBUTES : BYTEOP 2136 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2137 2138 PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8() 2139 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 2140 IFORM : OR_GPR8_IMMb_82r1 2141 } 2142 2143 2144 2145 { 2146 ICLASS : ADC_LOCK 2147 DISASM : adc 2148 CPL : 3 2149 CATEGORY : BINARY 2150 EXTENSION : BASE 2151 ISA_SET : I86 2152 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2153 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 2154 2155 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() lock_prefix 2156 OPERANDS : MEM0:rw:b IMM0:r:b:i8 2157 IFORM : ADC_LOCK_MEMb_IMMb_82r2 2158 } 2159 { 2160 ICLASS : ADC 2161 CPL : 3 2162 CATEGORY : BINARY 2163 EXTENSION : BASE 2164 ISA_SET : I86 2165 ATTRIBUTES : BYTEOP LOCKABLE 2166 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 2167 2168 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() nolock_prefix 2169 OPERANDS : MEM0:rw:b IMM0:r:b:i8 2170 IFORM : ADC_MEMb_IMMb_82r2 2171 } 2172 { 2173 ICLASS : ADC 2174 CPL : 3 2175 CATEGORY : BINARY 2176 EXTENSION : BASE 2177 ISA_SET : I86 2178 ATTRIBUTES : BYTEOP 2179 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 2180 PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8() 2181 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 2182 IFORM : ADC_GPR8_IMMb_82r2 2183 } 2184 2185 2186 2187 { 2188 ICLASS : SBB_LOCK 2189 DISASM : sbb 2190 CPL : 3 2191 CATEGORY : BINARY 2192 EXTENSION : BASE 2193 ISA_SET : I86 2194 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2195 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 2196 2197 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() lock_prefix 2198 OPERANDS : MEM0:rw:b IMM0:r:b:i8 2199 IFORM : SBB_LOCK_MEMb_IMMb_82r3 2200 } 2201 { 2202 ICLASS : SBB 2203 CPL : 3 2204 CATEGORY : BINARY 2205 EXTENSION : BASE 2206 ISA_SET : I86 2207 ATTRIBUTES : BYTEOP LOCKABLE 2208 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 2209 2210 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() nolock_prefix 2211 OPERANDS : MEM0:rw:b IMM0:r:b:i8 2212 IFORM : SBB_MEMb_IMMb_82r3 2213 } 2214 { 2215 ICLASS : SBB 2216 CPL : 3 2217 CATEGORY : BINARY 2218 EXTENSION : BASE 2219 ISA_SET : I86 2220 ATTRIBUTES : BYTEOP 2221 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 2222 2223 PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8() 2224 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 2225 IFORM : SBB_GPR8_IMMb_82r3 2226 } 2227 2228 2229 { 2230 ICLASS : AND_LOCK 2231 DISASM : and 2232 CPL : 3 2233 CATEGORY : LOGICAL 2234 EXTENSION : BASE 2235 ISA_SET : I86 2236 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2237 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2238 2239 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() lock_prefix 2240 OPERANDS : MEM0:rw:b IMM0:r:b 2241 IFORM : AND_LOCK_MEMb_IMMb_82r4 2242 } 2243 { 2244 ICLASS : AND 2245 CPL : 3 2246 CATEGORY : LOGICAL 2247 EXTENSION : BASE 2248 ISA_SET : I86 2249 ATTRIBUTES : BYTEOP LOCKABLE 2250 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2251 2252 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() nolock_prefix 2253 OPERANDS : MEM0:rw:b IMM0:r:b 2254 IFORM : AND_MEMb_IMMb_82r4 2255 } 2256 { 2257 ICLASS : AND 2258 CPL : 3 2259 CATEGORY : LOGICAL 2260 EXTENSION : BASE 2261 ISA_SET : I86 2262 ATTRIBUTES : BYTEOP 2263 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2264 2265 PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8() 2266 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 2267 IFORM : AND_GPR8_IMMb_82r4 2268 } 2269 2270 2271 2272 { 2273 ICLASS : SUB_LOCK 2274 DISASM : sub 2275 CPL : 3 2276 CATEGORY : BINARY 2277 EXTENSION : BASE 2278 ISA_SET : I86 2279 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2280 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2281 2282 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() lock_prefix 2283 OPERANDS : MEM0:rw:b IMM0:r:b:i8 2284 IFORM : SUB_LOCK_MEMb_IMMb_82r5 2285 } 2286 { 2287 ICLASS : SUB 2288 CPL : 3 2289 CATEGORY : BINARY 2290 EXTENSION : BASE 2291 ISA_SET : I86 2292 ATTRIBUTES : BYTEOP LOCKABLE 2293 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2294 2295 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() nolock_prefix 2296 OPERANDS : MEM0:rw:b IMM0:r:b:i8 2297 IFORM : SUB_MEMb_IMMb_82r5 2298 } 2299 { 2300 ICLASS : SUB 2301 CPL : 3 2302 CATEGORY : BINARY 2303 EXTENSION : BASE 2304 ISA_SET : I86 2305 ATTRIBUTES : BYTEOP 2306 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2307 2308 PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8() 2309 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 2310 IFORM : SUB_GPR8_IMMb_82r5 2311 } 2312 2313 2314 { 2315 ICLASS : XOR_LOCK 2316 DISASM : xor 2317 CPL : 3 2318 CATEGORY : LOGICAL 2319 EXTENSION : BASE 2320 ISA_SET : I86 2321 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2322 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2323 2324 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() lock_prefix 2325 OPERANDS : MEM0:rw:b IMM0:r:b 2326 IFORM : XOR_LOCK_MEMb_IMMb_82r6 2327 } 2328 { 2329 ICLASS : XOR 2330 CPL : 3 2331 CATEGORY : LOGICAL 2332 EXTENSION : BASE 2333 ISA_SET : I86 2334 ATTRIBUTES : BYTEOP LOCKABLE 2335 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2336 2337 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() nolock_prefix 2338 OPERANDS : MEM0:rw:b IMM0:r:b 2339 IFORM : XOR_MEMb_IMMb_82r6 2340 } 2341 { 2342 ICLASS : XOR 2343 CPL : 3 2344 CATEGORY : LOGICAL 2345 EXTENSION : BASE 2346 ISA_SET : I86 2347 ATTRIBUTES : BYTEOP 2348 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2349 2350 PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8() 2351 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 2352 IFORM : XOR_GPR8_IMMb_82r6 2353 } 2354 2355 { 2356 ICLASS : CMP 2357 CPL : 3 2358 CATEGORY : BINARY 2359 EXTENSION : BASE 2360 ISA_SET : I86 2361 ATTRIBUTES : BYTEOP 2362 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2363 PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8() 2364 OPERANDS : MEM0:r:b IMM0:r:b:i8 2365 IFORM : CMP_MEMb_IMMb_82r7 2366 2367 PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8() 2368 OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 2369 IFORM : CMP_GPR8_IMMb_82r7 2370 } 2371 2372 { 2373 ICLASS : ADD_LOCK 2374 DISASM : add 2375 CPL : 3 2376 CATEGORY : BINARY 2377 EXTENSION : BASE 2378 ISA_SET : I86 2379 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2380 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2381 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix 2382 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2383 } 2384 { 2385 ICLASS : ADD 2386 CPL : 3 2387 CATEGORY : BINARY 2388 EXTENSION : BASE 2389 ISA_SET : I86 2390 ATTRIBUTES : LOCKABLE 2391 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2392 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix 2393 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2394 } 2395 { 2396 ICLASS : ADD 2397 CPL : 3 2398 CATEGORY : BINARY 2399 EXTENSION : BASE 2400 ISA_SET : I86 2401 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2402 PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() 2403 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 2404 } 2405 { 2406 ICLASS : OR_LOCK 2407 DISASM : or 2408 CPL : 3 2409 CATEGORY : LOGICAL 2410 EXTENSION : BASE 2411 ISA_SET : I86 2412 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2413 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2414 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix 2415 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2416 } 2417 { 2418 ICLASS : OR 2419 CPL : 3 2420 CATEGORY : LOGICAL 2421 EXTENSION : BASE 2422 ISA_SET : I86 2423 ATTRIBUTES : LOCKABLE 2424 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2425 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix 2426 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2427 } 2428 { 2429 ICLASS : OR 2430 CPL : 3 2431 CATEGORY : LOGICAL 2432 EXTENSION : BASE 2433 ISA_SET : I86 2434 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2435 PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() 2436 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 2437 } 2438 { 2439 ICLASS : ADC_LOCK 2440 DISASM : adc 2441 CPL : 3 2442 CATEGORY : BINARY 2443 EXTENSION : BASE 2444 ISA_SET : I86 2445 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2446 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 2447 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix 2448 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2449 } 2450 { 2451 ICLASS : ADC 2452 CPL : 3 2453 CATEGORY : BINARY 2454 EXTENSION : BASE 2455 ISA_SET : I86 2456 ATTRIBUTES : LOCKABLE 2457 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 2458 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix 2459 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2460 } 2461 { 2462 ICLASS : ADC 2463 CPL : 3 2464 CATEGORY : BINARY 2465 EXTENSION : BASE 2466 ISA_SET : I86 2467 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 2468 PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8() 2469 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 2470 } 2471 { 2472 ICLASS : SBB_LOCK 2473 DISASM : sbb 2474 CPL : 3 2475 CATEGORY : BINARY 2476 EXTENSION : BASE 2477 ISA_SET : I86 2478 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2479 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 2480 2481 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix 2482 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2483 } 2484 { 2485 ICLASS : SBB 2486 CPL : 3 2487 CATEGORY : BINARY 2488 EXTENSION : BASE 2489 ISA_SET : I86 2490 ATTRIBUTES : LOCKABLE 2491 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 2492 2493 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix 2494 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2495 } 2496 { 2497 ICLASS : SBB 2498 CPL : 3 2499 CATEGORY : BINARY 2500 EXTENSION : BASE 2501 ISA_SET : I86 2502 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 2503 PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8() 2504 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 2505 } 2506 { 2507 ICLASS : AND_LOCK 2508 DISASM : and 2509 CPL : 3 2510 CATEGORY : LOGICAL 2511 EXTENSION : BASE 2512 ISA_SET : I86 2513 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2514 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2515 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() lock_prefix 2516 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2517 } 2518 { 2519 ICLASS : AND 2520 CPL : 3 2521 CATEGORY : LOGICAL 2522 EXTENSION : BASE 2523 ISA_SET : I86 2524 ATTRIBUTES : LOCKABLE 2525 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2526 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() nolock_prefix 2527 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2528 } 2529 { 2530 ICLASS : AND 2531 CPL : 3 2532 CATEGORY : LOGICAL 2533 EXTENSION : BASE 2534 ISA_SET : I86 2535 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2536 PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMM8() 2537 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 2538 } 2539 { 2540 ICLASS : SUB_LOCK 2541 DISASM : sub 2542 CPL : 3 2543 CATEGORY : BINARY 2544 EXTENSION : BASE 2545 ISA_SET : I86 2546 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2547 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2548 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix 2549 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2550 } 2551 { 2552 ICLASS : SUB 2553 CPL : 3 2554 CATEGORY : BINARY 2555 EXTENSION : BASE 2556 ISA_SET : I86 2557 ATTRIBUTES : LOCKABLE 2558 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2559 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix 2560 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2561 } 2562 { 2563 ICLASS : SUB 2564 CPL : 3 2565 CATEGORY : BINARY 2566 EXTENSION : BASE 2567 ISA_SET : I86 2568 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2569 PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8() 2570 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 2571 } 2572 { 2573 ICLASS : XOR_LOCK 2574 DISASM : xor 2575 CPL : 3 2576 CATEGORY : LOGICAL 2577 EXTENSION : BASE 2578 ISA_SET : I86 2579 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 2580 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2581 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() lock_prefix 2582 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2583 } 2584 { 2585 ICLASS : XOR 2586 CPL : 3 2587 CATEGORY : LOGICAL 2588 EXTENSION : BASE 2589 ISA_SET : I86 2590 ATTRIBUTES : LOCKABLE 2591 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2592 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() nolock_prefix 2593 OPERANDS : MEM0:rw:v IMM0:r:b:i8 2594 } 2595 { 2596 ICLASS : XOR 2597 CPL : 3 2598 CATEGORY : LOGICAL 2599 EXTENSION : BASE 2600 ISA_SET : I86 2601 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 2602 PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMM8() 2603 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 2604 } 2605 { 2606 ICLASS : CMP 2607 CPL : 3 2608 CATEGORY : BINARY 2609 EXTENSION : BASE 2610 ISA_SET : I86 2611 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 2612 PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8() 2613 OPERANDS : MEM0:r:v IMM0:r:b:i8 2614 2615 PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8() 2616 OPERANDS : REG0=GPRv_B():r IMM0:r:b:i8 2617 } 2618 { 2619 ICLASS : POP 2620 CPL : 3 2621 CATEGORY : POP 2622 EXTENSION : BASE 2623 ISA_SET : I86 2624 PATTERN : 0x8F MOD[mm] MOD!=3 REG[0b000] RM[nnn] DF64() MODRM() 2625 OPERANDS : MEM0:w:v REG0=XED_REG_STACKPOP:r:spw:SUPP 2626 2627 PATTERN : 0x8F MOD[0b11] MOD=3 REG[0b000] RM[nnn] DF64() 2628 OPERANDS : REG0=GPRv_B():w REG1=XED_REG_STACKPOP:r:spw:SUPP 2629 IFORM : POP_GPRv_8F 2630 } 2631 2632 2633 { 2634 ICLASS : ROL 2635 CPL : 3 2636 CATEGORY : ROTATE 2637 EXTENSION : BASE 2638 ISA_SET : I186 2639 ATTRIBUTES : BYTEOP 2640 FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] 2641 PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() 2642 OPERANDS : MEM0:rw:b IMM0:r:b 2643 PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() 2644 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 2645 } 2646 { 2647 ICLASS : ROL 2648 CPL : 3 2649 CATEGORY : ROTATE 2650 EXTENSION : BASE 2651 ISA_SET : I186 2652 FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] 2653 PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() 2654 OPERANDS : MEM0:rw:v IMM0:r:b 2655 2656 PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() 2657 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 2658 } 2659 2660 { 2661 ICLASS : ROR 2662 CPL : 3 2663 CATEGORY : ROTATE 2664 EXTENSION : BASE 2665 ISA_SET : I186 2666 ATTRIBUTES : BYTEOP 2667 FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] 2668 PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8() 2669 OPERANDS : MEM0:rw:b IMM0:r:b 2670 PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8() 2671 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 2672 } 2673 2674 { 2675 ICLASS : ROR 2676 CPL : 3 2677 CATEGORY : ROTATE 2678 EXTENSION : BASE 2679 ISA_SET : I186 2680 FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] 2681 PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8() 2682 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 2683 # 2009-02-09: THIS WAS MISSING ENTIRELY UNTIL NOW 2684 PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8() 2685 OPERANDS : MEM0:rw:v IMM0:r:b 2686 } 2687 2688 { 2689 ICLASS : ROR 2690 CPL : 3 2691 CATEGORY : ROTATE 2692 EXTENSION : BASE 2693 ISA_SET : I86 2694 ATTRIBUTES : BYTEOP IMPLICIT_ONE 2695 FLAGS : MUST [ of-mod cf-mod ] 2696 PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE() 2697 OPERANDS : MEM0:rw:b IMM0:r:b:IMPL 2698 IFORM : ROR_MEMb_ONE 2699 2700 PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE() 2701 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL 2702 IFORM : ROR_GPR8_ONE 2703 } 2704 2705 { 2706 ICLASS : ROR 2707 CPL : 3 2708 CATEGORY : ROTATE 2709 EXTENSION : BASE 2710 ISA_SET : I86 2711 ATTRIBUTES : IMPLICIT_ONE 2712 FLAGS : MUST [ of-mod cf-mod ] 2713 PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE() 2714 OPERANDS : MEM0:rw:v IMM0:r:b:IMPL 2715 IFORM : ROR_MEMv_ONE 2716 2717 PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE() 2718 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL 2719 IFORM : ROR_GPRv_ONE 2720 } 2721 2722 2723 { 2724 ICLASS : ROR 2725 CPL : 3 2726 CATEGORY : ROTATE 2727 EXTENSION : BASE 2728 ISA_SET : I86 2729 ATTRIBUTES : BYTEOP 2730 FLAGS : MAY [ of-u cf-mod ] 2731 PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 2732 OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL 2733 PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 2734 OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL 2735 } 2736 2737 { 2738 ICLASS : ROR 2739 CPL : 3 2740 CATEGORY : ROTATE 2741 EXTENSION : BASE 2742 ISA_SET : I86 2743 FLAGS : MAY [ of-u cf-mod ] 2744 PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 2745 OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL 2746 2747 PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 2748 OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL 2749 } 2750 2751 2752 2753 2754 2755 { 2756 ICLASS : ROL 2757 CPL : 3 2758 CATEGORY : ROTATE 2759 EXTENSION : BASE 2760 ISA_SET : I86 2761 ATTRIBUTES : BYTEOP IMPLICIT_ONE 2762 FLAGS : MUST [ of-mod cf-mod ] 2763 PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE() 2764 OPERANDS : MEM0:rw:b IMM0:r:b:IMPL 2765 IFORM : ROL_MEMb_ONE 2766 PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE() 2767 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL 2768 IFORM : ROL_GPR8_ONE 2769 } 2770 2771 { 2772 ICLASS : ROL 2773 CPL : 3 2774 CATEGORY : ROTATE 2775 EXTENSION : BASE 2776 ISA_SET : I86 2777 ATTRIBUTES : IMPLICIT_ONE 2778 FLAGS : MUST [ of-mod cf-mod ] 2779 PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE() 2780 OPERANDS : MEM0:rw:v IMM0:r:b:IMPL 2781 IFORM : ROL_MEMv_ONE 2782 2783 PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE() 2784 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL 2785 IFORM : ROL_GPRv_ONE 2786 } 2787 { 2788 ICLASS : ROL 2789 CPL : 3 2790 CATEGORY : ROTATE 2791 EXTENSION : BASE 2792 ISA_SET : I86 2793 ATTRIBUTES : BYTEOP 2794 FLAGS : MAY [ of-u cf-mod ] # REMOVED cf-tst 2009-02-08 2795 PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 2796 OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL 2797 PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b000] RM[nnn] 2798 OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL 2799 } 2800 { 2801 ICLASS : ROL 2802 CPL : 3 2803 CATEGORY : ROTATE 2804 EXTENSION : BASE 2805 ISA_SET : I86 2806 FLAGS : MAY [ of-u cf-mod ] 2807 PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 2808 OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL 2809 2810 PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b000] RM[nnn] 2811 OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL 2812 } 2813 2814 ################# 2815 2816 2817 2818 2819 { 2820 ICLASS : RCL 2821 CPL : 3 2822 CATEGORY : ROTATE 2823 EXTENSION : BASE 2824 ISA_SET : I186 2825 ATTRIBUTES : BYTEOP 2826 FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] 2827 PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() 2828 OPERANDS : MEM0:rw:b IMM0:r:b 2829 PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 2830 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 2831 } 2832 { 2833 ICLASS : RCR 2834 CPL : 3 2835 CATEGORY : ROTATE 2836 EXTENSION : BASE 2837 ISA_SET : I186 2838 ATTRIBUTES : BYTEOP 2839 FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] 2840 PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8() 2841 OPERANDS : MEM0:rw:b IMM0:r:b 2842 PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() 2843 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 2844 } 2845 { 2846 ICLASS : SHL 2847 CPL : 3 2848 CATEGORY : SHIFT 2849 EXTENSION : BASE 2850 ISA_SET : I186 2851 ATTRIBUTES : BYTEOP 2852 FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 2853 PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() 2854 OPERANDS : MEM0:rw:b IMM0:r:b 2855 IFORM : SHL_MEMb_IMMb_C0r4 2856 2857 PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 2858 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 2859 IFORM : SHL_GPR8_IMMb_C0r4 2860 } 2861 { 2862 ICLASS : SHR 2863 CPL : 3 2864 CATEGORY : SHIFT 2865 EXTENSION : BASE 2866 ISA_SET : I186 2867 ATTRIBUTES : BYTEOP 2868 FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 2869 PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() 2870 OPERANDS : MEM0:rw:b IMM0:r:b 2871 PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() 2872 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 2873 } 2874 { 2875 ICLASS : SHL 2876 CPL : 3 2877 CATEGORY : SHIFT 2878 EXTENSION : BASE 2879 ISA_SET : I186 2880 ATTRIBUTES : BYTEOP 2881 FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 2882 PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() 2883 OPERANDS : MEM0:rw:b IMM0:r:b 2884 IFORM : SHL_MEMb_IMMb_C0r6 2885 2886 PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 2887 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 2888 IFORM : SHL_GPR8_IMMb_C0r6 2889 } 2890 { 2891 ICLASS : SAR 2892 CPL : 3 2893 CATEGORY : SHIFT 2894 EXTENSION : BASE 2895 ISA_SET : I186 2896 ATTRIBUTES : BYTEOP 2897 FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 2898 PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() 2899 OPERANDS : MEM0:rw:b IMM0:r:b 2900 PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() 2901 OPERANDS : REG0=GPR8_B():rw IMM0:r:b 2902 } 2903 2904 { 2905 ICLASS : RCL 2906 CPL : 3 2907 CATEGORY : ROTATE 2908 EXTENSION : BASE 2909 ISA_SET : I186 2910 FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] 2911 PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() 2912 OPERANDS : MEM0:rw:v IMM0:r:b 2913 2914 PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 2915 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 2916 } 2917 { 2918 ICLASS : RCR 2919 CPL : 3 2920 CATEGORY : ROTATE 2921 EXTENSION : BASE 2922 ISA_SET : I186 2923 FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] 2924 PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8() 2925 OPERANDS : MEM0:rw:v IMM0:r:b 2926 2927 PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() 2928 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 2929 } 2930 { 2931 ICLASS : SHL 2932 CPL : 3 2933 CATEGORY : SHIFT 2934 EXTENSION : BASE 2935 ISA_SET : I186 2936 FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 2937 PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() 2938 OPERANDS : MEM0:rw:v IMM0:r:b 2939 IFORM : SHL_MEMv_IMMb_C1r4 2940 2941 PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 2942 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 2943 IFORM : SHL_GPRv_IMMb_C1r4 2944 } 2945 { 2946 ICLASS : SHR 2947 CPL : 3 2948 CATEGORY : SHIFT 2949 EXTENSION : BASE 2950 ISA_SET : I186 2951 FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 2952 PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() 2953 OPERANDS : MEM0:rw:v IMM0:r:b 2954 PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() 2955 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 2956 } 2957 { 2958 ICLASS : SHL 2959 CPL : 3 2960 CATEGORY : SHIFT 2961 EXTENSION : BASE 2962 ISA_SET : I186 2963 FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 2964 PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() 2965 OPERANDS : MEM0:rw:v IMM0:r:b 2966 IFORM : SHL_MEMv_IMMb_C1r6 2967 2968 PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 2969 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 2970 IFORM : SHL_GPRv_IMMb_C1r6 2971 } 2972 { 2973 ICLASS : SAR 2974 CPL : 3 2975 CATEGORY : SHIFT 2976 EXTENSION : BASE 2977 ISA_SET : I186 2978 FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 2979 PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() 2980 OPERANDS : MEM0:rw:v IMM0:r:b 2981 PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() 2982 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 2983 } 2984 { 2985 ICLASS : RCL 2986 CPL : 3 2987 CATEGORY : ROTATE 2988 EXTENSION : BASE 2989 ISA_SET : I86 2990 ATTRIBUTES : BYTEOP IMPLICIT_ONE 2991 FLAGS : MUST [ of-mod cf-tst cf-mod ] 2992 PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE() 2993 OPERANDS : MEM0:rw:b IMM0:r:b:IMPL 2994 IFORM : RCL_MEMb_ONE 2995 2996 PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE() 2997 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL 2998 IFORM : RCL_GPR8_ONE 2999 } 3000 { 3001 ICLASS : RCR 3002 CPL : 3 3003 CATEGORY : ROTATE 3004 EXTENSION : BASE 3005 ISA_SET : I86 3006 ATTRIBUTES : BYTEOP IMPLICIT_ONE 3007 FLAGS : MUST [ of-mod cf-tst cf-mod ] 3008 PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE() 3009 OPERANDS : MEM0:rw:b IMM0:r:b:IMPL 3010 IFORM : RCR_MEMb_ONE 3011 3012 PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE() 3013 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL 3014 IFORM : RCR_GPR8_ONE 3015 } 3016 { 3017 ICLASS : SHL 3018 CPL : 3 3019 CATEGORY : SHIFT 3020 EXTENSION : BASE 3021 ISA_SET : I86 3022 ATTRIBUTES : BYTEOP IMPLICIT_ONE 3023 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] 3024 PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() 3025 OPERANDS : MEM0:rw:b IMM0:r:b:IMPL 3026 IFORM : SHL_MEMb_ONE_D0r4 3027 3028 PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() 3029 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL 3030 IFORM : SHL_GPR8_ONE_D0r4 3031 3032 PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() 3033 OPERANDS : MEM0:rw:b IMM0:r:b:IMPL 3034 IFORM : SHL_MEMb_ONE_D0r6 3035 3036 PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE() 3037 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL 3038 IFORM : SHL_GPR8_ONE_D0r6 3039 } 3040 { 3041 ICLASS : SHR 3042 CPL : 3 3043 CATEGORY : SHIFT 3044 EXTENSION : BASE 3045 ISA_SET : I86 3046 ATTRIBUTES : BYTEOP IMPLICIT_ONE 3047 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] 3048 PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE() 3049 OPERANDS : MEM0:rw:b IMM0:r:b:IMPL 3050 IFORM : SHR_MEMb_ONE 3051 3052 PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE() 3053 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL 3054 IFORM : SHR_GPR8_ONE 3055 } 3056 3057 { 3058 ICLASS : SAR 3059 CPL : 3 3060 CATEGORY : SHIFT 3061 EXTENSION : BASE 3062 ISA_SET : I86 3063 ATTRIBUTES : BYTEOP IMPLICIT_ONE 3064 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] 3065 PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE() 3066 OPERANDS : MEM0:rw:b IMM0:r:b:IMPL 3067 IFORM : SAR_MEMb_ONE 3068 PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE() 3069 OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL 3070 IFORM : SAR_GPR8_ONE 3071 } 3072 { 3073 ICLASS : RCL 3074 CPL : 3 3075 CATEGORY : ROTATE 3076 EXTENSION : BASE 3077 ISA_SET : I86 3078 ATTRIBUTES : IMPLICIT_ONE 3079 FLAGS : MUST [ of-mod cf-tst cf-mod ] 3080 PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE() 3081 OPERANDS : MEM0:rw:v IMM0:r:b:IMPL 3082 IFORM : RCL_MEMv_ONE 3083 3084 PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE() 3085 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL 3086 IFORM : RCL_GPRv_ONE 3087 } 3088 { 3089 ICLASS : RCR 3090 CPL : 3 3091 CATEGORY : ROTATE 3092 EXTENSION : BASE 3093 ISA_SET : I86 3094 ATTRIBUTES : IMPLICIT_ONE 3095 FLAGS : MUST [ of-mod cf-tst cf-mod ] 3096 PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE() 3097 OPERANDS : MEM0:rw:v IMM0:r:b:IMPL 3098 IFORM : RCR_MEMv_ONE 3099 3100 PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE() 3101 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL 3102 IFORM : RCR_GPRv_ONE 3103 } 3104 3105 { 3106 ICLASS : SHR 3107 CPL : 3 3108 CATEGORY : SHIFT 3109 EXTENSION : BASE 3110 ISA_SET : I86 3111 ATTRIBUTES : IMPLICIT_ONE 3112 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] 3113 PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE() 3114 OPERANDS : MEM0:rw:v IMM0:r:b:IMPL 3115 IFORM : SHR_MEMv_ONE 3116 3117 PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE() 3118 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL 3119 IFORM : SHR_GPRv_ONE 3120 } 3121 { 3122 ICLASS : SHL 3123 CPL : 3 3124 CATEGORY : SHIFT 3125 EXTENSION : BASE 3126 ISA_SET : I86 3127 ATTRIBUTES : IMPLICIT_ONE 3128 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] 3129 PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() 3130 OPERANDS : MEM0:rw:v IMM0:r:b:IMPL 3131 IFORM : SHL_MEMv_ONE_D1r6 3132 3133 PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE() 3134 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL 3135 IFORM : SHL_GPRv_ONE_D1r6 3136 3137 PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() 3138 OPERANDS : MEM0:rw:v IMM0:r:b:IMPL 3139 IFORM : SHL_MEMv_ONE_D1r4 3140 3141 PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() 3142 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL 3143 IFORM : SHL_GPRv_ONE_D1r4 3144 } 3145 3146 3147 { 3148 ICLASS : SAR 3149 CPL : 3 3150 CATEGORY : SHIFT 3151 EXTENSION : BASE 3152 ISA_SET : I86 3153 ATTRIBUTES : IMPLICIT_ONE 3154 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] 3155 PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE() 3156 OPERANDS : MEM0:rw:v IMM0:r:b:IMPL 3157 IFORM : SAR_MEMv_ONE 3158 3159 PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE() 3160 OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL 3161 IFORM : SAR_GPRv_ONE 3162 } 3163 { 3164 ICLASS : RCL 3165 CPL : 3 3166 CATEGORY : ROTATE 3167 EXTENSION : BASE 3168 ISA_SET : I86 3169 ATTRIBUTES : BYTEOP 3170 FLAGS : MAY [ of-u cf-tst cf-mod ] 3171 PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 3172 OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL 3173 PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 3174 OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL 3175 } 3176 { 3177 ICLASS : RCR 3178 CPL : 3 3179 CATEGORY : ROTATE 3180 EXTENSION : BASE 3181 ISA_SET : I86 3182 ATTRIBUTES : BYTEOP 3183 FLAGS : MAY [ of-u cf-tst cf-mod ] 3184 PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 3185 OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL 3186 PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 3187 OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL 3188 } 3189 { 3190 ICLASS : SHL 3191 CPL : 3 3192 CATEGORY : SHIFT 3193 EXTENSION : BASE 3194 ISA_SET : I86 3195 ATTRIBUTES : BYTEOP 3196 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3197 PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 3198 OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL 3199 IFORM : SHL_MEMb_CL_D2r4 3200 3201 PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b100] RM[nnn] 3202 OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL 3203 IFORM : SHL_GPR8_CL_D2r4 3204 } 3205 { 3206 ICLASS : SHR 3207 CPL : 3 3208 CATEGORY : SHIFT 3209 EXTENSION : BASE 3210 ISA_SET : I86 3211 ATTRIBUTES : BYTEOP 3212 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3213 PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 3214 OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL 3215 PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b101] RM[nnn] 3216 OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL 3217 } 3218 { 3219 ICLASS : SHL 3220 CPL : 3 3221 CATEGORY : SHIFT 3222 EXTENSION : BASE 3223 ISA_SET : I86 3224 ATTRIBUTES : BYTEOP 3225 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3226 PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 3227 OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL 3228 IFORM : SHL_MEMb_CL_D2r6 3229 3230 PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b110] RM[nnn] 3231 OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL 3232 IFORM : SHL_GPR8_CL_D2r6 3233 } 3234 { 3235 ICLASS : SAR 3236 CPL : 3 3237 CATEGORY : SHIFT 3238 EXTENSION : BASE 3239 ISA_SET : I86 3240 ATTRIBUTES : BYTEOP 3241 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3242 PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 3243 OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL 3244 PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b111] RM[nnn] 3245 OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL 3246 } 3247 3248 { 3249 ICLASS : RCL 3250 CPL : 3 3251 CATEGORY : ROTATE 3252 EXTENSION : BASE 3253 ISA_SET : I86 3254 FLAGS : MAY [ of-u cf-tst cf-mod ] 3255 PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 3256 OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL 3257 } 3258 { 3259 ICLASS : RCL 3260 CPL : 3 3261 CATEGORY : ROTATE 3262 EXTENSION : BASE 3263 ISA_SET : I86 3264 FLAGS : MAY [ of-u cf-tst cf-mod ] 3265 PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 3266 OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL 3267 } 3268 { 3269 ICLASS : RCR 3270 CPL : 3 3271 CATEGORY : ROTATE 3272 EXTENSION : BASE 3273 ISA_SET : I86 3274 FLAGS : MAY [ of-u cf-tst cf-mod ] 3275 PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 3276 OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL 3277 } 3278 { 3279 ICLASS : RCR 3280 CPL : 3 3281 CATEGORY : ROTATE 3282 EXTENSION : BASE 3283 ISA_SET : I86 3284 FLAGS : MAY [ of-u cf-tst cf-mod ] 3285 PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 3286 OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL 3287 } 3288 { 3289 ICLASS : SHL 3290 CPL : 3 3291 CATEGORY : SHIFT 3292 EXTENSION : BASE 3293 ISA_SET : I86 3294 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3295 PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 3296 OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL 3297 IFORM : SHL_MEMv_CL_D3r4 3298 } 3299 { 3300 ICLASS : SHL 3301 CPL : 3 3302 CATEGORY : SHIFT 3303 EXTENSION : BASE 3304 ISA_SET : I86 3305 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3306 PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b100] RM[nnn] 3307 OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL 3308 IFORM : SHL_GPRv_CL_D3r4 3309 } 3310 { 3311 ICLASS : SHR 3312 CPL : 3 3313 CATEGORY : SHIFT 3314 EXTENSION : BASE 3315 ISA_SET : I86 3316 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3317 PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 3318 OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL 3319 } 3320 { 3321 ICLASS : SHR 3322 CPL : 3 3323 CATEGORY : SHIFT 3324 EXTENSION : BASE 3325 ISA_SET : I86 3326 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3327 PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b101] RM[nnn] 3328 OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL 3329 } 3330 { 3331 ICLASS : SHL 3332 CPL : 3 3333 CATEGORY : SHIFT 3334 EXTENSION : BASE 3335 ISA_SET : I86 3336 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3337 PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 3338 OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL 3339 IFORM : SHL_MEMv_CL_D3r6 3340 } 3341 { 3342 ICLASS : SHL 3343 CPL : 3 3344 CATEGORY : SHIFT 3345 EXTENSION : BASE 3346 ISA_SET : I86 3347 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3348 PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b110] RM[nnn] 3349 OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL 3350 IFORM : SHL_GPRv_CL_D3r6 3351 } 3352 { 3353 ICLASS : SAR 3354 CPL : 3 3355 CATEGORY : SHIFT 3356 EXTENSION : BASE 3357 ISA_SET : I86 3358 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3359 PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 3360 OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL 3361 } 3362 { 3363 ICLASS : SAR 3364 CPL : 3 3365 CATEGORY : SHIFT 3366 EXTENSION : BASE 3367 ISA_SET : I86 3368 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 3369 PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b111] RM[nnn] 3370 OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL 3371 } 3372 { 3373 ICLASS : TEST 3374 CPL : 3 3375 CATEGORY : LOGICAL 3376 EXTENSION : BASE 3377 ISA_SET : I86 3378 ATTRIBUTES : BYTEOP 3379 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 3380 PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() 3381 OPERANDS : MEM0:r:b IMM0:r:b:i8 3382 IFORM : TEST_MEMb_IMMb_F6r0 3383 3384 PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() 3385 OPERANDS : MEM0:r:b IMM0:r:b:i8 3386 IFORM : TEST_MEMb_IMMb_F6r1 3387 3388 PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() 3389 OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 3390 IFORM : TEST_GPR8_IMMb_F6r0 3391 3392 PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() 3393 OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 3394 IFORM : TEST_GPR8_IMMb_F6r1 3395 } 3396 3397 { 3398 ICLASS : NOT_LOCK 3399 DISASM : not 3400 CPL : 3 3401 CATEGORY : LOGICAL 3402 EXTENSION : BASE 3403 ISA_SET : I86 3404 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 3405 PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix 3406 OPERANDS : MEM0:rw:b 3407 } 3408 { 3409 ICLASS : NOT 3410 CPL : 3 3411 CATEGORY : LOGICAL 3412 EXTENSION : BASE 3413 ISA_SET : I86 3414 ATTRIBUTES : BYTEOP LOCKABLE 3415 PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix 3416 OPERANDS : MEM0:rw:b 3417 } 3418 { 3419 ICLASS : NOT 3420 CPL : 3 3421 CATEGORY : LOGICAL 3422 EXTENSION : BASE 3423 ISA_SET : I86 3424 ATTRIBUTES : BYTEOP 3425 PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 3426 OPERANDS : REG0=GPR8_B():rw 3427 } 3428 { 3429 ICLASS : NEG_LOCK 3430 DISASM : neg 3431 CPL : 3 3432 CATEGORY : BINARY 3433 EXTENSION : BASE 3434 ISA_SET : I86 3435 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 3436 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 3437 PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix 3438 OPERANDS : MEM0:rw:b 3439 } 3440 { 3441 ICLASS : NEG 3442 CPL : 3 3443 CATEGORY : BINARY 3444 EXTENSION : BASE 3445 ISA_SET : I86 3446 ATTRIBUTES : BYTEOP LOCKABLE 3447 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 3448 PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix 3449 OPERANDS : MEM0:rw:b 3450 } 3451 { 3452 ICLASS : NEG 3453 CPL : 3 3454 CATEGORY : BINARY 3455 EXTENSION : BASE 3456 ISA_SET : I86 3457 ATTRIBUTES : BYTEOP 3458 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 3459 PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 3460 OPERANDS : REG0=GPR8_B():rw 3461 } 3462 { 3463 ICLASS : MUL 3464 CPL : 3 3465 CATEGORY : BINARY 3466 EXTENSION : BASE 3467 ISA_SET : I86 3468 ATTRIBUTES : BYTEOP 3469 FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] 3470 PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 3471 OPERANDS : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP 3472 PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b100] RM[nnn] 3473 OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP 3474 } 3475 { 3476 ICLASS : IMUL 3477 CPL : 3 3478 CATEGORY : BINARY 3479 EXTENSION : BASE 3480 ISA_SET : I86 3481 ATTRIBUTES : BYTEOP 3482 FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] 3483 PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 3484 OPERANDS : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP 3485 3486 PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b101] RM[nnn] 3487 OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP 3488 } 3489 { 3490 ICLASS : DIV 3491 CPL : 3 3492 CATEGORY : BINARY 3493 EXTENSION : BASE 3494 ISA_SET : I86 3495 ATTRIBUTES : BYTEOP 3496 FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] 3497 PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 3498 OPERANDS : MEM0:r:b REG0=XED_REG_AX:rw:SUPP 3499 PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b110] RM[nnn] 3500 OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP 3501 } 3502 { 3503 ICLASS : IDIV 3504 CPL : 3 3505 CATEGORY : BINARY 3506 EXTENSION : BASE 3507 ISA_SET : I86 3508 ATTRIBUTES : BYTEOP 3509 FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] 3510 PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 3511 OPERANDS : MEM0:r:b REG0=XED_REG_AX:rw:SUPP 3512 PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b111] RM[nnn] 3513 OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP 3514 } 3515 { 3516 ICLASS : TEST 3517 CPL : 3 3518 CATEGORY : LOGICAL 3519 EXTENSION : BASE 3520 ISA_SET : I86 3521 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 3522 PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() 3523 OPERANDS : MEM0:r:v IMM0:r:z 3524 IFORM : TEST_MEMv_IMMz_F7r0 3525 3526 PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() 3527 OPERANDS : MEM0:r:v IMM0:r:z 3528 IFORM : TEST_MEMv_IMMz_F7r1 3529 3530 PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() 3531 OPERANDS : REG0=GPRv_B():r IMM0:r:z 3532 IFORM : TEST_GPRv_IMMz_F7r0 3533 3534 PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz() 3535 OPERANDS : REG0=GPRv_B():r IMM0:r:z 3536 IFORM : TEST_GPRv_IMMz_F7r1 3537 } 3538 { 3539 ICLASS : NOT_LOCK 3540 DISASM : not 3541 CPL : 3 3542 CATEGORY : LOGICAL 3543 EXTENSION : BASE 3544 ISA_SET : I86 3545 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 3546 PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix 3547 OPERANDS : MEM0:rw:v 3548 } 3549 { 3550 ICLASS : NOT 3551 CPL : 3 3552 CATEGORY : LOGICAL 3553 EXTENSION : BASE 3554 ISA_SET : I86 3555 ATTRIBUTES : LOCKABLE 3556 PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix 3557 OPERANDS : MEM0:rw:v 3558 } 3559 { 3560 ICLASS : NOT 3561 CPL : 3 3562 CATEGORY : LOGICAL 3563 EXTENSION : BASE 3564 ISA_SET : I86 3565 PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 3566 OPERANDS : REG0=GPRv_B():rw 3567 } 3568 { 3569 ICLASS : NEG_LOCK 3570 DISASM : neg 3571 CPL : 3 3572 CATEGORY : BINARY 3573 EXTENSION : BASE 3574 ISA_SET : I86 3575 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 3576 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 3577 PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix 3578 OPERANDS : MEM0:rw:v 3579 } 3580 { 3581 ICLASS : NEG 3582 CPL : 3 3583 CATEGORY : BINARY 3584 EXTENSION : BASE 3585 ISA_SET : I86 3586 ATTRIBUTES : LOCKABLE 3587 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 3588 PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix 3589 OPERANDS : MEM0:rw:v 3590 } 3591 { 3592 ICLASS : NEG 3593 CPL : 3 3594 CATEGORY : BINARY 3595 EXTENSION : BASE 3596 ISA_SET : I86 3597 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 3598 PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 3599 OPERANDS : REG0=GPRv_B():rw 3600 } 3601 { 3602 ICLASS : MUL 3603 CPL : 3 3604 CATEGORY : BINARY 3605 EXTENSION : BASE 3606 ISA_SET : I86 3607 FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] 3608 PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 3609 OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP 3610 } 3611 { 3612 ICLASS : MUL 3613 CPL : 3 3614 CATEGORY : BINARY 3615 EXTENSION : BASE 3616 ISA_SET : I86 3617 FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] 3618 PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b100] RM[nnn] 3619 OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP 3620 } 3621 { 3622 ICLASS : IMUL 3623 CPL : 3 3624 CATEGORY : BINARY 3625 EXTENSION : BASE 3626 ISA_SET : I86 3627 FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] 3628 PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 3629 OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP 3630 3631 PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b101] RM[nnn] 3632 OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP 3633 } 3634 { 3635 ICLASS : DIV 3636 CPL : 3 3637 CATEGORY : BINARY 3638 EXTENSION : BASE 3639 ISA_SET : I86 3640 FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] 3641 PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 3642 OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP 3643 PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] 3644 OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP 3645 } 3646 { 3647 ICLASS : IDIV 3648 CPL : 3 3649 CATEGORY : BINARY 3650 EXTENSION : BASE 3651 ISA_SET : I86 3652 FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] 3653 PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 3654 OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP 3655 PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] 3656 OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP 3657 } 3658 { 3659 ICLASS : INC_LOCK 3660 DISASM : inc 3661 CPL : 3 3662 CATEGORY : BINARY 3663 EXTENSION : BASE 3664 ISA_SET : I86 3665 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 3666 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3667 PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix 3668 OPERANDS : MEM0:rw:b 3669 } 3670 { 3671 ICLASS : INC 3672 CPL : 3 3673 CATEGORY : BINARY 3674 EXTENSION : BASE 3675 ISA_SET : I86 3676 ATTRIBUTES : BYTEOP LOCKABLE 3677 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3678 PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix 3679 OPERANDS : MEM0:rw:b 3680 } 3681 { 3682 ICLASS : INC 3683 CPL : 3 3684 CATEGORY : BINARY 3685 EXTENSION : BASE 3686 ISA_SET : I86 3687 ATTRIBUTES : BYTEOP 3688 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3689 PATTERN : 0xFE MOD[0b11] MOD=3 REG[0b000] RM[nnn] 3690 OPERANDS : REG0=GPR8_B():rw 3691 } 3692 { 3693 ICLASS : DEC_LOCK 3694 DISASM : dec 3695 CPL : 3 3696 CATEGORY : BINARY 3697 EXTENSION : BASE 3698 ISA_SET : I86 3699 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 3700 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3701 PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix 3702 OPERANDS : MEM0:rw:b 3703 } 3704 { 3705 ICLASS : DEC 3706 CPL : 3 3707 CATEGORY : BINARY 3708 EXTENSION : BASE 3709 ISA_SET : I86 3710 ATTRIBUTES : BYTEOP LOCKABLE 3711 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3712 PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix 3713 OPERANDS : MEM0:rw:b 3714 } 3715 { 3716 ICLASS : DEC 3717 CPL : 3 3718 CATEGORY : BINARY 3719 EXTENSION : BASE 3720 ISA_SET : I86 3721 ATTRIBUTES : BYTEOP 3722 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3723 PATTERN : 0xFE MOD[0b11] MOD=3 REG[0b001] RM[nnn] 3724 OPERANDS : REG0=GPR8_B():rw 3725 } 3726 { 3727 ICLASS : INC_LOCK 3728 DISASM : inc 3729 CPL : 3 3730 CATEGORY : BINARY 3731 EXTENSION : BASE 3732 ISA_SET : I86 3733 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 3734 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3735 3736 PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix 3737 OPERANDS : MEM0:rw:v 3738 } 3739 { 3740 ICLASS : INC 3741 CPL : 3 3742 CATEGORY : BINARY 3743 EXTENSION : BASE 3744 ISA_SET : I86 3745 ATTRIBUTES : LOCKABLE 3746 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3747 3748 PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix 3749 OPERANDS : MEM0:rw:v 3750 } 3751 { 3752 ICLASS : INC 3753 CPL : 3 3754 CATEGORY : BINARY 3755 EXTENSION : BASE 3756 ISA_SET : I86 3757 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3758 PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b000] RM[nnn] 3759 OPERANDS : REG0=GPRv_B():rw 3760 IFORM : INC_GPRv_FFr0 3761 } 3762 { 3763 ICLASS : DEC_LOCK 3764 DISASM : dec 3765 CPL : 3 3766 CATEGORY : BINARY 3767 EXTENSION : BASE 3768 ISA_SET : I86 3769 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 3770 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3771 3772 PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix 3773 OPERANDS : MEM0:rw:v 3774 } 3775 { 3776 ICLASS : DEC 3777 CPL : 3 3778 CATEGORY : BINARY 3779 EXTENSION : BASE 3780 ISA_SET : I86 3781 ATTRIBUTES : LOCKABLE 3782 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3783 3784 PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix 3785 OPERANDS : MEM0:rw:v 3786 } 3787 { 3788 ICLASS : DEC 3789 CPL : 3 3790 CATEGORY : BINARY 3791 EXTENSION : BASE 3792 ISA_SET : I86 3793 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 3794 PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn] 3795 OPERANDS : REG0=GPRv_B():rw 3796 IFORM : DEC_GPRv_FFr1 3797 } 3798 { 3799 ICLASS : CALL_NEAR 3800 DISASM_INTEL: call 3801 DISASM_ATTSV: call 3802 CPL : 3 3803 CATEGORY : CALL 3804 EXTENSION : BASE 3805 ISA_SET : I86 3806 ATTRIBUTES: MPX_PREFIX_ABLE 3807 3808 PATTERN : 0xE8 not64 BRDISPz() 3809 OPERANDS : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP 3810 PATTERN : 0xE8 mode64 BRDISP32() DF64() FORCE64() 3811 OPERANDS : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP 3812 3813 PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() 3814 OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP 3815 PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() 3816 OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP REG2=rIP():rw:SUPP 3817 } 3818 { 3819 ICLASS : JMP 3820 CPL : 3 3821 CATEGORY : UNCOND_BR 3822 EXTENSION : BASE 3823 ISA_SET : I86 3824 ATTRIBUTES: MPX_PREFIX_ABLE 3825 PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() 3826 OPERANDS : MEM0:r:v REG0=rIP():w:SUPP 3827 PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() 3828 OPERANDS : REG0=GPRv_B():r REG1=rIP():w:SUPP 3829 } 3830 { 3831 ICLASS : JMP_FAR 3832 DISASM_INTEL: jmp far 3833 DISASM_ATTSV: ljmp 3834 CPL : 3 3835 ATTRIBUTES : FAR_XFER NOTSX 3836 CATEGORY : UNCOND_BR 3837 EXTENSION : BASE 3838 ISA_SET : I86 3839 PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 3840 OPERANDS : MEM0:r:p2 REG0=rIP():w:SUPP 3841 } 3842 { 3843 ICLASS : PUSH 3844 CPL : 3 3845 CATEGORY : PUSH 3846 EXTENSION : BASE 3847 ISA_SET : I86 3848 PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b110] RM[nnn] DF64() MODRM() 3849 OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP 3850 3851 PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b110] RM[nnn] DF64() 3852 OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP 3853 IFORM : PUSH_GPRv_FFr6 3854 } 3855 { 3856 ICLASS : SLDT 3857 CPL : 3 3858 CATEGORY : SYSTEM 3859 EXTENSION : BASE 3860 ISA_SET : I286PROTECTED 3861 ATTRIBUTES: PROTECTED_MODE NOTSX 3862 PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 3863 OPERANDS : MEM0:w:w REG0=XED_REG_LDTR:r:SUPP 3864 3865 PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b000] RM[nnn] 3866 OPERANDS : REG0=GPRv_B():w REG1=XED_REG_LDTR:r:SUPP 3867 } 3868 { 3869 ICLASS : STR 3870 CPL : 3 3871 CATEGORY : SYSTEM 3872 EXTENSION : BASE 3873 ISA_SET : I286PROTECTED 3874 ATTRIBUTES: PROTECTED_MODE NOTSX 3875 PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 3876 OPERANDS : MEM0:w:w REG0=XED_REG_TR:r:SUPP 3877 3878 PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 3879 OPERANDS : REG0=GPRv_B():w REG1=XED_REG_TR:r:SUPP 3880 } 3881 { 3882 ICLASS : LLDT 3883 CPL : 0 3884 CATEGORY : SYSTEM 3885 EXTENSION : BASE 3886 ISA_SET : I286PROTECTED 3887 ATTRIBUTES : PROTECTED_MODE RING0 NOTSX 3888 PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 3889 OPERANDS : MEM0:r:w REG0=XED_REG_LDTR:w:SUPP 3890 3891 PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 3892 OPERANDS : REG0=GPR16_B():r REG1=XED_REG_LDTR:w:SUPP 3893 } 3894 { 3895 ICLASS : LTR 3896 CPL : 0 3897 CATEGORY : SYSTEM 3898 EXTENSION : BASE 3899 ISA_SET : I286PROTECTED 3900 ATTRIBUTES : PROTECTED_MODE RING0 NOTSX 3901 PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 3902 OPERANDS : MEM0:r:w REG0=XED_REG_TR:w:SUPP 3903 3904 PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 3905 OPERANDS : REG0=GPR16_B():r REG1=XED_REG_TR:w:SUPP 3906 } 3907 { 3908 ICLASS : VERR 3909 CPL : 3 3910 CATEGORY : SYSTEM 3911 EXTENSION : BASE 3912 ISA_SET : I286PROTECTED 3913 ATTRIBUTES: PROTECTED_MODE 3914 FLAGS : MUST [ zf-mod ] 3915 PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 3916 OPERANDS : MEM0:r:w 3917 COMMENT : reads a selector 3918 } 3919 { 3920 ICLASS : VERR 3921 CPL : 3 3922 CATEGORY : SYSTEM 3923 EXTENSION : BASE 3924 ISA_SET : I286PROTECTED 3925 ATTRIBUTES: PROTECTED_MODE 3926 FLAGS : MUST [ zf-mod ] 3927 PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b100] RM[nnn] 3928 OPERANDS : REG0=GPR16_B():r 3929 COMMENT : reads a selector 3930 } 3931 { 3932 ICLASS : VERW 3933 CPL : 3 3934 CATEGORY : SYSTEM 3935 EXTENSION : BASE 3936 ISA_SET : I286PROTECTED 3937 ATTRIBUTES: PROTECTED_MODE 3938 FLAGS : MUST [ zf-mod ] 3939 PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 3940 OPERANDS : MEM0:r:w 3941 COMMENT : reads a selector 3942 } 3943 { 3944 ICLASS : VERW 3945 CPL : 3 3946 CATEGORY : SYSTEM 3947 EXTENSION : BASE 3948 ISA_SET : I286PROTECTED 3949 ATTRIBUTES: PROTECTED_MODE 3950 FLAGS : MUST [ zf-mod ] 3951 PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b101] RM[nnn] 3952 OPERANDS : REG0=GPR16_B():r 3953 COMMENT : reads a selector 3954 } 3955 { 3956 ICLASS : LGDT 3957 CPL : 3 3958 CATEGORY : SYSTEM 3959 EXTENSION : BASE 3960 ISA_SET : I286REAL 3961 ATTRIBUTES: NOTSX 3962 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM() 3963 OPERANDS : MEM0:r:s64 REG0=XED_REG_GDTR:w:SUPP 3964 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() 3965 OPERANDS : MEM0:r:s REG0=XED_REG_GDTR:w:SUPP 3966 } 3967 { 3968 ICLASS : SMSW 3969 CPL : 3 3970 CATEGORY : SYSTEM 3971 EXTENSION : BASE 3972 ISA_SET : I286REAL 3973 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 3974 OPERANDS : MEM0:w:w REG0=XED_REG_CR0:r:SUPP 3975 } 3976 { 3977 ICLASS : SMSW 3978 CPL : 3 3979 CATEGORY : SYSTEM 3980 EXTENSION : BASE 3981 ISA_SET : I286REAL 3982 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn] 3983 OPERANDS : REG0=GPRv_B():w REG1=XED_REG_CR0:r:SUPP 3984 } 3985 { 3986 ICLASS : LMSW 3987 CPL : 0 3988 CATEGORY : SYSTEM 3989 EXTENSION : BASE 3990 ISA_SET : I286REAL 3991 ATTRIBUTES: RING0 NOTSX 3992 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 3993 OPERANDS : MEM0:r:w REG0=XED_REG_CR0:w:SUPP 3994 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn] 3995 OPERANDS : REG0=GPR16_B():r REG1=XED_REG_CR0:w:SUPP 3996 } 3997 { 3998 ICLASS : BT 3999 CPL : 3 4000 CATEGORY : BITBYTE 4001 EXTENSION : BASE 4002 ISA_SET : I386 4003 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4004 PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() 4005 OPERANDS : MEM0:r:v IMM0:r:b 4006 } 4007 { 4008 ICLASS : BT 4009 CPL : 3 4010 CATEGORY : BITBYTE 4011 EXTENSION : BASE 4012 ISA_SET : I386 4013 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4014 PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 4015 OPERANDS : REG0=GPRv_B():r IMM0:r:b 4016 } 4017 { 4018 ICLASS : BTS_LOCK 4019 DISASM : bts 4020 CPL : 3 4021 CATEGORY : BITBYTE 4022 EXTENSION : BASE 4023 ISA_SET : I386 4024 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 4025 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4026 PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() lock_prefix 4027 OPERANDS : MEM0:rw:v IMM0:r:b 4028 } 4029 { 4030 ICLASS : BTS 4031 CPL : 3 4032 CATEGORY : BITBYTE 4033 EXTENSION : BASE 4034 ISA_SET : I386 4035 ATTRIBUTES : LOCKABLE 4036 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4037 PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() nolock_prefix 4038 OPERANDS : MEM0:rw:v IMM0:r:b 4039 } 4040 { 4041 ICLASS : BTS 4042 CPL : 3 4043 CATEGORY : BITBYTE 4044 EXTENSION : BASE 4045 ISA_SET : I386 4046 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4047 PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() 4048 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 4049 } 4050 { 4051 ICLASS : BTR_LOCK 4052 DISASM : btr 4053 CPL : 3 4054 CATEGORY : BITBYTE 4055 EXTENSION : BASE 4056 ISA_SET : I386 4057 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 4058 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4059 PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix 4060 OPERANDS : MEM0:rw:v IMM0:r:b 4061 } 4062 { 4063 ICLASS : BTR 4064 CPL : 3 4065 CATEGORY : BITBYTE 4066 EXTENSION : BASE 4067 ISA_SET : I386 4068 ATTRIBUTES : LOCKABLE 4069 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4070 PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix 4071 OPERANDS : MEM0:rw:v IMM0:r:b 4072 } 4073 { 4074 ICLASS : BTR 4075 CPL : 3 4076 CATEGORY : BITBYTE 4077 EXTENSION : BASE 4078 ISA_SET : I386 4079 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4080 PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 4081 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 4082 } 4083 { 4084 ICLASS : BTC_LOCK 4085 DISASM : btc 4086 CPL : 3 4087 CATEGORY : BITBYTE 4088 EXTENSION : BASE 4089 ISA_SET : I386 4090 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 4091 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4092 PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() lock_prefix 4093 OPERANDS : MEM0:rw:v IMM0:r:b 4094 } 4095 { 4096 ICLASS : BTC 4097 CPL : 3 4098 CATEGORY : BITBYTE 4099 EXTENSION : BASE 4100 ISA_SET : I386 4101 ATTRIBUTES : LOCKABLE 4102 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4103 PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() nolock_prefix 4104 OPERANDS : MEM0:rw:v IMM0:r:b 4105 } 4106 { 4107 ICLASS : BTC 4108 CPL : 3 4109 CATEGORY : BITBYTE 4110 EXTENSION : BASE 4111 ISA_SET : I386 4112 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 4113 PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() 4114 OPERANDS : REG0=GPRv_B():rw IMM0:r:b 4115 } 4116 4117 # NOTE: VMXON and VMCLEAR almost conflict when there is a redundant 66 4118 # on VMXON. It should be (and is) a VMXON. VMCLEAR is required to 4119 # "not have" f2/f3; osz_refining_prefix handles this. 4120 4121 { 4122 ICLASS : VMCLEAR 4123 CPL : 3 4124 CATEGORY : VTX 4125 EXTENSION : VTX 4126 ATTRIBUTES: NOTSX 4127 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() 4128 OPERANDS : MEM0:r:q 4129 } 4130 { 4131 ICLASS : VMPTRLD 4132 CPL : 3 4133 CATEGORY : VTX 4134 EXTENSION : VTX 4135 ATTRIBUTES: NOTSX 4136 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM() 4137 OPERANDS : MEM0:r:q 4138 } 4139 { 4140 ICLASS : VMPTRST 4141 CPL : 3 4142 CATEGORY : VTX 4143 EXTENSION : VTX 4144 ATTRIBUTES: NOTSX 4145 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() 4146 OPERANDS : MEM0:w:q 4147 } 4148 4149 4150 { 4151 ICLASS : VMXON 4152 CPL : 3 4153 CATEGORY : VTX 4154 EXTENSION : VTX 4155 ATTRIBUTES: PROTECTED_MODE NOTSX 4156 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM() 4157 OPERANDS : MEM0:r:q 4158 } 4159 { 4160 ICLASS : CMPXCHG8B_LOCK 4161 DISASM : cmpxchg8b 4162 CPL : 3 4163 CATEGORY : SEMAPHORE 4164 EXTENSION : BASE 4165 ISA_SET : PENTIUMREAL 4166 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 4167 FLAGS : MUST [ zf-mod ] 4168 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix 4169 OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP 4170 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix 4171 OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP 4172 } 4173 { 4174 ICLASS : CMPXCHG8B 4175 CPL : 3 4176 CATEGORY : SEMAPHORE 4177 EXTENSION : BASE 4178 ISA_SET : PENTIUMREAL 4179 ATTRIBUTES : LOCKABLE 4180 FLAGS : MUST [ zf-mod ] 4181 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix 4182 OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP 4183 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix 4184 OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP 4185 } 4186 { 4187 ICLASS : CMPXCHG16B_LOCK 4188 DISASM : cmpxchg16b 4189 CPL : 3 4190 CATEGORY : SEMAPHORE 4191 EXTENSION : LONGMODE 4192 ISA_SET : CMPXCHG16B 4193 ATTRIBUTES: REQUIRES_ALIGNMENT LOCKED 4194 FLAGS : MUST [ zf-mod ] 4195 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix 4196 OPERANDS : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP 4197 } 4198 { 4199 ICLASS : CMPXCHG16B 4200 CPL : 3 4201 CATEGORY : SEMAPHORE 4202 EXTENSION : LONGMODE 4203 ISA_SET : CMPXCHG16B 4204 ATTRIBUTES: REQUIRES_ALIGNMENT LOCKABLE 4205 FLAGS : MUST [ zf-mod ] 4206 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix 4207 OPERANDS : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP 4208 } 4209 { 4210 ICLASS : MOV 4211 CPL : 3 4212 CATEGORY : DATAXFER 4213 EXTENSION : BASE 4214 ISA_SET : I86 4215 ATTRIBUTES : BYTEOP 4216 4217 PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() 4218 OPERANDS : REG0=GPR8_B():w IMM0:r:b 4219 IFORM : MOV_GPR8_IMMb_C6r0 4220 } 4221 { 4222 ICLASS : MOV 4223 CPL : 3 4224 CATEGORY : DATAXFER 4225 EXTENSION : BASE 4226 ISA_SET : I86 4227 ATTRIBUTES : BYTEOP HLE_REL_ABLE 4228 PATTERN : 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() 4229 OPERANDS : MEM0:w:b IMM0:r:b 4230 } 4231 { 4232 ICLASS : MOV 4233 CPL : 3 4234 CATEGORY : DATAXFER 4235 EXTENSION : BASE 4236 ISA_SET : I86 4237 PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() 4238 OPERANDS : REG0=GPRv_B():w IMM0:r:z 4239 } 4240 { 4241 ICLASS : MOV 4242 CPL : 3 4243 CATEGORY : DATAXFER 4244 EXTENSION : BASE 4245 ISA_SET : I86 4246 ATTRIBUTES : HLE_REL_ABLE 4247 PATTERN : 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() 4248 OPERANDS : MEM0:w:v IMM0:r:z 4249 } 4250 { 4251 ICLASS : PSRLW 4252 EXCEPTIONS: mmx-mem 4253 ATTRIBUTES: NOTSX 4254 CPL : 3 4255 CATEGORY : MMX 4256 EXTENSION : MMX 4257 ISA_SET : PENTIUMMMX 4258 PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 4259 OPERANDS : REG0=MMX_B():rw:q:u16 IMM0:r:b 4260 } 4261 { 4262 ICLASS : PSRAW 4263 EXCEPTIONS: mmx-mem 4264 ATTRIBUTES: NOTSX 4265 CPL : 3 4266 CATEGORY : MMX 4267 EXTENSION : MMX 4268 ISA_SET : PENTIUMMMX 4269 PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 4270 OPERANDS : REG0=MMX_B():rw:q:i16 IMM0:r:b 4271 } 4272 { 4273 ICLASS : PSLLW 4274 EXCEPTIONS: mmx-mem 4275 ATTRIBUTES: NOTSX 4276 CPL : 3 4277 CATEGORY : MMX 4278 EXTENSION : MMX 4279 ISA_SET : PENTIUMMMX 4280 PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 4281 OPERANDS : REG0=MMX_B():rw:q:u16 IMM0:r:b 4282 } 4283 { 4284 ICLASS : PSRLW 4285 CPL : 3 4286 CATEGORY : SSE 4287 EXTENSION : SSE2 4288 EXCEPTIONS: SSE_TYPE_7 4289 PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() 4290 OPERANDS : REG0=XMM_B():rw:dq:u16 IMM0:r:b 4291 } 4292 { 4293 ICLASS : PSRAW 4294 CPL : 3 4295 CATEGORY : SSE 4296 EXTENSION : SSE2 4297 EXCEPTIONS: SSE_TYPE_7 4298 PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8() 4299 OPERANDS : REG0=XMM_B():rw:dq:i16 IMM0:r:b 4300 } 4301 { 4302 ICLASS : PSLLW 4303 CPL : 3 4304 CATEGORY : SSE 4305 EXTENSION : SSE2 4306 EXCEPTIONS: SSE_TYPE_7 4307 PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() 4308 OPERANDS : REG0=XMM_B():rw:dq:u16 IMM0:r:b 4309 } 4310 { 4311 ICLASS : PSRLD 4312 EXCEPTIONS: mmx-mem 4313 ATTRIBUTES: NOTSX 4314 CPL : 3 4315 CATEGORY : MMX 4316 EXTENSION : MMX 4317 ISA_SET : PENTIUMMMX 4318 PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 4319 OPERANDS : REG0=MMX_B():rw:q:u32 IMM0:r:b 4320 } 4321 { 4322 ICLASS : PSRAD 4323 EXCEPTIONS: mmx-mem 4324 ATTRIBUTES: NOTSX 4325 CPL : 3 4326 CATEGORY : MMX 4327 EXTENSION : MMX 4328 ISA_SET : PENTIUMMMX 4329 PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 4330 OPERANDS : REG0=MMX_B():rw:q:i32 IMM0:r:b 4331 } 4332 { 4333 ICLASS : PSLLD 4334 EXCEPTIONS: mmx-mem 4335 ATTRIBUTES: NOTSX 4336 CPL : 3 4337 CATEGORY : MMX 4338 EXTENSION : MMX 4339 ISA_SET : PENTIUMMMX 4340 PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 4341 OPERANDS : REG0=MMX_B():rw:q:u32 IMM0:r:b 4342 } 4343 { 4344 ICLASS : PSRLD 4345 CPL : 3 4346 CATEGORY : SSE 4347 EXTENSION : SSE2 4348 EXCEPTIONS: SSE_TYPE_7 4349 PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() 4350 OPERANDS : REG0=XMM_B():rw:dq:u32 IMM0:r:b 4351 } 4352 { 4353 ICLASS : PSRAD 4354 CPL : 3 4355 CATEGORY : SSE 4356 EXTENSION : SSE2 4357 EXCEPTIONS: SSE_TYPE_7 4358 PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8() 4359 OPERANDS : REG0=XMM_B():rw:dq:i32 IMM0:r:b 4360 } 4361 { 4362 ICLASS : PSLLD 4363 CPL : 3 4364 CATEGORY : SSE 4365 EXTENSION : SSE2 4366 EXCEPTIONS: SSE_TYPE_7 4367 PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() 4368 OPERANDS : REG0=XMM_B():rw:dq:u32 IMM0:r:b 4369 } 4370 { 4371 ICLASS : PSRLQ 4372 EXCEPTIONS: mmx-mem 4373 ATTRIBUTES: NOTSX 4374 CPL : 3 4375 CATEGORY : MMX 4376 EXTENSION : MMX 4377 ISA_SET : PENTIUMMMX 4378 PATTERN : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 4379 OPERANDS : REG0=MMX_B():rw:q:u64 IMM0:r:b 4380 } 4381 { 4382 ICLASS : PSLLQ 4383 EXCEPTIONS: mmx-mem 4384 ATTRIBUTES: NOTSX 4385 CPL : 3 4386 CATEGORY : MMX 4387 EXTENSION : MMX 4388 ISA_SET : PENTIUMMMX 4389 PATTERN : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 4390 OPERANDS : REG0=MMX_B():rw:q:u64 IMM0:r:b 4391 } 4392 { 4393 ICLASS : PSRLQ 4394 CPL : 3 4395 CATEGORY : SSE 4396 EXTENSION : SSE2 4397 EXCEPTIONS: SSE_TYPE_7 4398 PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() 4399 OPERANDS : REG0=XMM_B():rw:dq:u64 IMM0:r:b 4400 } 4401 { 4402 ICLASS : PSRLDQ 4403 CPL : 3 4404 CATEGORY : SSE 4405 EXTENSION : SSE2 4406 EXCEPTIONS: SSE_TYPE_7 4407 PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b011] RM[nnn] REFINING66() UIMM8() 4408 OPERANDS : REG0=XMM_B():rw:dq:u128 IMM0:r:b 4409 } 4410 { 4411 ICLASS : PSLLQ 4412 CPL : 3 4413 CATEGORY : SSE 4414 EXTENSION : SSE2 4415 EXCEPTIONS: SSE_TYPE_7 4416 PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() 4417 OPERANDS : REG0=XMM_B():rw:dq:u64 IMM0:r:b 4418 } 4419 { 4420 ICLASS : PSLLDQ 4421 CPL : 3 4422 CATEGORY : SSE 4423 EXTENSION : SSE2 4424 EXCEPTIONS: SSE_TYPE_7 4425 PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b111] RM[nnn] REFINING66() UIMM8() 4426 OPERANDS : REG0=XMM_B():rw:dq:u128 IMM0:r:b 4427 } 4428 { 4429 ICLASS : FXSAVE 4430 CPL : 3 4431 CATEGORY : SSE 4432 EXTENSION : SSE 4433 ISA_SET : FXSAVE 4434 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX 4435 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix norexw_prefix MODRM() 4436 OPERANDS : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP 4437 } 4438 { 4439 ICLASS : FXRSTOR 4440 CPL : 3 4441 CATEGORY : SSE 4442 EXTENSION : SSE 4443 ISA_SET : FXSAVE 4444 ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX 4445 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix norexw_prefix MODRM() 4446 OPERANDS : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP 4447 } 4448 { 4449 ICLASS : FXSAVE64 4450 CPL : 3 4451 CATEGORY : SSE 4452 EXTENSION : SSE 4453 ISA_SET : FXSAVE64 4454 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX 4455 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix rexw_prefix MODRM() 4456 OPERANDS : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP 4457 } 4458 { 4459 ICLASS : FXRSTOR64 4460 CPL : 3 4461 CATEGORY : SSE 4462 EXTENSION : SSE 4463 ISA_SET : FXSAVE64 4464 ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX 4465 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix rexw_prefix MODRM() 4466 OPERANDS : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP 4467 } 4468 4469 4470 4471 4472 4473 { 4474 ICLASS : LDMXCSR 4475 CPL : 3 4476 CATEGORY : SSE 4477 EXTENSION : SSE 4478 ISA_SET : SSEMXCSR 4479 EXCEPTIONS: SSE_TYPE_5 4480 ATTRIBUTES : MXCSR 4481 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM() 4482 OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP 4483 } 4484 { 4485 ICLASS : STMXCSR 4486 CPL : 3 4487 CATEGORY : SSE 4488 EXTENSION : SSE 4489 ISA_SET : SSEMXCSR 4490 EXCEPTIONS: SSE_TYPE_5 4491 ATTRIBUTES : MXCSR_RD 4492 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM() 4493 OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP 4494 } 4495 { 4496 ICLASS : PREFETCHNTA 4497 CPL : 3 4498 CATEGORY : PREFETCH 4499 ATTRIBUTES: PREFETCH 4500 EXTENSION : SSE 4501 ISA_SET : SSE_PREFETCH 4502 PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 4503 OPERANDS : MEM0:r:mprefetch 4504 } 4505 { 4506 ICLASS : PREFETCHT0 4507 CPL : 3 4508 CATEGORY : PREFETCH 4509 ATTRIBUTES: PREFETCH 4510 EXTENSION : SSE 4511 ISA_SET : SSE_PREFETCH 4512 PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 4513 OPERANDS : MEM0:r:mprefetch 4514 } 4515 { 4516 ICLASS : PREFETCHT1 4517 CPL : 3 4518 CATEGORY : PREFETCH 4519 ATTRIBUTES: PREFETCH 4520 EXTENSION : SSE 4521 ISA_SET : SSE_PREFETCH 4522 PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 4523 OPERANDS : MEM0:r:mprefetch 4524 } 4525 { 4526 ICLASS : PREFETCHT2 4527 CPL : 3 4528 CATEGORY : PREFETCH 4529 ATTRIBUTES: PREFETCH 4530 EXTENSION : SSE 4531 ISA_SET : SSE_PREFETCH 4532 PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 4533 OPERANDS : MEM0:r:mprefetch 4534 } 4535 4536 4537 4538 { 4539 ICLASS : NOP 4540 CPL : 3 4541 UNAME : NOP0F18 4542 CATEGORY : WIDENOP 4543 ATTRIBUTES: NOP 4544 EXTENSION : BASE 4545 ISA_SET : FAT_NOP 4546 4547 PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b000] RM[nnn] 4548 OPERANDS : REG0=GPRv_B():r 4549 IFORM : NOP_GPRv_0F18r0 4550 4551 PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 4552 OPERANDS : REG0=GPRv_B():r 4553 IFORM : NOP_GPRv_0F18r1 4554 4555 PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 4556 OPERANDS : REG0=GPRv_B():r 4557 IFORM : NOP_GPRv_0F18r2 4558 4559 PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 4560 OPERANDS : REG0=GPRv_B():r 4561 IFORM : NOP_GPRv_0F18r3 4562 4563 4564 PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 4565 OPERANDS : MEM0:r:v 4566 IFORM : NOP_MEMv_0F18r4 4567 4568 PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b100] RM[nnn] 4569 OPERANDS : REG0=GPRv_B():r 4570 IFORM : NOP_GPRv_0F18r4 4571 4572 PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 4573 OPERANDS : MEM0:r:v 4574 IFORM : NOP_MEMv_0F18r5 4575 4576 PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b101] RM[nnn] 4577 OPERANDS : REG0=GPRv_B():r 4578 IFORM : NOP_GPRv_0F18r5 4579 4580 PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 4581 OPERANDS : MEM0:r:v 4582 IFORM : NOP_MEMv_0F18r6 4583 4584 PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b110] RM[nnn] 4585 OPERANDS : REG0=GPRv_B():r 4586 IFORM : NOP_GPRv_0F18r6 4587 4588 PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 4589 OPERANDS : MEM0:r:v 4590 IFORM : NOP_MEMv_0F18r7 4591 4592 PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b111] RM[nnn] 4593 OPERANDS : REG0=GPRv_B():r 4594 IFORM : NOP_GPRv_0F18r7 4595 } 4596 { 4597 ICLASS : NOP 4598 UNAME : NOP0F19 4599 CPL : 3 4600 CATEGORY : WIDENOP 4601 EXTENSION : BASE 4602 ATTRIBUTES: NOP 4603 ISA_SET : FAT_NOP 4604 PATTERN : 0x0F 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4605 OPERANDS : MEM0:r:v REG0=GPRv_R():r 4606 IFORM : NOP_MEMv_GPRv_0F19 4607 4608 PATTERN : 0x0F 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4609 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 4610 IFORM : NOP_GPRv_GPRv_0F19 4611 } 4612 { 4613 ICLASS : NOP 4614 CPL : 3 4615 UNAME : NOP0F1A 4616 CATEGORY : WIDENOP 4617 ATTRIBUTES: NOP 4618 EXTENSION : BASE 4619 ISA_SET : FAT_NOP 4620 PATTERN : 0x0F 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4621 OPERANDS : MEM0:r:v REG0=GPRv_R():r 4622 IFORM : NOP_MEMv_GPRv_0F1A 4623 4624 PATTERN : 0x0F 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4625 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 4626 IFORM : NOP_GPRv_GPRv_0F1A 4627 } 4628 { 4629 ICLASS : NOP 4630 UNAME : NOP0F1B 4631 CPL : 3 4632 CATEGORY : WIDENOP 4633 EXTENSION : BASE 4634 ATTRIBUTES: NOP 4635 ISA_SET : FAT_NOP 4636 PATTERN : 0x0F 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4637 OPERANDS : MEM0:r:v REG0=GPRv_R():r 4638 IFORM : NOP_MEMv_GPRv_0F1B 4639 4640 PATTERN : 0x0F 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4641 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 4642 IFORM : NOP_GPRv_GPRv_0F1B 4643 } 4644 { 4645 ICLASS : NOP 4646 UNAME : NOP0F1C 4647 CPL : 3 4648 CATEGORY : WIDENOP 4649 EXTENSION : BASE 4650 ATTRIBUTES: NOP 4651 ISA_SET : FAT_NOP 4652 PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4653 OPERANDS : MEM0:r:v REG0=GPRv_R():r 4654 IFORM : NOP_MEMv_GPRv_0F1C 4655 4656 PATTERN : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4657 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 4658 IFORM : NOP_GPRv_GPRv_0F1C 4659 } 4660 { 4661 ICLASS : NOP 4662 UNAME : NOP0F1D 4663 CPL : 3 4664 CATEGORY : WIDENOP 4665 EXTENSION : BASE 4666 ATTRIBUTES: NOP 4667 ISA_SET : FAT_NOP 4668 PATTERN : 0x0F 0x1D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4669 OPERANDS : MEM0:r:v REG0=GPRv_R():r 4670 IFORM : NOP_MEMv_GPRv_0F1D 4671 4672 PATTERN : 0x0F 0x1D MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4673 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 4674 IFORM : NOP_GPRv_GPRv_0F1D 4675 } 4676 { 4677 ICLASS : NOP 4678 UNAME : NOP0F1E 4679 CPL : 3 4680 CATEGORY : WIDENOP 4681 EXTENSION : BASE 4682 ATTRIBUTES: NOP 4683 ISA_SET : FAT_NOP 4684 PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4685 OPERANDS : MEM0:r:v REG0=GPRv_R():r 4686 IFORM : NOP_MEMv_GPRv_0F1E 4687 4688 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4689 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 4690 IFORM : NOP_GPRv_GPRv_0F1E 4691 } 4692 4693 { 4694 ICLASS : NOP 4695 UNAME : NOP0F1F 4696 CPL : 3 4697 CATEGORY : WIDENOP 4698 EXTENSION : BASE 4699 ATTRIBUTES: NOP 4700 ISA_SET : FAT_NOP 4701 PATTERN : 0x0F 0x1F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4702 OPERANDS : MEM0:r:v REG0=GPRv_R():r 4703 IFORM : NOP_MEMv_GPRv_0F1F 4704 PATTERN : 0x0F 0x1F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4705 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 4706 IFORM : NOP_GPRv_GPRv_0F1F 4707 } 4708 { 4709 ICLASS : VMCALL 4710 CPL : 3 4711 CATEGORY : VTX 4712 EXTENSION : VTX 4713 ATTRIBUTES: NOTSX 4714 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] 4715 OPERANDS : 4716 } 4717 { 4718 ICLASS : VMLAUNCH 4719 CPL : 3 4720 CATEGORY : VTX 4721 EXTENSION : VTX 4722 ATTRIBUTES: NOTSX 4723 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] 4724 OPERANDS : 4725 } 4726 { 4727 ICLASS : VMRESUME 4728 CPL : 3 4729 CATEGORY : VTX 4730 EXTENSION : VTX 4731 ATTRIBUTES: NOTSX 4732 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] 4733 OPERANDS : 4734 } 4735 { 4736 ICLASS : VMXOFF 4737 CPL : 3 4738 CATEGORY : VTX 4739 EXTENSION : VTX 4740 ATTRIBUTES: NOTSX 4741 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] 4742 OPERANDS : 4743 } 4744 { 4745 ICLASS : SGDT 4746 CPL : 3 4747 CATEGORY : SYSTEM 4748 EXTENSION : BASE 4749 ISA_SET : I286REAL 4750 ATTRIBUTES: NOTSX 4751 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM() 4752 OPERANDS : MEM0:w:s64 REG0=XED_REG_GDTR:r:SUPP 4753 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() 4754 OPERANDS : MEM0:w:s REG0=XED_REG_GDTR:r:SUPP 4755 } 4756 { 4757 ICLASS : LIDT 4758 CPL : 0 4759 CATEGORY : SYSTEM 4760 EXTENSION : BASE 4761 ISA_SET : I286REAL 4762 ATTRIBUTES: RING0 NOTSX 4763 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM() 4764 OPERANDS : MEM0:r:s64 REG0=XED_REG_IDTR:w:SUPP 4765 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() 4766 OPERANDS : MEM0:r:s REG0=XED_REG_IDTR:w:SUPP 4767 } 4768 { 4769 ICLASS : MONITOR 4770 CPL : 0 4771 CATEGORY : MISC 4772 EXTENSION : SSE3 4773 ATTRIBUTES: RING0 NOTSX 4774 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] 4775 OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP 4776 } 4777 { 4778 ICLASS : MWAIT 4779 CPL : 0 4780 CATEGORY : MISC 4781 EXTENSION : SSE3 4782 ATTRIBUTES: RING0 NOTSX 4783 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] 4784 OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_ECX:r:SUPP 4785 } 4786 { 4787 ICLASS : SIDT 4788 CPL : 3 4789 CATEGORY : SYSTEM 4790 EXTENSION : BASE 4791 ISA_SET : I286REAL 4792 ATTRIBUTES: NOTSX 4793 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() 4794 OPERANDS : MEM0:w:s REG0=XED_REG_IDTR:r:SUPP 4795 } 4796 { 4797 ICLASS : SIDT 4798 CPL : 3 4799 CATEGORY : SYSTEM 4800 EXTENSION : BASE 4801 ISA_SET : I286REAL 4802 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM() 4803 OPERANDS : MEM0:w:s64 REG0=XED_REG_IDTR:r:SUPP 4804 } 4805 { 4806 ICLASS : INVLPG 4807 CPL : 0 4808 CATEGORY : SYSTEM 4809 EXTENSION : BASE 4810 ISA_SET : I486REAL 4811 ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION BYTEOP RING0 NOTSX 4812 PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 4813 OPERANDS : MEM0:r:b 4814 } 4815 { 4816 ICLASS : SWAPGS 4817 CPL : 0 4818 CATEGORY : SYSTEM 4819 EXTENSION : LONGMODE 4820 ATTRIBUTES: RING0 NOTSX 4821 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64 4822 OPERANDS : 4823 } 4824 { 4825 ICLASS : RDTSCP 4826 CPL : 3 4827 CATEGORY : SYSTEM 4828 EXTENSION : RDTSCP 4829 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001] 4830 OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_TSC:r:SUPP REG4=XED_REG_TSCAUX:r:SUPP 4831 } 4832 { 4833 ICLASS : SFENCE 4834 CPL : 3 4835 CATEGORY : MISC 4836 EXTENSION : SSE 4837 ATTRIBUTES: IGNORES_OSFXSR 4838 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix 4839 OPERANDS : 4840 } 4841 { 4842 ICLASS : CLFLUSH 4843 ATTRIBUTES: NOTSX 4844 CPL : 3 4845 CATEGORY : MISC 4846 EXTENSION : CLFSH 4847 ISA_SET : CLFSH 4848 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() 4849 OPERANDS : MEM0:r:mprefetch 4850 } 4851 { 4852 ICLASS : LFENCE 4853 CPL : 3 4854 CATEGORY : MISC 4855 EXTENSION : SSE2 4856 ISA_SET : SSE2 4857 ATTRIBUTES: IGNORES_OSFXSR 4858 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix 4859 OPERANDS : 4860 } 4861 { 4862 ICLASS : MFENCE 4863 CPL : 3 4864 CATEGORY : MISC 4865 EXTENSION : SSE2 4866 ISA_SET : SSE2 4867 ATTRIBUTES: IGNORES_OSFXSR 4868 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix 4869 OPERANDS : 4870 } 4871 { 4872 ICLASS : MOVHLPS 4873 CPL : 3 4874 CATEGORY : DATAXFER 4875 EXTENSION : SSE 4876 EXCEPTIONS: SSE_TYPE_7 4877 PATTERN : 0x0F 0x12 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4878 OPERANDS : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32 4879 } 4880 { 4881 ICLASS : MOVLPS 4882 CPL : 3 4883 CATEGORY : DATAXFER 4884 EXTENSION : SSE 4885 EXCEPTIONS: SSE_TYPE_5 4886 ATTRIBUTES : 4887 PATTERN : 0x0F 0x12 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4888 OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:f32 4889 } 4890 { 4891 ICLASS : MOVLHPS 4892 CPL : 3 4893 CATEGORY : DATAXFER 4894 EXTENSION : SSE 4895 EXCEPTIONS: SSE_TYPE_7 4896 PATTERN : 0x0F 0x16 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4897 OPERANDS : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32 4898 } 4899 { 4900 ICLASS : MOVHPS 4901 CPL : 3 4902 CATEGORY : DATAXFER 4903 EXTENSION : SSE 4904 EXCEPTIONS: SSE_TYPE_5 4905 ATTRIBUTES : 4906 PATTERN : 0x0F 0x16 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4907 OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:f32 4908 } 4909 { 4910 ICLASS : ADD_LOCK 4911 DISASM : add 4912 CPL : 3 4913 CATEGORY : BINARY 4914 EXTENSION : BASE 4915 ISA_SET : I86 4916 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 4917 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 4918 4919 PATTERN : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 4920 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 4921 } 4922 { 4923 ICLASS : ADD 4924 CPL : 3 4925 CATEGORY : BINARY 4926 EXTENSION : BASE 4927 ISA_SET : I86 4928 ATTRIBUTES : BYTEOP LOCKABLE 4929 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 4930 4931 PATTERN : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 4932 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 4933 } 4934 { 4935 ICLASS : ADD 4936 CPL : 3 4937 CATEGORY : BINARY 4938 EXTENSION : BASE 4939 ISA_SET : I86 4940 ATTRIBUTES : BYTEOP 4941 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 4942 PATTERN : 0x00 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4943 OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r 4944 IFORM : ADD_GPR8_GPR8_00 4945 } 4946 4947 4948 4949 { 4950 ICLASS : ADD_LOCK 4951 DISASM : add 4952 CPL : 3 4953 CATEGORY : BINARY 4954 EXTENSION : BASE 4955 ISA_SET : I86 4956 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 4957 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 4958 4959 PATTERN : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 4960 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 4961 } 4962 { 4963 ICLASS : ADD 4964 CPL : 3 4965 CATEGORY : BINARY 4966 EXTENSION : BASE 4967 ISA_SET : I86 4968 ATTRIBUTES : LOCKABLE 4969 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 4970 4971 PATTERN : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 4972 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 4973 } 4974 { 4975 ICLASS : ADD 4976 CPL : 3 4977 CATEGORY : BINARY 4978 EXTENSION : BASE 4979 ISA_SET : I86 4980 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 4981 PATTERN : 0x01 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4982 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r 4983 IFORM : ADD_GPRv_GPRv_01 4984 } 4985 4986 4987 4988 { 4989 ICLASS : ADD 4990 CPL : 3 4991 CATEGORY : BINARY 4992 EXTENSION : BASE 4993 ISA_SET : I86 4994 ATTRIBUTES : BYTEOP 4995 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 4996 4997 PATTERN : 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4998 OPERANDS : REG0=GPR8_R():rw MEM0:r:b 4999 } 5000 { 5001 ICLASS : ADD 5002 CPL : 3 5003 CATEGORY : BINARY 5004 EXTENSION : BASE 5005 ISA_SET : I86 5006 ATTRIBUTES : BYTEOP 5007 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5008 PATTERN : 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5009 OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r 5010 IFORM : ADD_GPR8_GPR8_02 5011 } 5012 5013 5014 5015 { 5016 ICLASS : ADD 5017 CPL : 3 5018 CATEGORY : BINARY 5019 EXTENSION : BASE 5020 ISA_SET : I86 5021 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5022 5023 PATTERN : 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5024 OPERANDS : REG0=GPRv_R():rw MEM0:r:v 5025 } 5026 { 5027 ICLASS : ADD 5028 CPL : 3 5029 CATEGORY : BINARY 5030 EXTENSION : BASE 5031 ISA_SET : I86 5032 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5033 PATTERN : 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5034 OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r 5035 IFORM : ADD_GPRv_GPRv_03 5036 } 5037 5038 { 5039 ICLASS : ADD 5040 CPL : 3 5041 CATEGORY : BINARY 5042 EXTENSION : BASE 5043 ISA_SET : I86 5044 ATTRIBUTES : BYTEOP 5045 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5046 PATTERN : 0x04 SIMM8() 5047 OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 5048 } 5049 { 5050 ICLASS : ADD 5051 CPL : 3 5052 CATEGORY : BINARY 5053 EXTENSION : BASE 5054 ISA_SET : I86 5055 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5056 PATTERN : 0x05 SIMMz() 5057 OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z 5058 } 5059 { 5060 ICLASS : PUSH 5061 CPL : 3 5062 CATEGORY : PUSH 5063 EXTENSION : BASE 5064 ISA_SET : I86 5065 PATTERN : 0x06 not64 5066 OPERANDS : REG0=XED_REG_ES:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP 5067 } 5068 { 5069 ICLASS : POP 5070 CPL : 3 5071 CATEGORY : POP 5072 EXTENSION : BASE 5073 ISA_SET : I86 5074 ATTRIBUTES: NOTSX 5075 PATTERN : 0x07 not64 5076 OPERANDS : REG0=XED_REG_ES:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP 5077 } 5078 5079 { 5080 ICLASS : OR_LOCK 5081 DISASM : or 5082 CPL : 3 5083 CATEGORY : LOGICAL 5084 EXTENSION : BASE 5085 ISA_SET : I86 5086 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5087 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5088 5089 PATTERN : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5090 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5091 } 5092 { 5093 ICLASS : OR 5094 CPL : 3 5095 CATEGORY : LOGICAL 5096 EXTENSION : BASE 5097 ISA_SET : I86 5098 ATTRIBUTES : BYTEOP LOCKABLE 5099 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5100 5101 PATTERN : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5102 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5103 } 5104 { 5105 ICLASS : OR 5106 CPL : 3 5107 CATEGORY : LOGICAL 5108 EXTENSION : BASE 5109 ISA_SET : I86 5110 ATTRIBUTES : BYTEOP 5111 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5112 5113 PATTERN : 0x08 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5114 OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r 5115 IFORM : OR_GPR8_GPR8_08 5116 } 5117 5118 5119 5120 5121 { 5122 ICLASS : OR_LOCK 5123 DISASM : or 5124 CPL : 3 5125 CATEGORY : LOGICAL 5126 EXTENSION : BASE 5127 ISA_SET : I86 5128 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5129 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5130 5131 PATTERN : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5132 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5133 } 5134 { 5135 ICLASS : OR 5136 CPL : 3 5137 CATEGORY : LOGICAL 5138 EXTENSION : BASE 5139 ISA_SET : I86 5140 ATTRIBUTES : LOCKABLE 5141 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5142 5143 PATTERN : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5144 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5145 } 5146 { 5147 ICLASS : OR 5148 CPL : 3 5149 CATEGORY : LOGICAL 5150 EXTENSION : BASE 5151 ISA_SET : I86 5152 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5153 5154 PATTERN : 0x09 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5155 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r 5156 IFORM : OR_GPRv_GPRv_09 5157 } 5158 5159 5160 5161 { 5162 ICLASS : OR 5163 CPL : 3 5164 CATEGORY : LOGICAL 5165 EXTENSION : BASE 5166 ISA_SET : I86 5167 ATTRIBUTES : BYTEOP 5168 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5169 5170 PATTERN : 0x0A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5171 OPERANDS : REG0=GPR8_R():rw MEM0:r:b 5172 } 5173 { 5174 ICLASS : OR 5175 CPL : 3 5176 CATEGORY : LOGICAL 5177 EXTENSION : BASE 5178 ISA_SET : I86 5179 ATTRIBUTES : BYTEOP 5180 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5181 5182 PATTERN : 0x0A MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5183 OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r 5184 IFORM : OR_GPR8_GPR8_0A 5185 } 5186 5187 5188 5189 { 5190 ICLASS : OR 5191 CPL : 3 5192 CATEGORY : LOGICAL 5193 EXTENSION : BASE 5194 ISA_SET : I86 5195 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5196 5197 PATTERN : 0x0B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5198 OPERANDS : REG0=GPRv_R():rw MEM0:r:v 5199 } 5200 { 5201 ICLASS : OR 5202 CPL : 3 5203 CATEGORY : LOGICAL 5204 EXTENSION : BASE 5205 ISA_SET : I86 5206 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5207 5208 PATTERN : 0x0B MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5209 OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r 5210 IFORM : OR_GPRv_GPRv_0B 5211 } 5212 5213 5214 5215 { 5216 ICLASS : OR 5217 CPL : 3 5218 CATEGORY : LOGICAL 5219 EXTENSION : BASE 5220 ISA_SET : I86 5221 ATTRIBUTES : BYTEOP 5222 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5223 PATTERN : 0x0C UIMM8() 5224 OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b 5225 } 5226 { 5227 ICLASS : OR 5228 CPL : 3 5229 CATEGORY : LOGICAL 5230 EXTENSION : BASE 5231 ISA_SET : I86 5232 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5233 PATTERN : 0x0D SIMMz() 5234 OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z 5235 } 5236 { 5237 ICLASS : PUSH 5238 CPL : 3 5239 CATEGORY : PUSH 5240 EXTENSION : BASE 5241 ISA_SET : I86 5242 PATTERN : 0x0E not64 5243 OPERANDS : REG0=XED_REG_CS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP 5244 } 5245 5246 5247 { 5248 ICLASS : ADC_LOCK 5249 DISASM : adc 5250 CPL : 3 5251 CATEGORY : BINARY 5252 EXTENSION : BASE 5253 ISA_SET : I86 5254 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5255 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5256 5257 PATTERN : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5258 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5259 } 5260 { 5261 ICLASS : ADC 5262 CPL : 3 5263 CATEGORY : BINARY 5264 EXTENSION : BASE 5265 ISA_SET : I86 5266 ATTRIBUTES : BYTEOP LOCKABLE 5267 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5268 5269 PATTERN : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5270 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5271 } 5272 { 5273 ICLASS : ADC 5274 CPL : 3 5275 CATEGORY : BINARY 5276 EXTENSION : BASE 5277 ISA_SET : I86 5278 ATTRIBUTES : BYTEOP 5279 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5280 5281 PATTERN : 0x10 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5282 OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r 5283 IFORM : ADC_GPR8_GPR8_10 5284 } 5285 5286 5287 5288 { 5289 ICLASS : ADC_LOCK 5290 DISASM : adc 5291 CPL : 3 5292 CATEGORY : BINARY 5293 EXTENSION : BASE 5294 ISA_SET : I86 5295 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5296 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5297 5298 PATTERN : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5299 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5300 } 5301 { 5302 ICLASS : ADC 5303 CPL : 3 5304 CATEGORY : BINARY 5305 EXTENSION : BASE 5306 ISA_SET : I86 5307 ATTRIBUTES : LOCKABLE 5308 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5309 5310 PATTERN : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5311 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5312 } 5313 { 5314 ICLASS : ADC 5315 CPL : 3 5316 CATEGORY : BINARY 5317 EXTENSION : BASE 5318 ISA_SET : I86 5319 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5320 PATTERN : 0x11 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5321 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r 5322 IFORM : ADC_GPRv_GPRv_11 5323 } 5324 5325 5326 5327 { 5328 ICLASS : ADC 5329 CPL : 3 5330 CATEGORY : BINARY 5331 EXTENSION : BASE 5332 ISA_SET : I86 5333 ATTRIBUTES : BYTEOP 5334 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5335 5336 PATTERN : 0x12 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5337 OPERANDS : REG0=GPR8_R():rw MEM0:r:b 5338 } 5339 { 5340 ICLASS : ADC 5341 CPL : 3 5342 CATEGORY : BINARY 5343 EXTENSION : BASE 5344 ISA_SET : I86 5345 ATTRIBUTES : BYTEOP 5346 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5347 PATTERN : 0x12 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5348 OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r 5349 IFORM : ADC_GPR8_GPR8_12 5350 } 5351 5352 5353 5354 { 5355 ICLASS : ADC 5356 CPL : 3 5357 CATEGORY : BINARY 5358 EXTENSION : BASE 5359 ISA_SET : I86 5360 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5361 5362 PATTERN : 0x13 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5363 OPERANDS : REG0=GPRv_R():rw MEM0:r:v 5364 } 5365 { 5366 ICLASS : ADC 5367 CPL : 3 5368 CATEGORY : BINARY 5369 EXTENSION : BASE 5370 ISA_SET : I86 5371 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5372 PATTERN : 0x13 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5373 OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r 5374 IFORM : ADC_GPRv_GPRv_13 5375 } 5376 5377 5378 5379 5380 5381 { 5382 ICLASS : ADC 5383 CPL : 3 5384 CATEGORY : BINARY 5385 EXTENSION : BASE 5386 ISA_SET : I86 5387 ATTRIBUTES : BYTEOP 5388 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5389 PATTERN : 0x14 SIMM8() 5390 OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 5391 } 5392 { 5393 ICLASS : ADC 5394 CPL : 3 5395 CATEGORY : BINARY 5396 EXTENSION : BASE 5397 ISA_SET : I86 5398 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] 5399 PATTERN : 0x15 SIMMz() 5400 OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z 5401 } 5402 { 5403 ICLASS : PUSH 5404 CPL : 3 5405 CATEGORY : PUSH 5406 EXTENSION : BASE 5407 ISA_SET : I86 5408 PATTERN : 0x16 not64 5409 OPERANDS : REG0=XED_REG_SS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP 5410 } 5411 { 5412 ICLASS : POP 5413 CPL : 3 5414 CATEGORY : POP 5415 EXTENSION : BASE 5416 ISA_SET : I86 5417 ATTRIBUTES: NOTSX 5418 PATTERN : 0x17 not64 5419 COMMENT : Inhibits all interrupts until after next instr 5420 OPERANDS : REG0=XED_REG_SS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP 5421 } 5422 { 5423 ICLASS : SBB_LOCK 5424 DISASM : sbb 5425 CPL : 3 5426 CATEGORY : BINARY 5427 EXTENSION : BASE 5428 ISA_SET : I86 5429 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5430 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 5431 5432 PATTERN : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5433 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5434 } 5435 { 5436 ICLASS : SBB 5437 CPL : 3 5438 CATEGORY : BINARY 5439 EXTENSION : BASE 5440 ISA_SET : I86 5441 ATTRIBUTES : BYTEOP LOCKABLE 5442 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 5443 5444 PATTERN : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5445 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5446 } 5447 { 5448 ICLASS : SBB 5449 CPL : 3 5450 CATEGORY : BINARY 5451 EXTENSION : BASE 5452 ISA_SET : I86 5453 ATTRIBUTES : BYTEOP 5454 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 5455 PATTERN : 0x18 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5456 OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r 5457 IFORM : SBB_GPR8_GPR8_18 5458 } 5459 5460 5461 5462 5463 5464 5465 { 5466 ICLASS : SBB_LOCK 5467 DISASM : sbb 5468 CPL : 3 5469 CATEGORY : BINARY 5470 EXTENSION : BASE 5471 ISA_SET : I86 5472 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5473 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 5474 5475 PATTERN : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5476 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5477 } 5478 { 5479 ICLASS : SBB 5480 CPL : 3 5481 CATEGORY : BINARY 5482 EXTENSION : BASE 5483 ISA_SET : I86 5484 ATTRIBUTES : LOCKABLE 5485 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 5486 5487 PATTERN : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5488 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5489 } 5490 { 5491 ICLASS : SBB 5492 CPL : 3 5493 CATEGORY : BINARY 5494 EXTENSION : BASE 5495 ISA_SET : I86 5496 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 5497 PATTERN : 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5498 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r 5499 IFORM : SBB_GPRv_GPRv_19 5500 } 5501 5502 5503 { 5504 ICLASS : SBB 5505 CPL : 3 5506 CATEGORY : BINARY 5507 EXTENSION : BASE 5508 ISA_SET : I86 5509 ATTRIBUTES : BYTEOP 5510 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 5511 PATTERN : 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5512 OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r 5513 IFORM : SBB_GPR8_GPR8_1A 5514 5515 PATTERN : 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5516 OPERANDS : REG0=GPR8_R():rw MEM0:r:b 5517 } 5518 { 5519 ICLASS : SBB 5520 CPL : 3 5521 CATEGORY : BINARY 5522 EXTENSION : BASE 5523 ISA_SET : I86 5524 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 5525 PATTERN : 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5526 OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r 5527 IFORM : SBB_GPRv_GPRv_1B 5528 5529 PATTERN : 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5530 OPERANDS : REG0=GPRv_R():rw MEM0:r:v 5531 } 5532 { 5533 ICLASS : SBB 5534 CPL : 3 5535 CATEGORY : BINARY 5536 EXTENSION : BASE 5537 ISA_SET : I86 5538 ATTRIBUTES : BYTEOP 5539 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 5540 PATTERN : 0x1C SIMM8() 5541 OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 5542 } 5543 { 5544 ICLASS : SBB 5545 CPL : 3 5546 CATEGORY : BINARY 5547 EXTENSION : BASE 5548 ISA_SET : I86 5549 FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] 5550 PATTERN : 0x1D SIMMz() 5551 OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z 5552 } 5553 { 5554 ICLASS : PUSH 5555 CPL : 3 5556 CATEGORY : PUSH 5557 EXTENSION : BASE 5558 ISA_SET : I86 5559 PATTERN : 0x1E not64 5560 OPERANDS : REG0=XED_REG_DS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP 5561 } 5562 { 5563 ICLASS : POP 5564 CPL : 3 5565 CATEGORY : POP 5566 EXTENSION : BASE 5567 ISA_SET : I86 5568 ATTRIBUTES: NOTSX 5569 PATTERN : 0x1F not64 5570 OPERANDS : REG0=XED_REG_DS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP 5571 } 5572 5573 5574 5575 { 5576 ICLASS : AND_LOCK 5577 DISASM : and 5578 CPL : 3 5579 CATEGORY : LOGICAL 5580 EXTENSION : BASE 5581 ISA_SET : I86 5582 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5583 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5584 5585 PATTERN : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5586 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5587 } 5588 { 5589 ICLASS : AND 5590 CPL : 3 5591 CATEGORY : LOGICAL 5592 EXTENSION : BASE 5593 ISA_SET : I86 5594 ATTRIBUTES : BYTEOP LOCKABLE 5595 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5596 5597 PATTERN : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5598 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5599 } 5600 { 5601 ICLASS : AND 5602 CPL : 3 5603 CATEGORY : LOGICAL 5604 EXTENSION : BASE 5605 ISA_SET : I86 5606 ATTRIBUTES : BYTEOP 5607 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5608 5609 PATTERN : 0x20 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5610 OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r 5611 IFORM : AND_GPR8_GPR8_20 5612 } 5613 5614 5615 5616 { 5617 ICLASS : AND_LOCK 5618 DISASM : and 5619 CPL : 3 5620 CATEGORY : LOGICAL 5621 EXTENSION : BASE 5622 ISA_SET : I86 5623 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5624 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5625 5626 PATTERN : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5627 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5628 } 5629 { 5630 ICLASS : AND 5631 CPL : 3 5632 CATEGORY : LOGICAL 5633 EXTENSION : BASE 5634 ISA_SET : I86 5635 ATTRIBUTES : LOCKABLE 5636 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5637 5638 PATTERN : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5639 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5640 } 5641 { 5642 ICLASS : AND 5643 CPL : 3 5644 CATEGORY : LOGICAL 5645 EXTENSION : BASE 5646 ISA_SET : I86 5647 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5648 5649 PATTERN : 0x21 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5650 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r 5651 IFORM : AND_GPRv_GPRv_21 5652 } 5653 5654 5655 5656 { 5657 ICLASS : AND 5658 CPL : 3 5659 CATEGORY : LOGICAL 5660 EXTENSION : BASE 5661 ISA_SET : I86 5662 ATTRIBUTES : BYTEOP 5663 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5664 PATTERN : 0x22 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5665 OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r 5666 IFORM : AND_GPR8_GPR8_22 5667 5668 PATTERN : 0x22 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5669 OPERANDS : REG0=GPR8_R():rw MEM0:r:b 5670 } 5671 { 5672 ICLASS : AND 5673 CPL : 3 5674 CATEGORY : LOGICAL 5675 EXTENSION : BASE 5676 ISA_SET : I86 5677 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5678 PATTERN : 0x23 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5679 OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r 5680 IFORM : AND_GPRv_GPRv_23 5681 5682 PATTERN : 0x23 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5683 OPERANDS : REG0=GPRv_R():rw MEM0:r:v 5684 } 5685 { 5686 ICLASS : AND 5687 CPL : 3 5688 CATEGORY : LOGICAL 5689 EXTENSION : BASE 5690 ISA_SET : I86 5691 ATTRIBUTES : BYTEOP 5692 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5693 PATTERN : 0x24 SIMM8() 5694 OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 5695 } 5696 { 5697 ICLASS : AND 5698 CPL : 3 5699 CATEGORY : LOGICAL 5700 EXTENSION : BASE 5701 ISA_SET : I86 5702 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5703 PATTERN : 0x25 SIMMz() 5704 OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z 5705 } 5706 { 5707 ICLASS : DAA 5708 CPL : 3 5709 CATEGORY : DECIMAL 5710 EXTENSION : BASE 5711 ISA_SET : I86 5712 FLAGS : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ] 5713 PATTERN : 0x27 not64 5714 OPERANDS : REG0=XED_REG_AL:rw:SUPP 5715 } 5716 5717 5718 5719 { 5720 ICLASS : SUB_LOCK 5721 DISASM : sub 5722 CPL : 3 5723 CATEGORY : BINARY 5724 EXTENSION : BASE 5725 ISA_SET : I86 5726 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5727 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5728 5729 PATTERN : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5730 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5731 } 5732 { 5733 ICLASS : SUB 5734 CPL : 3 5735 CATEGORY : BINARY 5736 EXTENSION : BASE 5737 ISA_SET : I86 5738 ATTRIBUTES : BYTEOP LOCKABLE 5739 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5740 5741 PATTERN : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5742 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5743 } 5744 { 5745 ICLASS : SUB 5746 CPL : 3 5747 CATEGORY : BINARY 5748 EXTENSION : BASE 5749 ISA_SET : I86 5750 ATTRIBUTES : BYTEOP 5751 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5752 5753 PATTERN : 0x28 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5754 OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r 5755 IFORM : SUB_GPR8_GPR8_28 5756 } 5757 5758 5759 { 5760 ICLASS : SUB_LOCK 5761 DISASM : sub 5762 CPL : 3 5763 CATEGORY : BINARY 5764 EXTENSION : BASE 5765 ISA_SET : I86 5766 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5767 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5768 5769 PATTERN : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5770 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5771 } 5772 { 5773 ICLASS : SUB 5774 CPL : 3 5775 CATEGORY : BINARY 5776 EXTENSION : BASE 5777 ISA_SET : I86 5778 ATTRIBUTES : LOCKABLE 5779 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5780 5781 PATTERN : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5782 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5783 } 5784 { 5785 ICLASS : SUB 5786 CPL : 3 5787 CATEGORY : BINARY 5788 EXTENSION : BASE 5789 ISA_SET : I86 5790 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5791 5792 PATTERN : 0x29 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5793 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r 5794 IFORM : SUB_GPRv_GPRv_29 5795 } 5796 5797 5798 5799 { 5800 ICLASS : SUB 5801 CPL : 3 5802 CATEGORY : BINARY 5803 EXTENSION : BASE 5804 ISA_SET : I86 5805 ATTRIBUTES : BYTEOP 5806 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5807 PATTERN : 0x2A MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5808 OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r 5809 IFORM : SUB_GPR8_GPR8_2A 5810 PATTERN : 0x2A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5811 OPERANDS : REG0=GPR8_R():rw MEM0:r:b 5812 } 5813 { 5814 ICLASS : SUB 5815 CPL : 3 5816 CATEGORY : BINARY 5817 EXTENSION : BASE 5818 ISA_SET : I86 5819 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5820 PATTERN : 0x2B MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5821 OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r 5822 IFORM : SUB_GPRv_GPRv_2B 5823 5824 PATTERN : 0x2B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5825 OPERANDS : REG0=GPRv_R():rw MEM0:r:v 5826 } 5827 { 5828 ICLASS : SUB 5829 CPL : 3 5830 CATEGORY : BINARY 5831 EXTENSION : BASE 5832 ISA_SET : I86 5833 ATTRIBUTES : BYTEOP 5834 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5835 PATTERN : 0x2C SIMM8() 5836 OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 5837 } 5838 { 5839 ICLASS : SUB 5840 CPL : 3 5841 CATEGORY : BINARY 5842 EXTENSION : BASE 5843 ISA_SET : I86 5844 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 5845 PATTERN : 0x2D SIMMz() 5846 OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z 5847 } 5848 { 5849 ICLASS : DAS 5850 CPL : 3 5851 CATEGORY : DECIMAL 5852 EXTENSION : BASE 5853 ISA_SET : I86 5854 FLAGS : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ] 5855 PATTERN : 0x2F not64 5856 OPERANDS : REG0=XED_REG_AL:rw:SUPP 5857 } 5858 5859 { 5860 ICLASS : XOR_LOCK 5861 DISASM : xor 5862 CPL : 3 5863 CATEGORY : LOGICAL 5864 EXTENSION : BASE 5865 ISA_SET : I86 5866 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5867 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5868 5869 PATTERN : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5870 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5871 } 5872 { 5873 ICLASS : XOR 5874 CPL : 3 5875 CATEGORY : LOGICAL 5876 EXTENSION : BASE 5877 ISA_SET : I86 5878 ATTRIBUTES : BYTEOP LOCKABLE 5879 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5880 5881 PATTERN : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5882 OPERANDS : MEM0:rw:b REG0=GPR8_R():r 5883 } 5884 { 5885 ICLASS : XOR 5886 CPL : 3 5887 CATEGORY : LOGICAL 5888 EXTENSION : BASE 5889 ISA_SET : I86 5890 ATTRIBUTES : BYTEOP 5891 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5892 5893 PATTERN : 0x30 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5894 OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r 5895 IFORM : XOR_GPR8_GPR8_30 5896 } 5897 5898 5899 5900 5901 5902 { 5903 ICLASS : XOR_LOCK 5904 DISASM : xor 5905 CPL : 3 5906 CATEGORY : LOGICAL 5907 EXTENSION : BASE 5908 ISA_SET : I86 5909 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 5910 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5911 5912 PATTERN : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 5913 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5914 } 5915 { 5916 ICLASS : XOR 5917 CPL : 3 5918 CATEGORY : LOGICAL 5919 EXTENSION : BASE 5920 ISA_SET : I86 5921 ATTRIBUTES : LOCKABLE 5922 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5923 5924 PATTERN : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 5925 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 5926 } 5927 { 5928 ICLASS : XOR 5929 CPL : 3 5930 CATEGORY : LOGICAL 5931 EXTENSION : BASE 5932 ISA_SET : I86 5933 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5934 5935 PATTERN : 0x31 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5936 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r 5937 IFORM : XOR_GPRv_GPRv_31 5938 } 5939 5940 5941 5942 { 5943 ICLASS : XOR 5944 CPL : 3 5945 CATEGORY : LOGICAL 5946 EXTENSION : BASE 5947 ISA_SET : I86 5948 ATTRIBUTES : BYTEOP 5949 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5950 PATTERN : 0x32 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5951 OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r 5952 IFORM : XOR_GPR8_GPR8_32 5953 5954 PATTERN : 0x32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5955 OPERANDS : REG0=GPR8_R():rw MEM0:r:b 5956 } 5957 { 5958 ICLASS : XOR 5959 CPL : 3 5960 CATEGORY : LOGICAL 5961 EXTENSION : BASE 5962 ISA_SET : I86 5963 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5964 PATTERN : 0x33 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5965 OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r 5966 IFORM : XOR_GPRv_GPRv_33 5967 5968 PATTERN : 0x33 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5969 OPERANDS : REG0=GPRv_R():rw MEM0:r:v 5970 } 5971 { 5972 ICLASS : XOR 5973 CPL : 3 5974 CATEGORY : LOGICAL 5975 EXTENSION : BASE 5976 ISA_SET : I86 5977 ATTRIBUTES : BYTEOP 5978 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5979 PATTERN : 0x34 UIMM8() 5980 OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b 5981 } 5982 { 5983 ICLASS : XOR 5984 CPL : 3 5985 CATEGORY : LOGICAL 5986 EXTENSION : BASE 5987 ISA_SET : I86 5988 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 5989 PATTERN : 0x35 SIMMz() 5990 OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z 5991 } 5992 { 5993 ICLASS : AAA 5994 CPL : 3 5995 CATEGORY : DECIMAL 5996 EXTENSION : BASE 5997 ISA_SET : I86 5998 FLAGS : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ] 5999 PATTERN : 0x37 not64 6000 OPERANDS : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP 6001 } 6002 { 6003 ICLASS : CMP 6004 CPL : 3 6005 CATEGORY : BINARY 6006 EXTENSION : BASE 6007 ISA_SET : I86 6008 ATTRIBUTES : BYTEOP 6009 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 6010 PATTERN : 0x38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6011 OPERANDS : MEM0:r:b REG0=GPR8_R():r 6012 6013 PATTERN : 0x38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6014 OPERANDS : REG0=GPR8_B():r REG1=GPR8_R():r 6015 IFORM : CMP_GPR8_GPR8_38 6016 } 6017 { 6018 ICLASS : CMP 6019 CPL : 3 6020 CATEGORY : BINARY 6021 EXTENSION : BASE 6022 ISA_SET : I86 6023 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 6024 PATTERN : 0x39 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6025 OPERANDS : MEM0:r:v REG0=GPRv_R():r 6026 PATTERN : 0x39 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6027 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 6028 IFORM : CMP_GPRv_GPRv_39 6029 } 6030 { 6031 ICLASS : CMP 6032 CPL : 3 6033 CATEGORY : BINARY 6034 EXTENSION : BASE 6035 ISA_SET : I86 6036 ATTRIBUTES : BYTEOP 6037 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 6038 PATTERN : 0x3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6039 OPERANDS : REG0=GPR8_R():r MEM0:r:b 6040 PATTERN : 0x3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6041 OPERANDS : REG0=GPR8_R():r REG1=GPR8_B():r 6042 IFORM : CMP_GPR8_GPR8_3A 6043 } 6044 { 6045 ICLASS : CMP 6046 CPL : 3 6047 CATEGORY : BINARY 6048 EXTENSION : BASE 6049 ISA_SET : I86 6050 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 6051 PATTERN : 0x3B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6052 OPERANDS : REG0=GPRv_R():r MEM0:r:v 6053 PATTERN : 0x3B MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6054 OPERANDS : REG0=GPRv_R():r REG1=GPRv_B():r 6055 IFORM : CMP_GPRv_GPRv_3B 6056 } 6057 { 6058 ICLASS : CMP 6059 CPL : 3 6060 CATEGORY : BINARY 6061 EXTENSION : BASE 6062 ISA_SET : I86 6063 ATTRIBUTES : BYTEOP 6064 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 6065 PATTERN : 0x3C SIMM8() 6066 OPERANDS : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8 6067 } 6068 { 6069 ICLASS : CMP 6070 CPL : 3 6071 CATEGORY : BINARY 6072 EXTENSION : BASE 6073 ISA_SET : I86 6074 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 6075 PATTERN : 0x3D SIMMz() 6076 OPERANDS : REG0=OrAX():r:IMPL IMM0:r:z 6077 } 6078 { 6079 ICLASS : AAS 6080 CPL : 3 6081 CATEGORY : DECIMAL 6082 EXTENSION : BASE 6083 ISA_SET : I86 6084 FLAGS : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ] 6085 PATTERN : 0x3F not64 6086 OPERANDS : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP 6087 } 6088 { 6089 ICLASS : INC 6090 CPL : 3 6091 CATEGORY : BINARY 6092 EXTENSION : BASE 6093 ISA_SET : I86 6094 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 6095 PATTERN : 0b0100_0 SRM[rrr] not64 6096 OPERANDS : REG0=GPRv_SB():rw 6097 IFORM : INC_GPRv_40 6098 } 6099 { 6100 ICLASS : DEC 6101 CPL : 3 6102 CATEGORY : BINARY 6103 EXTENSION : BASE 6104 ISA_SET : I86 6105 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] 6106 PATTERN : 0b0100_1 SRM[rrr] not64 6107 OPERANDS : REG0=GPRv_SB():rw 6108 IFORM : DEC_GPRv_48 6109 } 6110 { 6111 ICLASS : PUSH 6112 CPL : 3 6113 CATEGORY : PUSH 6114 EXTENSION : BASE 6115 ISA_SET : I86 6116 PATTERN : 0b0101_0 SRM[rrr] DF64() 6117 OPERANDS : REG0=GPRv_SB():r REG1=XED_REG_STACKPUSH:w:spw:SUPP 6118 IFORM : PUSH_GPRv_50 6119 } 6120 { 6121 ICLASS : POP 6122 CPL : 3 6123 CATEGORY : POP 6124 EXTENSION : BASE 6125 ISA_SET : I86 6126 PATTERN : 0b0101_1 SRM[rrr] DF64() 6127 OPERANDS : REG0=GPRv_SB():w REG1=XED_REG_STACKPOP:r:spw:SUPP 6128 IFORM : POP_GPRv_51 6129 } 6130 { 6131 ICLASS : PUSHA 6132 CPL : 3 6133 CATEGORY : PUSH 6134 EXTENSION : BASE 6135 ISA_SET : I186 6136 PATTERN : 0x60 EOSZ=1 not64 6137 OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_AX:r:SUPP REG2=XED_REG_CX:r:SUPP REG3=XED_REG_DX:r:SUPP REG4=XED_REG_BX:r:SUPP REG5=XED_REG_SP:r:SUPP REG6=XED_REG_BP:r:SUPP REG7=XED_REG_SI:r:SUPP REG8=XED_REG_DI:r:SUPP 6138 } 6139 { 6140 ICLASS : PUSHAD 6141 CPL : 3 6142 CATEGORY : PUSH 6143 EXTENSION : BASE 6144 ISA_SET : I386 6145 PATTERN : 0x60 EOSZ=2 not64 6146 OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_EBX:r:SUPP REG5=XED_REG_ESP:r:SUPP REG6=XED_REG_EBP:r:SUPP REG7=XED_REG_ESI:r:SUPP REG8=XED_REG_EDI:r:SUPP 6147 } 6148 { 6149 ICLASS : POPA 6150 CPL : 3 6151 CATEGORY : POP 6152 EXTENSION : BASE 6153 ISA_SET : I186 6154 PATTERN : 0x61 EOSZ=1 not64 6155 OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_AX:w:SUPP REG2=XED_REG_CX:w:SUPP REG3=XED_REG_DX:w:SUPP REG4=XED_REG_BX:w:SUPP REG5=XED_REG_BP:w:SUPP REG6=XED_REG_SI:w:SUPP REG7=XED_REG_DI:w:SUPP 6156 COMMENT : eSP value on the stack is ignored! 2008-08-14 6157 } 6158 { 6159 ICLASS : POPAD 6160 CPL : 3 6161 CATEGORY : POP 6162 EXTENSION : BASE 6163 ISA_SET : I386 6164 PATTERN : 0x61 EOSZ=2 not64 6165 OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_EDX:w:SUPP REG4=XED_REG_EBX:w:SUPP REG5=XED_REG_EBP:w:SUPP REG6=XED_REG_ESI:w:SUPP REG7=XED_REG_EDI:w:SUPP 6166 COMMENT : eSP value on the stack is ignored! 2008-08-14 6167 } 6168 { 6169 ICLASS : BOUND 6170 CPL : 3 6171 CATEGORY : INTERRUPT 6172 EXTENSION : BASE 6173 ATTRIBUTES: EXCEPTION_BR 6174 ISA_SET : I186 6175 PATTERN : 0x62 mode16 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6176 OPERANDS : REG0=GPRv_R():r MEM0:r:a16 6177 PATTERN : 0x62 mode32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6178 OPERANDS : REG0=GPRv_R():r MEM0:r:a32 6179 } 6180 { 6181 ICLASS : ARPL 6182 CPL : 3 6183 CATEGORY : SYSTEM 6184 EXTENSION : BASE 6185 ISA_SET : I286PROTECTED 6186 ATTRIBUTES: PROTECTED_MODE 6187 FLAGS : MUST [ zf-mod ] 6188 PATTERN : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() 6189 OPERANDS : MEM0:rw:w REG0=GPR16_R():r 6190 } 6191 { 6192 ICLASS : ARPL 6193 CPL : 3 6194 CATEGORY : SYSTEM 6195 EXTENSION : BASE 6196 ISA_SET : I286PROTECTED 6197 ATTRIBUTES: PROTECTED_MODE 6198 FLAGS : MUST [ zf-mod ] 6199 PATTERN : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 6200 OPERANDS : REG0=GPR16_B():rw REG1=GPR16_R():r 6201 } 6202 { 6203 ICLASS : MOVSXD 6204 CPL : 3 6205 CATEGORY : DATAXFER 6206 EXTENSION : LONGMODE 6207 PATTERN : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() 6208 OPERANDS : REG0=GPRv_R():w MEM0:r:d 6209 } 6210 { 6211 ICLASS : MOVSXD 6212 CPL : 3 6213 CATEGORY : DATAXFER 6214 EXTENSION : LONGMODE 6215 PATTERN : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 6216 OPERANDS : REG0=GPRv_R():w REG1=GPR32_B():r 6217 } 6218 { 6219 ICLASS : PUSH 6220 CPL : 3 6221 CATEGORY : PUSH 6222 EXTENSION : BASE 6223 ISA_SET : I186 6224 PATTERN : 0x68 DF64() SIMMz() 6225 OPERANDS : IMM0:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP 6226 } 6227 { 6228 ICLASS : IMUL 6229 CPL : 3 6230 CATEGORY : BINARY 6231 EXTENSION : BASE 6232 ISA_SET : I186 6233 FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] 6234 PATTERN : 0x69 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMMz() 6235 OPERANDS : REG0=GPRv_R():w MEM0:r:v IMM0:r:z 6236 6237 PATTERN : 0x69 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMMz() 6238 OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:z 6239 } 6240 { 6241 ICLASS : PUSH 6242 CPL : 3 6243 CATEGORY : PUSH 6244 EXTENSION : BASE 6245 ISA_SET : I186 6246 PATTERN : 0x6A DF64() SIMM8() 6247 OPERANDS : IMM0:r:b:i8 REG0=XED_REG_STACKPUSH:w:spw:SUPP 6248 } 6249 { 6250 ICLASS : IMUL 6251 CPL : 3 6252 CATEGORY : BINARY 6253 EXTENSION : BASE 6254 ISA_SET : I186 6255 FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] 6256 PATTERN : 0x6B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMM8() 6257 OPERANDS : REG0=GPRv_R():w MEM0:r:v IMM0:r:b:i8 6258 6259 PATTERN : 0x6B MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMM8() 6260 OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:b:i8 6261 } 6262 6263 6264 { 6265 ICLASS : REP_INSB 6266 DISASM : insb 6267 CPL : 3 6268 CATEGORY : IOSTRINGOP 6269 EXTENSION : BASE 6270 ISA_SET : I186 6271 ATTRIBUTES :REP fixed_base0 NOTSX BYTEOP 6272 FLAGS : READONLY [ iopl-tst df-tst ] 6273 PATTERN : 0x6C repe 6274 OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 6275 PATTERN : 0x6C repne 6276 OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 6277 } 6278 6279 { 6280 ICLASS : INSB 6281 CPL : 3 6282 CATEGORY : IOSTRINGOP 6283 EXTENSION : BASE 6284 ISA_SET : I186 6285 ATTRIBUTES : fixed_base0 NOTSX BYTEOP 6286 FLAGS : READONLY [ iopl-tst df-tst ] 6287 PATTERN : 0x6C norep 6288 OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP 6289 } 6290 6291 6292 { 6293 ICLASS : REP_INSW 6294 DISASM : insw 6295 CPL : 3 6296 CATEGORY : IOSTRINGOP 6297 EXTENSION : BASE 6298 ISA_SET : I186 6299 ATTRIBUTES : REP fixed_base0 NOTSX 6300 FLAGS : READONLY [ iopl-tst df-tst ] 6301 PATTERN : 0x6D EOSZ=1 repe 6302 OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 6303 PATTERN : 0x6D EOSZ=1 repne 6304 OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 6305 } 6306 { 6307 ICLASS : INSW 6308 DISASM : insw 6309 CPL : 3 6310 CATEGORY : IOSTRINGOP 6311 EXTENSION : BASE 6312 ISA_SET : I186 6313 ATTRIBUTES : fixed_base0 NOTSX 6314 FLAGS : READONLY [ iopl-tst df-tst ] 6315 PATTERN : 0x6D EOSZ=1 norep 6316 OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP 6317 } 6318 6319 6320 { 6321 ICLASS : REP_INSD 6322 DISASM : insd 6323 CPL : 3 6324 CATEGORY : IOSTRINGOP 6325 EXTENSION : BASE 6326 ISA_SET : I386 6327 ATTRIBUTES :REP fixed_base0 NOTSX 6328 FLAGS : READONLY [ iopl-tst df-tst ] 6329 PATTERN : 0x6D EOSZ=2 repe 6330 OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 6331 6332 PATTERN : 0x6D EOSZ=3 repe 6333 OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 6334 6335 PATTERN : 0x6D EOSZ=2 repne 6336 OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 6337 6338 PATTERN : 0x6D EOSZ=3 repne 6339 OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP 6340 } 6341 6342 { 6343 ICLASS : INSD 6344 CPL : 3 6345 CATEGORY : IOSTRINGOP 6346 EXTENSION : BASE 6347 ISA_SET : I386 6348 ATTRIBUTES : fixed_base0 NOTSX 6349 FLAGS : READONLY [ iopl-tst df-tst ] 6350 PATTERN : 0x6D EOSZ=2 norep 6351 OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP 6352 6353 PATTERN : 0x6D EOSZ=3 norep 6354 OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP 6355 } 6356 6357 6358 { 6359 ICLASS : REP_OUTSB 6360 DISASM : outsb 6361 CPL : 3 6362 CATEGORY : IOSTRINGOP 6363 EXTENSION : BASE 6364 ISA_SET : I186 6365 ATTRIBUTES :REP fixed_base0 NOTSX BYTEOP 6366 FLAGS : READONLY [ iopl-tst df-tst ] 6367 PATTERN : 0x6E repe OVERRIDE_SEG0() 6368 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 6369 PATTERN : 0x6E repne OVERRIDE_SEG0() 6370 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 6371 } 6372 6373 { 6374 ICLASS : OUTSB 6375 CPL : 3 6376 CATEGORY : IOSTRINGOP 6377 EXTENSION : BASE 6378 ISA_SET : I186 6379 ATTRIBUTES : fixed_base0 NOTSX BYTEOP 6380 FLAGS : READONLY [ iopl-tst df-tst ] 6381 6382 PATTERN : 0x6E norep OVERRIDE_SEG0() 6383 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP 6384 } 6385 6386 6387 { 6388 ICLASS : REP_OUTSW 6389 DISASM : outsw 6390 CPL : 3 6391 CATEGORY : IOSTRINGOP 6392 EXTENSION : BASE 6393 ISA_SET : I186 6394 ATTRIBUTES :REP fixed_base0 NOTSX 6395 FLAGS : READONLY [ iopl-tst df-tst ] 6396 PATTERN : 0x6F EOSZ=1 repe OVERRIDE_SEG0() 6397 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 6398 PATTERN : 0x6F EOSZ=1 repne OVERRIDE_SEG0() 6399 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 6400 } 6401 6402 { 6403 ICLASS : OUTSW 6404 CPL : 3 6405 CATEGORY : IOSTRINGOP 6406 EXTENSION : BASE 6407 ISA_SET : I186 6408 ATTRIBUTES : fixed_base0 NOTSX 6409 FLAGS : READONLY [ iopl-tst df-tst ] 6410 PATTERN : 0x6F EOSZ=1 norep OVERRIDE_SEG0() 6411 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP 6412 } 6413 6414 6415 { 6416 ICLASS : REP_OUTSD 6417 DISASM : outsd 6418 CPL : 3 6419 CATEGORY : IOSTRINGOP 6420 EXTENSION : BASE 6421 ISA_SET : I386 6422 ATTRIBUTES :REP fixed_base0 NOTSX 6423 FLAGS : READONLY [ iopl-tst df-tst ] 6424 6425 PATTERN : 0x6F EOSZ=2 repe OVERRIDE_SEG0() 6426 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 6427 6428 PATTERN : 0x6F EOSZ=3 repe OVERRIDE_SEG0() 6429 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 6430 6431 PATTERN : 0x6F EOSZ=2 repne OVERRIDE_SEG0() 6432 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 6433 6434 PATTERN : 0x6F EOSZ=3 repne OVERRIDE_SEG0() 6435 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 6436 } 6437 { 6438 ICLASS : OUTSD 6439 CPL : 3 6440 CATEGORY : IOSTRINGOP 6441 EXTENSION : BASE 6442 ISA_SET : I386 6443 ATTRIBUTES : fixed_base0 NOTSX 6444 FLAGS : READONLY [ iopl-tst df-tst ] 6445 6446 PATTERN : 0x6F EOSZ=2 norep OVERRIDE_SEG0() 6447 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP 6448 6449 PATTERN : 0x6F EOSZ=3 norep OVERRIDE_SEG0() 6450 OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP 6451 } 6452 6453 6454 { 6455 ICLASS : JO 6456 CPL : 3 6457 CATEGORY : COND_BR 6458 EXTENSION : BASE 6459 ISA_SET : I86 6460 FLAGS : READONLY [ of-tst ] 6461 ATTRIBUTES: MPX_PREFIX_ABLE 6462 PATTERN : 0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8() 6463 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6464 PATTERN : 0x70 not64 BRANCH_HINT() BRDISP8() 6465 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6466 } 6467 { 6468 ICLASS : JNO 6469 CPL : 3 6470 CATEGORY : COND_BR 6471 EXTENSION : BASE 6472 ISA_SET : I86 6473 FLAGS : READONLY [ of-tst ] 6474 ATTRIBUTES: MPX_PREFIX_ABLE 6475 PATTERN : 0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8() 6476 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6477 PATTERN : 0x71 not64 BRANCH_HINT() BRDISP8() 6478 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6479 } 6480 { 6481 ICLASS : JB 6482 CPL : 3 6483 CATEGORY : COND_BR 6484 EXTENSION : BASE 6485 ISA_SET : I86 6486 FLAGS : READONLY [ cf-tst ] 6487 ATTRIBUTES: MPX_PREFIX_ABLE 6488 PATTERN : 0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8() 6489 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6490 PATTERN : 0x72 not64 BRANCH_HINT() BRDISP8() 6491 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6492 } 6493 { 6494 ICLASS : JNB 6495 CPL : 3 6496 CATEGORY : COND_BR 6497 EXTENSION : BASE 6498 ISA_SET : I86 6499 FLAGS : READONLY [ cf-tst ] 6500 ATTRIBUTES: MPX_PREFIX_ABLE 6501 PATTERN : 0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8() 6502 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6503 PATTERN : 0x73 not64 BRANCH_HINT() BRDISP8() 6504 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6505 } 6506 { 6507 ICLASS : JZ 6508 CPL : 3 6509 CATEGORY : COND_BR 6510 EXTENSION : BASE 6511 ISA_SET : I86 6512 FLAGS : READONLY [ zf-tst ] 6513 ATTRIBUTES: MPX_PREFIX_ABLE 6514 PATTERN : 0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8() 6515 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6516 PATTERN : 0x74 not64 BRANCH_HINT() BRDISP8() 6517 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6518 } 6519 { 6520 ICLASS : JNZ 6521 CPL : 3 6522 CATEGORY : COND_BR 6523 EXTENSION : BASE 6524 ISA_SET : I86 6525 FLAGS : READONLY [ zf-tst ] 6526 ATTRIBUTES: MPX_PREFIX_ABLE 6527 PATTERN : 0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8() 6528 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6529 PATTERN : 0x75 not64 BRANCH_HINT() BRDISP8() 6530 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6531 } 6532 { 6533 ICLASS : JBE 6534 CPL : 3 6535 CATEGORY : COND_BR 6536 EXTENSION : BASE 6537 ISA_SET : I86 6538 FLAGS : READONLY [ cf-tst zf-tst ] 6539 ATTRIBUTES: MPX_PREFIX_ABLE 6540 PATTERN : 0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8() 6541 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6542 PATTERN : 0x76 not64 BRANCH_HINT() BRDISP8() 6543 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6544 } 6545 { 6546 ICLASS : JNBE 6547 CPL : 3 6548 CATEGORY : COND_BR 6549 EXTENSION : BASE 6550 ISA_SET : I86 6551 FLAGS : READONLY [ cf-tst zf-tst ] 6552 ATTRIBUTES: MPX_PREFIX_ABLE 6553 PATTERN : 0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8() 6554 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6555 PATTERN : 0x77 not64 BRANCH_HINT() BRDISP8() 6556 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6557 } 6558 { 6559 ICLASS : JS 6560 CPL : 3 6561 CATEGORY : COND_BR 6562 EXTENSION : BASE 6563 ISA_SET : I86 6564 FLAGS : READONLY [ sf-tst ] 6565 ATTRIBUTES: MPX_PREFIX_ABLE 6566 PATTERN : 0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8() 6567 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6568 PATTERN : 0x78 not64 BRANCH_HINT() BRDISP8() 6569 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6570 } 6571 { 6572 ICLASS : JNS 6573 CPL : 3 6574 CATEGORY : COND_BR 6575 EXTENSION : BASE 6576 ISA_SET : I86 6577 FLAGS : READONLY [ sf-tst ] 6578 ATTRIBUTES: MPX_PREFIX_ABLE 6579 PATTERN : 0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8() 6580 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6581 PATTERN : 0x79 not64 BRANCH_HINT() BRDISP8() 6582 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6583 } 6584 { 6585 ICLASS : JP 6586 CPL : 3 6587 CATEGORY : COND_BR 6588 EXTENSION : BASE 6589 ISA_SET : I86 6590 FLAGS : READONLY [ pf-tst ] 6591 ATTRIBUTES: MPX_PREFIX_ABLE 6592 PATTERN : 0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8() 6593 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6594 PATTERN : 0x7A not64 BRANCH_HINT() BRDISP8() 6595 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6596 } 6597 { 6598 ICLASS : JNP 6599 CPL : 3 6600 CATEGORY : COND_BR 6601 EXTENSION : BASE 6602 ISA_SET : I86 6603 FLAGS : READONLY [ pf-tst ] 6604 ATTRIBUTES: MPX_PREFIX_ABLE 6605 PATTERN : 0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8() 6606 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6607 PATTERN : 0x7B not64 BRANCH_HINT() BRDISP8() 6608 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6609 } 6610 { 6611 ICLASS : JL 6612 CPL : 3 6613 CATEGORY : COND_BR 6614 EXTENSION : BASE 6615 ISA_SET : I86 6616 FLAGS : READONLY [ sf-tst of-tst ] 6617 ATTRIBUTES: MPX_PREFIX_ABLE 6618 PATTERN : 0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8() 6619 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6620 PATTERN : 0x7C not64 BRANCH_HINT() BRDISP8() 6621 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6622 } 6623 { 6624 ICLASS : JNL 6625 CPL : 3 6626 CATEGORY : COND_BR 6627 EXTENSION : BASE 6628 ISA_SET : I86 6629 FLAGS : READONLY [ sf-tst of-tst ] 6630 ATTRIBUTES: MPX_PREFIX_ABLE 6631 PATTERN : 0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8() 6632 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6633 PATTERN : 0x7D not64 BRANCH_HINT() BRDISP8() 6634 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6635 } 6636 { 6637 ICLASS : JLE 6638 CPL : 3 6639 CATEGORY : COND_BR 6640 EXTENSION : BASE 6641 ISA_SET : I86 6642 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 6643 ATTRIBUTES: MPX_PREFIX_ABLE 6644 PATTERN : 0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8() 6645 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6646 PATTERN : 0x7E not64 BRANCH_HINT() BRDISP8() 6647 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6648 } 6649 { 6650 ICLASS : JNLE 6651 CPL : 3 6652 CATEGORY : COND_BR 6653 EXTENSION : BASE 6654 ISA_SET : I86 6655 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 6656 ATTRIBUTES: MPX_PREFIX_ABLE 6657 PATTERN : 0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8() 6658 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6659 PATTERN : 0x7F not64 BRANCH_HINT() BRDISP8() 6660 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 6661 } 6662 { 6663 ICLASS : TEST 6664 CPL : 3 6665 CATEGORY : LOGICAL 6666 EXTENSION : BASE 6667 ISA_SET : I86 6668 ATTRIBUTES : BYTEOP 6669 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 6670 PATTERN : 0x84 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6671 OPERANDS : MEM0:r:b REG0=GPR8_R():r 6672 } 6673 { 6674 ICLASS : TEST 6675 CPL : 3 6676 CATEGORY : LOGICAL 6677 EXTENSION : BASE 6678 ISA_SET : I86 6679 ATTRIBUTES : BYTEOP 6680 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 6681 PATTERN : 0x84 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6682 OPERANDS : REG0=GPR8_B():r REG1=GPR8_R():r 6683 } 6684 { 6685 ICLASS : TEST 6686 CPL : 3 6687 CATEGORY : LOGICAL 6688 EXTENSION : BASE 6689 ISA_SET : I86 6690 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 6691 PATTERN : 0x85 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6692 OPERANDS : MEM0:r:v REG0=GPRv_R():r 6693 } 6694 { 6695 ICLASS : TEST 6696 CPL : 3 6697 CATEGORY : LOGICAL 6698 EXTENSION : BASE 6699 ISA_SET : I86 6700 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 6701 PATTERN : 0x85 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6702 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 6703 } 6704 { 6705 ICLASS : XCHG 6706 CPL : 3 6707 CATEGORY : DATAXFER 6708 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 6709 EXTENSION : BASE 6710 ISA_SET : I86 6711 PATTERN : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 6712 OPERANDS : MEM0:rw:b REG0=GPR8_R():rw 6713 PATTERN : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 6714 OPERANDS : MEM0:rw:b REG0=GPR8_R():rw 6715 } 6716 { 6717 ICLASS : XCHG 6718 CPL : 3 6719 CATEGORY : DATAXFER 6720 ATTRIBUTES : BYTEOP 6721 EXTENSION : BASE 6722 ISA_SET : I86 6723 PATTERN : 0x86 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6724 OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():rw 6725 } 6726 6727 6728 { 6729 ICLASS : XCHG 6730 CPL : 3 6731 CATEGORY : DATAXFER 6732 EXTENSION : BASE 6733 ISA_SET : I86 6734 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 6735 PATTERN : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 6736 OPERANDS : MEM0:rw:v REG0=GPRv_R():rw 6737 PATTERN : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 6738 OPERANDS : MEM0:rw:v REG0=GPRv_R():rw 6739 } 6740 { 6741 ICLASS : XCHG 6742 CPL : 3 6743 CATEGORY : DATAXFER 6744 EXTENSION : BASE 6745 ISA_SET : I86 6746 PATTERN : 0x87 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6747 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():rw 6748 } 6749 6750 6751 { 6752 ICLASS : MOV 6753 CPL : 3 6754 CATEGORY : DATAXFER 6755 ATTRIBUTES : BYTEOP 6756 EXTENSION : BASE 6757 ISA_SET : I86 6758 6759 PATTERN : 0x88 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6760 OPERANDS : REG0=GPR8_B():w REG1=GPR8_R():r 6761 IFORM : MOV_GPR8_GPR8_88 6762 } 6763 { 6764 ICLASS : MOV 6765 CPL : 3 6766 CATEGORY : DATAXFER 6767 ATTRIBUTES : BYTEOP HLE_REL_ABLE 6768 EXTENSION : BASE 6769 ISA_SET : I86 6770 PATTERN : 0x88 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6771 OPERANDS : MEM0:w:b REG0=GPR8_R():r 6772 } 6773 { 6774 ICLASS : MOV 6775 CPL : 3 6776 CATEGORY : DATAXFER 6777 EXTENSION : BASE 6778 ISA_SET : I86 6779 ATTRIBUTES : HLE_REL_ABLE 6780 PATTERN : 0x89 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6781 OPERANDS : MEM0:w:v REG0=GPRv_R():r 6782 } 6783 { 6784 ICLASS : MOV 6785 CPL : 3 6786 CATEGORY : DATAXFER 6787 EXTENSION : BASE 6788 ISA_SET : I86 6789 PATTERN : 0x89 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6790 OPERANDS : REG0=GPRv_B():w REG1=GPRv_R():r 6791 IFORM : MOV_GPRv_GPRv_89 6792 } 6793 { 6794 ICLASS : MOV 6795 CPL : 3 6796 CATEGORY : DATAXFER 6797 ATTRIBUTES : BYTEOP 6798 EXTENSION : BASE 6799 ISA_SET : I86 6800 PATTERN : 0x8A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6801 OPERANDS : REG0=GPR8_R():w MEM0:r:b 6802 6803 PATTERN : 0x8A MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6804 OPERANDS : REG0=GPR8_R():w REG1=GPR8_B():r 6805 IFORM : MOV_GPR8_GPR8_8A 6806 } 6807 { 6808 ICLASS : MOV 6809 CPL : 3 6810 CATEGORY : DATAXFER 6811 EXTENSION : BASE 6812 ISA_SET : I86 6813 PATTERN : 0x8B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6814 OPERANDS : REG0=GPRv_R():w MEM0:r:v 6815 } 6816 { 6817 ICLASS : MOV 6818 CPL : 3 6819 CATEGORY : DATAXFER 6820 EXTENSION : BASE 6821 ISA_SET : I86 6822 PATTERN : 0x8B MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6823 OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r 6824 IFORM : MOV_GPRv_GPRv_8B 6825 } 6826 { 6827 ICLASS : MOV 6828 CPL : 3 6829 CATEGORY : DATAXFER 6830 EXTENSION : BASE 6831 ISA_SET : I86 6832 PATTERN : 0x8C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6833 OPERANDS : MEM0:w:w REG0=SEG():r 6834 } 6835 { 6836 ICLASS : MOV 6837 CPL : 3 6838 CATEGORY : DATAXFER 6839 EXTENSION : BASE 6840 ISA_SET : I86 6841 PATTERN : 0x8C MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6842 OPERANDS : REG0=GPRv_B():w REG1=SEG():r 6843 } 6844 { 6845 ICLASS : LEA 6846 CPL : 3 6847 CATEGORY : MISC 6848 EXTENSION : BASE 6849 ISA_SET : I86 6850 PATTERN : 0x8D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() REMOVE_SEGMENT() 6851 OPERANDS : REG0=GPRv_R():w AGEN:r 6852 } 6853 { 6854 ICLASS : MOV 6855 CPL : 3 6856 CATEGORY : DATAXFER 6857 EXTENSION : BASE 6858 ISA_SET : I86 6859 ATTRIBUTES: NOTSX 6860 COMMENT : MOV to SS Inhibits all interrupts until after next instr 6861 PATTERN : 0x8E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6862 OPERANDS : REG0=SEG():w MEM0:r:w 6863 } 6864 { 6865 ICLASS : MOV 6866 CPL : 3 6867 CATEGORY : DATAXFER 6868 EXTENSION : BASE 6869 ISA_SET : I86 6870 ATTRIBUTES: NOTSX 6871 PATTERN : 0x8E MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6872 OPERANDS : REG0=SEG():w REG1=GPR16_B():r 6873 } 6874 6875 6876 6877 { 6878 ICLASS : NOP 6879 UNAME : NOP90 6880 CPL : 3 6881 CATEGORY : NOP 6882 EXTENSION : BASE 6883 ATTRIBUTES: NOP 6884 ISA_SET : I86 6885 PATTERN : 0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix 6886 OPERANDS : 6887 IFORM : NOP_90 6888 } 6889 { 6890 ICLASS : PAUSE 6891 ATTRIBUTES: NOTSX 6892 CPL : 3 6893 CATEGORY : MISC 6894 EXTENSION : PAUSE 6895 ISA_SET : PAUSE 6896 PATTERN : 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=1 6897 OPERANDS : 6898 COMMENT : 2008-06-11 Ignores REX completely. Introduced on PENTIUM4 6899 } 6900 { 6901 ICLASS : NOP 6902 CPL : 3 6903 CATEGORY : NOP 6904 EXTENSION : BASE 6905 ATTRIBUTES: NOP 6906 ISA_SET : I86 6907 PATTERN : 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=0 6908 OPERANDS : 6909 IFORM : NOP_90 6910 COMMENT : This is the encoding of PAUSE on pre-P4 systems 6911 6912 } 6913 6914 { 6915 ICLASS : XCHG 6916 CPL : 3 6917 CATEGORY : DATAXFER 6918 EXTENSION : BASE 6919 ISA_SET : I86 6920 6921 PATTERN : 0b1001_0 SRM[rrr] SRM!=0 6922 OPERANDS : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL 6923 6924 PATTERN : 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix 6925 OPERANDS : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL 6926 } 6927 { 6928 ICLASS : CBW 6929 CPL : 3 6930 CATEGORY : CONVERT 6931 EXTENSION : BASE 6932 ISA_SET : I86 6933 PATTERN : 0x98 EOSZ=1 6934 OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP 6935 } 6936 { 6937 ICLASS : CDQE 6938 CPL : 3 6939 CATEGORY : CONVERT 6940 EXTENSION : LONGMODE 6941 PATTERN : 0x98 EOSZ=3 mode64 rexw_prefix 6942 OPERANDS : REG0=XED_REG_RAX:w:SUPP REG1=XED_REG_EAX:r:SUPP 6943 } 6944 { 6945 ICLASS : CWDE 6946 CPL : 3 6947 CATEGORY : CONVERT 6948 EXTENSION : BASE 6949 ISA_SET : I386 6950 PATTERN : 0x98 EOSZ=2 6951 OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP 6952 } 6953 { 6954 ICLASS : CWD 6955 CPL : 3 6956 CATEGORY : CONVERT 6957 EXTENSION : BASE 6958 ISA_SET : I86 6959 PATTERN : 0x99 EOSZ=1 6960 OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP 6961 } 6962 { 6963 ICLASS : CQO 6964 CPL : 3 6965 CATEGORY : CONVERT 6966 EXTENSION : LONGMODE 6967 PATTERN : 0x99 EOSZ=3 mode64 rexw_prefix 6968 OPERANDS : REG0=XED_REG_RDX:w:SUPP REG1=XED_REG_RAX:r:SUPP 6969 } 6970 { 6971 ICLASS : CDQ 6972 CPL : 3 6973 CATEGORY : CONVERT 6974 EXTENSION : BASE 6975 ISA_SET : I386 6976 PATTERN : 0x99 EOSZ=2 6977 OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP 6978 } 6979 { 6980 ICLASS : CALL_FAR 6981 DISASM_INTEL : call far 6982 DISASM_ATTSV : lcall 6983 CPL : 3 6984 CATEGORY : CALL 6985 ATTRIBUTES : FAR_XFER NOTSX 6986 EXTENSION : BASE 6987 ISA_SET : I86 6988 COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented) 6989 PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 6990 OPERANDS : MEM0:r:p2 REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP 6991 PATTERN : 0x9A not64 BRDISPz() UIMM16() 6992 OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP 6993 } 6994 { 6995 ICLASS : FWAIT 6996 CPL : 3 6997 CATEGORY : X87_ALU 6998 EXTENSION : X87 6999 ATTRIBUTES : X87_CONTROL NOTSX 7000 PATTERN : 0x9B 7001 OPERANDS : 7002 } 7003 { 7004 ICLASS : PUSHF 7005 CPL : 3 7006 CATEGORY : PUSH 7007 EXTENSION : BASE 7008 ISA_SET : I86 7009 FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] 7010 PATTERN : 0x9C DF64() EOSZ=1 7011 OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP 7012 } 7013 { 7014 ICLASS : PUSHFD 7015 CPL : 3 7016 CATEGORY : PUSH 7017 EXTENSION : BASE 7018 ISA_SET : I386 7019 FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] 7020 PATTERN : 0x9C DF64() EOSZ=2 not64 7021 OPERANDS : REG0=XED_REG_STACKPUSH:w:d:SUPP 7022 } 7023 { 7024 ICLASS : PUSHFQ 7025 CPL : 3 7026 CATEGORY : PUSH 7027 EXTENSION : LONGMODE 7028 FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] 7029 PATTERN : 0x9C DF64() EOSZ=3 mode64 7030 OPERANDS : REG0=XED_REG_STACKPUSH:w:q:SUPP 7031 } 7032 { 7033 ICLASS : POPF 7034 ATTRIBUTES: NOTSX 7035 CPL : 3 7036 CATEGORY : POP 7037 EXTENSION : BASE 7038 ISA_SET : I86 7039 FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] 7040 PATTERN : 0x9D DF64() EOSZ=1 7041 OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP 7042 } 7043 { 7044 ICLASS : POPFD 7045 ATTRIBUTES: NOTSX 7046 CPL : 3 7047 CATEGORY : POP 7048 EXTENSION : BASE 7049 ISA_SET : I386 7050 FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] 7051 PATTERN : 0x9D DF64() EOSZ=2 not64 7052 OPERANDS : REG0=XED_REG_STACKPOP:r:d:SUPP 7053 } 7054 { 7055 ICLASS : POPFQ 7056 ATTRIBUTES: NOTSX 7057 CPL : 3 7058 CATEGORY : POP 7059 EXTENSION : LONGMODE 7060 FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] 7061 PATTERN : 0x9D DF64() EOSZ=3 mode64 7062 OPERANDS : REG0=XED_REG_STACKPOP:r:q:SUPP 7063 } 7064 { 7065 ICLASS : SAHF 7066 CPL : 3 7067 CATEGORY : FLAGOP 7068 EXTENSION : BASE 7069 ISA_SET : LAHF 7070 FLAGS : MUST [ sf-ah zf-ah af-ah pf-ah cf-ah ] 7071 PATTERN : 0x9E 7072 OPERANDS : REG0=XED_REG_AH:r:SUPP 7073 } 7074 { 7075 ICLASS : LAHF 7076 CPL : 3 7077 CATEGORY : FLAGOP 7078 EXTENSION : BASE 7079 ISA_SET : LAHF 7080 FLAGS : MUST [ sf-tst zf-tst af-tst pf-tst cf-tst ] 7081 PATTERN : 0x9F 7082 OPERANDS : REG0=XED_REG_AH:w:SUPP 7083 } 7084 { 7085 ICLASS : MOV 7086 CPL : 3 7087 CATEGORY : DATAXFER 7088 EXTENSION : BASE 7089 ISA_SET : I86 7090 ATTRIBUTES : fixed_base0 BYTEOP 7091 PATTERN : 0xA0 MEMDISPv() OVERRIDE_SEG0() 7092 OPERANDS : REG0=XED_REG_AL:w:IMPL MEM0:r:b SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND 7093 } 7094 { 7095 ICLASS : MOV 7096 CPL : 3 7097 CATEGORY : DATAXFER 7098 EXTENSION : BASE 7099 ISA_SET : I86 7100 ATTRIBUTES : fixed_base0 7101 PATTERN : 0xA1 MEMDISPv() OVERRIDE_SEG0() 7102 OPERANDS : REG0=OrAX():w:IMPL MEM0:r:v SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND 7103 } 7104 { 7105 ICLASS : MOV 7106 CPL : 3 7107 CATEGORY : DATAXFER 7108 EXTENSION : BASE 7109 ISA_SET : I86 7110 ATTRIBUTES : fixed_base0 BYTEOP 7111 PATTERN : 0xA2 MEMDISPv() OVERRIDE_SEG0() 7112 OPERANDS : MEM0:w:b REG0=XED_REG_AL:r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND 7113 } 7114 { 7115 ICLASS : MOV 7116 CPL : 3 7117 CATEGORY : DATAXFER 7118 EXTENSION : BASE 7119 ISA_SET : I86 7120 ATTRIBUTES : fixed_base0 7121 PATTERN : 0xA3 MEMDISPv() OVERRIDE_SEG0() 7122 OPERANDS : MEM0:w:v REG0=OrAX():r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND 7123 } 7124 7125 7126 { 7127 ICLASS : REP_MOVSB 7128 DISASM : movsb 7129 CPL : 3 7130 CATEGORY : STRINGOP 7131 EXTENSION : BASE 7132 ISA_SET : I86 7133 ATTRIBUTES :REP fixed_base0 fixed_base1 BYTEOP 7134 FLAGS : READONLY [ df-tst ] 7135 7136 PATTERN : 0xA4 repe OVERRIDE_SEG1() 7137 OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 7138 7139 PATTERN : 0xA4 repne OVERRIDE_SEG1() 7140 OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 7141 } 7142 { 7143 ICLASS : MOVSB 7144 CPL : 3 7145 CATEGORY : STRINGOP 7146 EXTENSION : BASE 7147 ISA_SET : I86 7148 ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP 7149 FLAGS : READONLY [ df-tst ] 7150 7151 PATTERN : 0xA4 norep OVERRIDE_SEG1() 7152 OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP 7153 } 7154 7155 7156 7157 { 7158 ICLASS : REP_MOVSW 7159 DISASM : movsw 7160 CPL : 3 7161 CATEGORY : STRINGOP 7162 EXTENSION : BASE 7163 ISA_SET : I86 7164 ATTRIBUTES :REP fixed_base0 fixed_base1 7165 FLAGS : READONLY [ df-tst ] 7166 7167 PATTERN : 0xA5 EOSZ=1 repe OVERRIDE_SEG1() 7168 OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 7169 7170 PATTERN : 0xA5 EOSZ=1 repne OVERRIDE_SEG1() 7171 OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 7172 } 7173 { 7174 ICLASS : MOVSW 7175 CPL : 3 7176 CATEGORY : STRINGOP 7177 EXTENSION : BASE 7178 ISA_SET : I86 7179 ATTRIBUTES : fixed_base0 fixed_base1 7180 FLAGS : READONLY [ df-tst ] 7181 7182 PATTERN : 0xA5 EOSZ=1 norep OVERRIDE_SEG1() 7183 OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP 7184 } 7185 7186 7187 7188 { 7189 ICLASS : REP_MOVSD 7190 DISASM : movsd 7191 CPL : 3 7192 CATEGORY : STRINGOP 7193 EXTENSION : BASE 7194 ISA_SET : I386 7195 ATTRIBUTES :REP fixed_base0 fixed_base1 7196 FLAGS : READONLY [ df-tst ] 7197 7198 PATTERN : 0xA5 EOSZ=2 repe OVERRIDE_SEG1() 7199 OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 7200 7201 PATTERN : 0xA5 EOSZ=2 repne OVERRIDE_SEG1() 7202 OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 7203 } 7204 { 7205 ICLASS : MOVSD 7206 CPL : 3 7207 CATEGORY : STRINGOP 7208 EXTENSION : BASE 7209 ISA_SET : I386 7210 ATTRIBUTES : fixed_base0 fixed_base1 7211 FLAGS : READONLY [ df-tst ] 7212 7213 PATTERN : 0xA5 EOSZ=2 norep OVERRIDE_SEG1() 7214 OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP 7215 } 7216 7217 7218 { 7219 ICLASS : REP_MOVSQ 7220 DISASM : movsq 7221 CPL : 3 7222 CATEGORY : STRINGOP 7223 EXTENSION : LONGMODE 7224 ATTRIBUTES :REP fixed_base0 fixed_base1 7225 FLAGS : READONLY [ df-tst ] 7226 7227 PATTERN : 0xA5 EOSZ=3 repe OVERRIDE_SEG1() 7228 OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 7229 7230 PATTERN : 0xA5 EOSZ=3 repne OVERRIDE_SEG1() 7231 OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP 7232 } 7233 7234 { 7235 ICLASS : MOVSQ 7236 CPL : 3 7237 CATEGORY : STRINGOP 7238 EXTENSION : LONGMODE 7239 ATTRIBUTES : fixed_base0 fixed_base1 7240 FLAGS : READONLY [ df-tst ] 7241 7242 PATTERN : 0xA5 EOSZ=3 norep OVERRIDE_SEG1() 7243 OPERANDS : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:q BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP 7244 } 7245 7246 7247 { 7248 ICLASS : REPE_CMPSB 7249 DISASM : cmpsb 7250 CPL : 3 7251 CATEGORY : STRINGOP 7252 EXTENSION : BASE 7253 ISA_SET : I86 7254 ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP 7255 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7256 7257 PATTERN : 0xA6 repe OVERRIDE_SEG0() 7258 OPERANDS : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 7259 } 7260 { 7261 ICLASS : REPNE_CMPSB 7262 DISASM : cmpsb 7263 CPL : 3 7264 CATEGORY : STRINGOP 7265 EXTENSION : BASE 7266 ISA_SET : I86 7267 ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP 7268 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7269 7270 PATTERN : 0xA6 repne OVERRIDE_SEG0() 7271 OPERANDS : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 7272 } 7273 7274 { 7275 ICLASS : CMPSB 7276 CPL : 3 7277 CATEGORY : STRINGOP 7278 EXTENSION : BASE 7279 ISA_SET : I86 7280 ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP 7281 FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] 7282 7283 PATTERN : 0xA6 norep OVERRIDE_SEG0() 7284 OPERANDS : MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP 7285 } 7286 7287 7288 { 7289 ICLASS : REPE_CMPSW 7290 DISASM : cmpsw 7291 CPL : 3 7292 CATEGORY : STRINGOP 7293 EXTENSION : BASE 7294 ISA_SET : I86 7295 ATTRIBUTES : REP fixed_base0 fixed_base1 7296 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7297 7298 PATTERN : 0xA7 EOSZ=1 repe OVERRIDE_SEG0() 7299 OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 7300 } 7301 { 7302 ICLASS : REPNE_CMPSW 7303 DISASM : cmpsw 7304 CPL : 3 7305 CATEGORY : STRINGOP 7306 EXTENSION : BASE 7307 ISA_SET : I86 7308 ATTRIBUTES : REP fixed_base0 fixed_base1 7309 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7310 7311 PATTERN : 0xA7 EOSZ=1 repne OVERRIDE_SEG0() 7312 OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 7313 } 7314 7315 { 7316 ICLASS : CMPSW 7317 CPL : 3 7318 CATEGORY : STRINGOP 7319 EXTENSION : BASE 7320 ISA_SET : I86 7321 ATTRIBUTES : fixed_base0 fixed_base1 7322 FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] 7323 PATTERN : 0xA7 EOSZ=1 norep OVERRIDE_SEG0() 7324 OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP 7325 } 7326 7327 7328 7329 7330 { 7331 ICLASS : REPE_CMPSD 7332 DISASM : cmpsd 7333 CPL : 3 7334 CATEGORY : STRINGOP 7335 EXTENSION : BASE 7336 ISA_SET : I386 7337 ATTRIBUTES : REP fixed_base0 fixed_base1 7338 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7339 7340 PATTERN : 0xA7 EOSZ=2 repe OVERRIDE_SEG0() 7341 OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 7342 } 7343 { 7344 ICLASS : REPNE_CMPSD 7345 DISASM : cmpsd 7346 CPL : 3 7347 CATEGORY : STRINGOP 7348 EXTENSION : BASE 7349 ISA_SET : I386 7350 ATTRIBUTES : REP fixed_base0 fixed_base1 7351 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7352 7353 PATTERN : 0xA7 EOSZ=2 repne OVERRIDE_SEG0() 7354 OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 7355 } 7356 7357 7358 { 7359 ICLASS : CMPSD 7360 CPL : 3 7361 CATEGORY : STRINGOP 7362 EXTENSION : BASE 7363 ISA_SET : I386 7364 ATTRIBUTES : fixed_base0 fixed_base1 7365 FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] 7366 7367 PATTERN : 0xA7 EOSZ=2 norep OVERRIDE_SEG0() 7368 OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP 7369 } 7370 7371 7372 { 7373 ICLASS : REPE_CMPSQ 7374 DISASM : cmpsq 7375 CPL : 3 7376 CATEGORY : STRINGOP 7377 EXTENSION : LONGMODE 7378 ATTRIBUTES : REP fixed_base0 fixed_base1 7379 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7380 7381 PATTERN : 0xA7 EOSZ=3 repe OVERRIDE_SEG0() 7382 OPERANDS : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 7383 } 7384 { 7385 ICLASS : REPNE_CMPSQ 7386 DISASM : cmpsq 7387 CPL : 3 7388 CATEGORY : STRINGOP 7389 EXTENSION : LONGMODE 7390 ATTRIBUTES : REP fixed_base0 fixed_base1 7391 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7392 7393 PATTERN : 0xA7 EOSZ=3 repne OVERRIDE_SEG0() 7394 OPERANDS : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP 7395 } 7396 { 7397 ICLASS : CMPSQ 7398 CPL : 3 7399 CATEGORY : STRINGOP 7400 EXTENSION : LONGMODE 7401 ATTRIBUTES : fixed_base0 fixed_base1 7402 FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] 7403 PATTERN : 0xA7 EOSZ=3 norep OVERRIDE_SEG0() 7404 OPERANDS : MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:q BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP 7405 } 7406 7407 7408 { 7409 ICLASS : TEST 7410 CPL : 3 7411 CATEGORY : LOGICAL 7412 EXTENSION : BASE 7413 ISA_SET : I86 7414 ATTRIBUTES : BYTEOP 7415 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 7416 PATTERN : 0xA8 SIMM8() 7417 OPERANDS : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8 7418 } 7419 { 7420 ICLASS : TEST 7421 CPL : 3 7422 CATEGORY : LOGICAL 7423 EXTENSION : BASE 7424 ISA_SET : I86 7425 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 7426 PATTERN : 0xA9 SIMMz() 7427 OPERANDS : REG0=OrAX():r:IMPL IMM0:r:z 7428 } 7429 7430 { 7431 ICLASS : REP_STOSB 7432 DISASM : stosb 7433 CPL : 3 7434 CATEGORY : STRINGOP 7435 EXTENSION : BASE 7436 ISA_SET : I86 7437 ATTRIBUTES :REP fixed_base0 BYTEOP 7438 FLAGS : READONLY [ df-tst ] 7439 PATTERN : 0xAA repe 7440 OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP 7441 PATTERN : 0xAA repne 7442 OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP 7443 } 7444 { 7445 ICLASS : STOSB 7446 CPL : 3 7447 CATEGORY : STRINGOP 7448 EXTENSION : BASE 7449 ISA_SET : I86 7450 ATTRIBUTES : fixed_base0 BYTEOP 7451 FLAGS : READONLY [ df-tst ] 7452 PATTERN : 0xAA norep 7453 OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP 7454 } 7455 7456 7457 7458 { 7459 ICLASS : REP_STOSW 7460 DISASM : stosw 7461 CPL : 3 7462 CATEGORY : STRINGOP 7463 EXTENSION : BASE 7464 ISA_SET : I86 7465 ATTRIBUTES :REP fixed_base0 7466 FLAGS : READONLY [ df-tst ] 7467 PATTERN : 0xAB EOSZ=1 repe 7468 OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP 7469 PATTERN : 0xAB EOSZ=1 repne 7470 OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP 7471 } 7472 { 7473 ICLASS : STOSW 7474 CPL : 3 7475 CATEGORY : STRINGOP 7476 EXTENSION : BASE 7477 ISA_SET : I86 7478 ATTRIBUTES : fixed_base0 7479 FLAGS : READONLY [ df-tst ] 7480 PATTERN : 0xAB EOSZ=1 norep 7481 OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP 7482 } 7483 7484 7485 7486 7487 { 7488 ICLASS : REP_STOSD 7489 DISASM : stosd 7490 CPL : 3 7491 CATEGORY : STRINGOP 7492 EXTENSION : BASE 7493 ISA_SET : I386 7494 ATTRIBUTES :REP fixed_base0 7495 FLAGS : READONLY [ df-tst ] 7496 PATTERN : 0xAB EOSZ=2 repe 7497 OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP 7498 PATTERN : 0xAB EOSZ=2 repne 7499 OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP 7500 } 7501 { 7502 ICLASS : STOSD 7503 CPL : 3 7504 CATEGORY : STRINGOP 7505 EXTENSION : BASE 7506 ISA_SET : I386 7507 ATTRIBUTES : fixed_base0 7508 FLAGS : READONLY [ df-tst ] 7509 PATTERN : 0xAB EOSZ=2 norep 7510 OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP 7511 } 7512 7513 7514 7515 7516 { 7517 ICLASS : REP_STOSQ 7518 DISASM : stosq 7519 CPL : 3 7520 CATEGORY : STRINGOP 7521 EXTENSION : LONGMODE 7522 ATTRIBUTES :REP fixed_base0 7523 FLAGS : READONLY [ df-tst ] 7524 PATTERN : 0xAB EOSZ=3 repe 7525 OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP 7526 PATTERN : 0xAB EOSZ=3 repne 7527 OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP 7528 } 7529 { 7530 ICLASS : STOSQ 7531 CPL : 3 7532 CATEGORY : STRINGOP 7533 EXTENSION : LONGMODE 7534 ATTRIBUTES : fixed_base0 7535 FLAGS : READONLY [ df-tst ] 7536 PATTERN : 0xAB EOSZ=3 norep 7537 OPERANDS : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP 7538 } 7539 7540 7541 7542 7543 { 7544 ICLASS : REP_LODSB 7545 DISASM : lodsb 7546 CPL : 3 7547 CATEGORY : STRINGOP 7548 EXTENSION : BASE 7549 ISA_SET : I86 7550 ATTRIBUTES :REP fixed_base0 BYTEOP 7551 FLAGS : READONLY [ df-tst ] 7552 PATTERN : 0xAC repe OVERRIDE_SEG0() 7553 OPERANDS : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 7554 PATTERN : 0xAC repne OVERRIDE_SEG0() 7555 OPERANDS : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 7556 } 7557 { 7558 ICLASS : LODSB 7559 CPL : 3 7560 CATEGORY : STRINGOP 7561 EXTENSION : BASE 7562 ISA_SET : I86 7563 ATTRIBUTES : fixed_base0 BYTEOP 7564 FLAGS : READONLY [ df-tst ] 7565 PATTERN : 0xAC norep OVERRIDE_SEG0() 7566 OPERANDS : REG0=XED_REG_AL:w:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP 7567 } 7568 7569 7570 7571 7572 { 7573 ICLASS : REP_LODSW 7574 DISASM : lodsw 7575 CPL : 3 7576 CATEGORY : STRINGOP 7577 EXTENSION : BASE 7578 ISA_SET : I86 7579 ATTRIBUTES :REP fixed_base0 7580 FLAGS : READONLY [ df-tst ] 7581 PATTERN : 0xAD EOSZ=1 repe OVERRIDE_SEG0() 7582 OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 7583 PATTERN : 0xAD EOSZ=1 repne OVERRIDE_SEG0() 7584 OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 7585 } 7586 { 7587 ICLASS : LODSW 7588 CPL : 3 7589 CATEGORY : STRINGOP 7590 EXTENSION : BASE 7591 ISA_SET : I86 7592 ATTRIBUTES : fixed_base0 7593 FLAGS : READONLY [ df-tst ] 7594 PATTERN : 0xAD EOSZ=1 norep OVERRIDE_SEG0() 7595 OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP 7596 } 7597 7598 7599 7600 7601 { 7602 ICLASS : REP_LODSD 7603 DISASM : lodsd 7604 CPL : 3 7605 CATEGORY : STRINGOP 7606 EXTENSION : BASE 7607 ISA_SET : I386 7608 ATTRIBUTES :REP fixed_base0 7609 FLAGS : READONLY [ df-tst ] 7610 PATTERN : 0xAD EOSZ=2 repe OVERRIDE_SEG0() 7611 OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 7612 PATTERN : 0xAD EOSZ=2 repne OVERRIDE_SEG0() 7613 OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 7614 } 7615 { 7616 ICLASS : LODSD 7617 CPL : 3 7618 CATEGORY : STRINGOP 7619 EXTENSION : BASE 7620 ISA_SET : I386 7621 ATTRIBUTES : fixed_base0 7622 FLAGS : READONLY [ df-tst ] 7623 PATTERN : 0xAD EOSZ=2 norep OVERRIDE_SEG0() 7624 OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP 7625 } 7626 7627 7628 7629 { 7630 ICLASS : REP_LODSQ 7631 DISASM : lodsq 7632 CPL : 3 7633 CATEGORY : STRINGOP 7634 EXTENSION : LONGMODE 7635 ATTRIBUTES :REP fixed_base0 7636 FLAGS : READONLY [ df-tst ] 7637 PATTERN : 0xAD EOSZ=3 repe OVERRIDE_SEG0() 7638 OPERANDS : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 7639 PATTERN : 0xAD EOSZ=3 repne OVERRIDE_SEG0() 7640 OPERANDS : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP 7641 } 7642 { 7643 ICLASS : LODSQ 7644 CPL : 3 7645 CATEGORY : STRINGOP 7646 EXTENSION : LONGMODE 7647 ATTRIBUTES : fixed_base0 7648 FLAGS : READONLY [ df-tst ] 7649 PATTERN : 0xAD EOSZ=3 norep OVERRIDE_SEG0() 7650 OPERANDS : REG0=XED_REG_RAX:w:SUPP MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP 7651 } 7652 7653 7654 7655 { 7656 ICLASS : REPE_SCASB 7657 DISASM : scasb 7658 CPL : 3 7659 CATEGORY : STRINGOP 7660 EXTENSION : BASE 7661 ISA_SET : I86 7662 ATTRIBUTES : REP fixed_base0 BYTEOP 7663 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7664 PATTERN : 0xAE repe 7665 OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 7666 } 7667 { 7668 ICLASS : REPNE_SCASB 7669 DISASM : scasb 7670 CPL : 3 7671 CATEGORY : STRINGOP 7672 EXTENSION : BASE 7673 ISA_SET : I86 7674 ATTRIBUTES : REP fixed_base0 BYTEOP 7675 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7676 PATTERN : 0xAE repne 7677 OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 7678 } 7679 7680 { 7681 ICLASS : SCASB 7682 CPL : 3 7683 CATEGORY : STRINGOP 7684 EXTENSION : BASE 7685 ISA_SET : I86 7686 ATTRIBUTES : fixed_base0 BYTEOP 7687 FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] 7688 PATTERN : 0xAE norep 7689 OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:r:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP 7690 } 7691 7692 7693 7694 7695 { 7696 ICLASS : REPE_SCASW 7697 DISASM : scasw 7698 CPL : 3 7699 CATEGORY : STRINGOP 7700 EXTENSION : BASE 7701 ISA_SET : I86 7702 ATTRIBUTES : REP fixed_base0 7703 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7704 PATTERN : 0xAF EOSZ=1 repe 7705 OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 7706 } 7707 { 7708 ICLASS : REPNE_SCASW 7709 DISASM : scasw 7710 CPL : 3 7711 CATEGORY : STRINGOP 7712 EXTENSION : BASE 7713 ISA_SET : I86 7714 ATTRIBUTES : REP fixed_base0 7715 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7716 PATTERN : 0xAF EOSZ=1 repne 7717 OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 7718 } 7719 { 7720 ICLASS : SCASW 7721 CPL : 3 7722 CATEGORY : STRINGOP 7723 EXTENSION : BASE 7724 ISA_SET : I86 7725 ATTRIBUTES : fixed_base0 7726 FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] 7727 PATTERN : 0xAF EOSZ=1 norep 7728 OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP 7729 } 7730 7731 7732 7733 7734 { 7735 ICLASS : REPE_SCASD 7736 DISASM : scasd 7737 CPL : 3 7738 CATEGORY : STRINGOP 7739 EXTENSION : BASE 7740 ISA_SET : I386 7741 ATTRIBUTES : REP fixed_base0 7742 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7743 PATTERN : 0xAF EOSZ=2 repe 7744 OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 7745 } 7746 { 7747 ICLASS : REPNE_SCASD 7748 DISASM : scasd 7749 CPL : 3 7750 CATEGORY : STRINGOP 7751 EXTENSION : BASE 7752 ISA_SET : I386 7753 ATTRIBUTES : REP fixed_base0 7754 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7755 PATTERN : 0xAF EOSZ=2 repne 7756 OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 7757 } 7758 { 7759 ICLASS : SCASD 7760 CPL : 3 7761 CATEGORY : STRINGOP 7762 EXTENSION : BASE 7763 ISA_SET : I386 7764 ATTRIBUTES : fixed_base0 7765 FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] 7766 PATTERN : 0xAF EOSZ=2 norep 7767 OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP 7768 } 7769 7770 7771 7772 7773 { 7774 ICLASS : REPE_SCASQ 7775 DISASM : scasq 7776 CPL : 3 7777 CATEGORY : STRINGOP 7778 EXTENSION : LONGMODE 7779 ATTRIBUTES : REP fixed_base0 7780 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7781 PATTERN : 0xAF EOSZ=3 repe 7782 OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 7783 } 7784 { 7785 ICLASS : REPNE_SCASQ 7786 DISASM : scasq 7787 CPL : 3 7788 CATEGORY : STRINGOP 7789 EXTENSION : LONGMODE 7790 ATTRIBUTES : REP fixed_base0 7791 FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] 7792 PATTERN : 0xAF EOSZ=3 repne 7793 OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP 7794 } 7795 { 7796 ICLASS : SCASQ 7797 CPL : 3 7798 CATEGORY : STRINGOP 7799 EXTENSION : LONGMODE 7800 ATTRIBUTES : fixed_base0 7801 FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] 7802 PATTERN : 0xAF EOSZ=3 norep 7803 OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:r:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP 7804 } 7805 7806 7807 7808 7809 { 7810 ICLASS : MOV 7811 CPL : 3 7812 CATEGORY : DATAXFER 7813 ATTRIBUTES : BYTEOP 7814 EXTENSION : BASE 7815 ISA_SET : I86 7816 PATTERN : 0b1011_0 SRM[rrr] UIMM8() 7817 OPERANDS : REG0=GPR8_SB():w IMM0:r:b 7818 # i had to come up with a partial nibble name 7819 IFORM : MOV_GPR8_IMMb_D0 7820 } 7821 { 7822 ICLASS : MOV 7823 CPL : 3 7824 CATEGORY : DATAXFER 7825 EXTENSION : BASE 7826 ISA_SET : I86 7827 PATTERN : 0b1011_1 SRM[rrr] UIMMv() 7828 OPERANDS : REG0=GPRv_SB():w IMM0:r:v 7829 } 7830 { 7831 ICLASS : RET_NEAR 7832 DISASM : ret 7833 CPL : 3 7834 CATEGORY : RET 7835 EXTENSION : BASE 7836 ISA_SET : I86 7837 ATTRIBUTES: MPX_PREFIX_ABLE 7838 PATTERN : 0xC2 DF64() UIMM16() IMMUNE66_LOOP64() 7839 OPERANDS : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP 7840 } 7841 { 7842 ICLASS : RET_NEAR 7843 DISASM : ret 7844 CPL : 3 7845 CATEGORY : RET 7846 EXTENSION : BASE 7847 ISA_SET : I86 7848 ATTRIBUTES: MPX_PREFIX_ABLE 7849 PATTERN : 0xC3 DF64() IMMUNE66_LOOP64() 7850 OPERANDS : REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP 7851 } 7852 { 7853 ICLASS : LES 7854 CPL : 3 7855 CATEGORY : SEGOP 7856 EXTENSION : BASE 7857 ISA_SET : I86 7858 ATTRIBUTES: NOTSX 7859 PATTERN : 0xC4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() 7860 OPERANDS : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_ES:w:SUPP 7861 } 7862 { 7863 ICLASS : LDS 7864 CPL : 3 7865 CATEGORY : SEGOP 7866 EXTENSION : BASE 7867 ISA_SET : I86 7868 ATTRIBUTES: NOTSX 7869 PATTERN : 0xC5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() 7870 OPERANDS : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_DS:w:SUPP 7871 } 7872 { 7873 ICLASS : ENTER 7874 CPL : 3 7875 CATEGORY : MISC 7876 EXTENSION : BASE 7877 ISA_SET : I186 7878 ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION 7879 PATTERN : 0xC8 DF64() UIMM16() UIMM8_1() 7880 OPERANDS : IMM0:r:w IMM1:r:b REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=OrBP():rw:SUPP 7881 } 7882 { 7883 ICLASS : LEAVE 7884 CPL : 3 7885 CATEGORY : MISC 7886 EXTENSION : BASE 7887 ISA_SET : I186 7888 ATTRIBUTES : fixed_base0 7889 PATTERN : 0xC9 DF64() 7890 # Ignoring STACKPOP semantics for LEAVE because it accesses memory at rBP because of 7891 # the initial copy of rBP to rSP as part of the LEAVE's execution. 7892 OPERANDS : MEM0:r:SUPP:v BASE0=ArBP():r:SUPP SEG0=FINAL_SSEG0():r:SUPP REG0=OrBP():rw:SUPP REG1=OrSP():rw:SUPP 7893 } 7894 { 7895 ICLASS : RET_FAR 7896 DISASM_INTEL: ret far 7897 DISASM_ATTSV: lcall 7898 CPL : 3 7899 CATEGORY : RET 7900 ATTRIBUTES : FAR_XFER NOTSX 7901 EXTENSION : BASE 7902 ISA_SET : I86 7903 COMMENT : same privilege level does 2 pops (spw2). inter-privilege level does 4 (not represented) 7904 PATTERN : 0xCA UIMM16() 7905 OPERANDS : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP 7906 } 7907 { 7908 ICLASS : RET_FAR 7909 DISASM_INTEL: ret far 7910 DISASM_ATTSV: lcall 7911 CPL : 3 7912 CATEGORY : RET 7913 ATTRIBUTES : FAR_XFER NOTSX 7914 EXTENSION : BASE 7915 ISA_SET : I86 7916 PATTERN : 0xCB 7917 OPERANDS : REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP 7918 } 7919 { 7920 ICLASS : INT3 7921 ATTRIBUTES: NOTSX 7922 CPL : 3 7923 CATEGORY : INTERRUPT 7924 EXTENSION : BASE 7925 ISA_SET : I86 7926 FLAGS : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ] 7927 PATTERN : 0xCC 7928 OPERANDS : REG0=rIP():w:SUPP 7929 } 7930 { 7931 ICLASS : INT 7932 ATTRIBUTES: NOTSX 7933 CPL : 3 7934 CATEGORY : INTERRUPT 7935 EXTENSION : BASE 7936 ISA_SET : I86 7937 FLAGS : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ] 7938 PATTERN : 0xCD UIMM8() 7939 OPERANDS : IMM0:r:b REG0=rIP():w:SUPP 7940 } 7941 { 7942 ICLASS : INTO 7943 ATTRIBUTES: NOTSX 7944 CPL : 3 7945 CATEGORY : INTERRUPT 7946 EXTENSION : BASE 7947 ISA_SET : I86 7948 FLAGS : MUST [ ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst of-tst if-mod tf-mod ] 7949 PATTERN : 0xCE not64 7950 OPERANDS : REG0=rIP():w:SUPP 7951 } 7952 { 7953 ICLASS : IRET 7954 ATTRIBUTES: NOTSX 7955 CPL : 3 7956 CATEGORY : RET 7957 EXTENSION : BASE 7958 ISA_SET : I86 7959 FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] 7960 PATTERN : 0xCF EOSZ=1 7961 OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP 7962 } 7963 { 7964 ICLASS : IRETD 7965 ATTRIBUTES: NOTSX 7966 CPL : 3 7967 CATEGORY : RET 7968 EXTENSION : BASE 7969 ISA_SET : I386 7970 FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] 7971 PATTERN : 0xCF EOSZ=2 7972 OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP 7973 } 7974 { 7975 ICLASS : IRETQ 7976 ATTRIBUTES: NOTSX 7977 CPL : 3 7978 CATEGORY : RET 7979 EXTENSION : LONGMODE 7980 FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] 7981 PATTERN : 0xCF EOSZ=3 mode64 7982 # FIXME: This is only an approximate width for the stack pops 7983 OPERANDS : REG0=XED_REG_STACKPOP:r:spw3:SUPP REG1=rIP():w:SUPP 7984 } 7985 { 7986 ICLASS : AAM 7987 CPL : 3 7988 CATEGORY : DECIMAL 7989 EXTENSION : BASE 7990 ISA_SET : I86 7991 FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ] 7992 PATTERN : 0xD4 not64 SIMM8() 7993 OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:w:SUPP 7994 } 7995 { 7996 ICLASS : AAD 7997 CPL : 3 7998 CATEGORY : DECIMAL 7999 EXTENSION : BASE 8000 ISA_SET : I86 8001 FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ] 8002 PATTERN : 0xD5 not64 SIMM8() 8003 OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP 8004 } 8005 { 8006 ICLASS : SALC 8007 CPL : 3 8008 CATEGORY : FLAGOP 8009 EXTENSION : BASE 8010 ISA_SET : I86 8011 FLAGS : MUST [ cf-tst ] 8012 PATTERN : 0xD6 not64 8013 OPERANDS : REG0=XED_REG_AL:w:SUPP 8014 COMMENT : UNDOC - "The Undocumented PC", 2nd ed 1997, says it is present on all Intel CPUs of that time. 8015 } 8016 { 8017 ICLASS : XLAT 8018 CPL : 3 8019 CATEGORY : MISC 8020 EXTENSION : BASE 8021 ISA_SET : I86 8022 ATTRIBUTES : fixed_base0 8023 PATTERN : 0xD7 OVERRIDE_SEG0() 8024 OPERANDS : MEM0:r:SUPP:b BASE0=ArBX():r:SUPP INDEX=XED_REG_AL:r:SUPP REG0=XED_REG_AL:w:SUPP SEG0=FINAL_DSEG():r:SUPP SCALE=1:r:SUPP 8025 } 8026 8027 8028 { 8029 ICLASS : LOOPNE 8030 CPL : 3 8031 CATEGORY : COND_BR 8032 EXTENSION : BASE 8033 ISA_SET : I86 8034 FLAGS : READONLY [ zf-tst ] 8035 PATTERN : 0xE0 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64() 8036 OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP 8037 PATTERN : 0xE0 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() 8038 OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP 8039 PATTERN : 0xE0 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() 8040 OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP 8041 8042 # REPNE WITH A E1 (LOOPE) makes a LOOPNE on P5-class machines UNDOC 8043 PATTERN : 0xE1 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() 8044 OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP 8045 } 8046 { 8047 ICLASS : LOOPE 8048 CPL : 3 8049 CATEGORY : COND_BR 8050 EXTENSION : BASE 8051 ISA_SET : I86 8052 FLAGS : READONLY [ zf-tst ] 8053 PATTERN : 0xE1 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64() 8054 OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP 8055 PATTERN : 0xE1 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() 8056 OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP 8057 PATTERN : 0xE1 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() 8058 OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP 8059 8060 # REPE WITH A E0 (LOOPNE) makes a LOOPE on P5-class machines UNDOC 8061 PATTERN : 0xE0 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() 8062 OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP 8063 } 8064 8065 8066 8067 { 8068 ICLASS : LOOP 8069 CPL : 3 8070 CATEGORY : COND_BR 8071 EXTENSION : BASE 8072 ISA_SET : I86 8073 PATTERN : 0xE2 DF64() BRDISP8() IMMUNE66_LOOP64() 8074 OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP 8075 } 8076 8077 { 8078 ICLASS : JCXZ 8079 COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated 8080 CPL : 3 8081 CATEGORY : COND_BR 8082 EXTENSION : BASE 8083 ISA_SET : I386 8084 PATTERN : 0xE3 eamode16 BRDISP8() 8085 OPERANDS : RELBR:r:b:i8 REG0=XED_REG_CX:r:SUPP REG1=rIP():rw:SUPP 8086 } 8087 { 8088 ICLASS : JECXZ 8089 COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated 8090 CPL : 3 8091 CATEGORY : COND_BR 8092 EXTENSION : BASE 8093 ISA_SET : I386 8094 PATTERN : 0xE3 eamode32 BRDISP8() 8095 OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=rIP():rw:SUPP 8096 } 8097 { 8098 ICLASS : JRCXZ 8099 COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated 8100 CPL : 3 8101 CATEGORY : COND_BR 8102 EXTENSION : BASE 8103 ISA_SET : LONGMODE 8104 PATTERN : 0xE3 eamode64 BRDISP8() FORCE64() 8105 OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RCX:r:SUPP REG1=rIP():rw:SUPP 8106 } 8107 8108 { 8109 ICLASS : IN 8110 CPL : 3 8111 CATEGORY : IO 8112 EXTENSION : BASE 8113 ISA_SET : I86 8114 ATTRIBUTES : BYTEOP NOTSX 8115 FLAGS : READONLY [ iopl-tst ] 8116 PATTERN : 0xE4 UIMM8() IMMUNE_REXW() 8117 OPERANDS : REG0=XED_REG_AL:w:IMPL IMM0:r:b 8118 } 8119 { 8120 ICLASS : IN 8121 CPL : 3 8122 CATEGORY : IO 8123 EXTENSION : BASE 8124 ISA_SET : I86 8125 ATTRIBUTES: NOTSX 8126 FLAGS : READONLY [ iopl-tst ] 8127 PATTERN : 0xE5 UIMM8() IMMUNE_REXW() 8128 OPERANDS : REG0=OeAX():w:IMPL IMM0:r:b 8129 } 8130 8131 { 8132 ICLASS : OUT 8133 CPL : 3 8134 CATEGORY : IO 8135 EXTENSION : BASE 8136 ISA_SET : I86 8137 ATTRIBUTES: NOTSX BYTEOP 8138 FLAGS : READONLY [ iopl-tst ] 8139 PATTERN : 0xE6 UIMM8() IMMUNE_REXW() 8140 OPERANDS : IMM0:r:b REG0=XED_REG_AL:r:IMPL 8141 } 8142 8143 { 8144 ICLASS : OUT 8145 CPL : 3 8146 CATEGORY : IO 8147 EXTENSION : BASE 8148 ISA_SET : I86 8149 ATTRIBUTES: NOTSX 8150 FLAGS : READONLY [ iopl-tst ] 8151 PATTERN : 0xE7 UIMM8() IMMUNE_REXW() 8152 OPERANDS : IMM0:r:b REG0=OeAX():r:IMPL 8153 } 8154 8155 { 8156 ICLASS : JMP 8157 CPL : 3 8158 CATEGORY : UNCOND_BR 8159 EXTENSION : BASE 8160 ISA_SET : I86 8161 ATTRIBUTES: MPX_PREFIX_ABLE 8162 PATTERN : 0xE9 not64 BRDISPz() 8163 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 8164 PATTERN : 0xE9 mode64 FORCE64() BRDISP32() 8165 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 8166 } 8167 { 8168 ICLASS : JMP_FAR 8169 DISASM_INTEL: jmp far 8170 DISASM_ATTSV: ljmp 8171 CPL : 3 8172 CATEGORY : UNCOND_BR 8173 ATTRIBUTES : FAR_XFER NOTSX 8174 EXTENSION : BASE 8175 ISA_SET : I86 8176 PATTERN : 0xEA not64 BRDISPz() UIMM16() 8177 OPERANDS : PTR:r:p IMM0:r:w REG0=rIP():w:SUPP 8178 } 8179 { 8180 ICLASS : JMP 8181 CPL : 3 8182 CATEGORY : UNCOND_BR 8183 EXTENSION : BASE 8184 ISA_SET : I86 8185 PATTERN : 0xEB DF64() BRDISP8() 8186 OPERANDS : RELBR:r:b:i8 REG0=rIP():rw:SUPP 8187 } 8188 { 8189 ICLASS : IN 8190 CPL : 3 8191 CATEGORY : IO 8192 EXTENSION : BASE 8193 ISA_SET : I86 8194 ATTRIBUTES : BYTEOP 8195 FLAGS : READONLY [ iopl-tst ] 8196 PATTERN : 0xEC IMMUNE_REXW() 8197 OPERANDS : REG0=XED_REG_AL:w:IMPL REG1=XED_REG_DX:r:IMPL 8198 } 8199 { 8200 ICLASS : IN 8201 CPL : 3 8202 CATEGORY : IO 8203 EXTENSION : BASE 8204 ISA_SET : I86 8205 FLAGS : READONLY [ iopl-tst ] 8206 PATTERN : 0xED IMMUNE_REXW() 8207 OPERANDS : REG0=OeAX():w:IMPL REG1=XED_REG_DX:r:IMPL 8208 } 8209 { 8210 ICLASS : OUT 8211 CPL : 3 8212 CATEGORY : IO 8213 EXTENSION : BASE 8214 ISA_SET : I86 8215 ATTRIBUTES : BYTEOP 8216 FLAGS : READONLY [ iopl-tst ] 8217 PATTERN : 0xEE IMMUNE_REXW() 8218 OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=XED_REG_AL:r:IMPL 8219 } 8220 { 8221 ICLASS : OUT 8222 CPL : 3 8223 CATEGORY : IO 8224 EXTENSION : BASE 8225 ISA_SET : I86 8226 FLAGS : READONLY [ iopl-tst ] 8227 PATTERN : 0xEF IMMUNE_REXW() 8228 OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=OeAX():r:IMPL 8229 } 8230 { 8231 ICLASS : INT1 8232 CPL : 3 8233 CATEGORY : INTERRUPT 8234 EXTENSION : BASE 8235 ISA_SET : I86 8236 PATTERN : 0xF1 8237 OPERANDS : 8238 COMMENT : UNDOC by Intel, but in AMD's opcode map 8239 } 8240 { 8241 ICLASS : HLT 8242 CPL : 0 8243 CATEGORY : SYSTEM 8244 EXTENSION : BASE 8245 ATTRIBUTES : RING0 NOTSX 8246 ISA_SET : I86 8247 PATTERN : 0xF4 8248 OPERANDS : 8249 } 8250 { 8251 ICLASS : CMC 8252 CPL : 3 8253 CATEGORY : FLAGOP 8254 EXTENSION : BASE 8255 ISA_SET : I86 8256 FLAGS : MUST [ cf-tst cf-mod ] 8257 PATTERN : 0xF5 8258 OPERANDS : 8259 } 8260 { 8261 ICLASS : CLC 8262 CPL : 3 8263 CATEGORY : FLAGOP 8264 EXTENSION : BASE 8265 ISA_SET : I86 8266 FLAGS : MUST [ cf-0 ] 8267 PATTERN : 0xF8 8268 OPERANDS : 8269 } 8270 { 8271 ICLASS : STC 8272 CPL : 3 8273 CATEGORY : FLAGOP 8274 EXTENSION : BASE 8275 ISA_SET : I86 8276 FLAGS : MUST [ cf-1 ] 8277 PATTERN : 0xF9 8278 OPERANDS : 8279 } 8280 { 8281 ICLASS : CLI 8282 ATTRIBUTES: NOTSX 8283 CPL : 3 8284 CATEGORY : FLAGOP 8285 EXTENSION : BASE 8286 ISA_SET : I86 8287 FLAGS : MUST [ vif-mod iopl-tst if-mod ] 8288 PATTERN : 0xFA 8289 OPERANDS : 8290 } 8291 { 8292 ICLASS : STI 8293 ATTRIBUTES: NOTSX 8294 CPL : 3 8295 CATEGORY : FLAGOP 8296 EXTENSION : BASE 8297 ISA_SET : I86 8298 COMMENT : Inhibits all interrupts until after next instr 8299 FLAGS : MUST [ vif-mod iopl-tst if-mod ] 8300 PATTERN : 0xFB 8301 OPERANDS : 8302 } 8303 { 8304 ICLASS : CLD 8305 ATTRIBUTES: NOTSX_COND 8306 CPL : 3 8307 CATEGORY : FLAGOP 8308 EXTENSION : BASE 8309 ISA_SET : I86 8310 FLAGS : MUST [ df-0 ] 8311 PATTERN : 0xFC 8312 OPERANDS : 8313 } 8314 { 8315 ICLASS : STD 8316 ATTRIBUTES: NOTSX_COND 8317 CPL : 3 8318 CATEGORY : FLAGOP 8319 EXTENSION : BASE 8320 ISA_SET : I86 8321 FLAGS : MUST [ df-1 ] 8322 PATTERN : 0xFD 8323 OPERANDS : 8324 } 8325 { 8326 ICLASS : LAR 8327 CPL : 3 8328 CATEGORY : SYSTEM 8329 EXTENSION : BASE 8330 ISA_SET : I286PROTECTED 8331 ATTRIBUTES : PROTECTED_MODE 8332 FLAGS : MUST [ zf-mod ] 8333 COMMENT : LAR only sometimes writes its destination register. 8334 PATTERN : 0x0F 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8335 OPERANDS : REG0=GPRv_R():cw MEM0:r:w 8336 PATTERN : 0x0F 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8337 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8338 } 8339 { 8340 ICLASS : LSL 8341 CPL : 3 8342 CATEGORY : SYSTEM 8343 EXTENSION : BASE 8344 ISA_SET : I286PROTECTED 8345 ATTRIBUTES : PROTECTED_MODE 8346 FLAGS : MUST [ zf-mod ] 8347 PATTERN : 0x0F 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8348 OPERANDS : REG0=GPRv_R():rw MEM0:r:w 8349 8350 PATTERN : 0x0F 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8351 OPERANDS : REG0=GPRv_R():rw REG1=GPRz_B():r 8352 } 8353 { 8354 ICLASS : SYSCALL 8355 ATTRIBUTES: NOTSX 8356 CPL : 3 8357 CATEGORY : SYSCALL 8358 EXTENSION : LONGMODE 8359 ISA_SET : LONGMODE 8360 FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 8361 PATTERN : 0x0F 0x05 mode64 FORCE64() 8362 OPERANDS : REG0=rIP():w:SUPP 8363 COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD 8364 } 8365 { 8366 ICLASS : CLTS 8367 CPL : 0 8368 CATEGORY : SYSTEM 8369 EXTENSION : BASE 8370 ISA_SET : I286REAL 8371 ATTRIBUTES : RING0 NOTSX 8372 PATTERN : 0x0F 0x06 8373 OPERANDS : 8374 } 8375 { 8376 ICLASS : SYSRET 8377 CPL : 0 8378 CATEGORY : SYSRET 8379 ATTRIBUTES: PROTECTED_MODE RING0 NOTSX 8380 EXTENSION : LONGMODE 8381 ISA_SET : LONGMODE 8382 FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 8383 PATTERN : 0x0F 0x07 mode64 eosz64 8384 OPERANDS : REG0=XED_REG_RIP:w:SUPP 8385 PATTERN : 0x0F 0x07 mode64 eosz32 8386 OPERANDS : REG0=XED_REG_EIP:w:SUPP 8387 COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD 8388 } 8389 { 8390 ICLASS : MOVUPS 8391 CPL : 3 8392 CATEGORY : DATAXFER 8393 EXTENSION : SSE 8394 EXCEPTIONS: SSE_TYPE_4M 8395 ATTRIBUTES : 8396 PATTERN : 0x0F 0x10 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8397 OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps 8398 8399 PATTERN : 0x0F 0x10 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8400 OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps 8401 IFORM : MOVUPS_XMMps_XMMps_0F10 8402 8403 PATTERN : 0x0F 0x11 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8404 OPERANDS : MEM0:w:ps REG0=XMM_R():r:ps 8405 8406 PATTERN : 0x0F 0x11 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8407 OPERANDS : REG0=XMM_B():w:ps REG1=XMM_R():r:ps 8408 IFORM : MOVUPS_XMMps_XMMps_0F11 8409 } 8410 { 8411 ICLASS : MOVLPS 8412 CPL : 3 8413 CATEGORY : DATAXFER 8414 EXTENSION : SSE 8415 EXCEPTIONS: SSE_TYPE_5 8416 ATTRIBUTES : 8417 PATTERN : 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] no_refining_prefix MODRM() 8418 OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32 8419 } 8420 { 8421 ICLASS : UNPCKLPS 8422 CPL : 3 8423 CATEGORY : SSE 8424 EXTENSION : SSE 8425 EXCEPTIONS: SSE_TYPE_4 8426 ATTRIBUTES : REQUIRES_ALIGNMENT 8427 COMMENT : mem form only uses q portion of the dq load. See SDM. 8428 PATTERN : 0x0F 0x14 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8429 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:dq 8430 PATTERN : 0x0F 0x14 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8431 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:q 8432 } 8433 { 8434 ICLASS : UNPCKHPS 8435 CPL : 3 8436 CATEGORY : SSE 8437 EXTENSION : SSE 8438 EXCEPTIONS: SSE_TYPE_4 8439 ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT 8440 PATTERN : 0x0F 0x15 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8441 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:dq 8442 PATTERN : 0x0F 0x15 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8443 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:dq 8444 } 8445 { 8446 ICLASS : MOVHPS 8447 CPL : 3 8448 CATEGORY : DATAXFER 8449 EXTENSION : SSE 8450 EXCEPTIONS: SSE_TYPE_5 8451 ATTRIBUTES : 8452 PATTERN : 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] no_refining_prefix MODRM() 8453 OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32 8454 } 8455 { 8456 ICLASS : MOVSS 8457 CPL : 3 8458 ATTRIBUTES : simd_scalar 8459 CATEGORY : DATAXFER 8460 EXTENSION : SSE 8461 EXCEPTIONS: SSE_TYPE_5 8462 PATTERN : 0x0F 0x10 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 8463 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:ss 8464 8465 PATTERN : 0x0F 0x10 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 8466 OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss 8467 IFORM : MOVSS_XMMss_XMMss_0F10 8468 8469 PATTERN : 0x0F 0x11 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 8470 OPERANDS : MEM0:w:ss REG0=XMM_R():r:ss 8471 8472 PATTERN : 0x0F 0x11 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 8473 OPERANDS : REG0=XMM_B():w:ss REG1=XMM_R():r:ss 8474 IFORM : MOVSS_XMMss_XMMss_0F11 8475 } 8476 { 8477 ICLASS : MOVSLDUP 8478 CPL : 3 8479 CATEGORY : DATAXFER 8480 EXTENSION : SSE3 8481 EXCEPTIONS: SSE_TYPE_4 8482 ATTRIBUTES: REQUIRES_ALIGNMENT 8483 PATTERN : 0x0F 0x12 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 8484 OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps 8485 PATTERN : 0x0F 0x12 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 8486 OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps 8487 } 8488 { 8489 ICLASS : MOVSHDUP 8490 CPL : 3 8491 CATEGORY : DATAXFER 8492 EXTENSION : SSE3 8493 EXCEPTIONS: SSE_TYPE_4 8494 ATTRIBUTES: REQUIRES_ALIGNMENT 8495 PATTERN : 0x0F 0x16 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 8496 OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps 8497 PATTERN : 0x0F 0x16 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 8498 OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps 8499 } 8500 { 8501 ICLASS : MOVUPD 8502 CPL : 3 8503 CATEGORY : DATAXFER 8504 EXTENSION : SSE2 8505 EXCEPTIONS: SSE_TYPE_4M 8506 ATTRIBUTES : 8507 PATTERN : 0x0F 0x10 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8508 OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd 8509 8510 PATTERN : 0x0F 0x10 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 8511 OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd 8512 IFORM : MOVUPD_XMMpd_XMMpd_0F10 8513 8514 PATTERN : 0x0F 0x11 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8515 OPERANDS : MEM0:w:pd REG0=XMM_R():r:pd 8516 8517 PATTERN : 0x0F 0x11 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 8518 OPERANDS : REG0=XMM_B():w:pd REG1=XMM_R():r:pd 8519 IFORM : MOVUPD_XMMpd_XMMpd_0F11 8520 } 8521 { 8522 ICLASS : MOVLPD 8523 CPL : 3 8524 CATEGORY : DATAXFER 8525 EXTENSION : SSE2 8526 EXCEPTIONS: SSE_TYPE_5 8527 ATTRIBUTES : 8528 PATTERN : 0x0F 0x12 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8529 OPERANDS : REG0=XMM_R():w:sd MEM0:r:q 8530 PATTERN : 0x0F 0x13 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8531 OPERANDS : MEM0:w:q REG0=XMM_R():r:sd 8532 } 8533 { 8534 ICLASS : UNPCKLPD 8535 CPL : 3 8536 CATEGORY : SSE 8537 EXTENSION : SSE2 8538 EXCEPTIONS: SSE_TYPE_4 8539 ATTRIBUTES : REQUIRES_ALIGNMENT 8540 COMMENT : mem form only uses q portion of the dq load. See SDM. 8541 PATTERN : 0x0F 0x14 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8542 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:dq 8543 PATTERN : 0x0F 0x14 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 8544 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:q 8545 } 8546 { 8547 ICLASS : UNPCKHPD 8548 CPL : 3 8549 CATEGORY : SSE 8550 EXTENSION : SSE2 8551 EXCEPTIONS: SSE_TYPE_4 8552 ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT 8553 PATTERN : 0x0F 0x15 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8554 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:dq 8555 PATTERN : 0x0F 0x15 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 8556 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:q 8557 } 8558 { 8559 ICLASS : MOVHPD 8560 CPL : 3 8561 CATEGORY : DATAXFER 8562 EXTENSION : SSE2 8563 EXCEPTIONS: SSE_TYPE_5 8564 ATTRIBUTES : 8565 PATTERN : 0x0F 0x16 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8566 OPERANDS : REG0=XMM_R():w:sd MEM0:r:q 8567 PATTERN : 0x0F 0x17 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8568 OPERANDS : MEM0:w:q REG0=XMM_R():r:sd 8569 } 8570 { 8571 ICLASS : MOVSD_XMM 8572 DISASM : movsd 8573 CPL : 3 8574 ATTRIBUTES : simd_scalar 8575 CATEGORY : DATAXFER 8576 EXTENSION : SSE2 8577 EXCEPTIONS: SSE_TYPE_5 8578 PATTERN : 0x0F 0x10 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 8579 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:sd 8580 8581 PATTERN : 0x0F 0x10 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 8582 OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd 8583 IFORM : MOVSD_XMM_XMMsd_XMMsd_0F10 8584 8585 PATTERN : 0x0F 0x11 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 8586 OPERANDS : MEM0:w:sd REG0=XMM_R():r:sd 8587 8588 PATTERN : 0x0F 0x11 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 8589 OPERANDS : REG0=XMM_B():w:sd REG1=XMM_R():r:sd 8590 IFORM : MOVSD_XMM_XMMsd_XMMsd_0F11 8591 } 8592 { 8593 ICLASS : MOVDDUP 8594 CPL : 3 8595 CATEGORY : DATAXFER 8596 EXTENSION : SSE3 8597 EXCEPTIONS: SSE_TYPE_5 8598 ATTRIBUTES : 8599 PATTERN : 0x0F 0x12 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 8600 OPERANDS : REG0=XMM_R():w:dq MEM0:r:q 8601 PATTERN : 0x0F 0x12 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 8602 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q 8603 } 8604 8605 { 8606 ICLASS : MOV_CR 8607 DISASM : mov 8608 CPL : 0 8609 CATEGORY : DATAXFER 8610 EXTENSION : BASE 8611 ISA_SET : I86 8612 ATTRIBUTES : RING0 NOTSX 8613 COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 8614 PATTERN : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 8615 OPERANDS : REG0=CR_R():w REG1=GPR32_B():r 8616 8617 PATTERN : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 8618 OPERANDS : REG0=CR_R():w REG1=GPR64_B():r 8619 } 8620 8621 { 8622 ICLASS : MOV_CR 8623 DISASM : mov 8624 CPL : 0 8625 CATEGORY : DATAXFER 8626 EXTENSION : BASE 8627 ISA_SET : I86 8628 ATTRIBUTES : RING0 8629 COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 8630 PATTERN : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 8631 OPERANDS : REG0=GPR32_B():w REG1=CR_R():r 8632 8633 PATTERN : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 8634 OPERANDS : REG0=GPR64_B():w REG1=CR_R():r 8635 } 8636 8637 { 8638 ICLASS : MOV_DR 8639 DISASM : mov 8640 CPL : 0 8641 CATEGORY : DATAXFER 8642 EXTENSION : BASE 8643 ISA_SET : I86 8644 ATTRIBUTES : RING0 NOTSX 8645 COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 8646 PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] DF64() not64 8647 OPERANDS : REG0=DR_R():w REG1=GPR32_B():r 8648 8649 PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] DF64() mode64 8650 OPERANDS : REG0=DR_R():w REG1=GPR64_B():r 8651 } 8652 8653 { 8654 ICLASS : MOV_DR 8655 DISASM : mov 8656 CPL : 0 8657 CATEGORY : DATAXFER 8658 EXTENSION : BASE 8659 ISA_SET : I86 8660 ATTRIBUTES : RING0 8661 COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 8662 PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] DF64() not64 8663 OPERANDS : REG0=GPR32_B():w REG1=DR_R():r 8664 8665 PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] DF64() mode64 8666 OPERANDS : REG0=GPR64_B():w REG1=DR_R():r 8667 } 8668 8669 8670 { 8671 ICLASS : WRMSR 8672 CPL : 0 8673 CATEGORY : SYSTEM 8674 EXTENSION : BASE 8675 ISA_SET : PENTIUMREAL 8676 ATTRIBUTES : RING0 NOTSX 8677 PATTERN : 0x0F 0x30 8678 OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:w:SUPP 8679 } 8680 { 8681 ICLASS : RDTSC 8682 CPL : 3 8683 CATEGORY : SYSTEM 8684 EXTENSION : BASE 8685 ISA_SET : PENTIUMREAL 8686 PATTERN : 0x0F 0x31 8687 OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_TSC:r:SUPP 8688 } 8689 { 8690 ICLASS : RDMSR 8691 CPL : 0 8692 CATEGORY : SYSTEM 8693 EXTENSION : BASE 8694 ISA_SET : PENTIUMREAL 8695 ATTRIBUTES : RING0 NOTSX 8696 PATTERN : 0x0F 0x32 8697 OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP 8698 } 8699 { 8700 ICLASS : RDPMC 8701 CPL : 3 8702 CATEGORY : SYSTEM 8703 EXTENSION : BASE 8704 ISA_SET : RDPMC 8705 PATTERN : 0x0F 0x33 8706 OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP 8707 } 8708 { 8709 ICLASS : SYSENTER 8710 CPL : 3 8711 CATEGORY : SYSCALL 8712 EXTENSION : BASE 8713 ISA_SET : PPRO 8714 ATTRIBUTES: PROTECTED_MODE NOTSX 8715 FLAGS : MUST [ vm-0 rf-0 if-0 ] 8716 PATTERN : 0x0F 0x34 8717 OPERANDS : REG0=rIP():w:SUPP 8718 COMMENT : AMD does not document support for this in 64b mode 8719 } 8720 { 8721 ICLASS : SYSEXIT 8722 CPL : 0 8723 CATEGORY : SYSRET 8724 EXTENSION : BASE 8725 ISA_SET : PPRO 8726 ATTRIBUTES: PROTECTED_MODE RING0 NOTSX 8727 PATTERN : 0x0F 0x35 8728 OPERANDS : REG0=rIP():w:SUPP 8729 COMMENT : AMD does not document support for this in 64b mode 8730 } 8731 { 8732 ICLASS : CMOVO 8733 CPL : 3 8734 CATEGORY : CMOV 8735 EXTENSION : BASE 8736 ISA_SET : PPRO 8737 FLAGS : READONLY [ of-tst ] 8738 PATTERN : 0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8739 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8740 PATTERN : 0x0F 0x40 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8741 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8742 } 8743 { 8744 ICLASS : CMOVNO 8745 CPL : 3 8746 CATEGORY : CMOV 8747 EXTENSION : BASE 8748 ISA_SET : PPRO 8749 FLAGS : READONLY [ of-tst ] 8750 PATTERN : 0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8751 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8752 PATTERN : 0x0F 0x41 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8753 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8754 } 8755 { 8756 ICLASS : CMOVB 8757 CPL : 3 8758 CATEGORY : CMOV 8759 EXTENSION : BASE 8760 ISA_SET : PPRO 8761 FLAGS : READONLY [ cf-tst ] 8762 PATTERN : 0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8763 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8764 PATTERN : 0x0F 0x42 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8765 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8766 } 8767 { 8768 ICLASS : CMOVNB 8769 CPL : 3 8770 CATEGORY : CMOV 8771 EXTENSION : BASE 8772 ISA_SET : PPRO 8773 FLAGS : READONLY [ cf-tst ] 8774 PATTERN : 0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8775 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8776 PATTERN : 0x0F 0x43 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8777 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8778 } 8779 { 8780 ICLASS : CMOVZ 8781 CPL : 3 8782 CATEGORY : CMOV 8783 EXTENSION : BASE 8784 ISA_SET : PPRO 8785 FLAGS : READONLY [ zf-tst ] 8786 PATTERN : 0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8787 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8788 PATTERN : 0x0F 0x44 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8789 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8790 } 8791 { 8792 ICLASS : CMOVNZ 8793 CPL : 3 8794 CATEGORY : CMOV 8795 EXTENSION : BASE 8796 ISA_SET : PPRO 8797 FLAGS : READONLY [ zf-tst ] 8798 PATTERN : 0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8799 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8800 PATTERN : 0x0F 0x45 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8801 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8802 } 8803 { 8804 ICLASS : CMOVBE 8805 CPL : 3 8806 CATEGORY : CMOV 8807 EXTENSION : BASE 8808 ISA_SET : PPRO 8809 FLAGS : READONLY [ cf-tst zf-tst ] 8810 PATTERN : 0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8811 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8812 PATTERN : 0x0F 0x46 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8813 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8814 } 8815 { 8816 ICLASS : CMOVNBE 8817 CPL : 3 8818 CATEGORY : CMOV 8819 EXTENSION : BASE 8820 ISA_SET : PPRO 8821 FLAGS : READONLY [ cf-tst zf-tst ] 8822 PATTERN : 0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8823 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8824 PATTERN : 0x0F 0x47 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8825 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8826 } 8827 { 8828 ICLASS : MOVMSKPS 8829 CPL : 3 8830 CATEGORY : DATAXFER 8831 EXTENSION : SSE 8832 EXCEPTIONS: SSE_TYPE_7 8833 PATTERN : 0x0F 0x50 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8834 OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:ps 8835 } 8836 { 8837 ICLASS : SQRTPS 8838 CPL : 3 8839 CATEGORY : SSE 8840 EXTENSION : SSE 8841 EXCEPTIONS: SSE_TYPE_2 8842 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 8843 PATTERN : 0x0F 0x51 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8844 OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps 8845 PATTERN : 0x0F 0x51 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8846 OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps 8847 } 8848 { 8849 ICLASS : RSQRTPS 8850 CPL : 3 8851 CATEGORY : SSE 8852 EXTENSION : SSE 8853 EXCEPTIONS: SSE_TYPE_4 8854 ATTRIBUTES : REQUIRES_ALIGNMENT 8855 PATTERN : 0x0F 0x52 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8856 OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps 8857 PATTERN : 0x0F 0x52 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8858 OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps 8859 } 8860 { 8861 ICLASS : RCPPS 8862 CPL : 3 8863 CATEGORY : SSE 8864 EXTENSION : SSE 8865 EXCEPTIONS: SSE_TYPE_4 8866 ATTRIBUTES : REQUIRES_ALIGNMENT 8867 PATTERN : 0x0F 0x53 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8868 OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps 8869 PATTERN : 0x0F 0x53 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8870 OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps 8871 } 8872 { 8873 ICLASS : ANDPS 8874 CPL : 3 8875 CATEGORY : LOGICAL_FP 8876 EXTENSION : SSE 8877 EXCEPTIONS: SSE_TYPE_4 8878 ATTRIBUTES : REQUIRES_ALIGNMENT 8879 PATTERN : 0x0F 0x54 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8880 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 8881 PATTERN : 0x0F 0x54 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8882 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 8883 } 8884 { 8885 ICLASS : ANDNPS 8886 CPL : 3 8887 CATEGORY : LOGICAL_FP 8888 EXTENSION : SSE 8889 EXCEPTIONS: SSE_TYPE_4 8890 ATTRIBUTES : REQUIRES_ALIGNMENT 8891 PATTERN : 0x0F 0x55 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8892 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 8893 PATTERN : 0x0F 0x55 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8894 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 8895 } 8896 { 8897 ICLASS : ORPS 8898 CPL : 3 8899 CATEGORY : LOGICAL_FP 8900 EXTENSION : SSE 8901 EXCEPTIONS: SSE_TYPE_4 8902 ATTRIBUTES : REQUIRES_ALIGNMENT 8903 PATTERN : 0x0F 0x56 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8904 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 8905 PATTERN : 0x0F 0x56 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8906 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 8907 } 8908 { 8909 ICLASS : XORPS 8910 CPL : 3 8911 CATEGORY : LOGICAL_FP 8912 EXTENSION : SSE 8913 EXCEPTIONS: SSE_TYPE_4 8914 ATTRIBUTES : REQUIRES_ALIGNMENT 8915 PATTERN : 0x0F 0x57 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8916 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 8917 PATTERN : 0x0F 0x57 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8918 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 8919 } 8920 { 8921 ICLASS : SQRTSS 8922 CPL : 3 8923 ATTRIBUTES : simd_scalar MXCSR 8924 CATEGORY : SSE 8925 EXTENSION : SSE 8926 EXCEPTIONS: SSE_TYPE_3 8927 PATTERN : 0x0F 0x51 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 8928 OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss 8929 PATTERN : 0x0F 0x51 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 8930 OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss 8931 } 8932 { 8933 ICLASS : RSQRTSS 8934 CPL : 3 8935 ATTRIBUTES : simd_scalar 8936 CATEGORY : SSE 8937 EXTENSION : SSE 8938 EXCEPTIONS: SSE_TYPE_5 8939 PATTERN : 0x0F 0x52 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 8940 OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss 8941 PATTERN : 0x0F 0x52 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 8942 OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss 8943 } 8944 { 8945 ICLASS : RCPSS 8946 CPL : 3 8947 ATTRIBUTES : simd_scalar 8948 CATEGORY : SSE 8949 EXTENSION : SSE 8950 EXCEPTIONS: SSE_TYPE_5 8951 PATTERN : 0x0F 0x53 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 8952 OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss 8953 PATTERN : 0x0F 0x53 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 8954 OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss 8955 } 8956 { 8957 ICLASS : MOVMSKPD 8958 CPL : 3 8959 CATEGORY : DATAXFER 8960 EXTENSION : SSE2 8961 EXCEPTIONS: SSE_TYPE_7 8962 PATTERN : 0x0F 0x50 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 8963 OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:pd 8964 } 8965 { 8966 ICLASS : SQRTPD 8967 CPL : 3 8968 CATEGORY : SSE 8969 EXTENSION : SSE2 8970 EXCEPTIONS: SSE_TYPE_2 8971 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 8972 PATTERN : 0x0F 0x51 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8973 OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd 8974 PATTERN : 0x0F 0x51 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 8975 OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd 8976 } 8977 { 8978 ICLASS : ANDPD 8979 CPL : 3 8980 CATEGORY : LOGICAL_FP 8981 EXTENSION : SSE2 8982 EXCEPTIONS: SSE_TYPE_4 8983 ATTRIBUTES : REQUIRES_ALIGNMENT 8984 PATTERN : 0x0F 0x54 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8985 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 8986 PATTERN : 0x0F 0x54 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 8987 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 8988 } 8989 { 8990 ICLASS : ANDNPD 8991 CPL : 3 8992 CATEGORY : LOGICAL_FP 8993 EXTENSION : SSE2 8994 EXCEPTIONS: SSE_TYPE_4 8995 ATTRIBUTES : REQUIRES_ALIGNMENT 8996 PATTERN : 0x0F 0x55 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 8997 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 8998 PATTERN : 0x0F 0x55 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 8999 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 9000 } 9001 { 9002 ICLASS : ORPD 9003 CPL : 3 9004 CATEGORY : LOGICAL_FP 9005 EXTENSION : SSE2 9006 EXCEPTIONS: SSE_TYPE_4 9007 ATTRIBUTES : REQUIRES_ALIGNMENT 9008 PATTERN : 0x0F 0x56 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9009 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 9010 PATTERN : 0x0F 0x56 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9011 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 9012 } 9013 { 9014 ICLASS : XORPD 9015 CPL : 3 9016 CATEGORY : LOGICAL_FP 9017 EXTENSION : SSE2 9018 EXCEPTIONS: SSE_TYPE_4 9019 ATTRIBUTES : REQUIRES_ALIGNMENT 9020 PATTERN : 0x0F 0x57 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9021 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 9022 PATTERN : 0x0F 0x57 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9023 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 9024 } 9025 { 9026 ICLASS : SQRTSD 9027 CPL : 3 9028 ATTRIBUTES : simd_scalar MXCSR 9029 CATEGORY : SSE 9030 EXTENSION : SSE2 9031 EXCEPTIONS: SSE_TYPE_3 9032 PATTERN : 0x0F 0x51 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 9033 OPERANDS : REG0=XMM_R():w:sd MEM0:r:sd 9034 PATTERN : 0x0F 0x51 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 9035 OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd 9036 } 9037 { 9038 ICLASS : PUNPCKLBW 9039 EXCEPTIONS: mmx-mem 9040 ATTRIBUTES: NOTSX 9041 CPL : 3 9042 CATEGORY : MMX 9043 EXTENSION : MMX 9044 ISA_SET : PENTIUMMMX 9045 PATTERN : 0x0F 0x60 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9046 OPERANDS : REG0=MMX_R():rw:q:u8 MEM0:r:d:u8 9047 9048 PATTERN : 0x0F 0x60 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9049 OPERANDS : REG0=MMX_R():rw:q:u8 REG1=MMX_B():r:d:u8 9050 } 9051 { 9052 ICLASS : PUNPCKLWD 9053 EXCEPTIONS: mmx-mem 9054 ATTRIBUTES: NOTSX 9055 CPL : 3 9056 CATEGORY : MMX 9057 EXTENSION : MMX 9058 ISA_SET : PENTIUMMMX 9059 PATTERN : 0x0F 0x61 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9060 OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:d:u16 9061 PATTERN : 0x0F 0x61 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9062 OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:d:u16 9063 } 9064 { 9065 ICLASS : PUNPCKLDQ 9066 ATTRIBUTES: NOTSX 9067 CPL : 3 9068 CATEGORY : MMX 9069 EXTENSION : MMX 9070 ISA_SET : PENTIUMMMX 9071 PATTERN : 0x0F 0x62 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9072 OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:d:u32 9073 PATTERN : 0x0F 0x62 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9074 OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:d:u32 9075 } 9076 { 9077 ICLASS : PACKSSWB 9078 EXCEPTIONS: mmx-mem 9079 CPL : 3 9080 CATEGORY : MMX 9081 EXTENSION : MMX 9082 ISA_SET : PENTIUMMMX 9083 ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX 9084 PATTERN : 0x0F 0x63 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9085 OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 9086 } 9087 { 9088 ICLASS : PACKSSWB 9089 CPL : 3 9090 CATEGORY : MMX 9091 EXTENSION : MMX 9092 ISA_SET : PENTIUMMMX 9093 ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX 9094 PATTERN : 0x0F 0x63 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9095 OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 9096 } 9097 { 9098 ICLASS : PCMPGTB 9099 EXCEPTIONS: mmx-mem 9100 ATTRIBUTES: NOTSX 9101 CPL : 3 9102 CATEGORY : MMX 9103 EXTENSION : MMX 9104 ISA_SET : PENTIUMMMX 9105 PATTERN : 0x0F 0x64 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9106 OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 9107 } 9108 { 9109 ICLASS : PCMPGTB 9110 ATTRIBUTES: NOTSX 9111 CPL : 3 9112 CATEGORY : MMX 9113 EXTENSION : MMX 9114 ISA_SET : PENTIUMMMX 9115 PATTERN : 0x0F 0x64 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9116 OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 9117 } 9118 { 9119 ICLASS : PCMPGTW 9120 EXCEPTIONS: mmx-mem 9121 ATTRIBUTES: NOTSX 9122 CPL : 3 9123 CATEGORY : MMX 9124 EXTENSION : MMX 9125 ISA_SET : PENTIUMMMX 9126 PATTERN : 0x0F 0x65 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9127 OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 9128 } 9129 { 9130 ICLASS : PCMPGTW 9131 ATTRIBUTES: NOTSX 9132 CPL : 3 9133 CATEGORY : MMX 9134 EXTENSION : MMX 9135 ISA_SET : PENTIUMMMX 9136 PATTERN : 0x0F 0x65 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9137 OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 9138 } 9139 { 9140 ICLASS : PCMPGTD 9141 EXCEPTIONS: mmx-mem 9142 ATTRIBUTES: NOTSX 9143 CPL : 3 9144 CATEGORY : MMX 9145 EXTENSION : MMX 9146 ISA_SET : PENTIUMMMX 9147 PATTERN : 0x0F 0x66 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9148 OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 9149 } 9150 { 9151 ICLASS : PCMPGTD 9152 ATTRIBUTES: NOTSX 9153 CPL : 3 9154 CATEGORY : MMX 9155 EXTENSION : MMX 9156 ISA_SET : PENTIUMMMX 9157 PATTERN : 0x0F 0x66 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9158 OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 9159 } 9160 { 9161 ICLASS : PACKUSWB 9162 EXCEPTIONS: mmx-mem 9163 CPL : 3 9164 CATEGORY : MMX 9165 EXTENSION : MMX 9166 ISA_SET : PENTIUMMMX 9167 ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX 9168 PATTERN : 0x0F 0x67 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9169 OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 9170 } 9171 { 9172 ICLASS : PACKUSWB 9173 CPL : 3 9174 CATEGORY : MMX 9175 EXTENSION : MMX 9176 ISA_SET : PENTIUMMMX 9177 ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX 9178 PATTERN : 0x0F 0x67 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9179 OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 9180 } 9181 { 9182 ICLASS : PUNPCKLBW 9183 CPL : 3 9184 CATEGORY : SSE 9185 EXTENSION : SSE2 9186 EXCEPTIONS: SSE_TYPE_4 9187 ATTRIBUTES : REQUIRES_ALIGNMENT 9188 COMMENT : mem form only uses q portion of the dq load. See SDM. 9189 PATTERN : 0x0F 0x60 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9190 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 9191 PATTERN : 0x0F 0x60 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9192 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q 9193 } 9194 { 9195 ICLASS : PUNPCKLWD 9196 CPL : 3 9197 CATEGORY : SSE 9198 EXTENSION : SSE2 9199 EXCEPTIONS: SSE_TYPE_4 9200 ATTRIBUTES : REQUIRES_ALIGNMENT 9201 COMMENT : mem form only uses q portion of the dq load. See SDM. 9202 PATTERN : 0x0F 0x61 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9203 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 9204 PATTERN : 0x0F 0x61 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9205 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q 9206 } 9207 { 9208 ICLASS : PUNPCKLDQ 9209 CPL : 3 9210 CATEGORY : SSE 9211 EXTENSION : SSE2 9212 EXCEPTIONS: SSE_TYPE_4 9213 ATTRIBUTES : REQUIRES_ALIGNMENT 9214 COMMENT : mem form only uses q portion of the dq load. See SDM. 9215 PATTERN : 0x0F 0x62 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9216 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 9217 PATTERN : 0x0F 0x62 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9218 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q 9219 } 9220 { 9221 ICLASS : PACKSSWB 9222 CPL : 3 9223 CATEGORY : SSE 9224 EXTENSION : SSE2 9225 EXCEPTIONS: SSE_TYPE_4 9226 ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT 9227 PATTERN : 0x0F 0x63 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9228 OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 9229 PATTERN : 0x0F 0x63 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9230 OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 9231 } 9232 { 9233 ICLASS : PCMPGTB 9234 CPL : 3 9235 CATEGORY : SSE 9236 EXTENSION : SSE2 9237 EXCEPTIONS: SSE_TYPE_4 9238 ATTRIBUTES : REQUIRES_ALIGNMENT 9239 PATTERN : 0x0F 0x64 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9240 OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 9241 PATTERN : 0x0F 0x64 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9242 OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 9243 } 9244 { 9245 ICLASS : PCMPGTW 9246 CPL : 3 9247 CATEGORY : SSE 9248 EXTENSION : SSE2 9249 EXCEPTIONS: SSE_TYPE_4 9250 ATTRIBUTES : REQUIRES_ALIGNMENT 9251 PATTERN : 0x0F 0x65 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9252 OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 9253 PATTERN : 0x0F 0x65 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9254 OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 9255 } 9256 { 9257 ICLASS : PCMPGTD 9258 CPL : 3 9259 CATEGORY : SSE 9260 EXTENSION : SSE2 9261 EXCEPTIONS: SSE_TYPE_4 9262 ATTRIBUTES : REQUIRES_ALIGNMENT 9263 PATTERN : 0x0F 0x66 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9264 OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 9265 PATTERN : 0x0F 0x66 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9266 OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 9267 } 9268 { 9269 ICLASS : PACKUSWB 9270 CPL : 3 9271 CATEGORY : SSE 9272 EXTENSION : SSE2 9273 EXCEPTIONS: SSE_TYPE_4 9274 ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT 9275 PATTERN : 0x0F 0x67 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9276 OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 9277 PATTERN : 0x0F 0x67 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9278 OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 9279 } 9280 { 9281 ICLASS : PSHUFW 9282 EXCEPTIONS: mmx-mem 9283 ATTRIBUTES: NOTSX 9284 CPL : 3 9285 CATEGORY : MMX 9286 EXTENSION : MMX 9287 ISA_SET : PENTIUMMMX 9288 PATTERN : 0x0F 0x70 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 9289 OPERANDS : REG0=MMX_R():w:q:u16 MEM0:r:q:u16 IMM0:r:b 9290 PATTERN : 0x0F 0x70 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 9291 OPERANDS : REG0=MMX_R():w:q:u16 REG1=MMX_B():r:q:u16 IMM0:r:b 9292 } 9293 { 9294 ICLASS : PCMPEQB 9295 EXCEPTIONS: mmx-mem 9296 ATTRIBUTES: NOTSX 9297 CPL : 3 9298 CATEGORY : MMX 9299 EXTENSION : MMX 9300 ISA_SET : PENTIUMMMX 9301 PATTERN : 0x0F 0x74 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9302 OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 9303 PATTERN : 0x0F 0x74 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9304 OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 9305 } 9306 { 9307 ICLASS : PCMPEQW 9308 EXCEPTIONS: mmx-mem 9309 ATTRIBUTES: NOTSX 9310 CPL : 3 9311 CATEGORY : MMX 9312 EXTENSION : MMX 9313 ISA_SET : PENTIUMMMX 9314 PATTERN : 0x0F 0x75 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9315 OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 9316 PATTERN : 0x0F 0x75 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9317 OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 9318 } 9319 { 9320 ICLASS : PCMPEQD 9321 EXCEPTIONS: mmx-mem 9322 ATTRIBUTES: NOTSX 9323 CPL : 3 9324 CATEGORY : MMX 9325 EXTENSION : MMX 9326 ISA_SET : PENTIUMMMX 9327 PATTERN : 0x0F 0x76 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9328 OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 9329 PATTERN : 0x0F 0x76 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9330 OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 9331 } 9332 { 9333 ICLASS : EMMS 9334 CPL : 3 9335 CATEGORY : MMX 9336 EXTENSION : MMX 9337 ISA_SET : PENTIUMMMX 9338 ATTRIBUTES : x87_mmx_state_w NOTSX 9339 PATTERN : 0x0F 0x77 no_refining_prefix 9340 OPERANDS : 9341 } 9342 { 9343 ICLASS : PSHUFD 9344 CPL : 3 9345 CATEGORY : SSE 9346 EXTENSION : SSE2 9347 EXCEPTIONS: SSE_TYPE_4 9348 ATTRIBUTES : REQUIRES_ALIGNMENT 9349 PATTERN : 0x0F 0x70 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() 9350 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b 9351 PATTERN : 0x0F 0x70 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() 9352 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b 9353 } 9354 { 9355 ICLASS : PCMPEQB 9356 CPL : 3 9357 CATEGORY : SSE 9358 EXTENSION : SSE2 9359 EXCEPTIONS: SSE_TYPE_4 9360 ATTRIBUTES : REQUIRES_ALIGNMENT 9361 PATTERN : 0x0F 0x74 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9362 OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 9363 PATTERN : 0x0F 0x74 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9364 OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 9365 } 9366 { 9367 ICLASS : PCMPEQW 9368 CPL : 3 9369 CATEGORY : SSE 9370 EXTENSION : SSE2 9371 EXCEPTIONS: SSE_TYPE_4 9372 ATTRIBUTES : REQUIRES_ALIGNMENT 9373 PATTERN : 0x0F 0x75 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9374 OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 9375 PATTERN : 0x0F 0x75 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9376 OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 9377 } 9378 { 9379 ICLASS : PCMPEQD 9380 CPL : 3 9381 CATEGORY : SSE 9382 EXTENSION : SSE2 9383 EXCEPTIONS: SSE_TYPE_4 9384 ATTRIBUTES : REQUIRES_ALIGNMENT 9385 PATTERN : 0x0F 0x76 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 9386 OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 9387 PATTERN : 0x0F 0x76 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 9388 OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 9389 } 9390 { 9391 ICLASS : PSHUFLW 9392 CPL : 3 9393 CATEGORY : SSE 9394 EXTENSION : SSE2 9395 EXCEPTIONS: SSE_TYPE_4 9396 ATTRIBUTES : REQUIRES_ALIGNMENT 9397 PATTERN : 0x0F 0x70 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() 9398 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b 9399 PATTERN : 0x0F 0x70 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() 9400 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b 9401 } 9402 { 9403 ICLASS : PSHUFHW 9404 CPL : 3 9405 CATEGORY : SSE 9406 EXTENSION : SSE2 9407 EXCEPTIONS: SSE_TYPE_4 9408 ATTRIBUTES : REQUIRES_ALIGNMENT 9409 PATTERN : 0x0F 0x70 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() 9410 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b 9411 PATTERN : 0x0F 0x70 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() 9412 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b 9413 } 9414 { 9415 ICLASS : JO 9416 CPL : 3 9417 CATEGORY : COND_BR 9418 EXTENSION : BASE 9419 ISA_SET : I86 9420 FLAGS : READONLY [ of-tst ] 9421 ATTRIBUTES: MPX_PREFIX_ABLE 9422 9423 PATTERN : 0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32() 9424 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 9425 } 9426 { 9427 ICLASS : JO 9428 CPL : 3 9429 CATEGORY : COND_BR 9430 EXTENSION : BASE 9431 ISA_SET : I86 9432 FLAGS : READONLY [ of-tst ] 9433 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 9434 PATTERN : 0x0F 0x80 not64 BRANCH_HINT() BRDISPz() 9435 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 9436 } 9437 9438 9439 { 9440 ICLASS : JNO 9441 CPL : 3 9442 CATEGORY : COND_BR 9443 EXTENSION : BASE 9444 ISA_SET : I86 9445 FLAGS : READONLY [ of-tst ] 9446 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 9447 PATTERN : 0x0F 0x81 not64 BRANCH_HINT() BRDISPz() 9448 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 9449 } 9450 { 9451 ICLASS : JNO 9452 CPL : 3 9453 CATEGORY : COND_BR 9454 EXTENSION : BASE 9455 ISA_SET : I86 9456 FLAGS : READONLY [ of-tst ] 9457 ATTRIBUTES: MPX_PREFIX_ABLE 9458 9459 PATTERN : 0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32() 9460 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 9461 } 9462 9463 9464 { 9465 ICLASS : JB 9466 CPL : 3 9467 CATEGORY : COND_BR 9468 EXTENSION : BASE 9469 ISA_SET : I86 9470 FLAGS : READONLY [ cf-tst ] 9471 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 9472 PATTERN : 0x0F 0x82 not64 BRANCH_HINT() BRDISPz() 9473 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 9474 } 9475 { 9476 ICLASS : JB 9477 CPL : 3 9478 CATEGORY : COND_BR 9479 EXTENSION : BASE 9480 ISA_SET : I86 9481 FLAGS : READONLY [ cf-tst ] 9482 ATTRIBUTES: MPX_PREFIX_ABLE 9483 9484 PATTERN : 0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32() 9485 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 9486 } 9487 9488 9489 9490 { 9491 ICLASS : JNB 9492 CPL : 3 9493 CATEGORY : COND_BR 9494 EXTENSION : BASE 9495 ISA_SET : I86 9496 FLAGS : READONLY [ cf-tst ] 9497 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 9498 PATTERN : 0x0F 0x83 not64 BRANCH_HINT() BRDISPz() 9499 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 9500 9501 } 9502 { 9503 ICLASS : JNB 9504 CPL : 3 9505 CATEGORY : COND_BR 9506 EXTENSION : BASE 9507 ISA_SET : I86 9508 FLAGS : READONLY [ cf-tst ] 9509 ATTRIBUTES: MPX_PREFIX_ABLE 9510 9511 PATTERN : 0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32() 9512 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 9513 } 9514 9515 9516 { 9517 ICLASS : JZ 9518 CPL : 3 9519 CATEGORY : COND_BR 9520 EXTENSION : BASE 9521 ISA_SET : I86 9522 FLAGS : READONLY [ zf-tst ] 9523 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 9524 PATTERN : 0x0F 0x84 not64 BRANCH_HINT() BRDISPz() 9525 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 9526 } 9527 { 9528 ICLASS : JZ 9529 CPL : 3 9530 CATEGORY : COND_BR 9531 EXTENSION : BASE 9532 ISA_SET : I86 9533 FLAGS : READONLY [ zf-tst ] 9534 ATTRIBUTES: MPX_PREFIX_ABLE 9535 9536 PATTERN : 0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32() 9537 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 9538 } 9539 9540 9541 { 9542 ICLASS : JNZ 9543 CPL : 3 9544 CATEGORY : COND_BR 9545 EXTENSION : BASE 9546 ISA_SET : I86 9547 FLAGS : READONLY [ zf-tst ] 9548 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 9549 PATTERN : 0x0F 0x85 not64 BRANCH_HINT() BRDISPz() 9550 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 9551 9552 } 9553 { 9554 ICLASS : JNZ 9555 CPL : 3 9556 CATEGORY : COND_BR 9557 EXTENSION : BASE 9558 ISA_SET : I86 9559 FLAGS : READONLY [ zf-tst ] 9560 ATTRIBUTES: MPX_PREFIX_ABLE 9561 9562 PATTERN : 0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32() 9563 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 9564 } 9565 9566 9567 9568 { 9569 ICLASS : JBE 9570 CPL : 3 9571 CATEGORY : COND_BR 9572 EXTENSION : BASE 9573 ISA_SET : I86 9574 FLAGS : READONLY [ cf-tst zf-tst ] 9575 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 9576 PATTERN : 0x0F 0x86 not64 BRANCH_HINT() BRDISPz() 9577 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 9578 } 9579 { 9580 ICLASS : JBE 9581 CPL : 3 9582 CATEGORY : COND_BR 9583 EXTENSION : BASE 9584 ISA_SET : I86 9585 FLAGS : READONLY [ cf-tst zf-tst ] 9586 ATTRIBUTES: MPX_PREFIX_ABLE 9587 9588 PATTERN : 0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32() 9589 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 9590 } 9591 9592 9593 9594 { 9595 ICLASS : JNBE 9596 CPL : 3 9597 CATEGORY : COND_BR 9598 EXTENSION : BASE 9599 ISA_SET : I86 9600 FLAGS : READONLY [ cf-tst zf-tst ] 9601 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 9602 PATTERN : 0x0F 0x87 not64 BRANCH_HINT() BRDISPz() 9603 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 9604 } 9605 { 9606 ICLASS : JNBE 9607 CPL : 3 9608 CATEGORY : COND_BR 9609 EXTENSION : BASE 9610 ISA_SET : I86 9611 FLAGS : READONLY [ cf-tst zf-tst ] 9612 ATTRIBUTES: MPX_PREFIX_ABLE 9613 9614 PATTERN : 0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32() 9615 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 9616 } 9617 9618 9619 9620 9621 { 9622 ICLASS : SETO 9623 CPL : 3 9624 CATEGORY : SETCC 9625 EXTENSION : BASE 9626 ISA_SET : I386 9627 ATTRIBUTES : BYTEOP 9628 FLAGS : READONLY [ of-tst ] 9629 PATTERN : 0x0F 0x90 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9630 OPERANDS : MEM0:w:b 9631 PATTERN : 0x0F 0x90 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9632 OPERANDS : REG0=GPR8_B():w 9633 } 9634 { 9635 ICLASS : SETNO 9636 CPL : 3 9637 CATEGORY : SETCC 9638 EXTENSION : BASE 9639 ISA_SET : I386 9640 ATTRIBUTES : BYTEOP 9641 FLAGS : READONLY [ of-tst ] 9642 PATTERN : 0x0F 0x91 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9643 OPERANDS : MEM0:w:b 9644 PATTERN : 0x0F 0x91 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9645 OPERANDS : REG0=GPR8_B():w 9646 } 9647 { 9648 ICLASS : SETB 9649 CPL : 3 9650 CATEGORY : SETCC 9651 EXTENSION : BASE 9652 ISA_SET : I386 9653 ATTRIBUTES : BYTEOP 9654 FLAGS : READONLY [ cf-tst ] 9655 PATTERN : 0x0F 0x92 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9656 OPERANDS : MEM0:w:b 9657 PATTERN : 0x0F 0x92 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9658 OPERANDS : REG0=GPR8_B():w 9659 } 9660 { 9661 ICLASS : SETNB 9662 CPL : 3 9663 CATEGORY : SETCC 9664 EXTENSION : BASE 9665 ISA_SET : I386 9666 ATTRIBUTES : BYTEOP 9667 FLAGS : READONLY [ cf-tst ] 9668 PATTERN : 0x0F 0x93 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9669 OPERANDS : MEM0:w:b 9670 PATTERN : 0x0F 0x93 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9671 OPERANDS : REG0=GPR8_B():w 9672 } 9673 { 9674 ICLASS : SETZ 9675 CPL : 3 9676 CATEGORY : SETCC 9677 EXTENSION : BASE 9678 ISA_SET : I386 9679 ATTRIBUTES : BYTEOP 9680 FLAGS : READONLY [ zf-tst ] 9681 PATTERN : 0x0F 0x94 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9682 OPERANDS : MEM0:w:b 9683 PATTERN : 0x0F 0x94 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9684 OPERANDS : REG0=GPR8_B():w 9685 } 9686 { 9687 ICLASS : SETNZ 9688 CPL : 3 9689 CATEGORY : SETCC 9690 EXTENSION : BASE 9691 ISA_SET : I386 9692 ATTRIBUTES : BYTEOP 9693 FLAGS : READONLY [ zf-tst ] 9694 PATTERN : 0x0F 0x95 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9695 OPERANDS : MEM0:w:b 9696 PATTERN : 0x0F 0x95 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9697 OPERANDS : REG0=GPR8_B():w 9698 } 9699 { 9700 ICLASS : SETBE 9701 CPL : 3 9702 CATEGORY : SETCC 9703 EXTENSION : BASE 9704 ISA_SET : I386 9705 ATTRIBUTES : BYTEOP 9706 FLAGS : READONLY [ cf-tst zf-tst ] 9707 PATTERN : 0x0F 0x96 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9708 OPERANDS : MEM0:w:b 9709 PATTERN : 0x0F 0x96 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9710 OPERANDS : REG0=GPR8_B():w 9711 } 9712 { 9713 ICLASS : SETNBE 9714 CPL : 3 9715 CATEGORY : SETCC 9716 EXTENSION : BASE 9717 ISA_SET : I386 9718 ATTRIBUTES : BYTEOP 9719 FLAGS : READONLY [ cf-tst zf-tst ] 9720 PATTERN : 0x0F 0x97 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9721 OPERANDS : MEM0:w:b 9722 PATTERN : 0x0F 0x97 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9723 OPERANDS : REG0=GPR8_B():w 9724 } 9725 { 9726 ICLASS : PUSH 9727 CPL : 3 9728 CATEGORY : PUSH 9729 EXTENSION : BASE 9730 ISA_SET : I86 9731 PATTERN : 0x0F 0xA0 DF64() 9732 OPERANDS : REG0=XED_REG_FS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP 9733 } 9734 { 9735 ICLASS : POP 9736 CPL : 3 9737 CATEGORY : POP 9738 EXTENSION : BASE 9739 ISA_SET : I86 9740 ATTRIBUTES: NOTSX 9741 PATTERN : 0x0F 0xA1 DF64() 9742 OPERANDS : REG0=XED_REG_FS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP 9743 } 9744 { 9745 ICLASS : CPUID 9746 ATTRIBUTES: NOTSX 9747 CPL : 3 9748 CATEGORY : MISC 9749 EXTENSION : BASE 9750 ISA_SET : I486REAL 9751 PATTERN : 0x0F 0xA2 9752 OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_EBX:w:SUPP REG2=XED_REG_ECX:crw:SUPP REG3=XED_REG_EDX:w:SUPP 9753 } 9754 { 9755 ICLASS : BT 9756 CPL : 3 9757 CATEGORY : BITBYTE 9758 EXTENSION : BASE 9759 ISA_SET : I386 9760 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 9761 PATTERN : 0x0F 0xA3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9762 OPERANDS : MEM0:r:v REG0=GPRv_R():r 9763 PATTERN : 0x0F 0xA3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9764 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 9765 } 9766 9767 { 9768 ICLASS : CMPXCHG_LOCK 9769 DISASM : cmpxchg 9770 CPL : 3 9771 CATEGORY : SEMAPHORE 9772 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 9773 EXTENSION : BASE 9774 ISA_SET : I486REAL 9775 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9776 PATTERN : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 9777 OPERANDS : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP 9778 } 9779 { 9780 ICLASS : CMPXCHG 9781 CPL : 3 9782 CATEGORY : SEMAPHORE 9783 ATTRIBUTES : BYTEOP LOCKABLE 9784 EXTENSION : BASE 9785 ISA_SET : I486REAL 9786 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9787 PATTERN : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 9788 OPERANDS : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP 9789 } 9790 { 9791 ICLASS : CMPXCHG 9792 CPL : 3 9793 CATEGORY : SEMAPHORE 9794 ATTRIBUTES : BYTEOP 9795 EXTENSION : BASE 9796 ISA_SET : I486REAL 9797 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9798 PATTERN : 0x0F 0xB0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9799 OPERANDS : REG0=GPR8_B():rcw REG1=GPR8_R():r REG2=XED_REG_AL:rcw:SUPP 9800 } 9801 9802 9803 9804 { 9805 ICLASS : CMPXCHG_LOCK 9806 DISASM : cmpxchg 9807 CPL : 3 9808 CATEGORY : SEMAPHORE 9809 EXTENSION : BASE 9810 ISA_SET : I486REAL 9811 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 9812 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9813 PATTERN : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 9814 OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP 9815 } 9816 { 9817 ICLASS : CMPXCHG 9818 CPL : 3 9819 CATEGORY : SEMAPHORE 9820 EXTENSION : BASE 9821 ISA_SET : I486REAL 9822 ATTRIBUTES : LOCKABLE 9823 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9824 PATTERN : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 9825 OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP 9826 } 9827 { 9828 ICLASS : CMPXCHG 9829 CPL : 3 9830 CATEGORY : SEMAPHORE 9831 EXTENSION : BASE 9832 ISA_SET : I486REAL 9833 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9834 PATTERN : 0x0F 0xB1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9835 OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=OrAX():rcw:SUPP 9836 } 9837 9838 9839 9840 { 9841 ICLASS : LSS 9842 CPL : 3 9843 CATEGORY : SEGOP 9844 EXTENSION : BASE 9845 ISA_SET : I386 9846 ATTRIBUTES: NOTSX 9847 PATTERN : 0x0F 0xB2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9848 OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_SS:w:SUPP 9849 } 9850 { 9851 ICLASS : BTR_LOCK 9852 DISASM : btr 9853 CPL : 3 9854 CATEGORY : BITBYTE 9855 EXTENSION : BASE 9856 ISA_SET : I386 9857 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 9858 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 9859 PATTERN : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 9860 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 9861 } 9862 { 9863 ICLASS : BTR 9864 CPL : 3 9865 CATEGORY : BITBYTE 9866 EXTENSION : BASE 9867 ISA_SET : I386 9868 ATTRIBUTES : LOCKABLE 9869 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 9870 PATTERN : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 9871 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 9872 } 9873 { 9874 ICLASS : BTR 9875 CPL : 3 9876 CATEGORY : BITBYTE 9877 EXTENSION : BASE 9878 ISA_SET : I386 9879 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 9880 PATTERN : 0x0F 0xB3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9881 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r 9882 } 9883 9884 { 9885 ICLASS : LFS 9886 CPL : 3 9887 CATEGORY : SEGOP 9888 EXTENSION : BASE 9889 ISA_SET : I386 9890 ATTRIBUTES: NOTSX 9891 PATTERN : 0x0F 0xB4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9892 OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_FS:w:SUPP 9893 } 9894 { 9895 ICLASS : LGS 9896 CPL : 3 9897 CATEGORY : SEGOP 9898 EXTENSION : BASE 9899 ISA_SET : I386 9900 ATTRIBUTES: NOTSX 9901 PATTERN : 0x0F 0xB5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9902 OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_GS:w:SUPP 9903 } 9904 { 9905 ICLASS : MOVZX 9906 CPL : 3 9907 CATEGORY : DATAXFER 9908 EXTENSION : BASE 9909 ISA_SET : I386 9910 PATTERN : 0x0F 0xB6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9911 OPERANDS : REG0=GPRv_R():w MEM0:r:b 9912 PATTERN : 0x0F 0xB6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9913 OPERANDS : REG0=GPRv_R():w REG1=GPR8_B():r 9914 PATTERN : 0x0F 0xB7 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9915 OPERANDS : REG0=GPRv_R():w MEM0:r:w 9916 PATTERN : 0x0F 0xB7 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9917 OPERANDS : REG0=GPRv_R():w REG1=GPR16_B():r 9918 } 9919 { 9920 ICLASS : XADD_LOCK 9921 DISASM : xadd 9922 CPL : 3 9923 CATEGORY : SEMAPHORE 9924 EXTENSION : BASE 9925 ISA_SET : I486REAL 9926 ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 9927 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9928 PATTERN : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 9929 OPERANDS : MEM0:rw:b REG0=GPR8_R():rw 9930 } 9931 { 9932 ICLASS : XADD 9933 CPL : 3 9934 CATEGORY : SEMAPHORE 9935 EXTENSION : BASE 9936 ISA_SET : I486REAL 9937 ATTRIBUTES : BYTEOP LOCKABLE 9938 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9939 PATTERN : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 9940 OPERANDS : MEM0:rw:b REG0=GPR8_R():rw 9941 } 9942 { 9943 ICLASS : XADD 9944 CPL : 3 9945 CATEGORY : SEMAPHORE 9946 EXTENSION : BASE 9947 ISA_SET : I486REAL 9948 ATTRIBUTES : BYTEOP 9949 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9950 PATTERN : 0x0F 0xC0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9951 OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():rw 9952 } 9953 9954 9955 9956 { 9957 ICLASS : XADD_LOCK 9958 DISASM : xadd 9959 CPL : 3 9960 CATEGORY : SEMAPHORE 9961 EXTENSION : BASE 9962 ISA_SET : I486REAL 9963 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 9964 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9965 9966 PATTERN : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 9967 OPERANDS : MEM0:rw:v REG0=GPRv_R():rw 9968 } 9969 { 9970 ICLASS : XADD 9971 CPL : 3 9972 CATEGORY : SEMAPHORE 9973 EXTENSION : BASE 9974 ISA_SET : I486REAL 9975 ATTRIBUTES : LOCKABLE 9976 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9977 9978 PATTERN : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 9979 OPERANDS : MEM0:rw:v REG0=GPRv_R():rw 9980 } 9981 { 9982 ICLASS : XADD 9983 CPL : 3 9984 CATEGORY : SEMAPHORE 9985 EXTENSION : BASE 9986 ISA_SET : I486REAL 9987 FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 9988 9989 PATTERN : 0x0F 0xC1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9990 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():rw 9991 } 9992 9993 9994 { 9995 ICLASS : CMPPS 9996 CPL : 3 9997 CATEGORY : SSE 9998 EXTENSION : SSE 9999 EXCEPTIONS: SSE_TYPE_2 10000 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 10001 PATTERN : 0x0F 0xC2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 10002 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b 10003 PATTERN : 0x0F 0xC2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 10004 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b 10005 } 10006 { 10007 ICLASS : MOVNTI 10008 CPL : 3 10009 CATEGORY : DATAXFER 10010 EXTENSION : SSE2 10011 ATTRIBUTES : IGNORES_OSFXSR NOTSX 10012 PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] EOSZ!=3 MODRM() 10013 OPERANDS : MEM0:w:d REG0=GPR32_R():r 10014 PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] EOSZ=3 MODRM() 10015 OPERANDS : MEM0:w:q REG0=GPR64_R():r 10016 } 10017 { 10018 ICLASS : PINSRW 10019 EXCEPTIONS: mmx-mem 10020 CPL : 3 10021 CATEGORY : MMX 10022 EXTENSION : MMX 10023 ISA_SET : PENTIUMMMX 10024 ATTRIBUTES : NOTSX 10025 PATTERN : 0x0F 0xC4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 10026 OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:w:u16 IMM0:r:b 10027 PATTERN : 0x0F 0xC4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 10028 OPERANDS : REG0=MMX_R():rw:q:u16 REG1=GPR32_B():r IMM0:r:b 10029 } 10030 { 10031 ICLASS : PEXTRW 10032 EXCEPTIONS: mmx-nomem 10033 ATTRIBUTES: NOTSX 10034 CPL : 3 10035 CATEGORY : MMX 10036 EXTENSION : MMX 10037 ISA_SET : PENTIUMMMX 10038 PATTERN : 0x0F 0xC5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 10039 OPERANDS : REG0=GPR32_R():w REG1=MMX_B():r:q:u16 IMM0:r:b 10040 } 10041 { 10042 ICLASS : SHUFPS 10043 CPL : 3 10044 CATEGORY : SSE 10045 EXTENSION : SSE 10046 EXCEPTIONS: SSE_TYPE_4 10047 ATTRIBUTES : REQUIRES_ALIGNMENT 10048 PATTERN : 0x0F 0xC6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 10049 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b 10050 PATTERN : 0x0F 0xC6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 10051 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b 10052 } 10053 { 10054 ICLASS : CMPSS 10055 CPL : 3 10056 ATTRIBUTES : simd_scalar MXCSR 10057 CATEGORY : SSE 10058 EXTENSION : SSE 10059 EXCEPTIONS: SSE_TYPE_3 10060 PATTERN : 0x0F 0xC2 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() 10061 OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss IMM0:r:b 10062 PATTERN : 0x0F 0xC2 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() 10063 OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss IMM0:r:b 10064 } 10065 { 10066 ICLASS : CMPPD 10067 CPL : 3 10068 CATEGORY : SSE 10069 EXTENSION : SSE2 10070 EXCEPTIONS: SSE_TYPE_2 10071 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 10072 PATTERN : 0x0F 0xC2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() 10073 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b 10074 PATTERN : 0x0F 0xC2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() 10075 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b 10076 } 10077 { 10078 ICLASS : PINSRW 10079 CPL : 3 10080 CATEGORY : SSE 10081 EXTENSION : SSE2 10082 EXCEPTIONS: SSE_TYPE_5 10083 ATTRIBUTES : 10084 PATTERN : 0x0F 0xC4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() 10085 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:w IMM0:r:b 10086 PATTERN : 0x0F 0xC4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() 10087 OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r IMM0:r:b 10088 } 10089 { 10090 ICLASS : PEXTRW 10091 CPL : 3 10092 CATEGORY : SSE 10093 EXTENSION : SSE2 10094 EXCEPTIONS: SSE_TYPE_5 10095 PATTERN : 0x0F 0xC5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() 10096 OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:dq IMM0:r:b 10097 } 10098 { 10099 ICLASS : SHUFPD 10100 CPL : 3 10101 CATEGORY : SSE 10102 EXTENSION : SSE2 10103 EXCEPTIONS: SSE_TYPE_4 10104 ATTRIBUTES : REQUIRES_ALIGNMENT 10105 PATTERN : 0x0F 0xC6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() 10106 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b 10107 PATTERN : 0x0F 0xC6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() 10108 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b 10109 } 10110 { 10111 ICLASS : CMPSD_XMM 10112 DISASM : cmpsd 10113 CPL : 3 10114 ATTRIBUTES : simd_scalar MXCSR 10115 CATEGORY : SSE 10116 EXTENSION : SSE2 10117 EXCEPTIONS: SSE_TYPE_3 10118 PATTERN : 0x0F 0xC2 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() 10119 OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd IMM0:r:b 10120 PATTERN : 0x0F 0xC2 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() 10121 OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd IMM0:r:b 10122 } 10123 { 10124 ICLASS : PSRLW 10125 EXCEPTIONS: mmx-mem 10126 ATTRIBUTES: NOTSX 10127 CPL : 3 10128 CATEGORY : MMX 10129 EXTENSION : MMX 10130 ISA_SET : PENTIUMMMX 10131 PATTERN : 0x0F 0xD1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10132 OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q 10133 } 10134 { 10135 ICLASS : PSRLW 10136 EXCEPTIONS: mmx-mem 10137 ATTRIBUTES: NOTSX 10138 CPL : 3 10139 CATEGORY : MMX 10140 EXTENSION : MMX 10141 ISA_SET : PENTIUMMMX 10142 PATTERN : 0x0F 0xD1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10143 OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q 10144 } 10145 { 10146 ICLASS : PSRLD 10147 EXCEPTIONS: mmx-mem 10148 ATTRIBUTES: NOTSX 10149 CPL : 3 10150 CATEGORY : MMX 10151 EXTENSION : MMX 10152 ISA_SET : PENTIUMMMX 10153 PATTERN : 0x0F 0xD2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10154 OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q 10155 } 10156 { 10157 ICLASS : PSRLD 10158 EXCEPTIONS: mmx-mem 10159 ATTRIBUTES: NOTSX 10160 CPL : 3 10161 CATEGORY : MMX 10162 EXTENSION : MMX 10163 ISA_SET : PENTIUMMMX 10164 PATTERN : 0x0F 0xD2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10165 OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q 10166 } 10167 { 10168 ICLASS : PSRLQ 10169 EXCEPTIONS: mmx-mem 10170 ATTRIBUTES: NOTSX 10171 CPL : 3 10172 CATEGORY : MMX 10173 EXTENSION : MMX 10174 ISA_SET : PENTIUMMMX 10175 PATTERN : 0x0F 0xD3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10176 OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q 10177 } 10178 { 10179 ICLASS : PSRLQ 10180 EXCEPTIONS: mmx-mem 10181 ATTRIBUTES: NOTSX 10182 CPL : 3 10183 CATEGORY : MMX 10184 EXTENSION : MMX 10185 ISA_SET : PENTIUMMMX 10186 PATTERN : 0x0F 0xD3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10187 OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q 10188 } 10189 { 10190 ICLASS : PADDQ 10191 EXCEPTIONS: mmx-mem 10192 ATTRIBUTES: NOTSX 10193 CPL : 3 10194 CATEGORY : MMX 10195 EXTENSION : SSE2 10196 PATTERN : 0x0F 0xD4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10197 OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q:u64 10198 PATTERN : 0x0F 0xD4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10199 OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q:u64 10200 } 10201 { 10202 ICLASS : PMULLW 10203 EXCEPTIONS: mmx-mem 10204 ATTRIBUTES: NOTSX 10205 CPL : 3 10206 CATEGORY : MMX 10207 EXTENSION : MMX 10208 ISA_SET : PENTIUMMMX 10209 PATTERN : 0x0F 0xD5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10210 OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 10211 PATTERN : 0x0F 0xD5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10212 OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 10213 } 10214 { 10215 ICLASS : PMOVMSKB 10216 EXCEPTIONS: mmx-nomem 10217 ATTRIBUTES: NOTSX 10218 CPL : 3 10219 CATEGORY : MMX 10220 EXTENSION : MMX 10221 ISA_SET : SSE 10222 COMMENT : KNI on PentiumIII. MMX instructions intro'd w/SSE 10223 PATTERN : 0x0F 0xD7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10224 OPERANDS : REG0=GPR32_R():w REG1=MMX_B():r:q:i8 10225 } 10226 { 10227 ICLASS : ADDSUBPD 10228 CPL : 3 10229 CATEGORY : SSE 10230 EXTENSION : SSE3 10231 EXCEPTIONS: SSE_TYPE_2 10232 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 10233 PATTERN : 0x0F 0xD0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10234 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 10235 PATTERN : 0x0F 0xD0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10236 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 10237 } 10238 { 10239 ICLASS : PSRLW 10240 CPL : 3 10241 CATEGORY : SSE 10242 EXTENSION : SSE2 10243 EXCEPTIONS: SSE_TYPE_4 10244 ATTRIBUTES : REQUIRES_ALIGNMENT 10245 PATTERN : 0x0F 0xD1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10246 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 10247 } 10248 { 10249 ICLASS : PSRLW 10250 CPL : 3 10251 CATEGORY : SSE 10252 EXTENSION : SSE2 10253 EXCEPTIONS: SSE_TYPE_7 10254 ATTRIBUTES : REQUIRES_ALIGNMENT 10255 PATTERN : 0x0F 0xD1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10256 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 10257 } 10258 10259 10260 10261 { 10262 ICLASS : PSRLD 10263 CPL : 3 10264 CATEGORY : SSE 10265 EXTENSION : SSE2 10266 EXCEPTIONS: SSE_TYPE_4 10267 ATTRIBUTES : REQUIRES_ALIGNMENT 10268 PATTERN : 0x0F 0xD2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10269 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 10270 } 10271 { 10272 ICLASS : PSRLD 10273 CPL : 3 10274 CATEGORY : SSE 10275 EXTENSION : SSE2 10276 EXCEPTIONS: SSE_TYPE_7 10277 ATTRIBUTES : REQUIRES_ALIGNMENT 10278 PATTERN : 0x0F 0xD2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10279 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 10280 } 10281 10282 10283 10284 10285 { 10286 ICLASS : PSRLQ 10287 CPL : 3 10288 CATEGORY : SSE 10289 EXTENSION : SSE2 10290 EXCEPTIONS: SSE_TYPE_4 10291 ATTRIBUTES : REQUIRES_ALIGNMENT 10292 PATTERN : 0x0F 0xD3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10293 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 10294 } 10295 { 10296 ICLASS : PSRLQ 10297 CPL : 3 10298 CATEGORY : SSE 10299 EXTENSION : SSE2 10300 EXCEPTIONS: SSE_TYPE_7 10301 ATTRIBUTES : REQUIRES_ALIGNMENT 10302 PATTERN : 0x0F 0xD3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10303 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 10304 } 10305 10306 10307 10308 10309 { 10310 ICLASS : PADDQ 10311 CPL : 3 10312 CATEGORY : SSE 10313 EXTENSION : SSE2 10314 EXCEPTIONS: SSE_TYPE_4 10315 ATTRIBUTES : REQUIRES_ALIGNMENT 10316 PATTERN : 0x0F 0xD4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10317 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 10318 PATTERN : 0x0F 0xD4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10319 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 10320 } 10321 { 10322 ICLASS : PMULLW 10323 CPL : 3 10324 CATEGORY : SSE 10325 EXTENSION : SSE2 10326 EXCEPTIONS: SSE_TYPE_4 10327 ATTRIBUTES : REQUIRES_ALIGNMENT 10328 PATTERN : 0x0F 0xD5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10329 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 10330 PATTERN : 0x0F 0xD5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10331 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 10332 } 10333 { 10334 ICLASS : PMOVMSKB 10335 CPL : 3 10336 CATEGORY : SSE 10337 EXTENSION : SSE2 10338 EXCEPTIONS: SSE_TYPE_7 10339 PATTERN : 0x0F 0xD7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10340 OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:dq:i8 10341 } 10342 { 10343 ICLASS : MOVQ2DQ 10344 CPL : 3 10345 CATEGORY : DATAXFER 10346 EXTENSION : SSE2 10347 ATTRIBUTES : MMX_EXCEPT NOTSX 10348 PATTERN : 0x0F 0xD6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 10349 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=MMX_B():r:q:u64 10350 } 10351 { 10352 ICLASS : ADDSUBPS 10353 CPL : 3 10354 CATEGORY : SSE 10355 EXTENSION : SSE3 10356 EXCEPTIONS: SSE_TYPE_2 10357 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 10358 PATTERN : 0x0F 0xD0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 10359 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 10360 PATTERN : 0x0F 0xD0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 10361 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 10362 } 10363 { 10364 ICLASS : MOVDQ2Q 10365 CPL : 3 10366 CATEGORY : DATAXFER 10367 EXTENSION : SSE2 10368 ATTRIBUTES : MMX_EXCEPT NOTSX 10369 PATTERN : 0x0F 0xD6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 10370 OPERANDS : REG0=MMX_R():w:q:u64 REG1=XMM_B():r:q:u64 10371 } 10372 { 10373 ICLASS : PAVGB 10374 EXCEPTIONS: mmx-mem 10375 ATTRIBUTES: NOTSX 10376 CPL : 3 10377 CATEGORY : MMX 10378 EXTENSION : MMX 10379 ISA_SET : PENTIUMMMX 10380 PATTERN : 0x0F 0xE0 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10381 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 10382 } 10383 { 10384 ICLASS : PAVGB 10385 ATTRIBUTES: NOTSX 10386 CPL : 3 10387 CATEGORY : MMX 10388 EXTENSION : MMX 10389 ISA_SET : PENTIUMMMX 10390 PATTERN : 0x0F 0xE0 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10391 OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 10392 } 10393 { 10394 ICLASS : PSRAW 10395 EXCEPTIONS: mmx-mem 10396 ATTRIBUTES: NOTSX 10397 CPL : 3 10398 CATEGORY : MMX 10399 EXTENSION : MMX 10400 ISA_SET : PENTIUMMMX 10401 PATTERN : 0x0F 0xE1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10402 OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q 10403 } 10404 { 10405 ICLASS : PSRAW 10406 EXCEPTIONS: mmx-mem 10407 ATTRIBUTES: NOTSX 10408 CPL : 3 10409 CATEGORY : MMX 10410 EXTENSION : MMX 10411 ISA_SET : PENTIUMMMX 10412 PATTERN : 0x0F 0xE1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10413 OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q 10414 } 10415 { 10416 ICLASS : PSRAD 10417 EXCEPTIONS: mmx-mem 10418 ATTRIBUTES: NOTSX 10419 CPL : 3 10420 CATEGORY : MMX 10421 EXTENSION : MMX 10422 ISA_SET : PENTIUMMMX 10423 PATTERN : 0x0F 0xE2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10424 OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q 10425 } 10426 { 10427 ICLASS : PSRAD 10428 EXCEPTIONS: mmx-mem 10429 ATTRIBUTES: NOTSX 10430 CPL : 3 10431 CATEGORY : MMX 10432 EXTENSION : MMX 10433 ISA_SET : PENTIUMMMX 10434 PATTERN : 0x0F 0xE2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10435 OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q 10436 } 10437 { 10438 ICLASS : PAVGW 10439 EXCEPTIONS: mmx-mem 10440 ATTRIBUTES: NOTSX 10441 CPL : 3 10442 CATEGORY : MMX 10443 EXTENSION : MMX 10444 ISA_SET : PENTIUMMMX 10445 PATTERN : 0x0F 0xE3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10446 OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 10447 } 10448 { 10449 ICLASS : PAVGW 10450 ATTRIBUTES: NOTSX 10451 CPL : 3 10452 CATEGORY : MMX 10453 EXTENSION : MMX 10454 ISA_SET : PENTIUMMMX 10455 PATTERN : 0x0F 0xE3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10456 OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 10457 } 10458 { 10459 ICLASS : PMULHUW 10460 EXCEPTIONS: mmx-mem 10461 ATTRIBUTES: NOTSX 10462 CPL : 3 10463 CATEGORY : MMX 10464 EXTENSION : MMX 10465 ISA_SET : PENTIUMMMX 10466 PATTERN : 0x0F 0xE4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10467 OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q:u16 10468 } 10469 { 10470 ICLASS : PMULHUW 10471 ATTRIBUTES: NOTSX 10472 CPL : 3 10473 CATEGORY : MMX 10474 EXTENSION : MMX 10475 ISA_SET : PENTIUMMMX 10476 PATTERN : 0x0F 0xE4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10477 OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q:u16 10478 } 10479 { 10480 ICLASS : PMULHW 10481 EXCEPTIONS: mmx-mem 10482 ATTRIBUTES: NOTSX 10483 CPL : 3 10484 CATEGORY : MMX 10485 EXTENSION : MMX 10486 ISA_SET : PENTIUMMMX 10487 PATTERN : 0x0F 0xE5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10488 OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 10489 } 10490 { 10491 ICLASS : PMULHW 10492 ATTRIBUTES: NOTSX 10493 CPL : 3 10494 CATEGORY : MMX 10495 EXTENSION : MMX 10496 ISA_SET : PENTIUMMMX 10497 PATTERN : 0x0F 0xE5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10498 OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 10499 } 10500 { 10501 ICLASS : MOVNTQ 10502 EXCEPTIONS: mmx-nofp2 10503 ATTRIBUTES: NOTSX 10504 CPL : 3 10505 CATEGORY : DATAXFER 10506 EXTENSION : MMX 10507 ISA_SET : PENTIUMMMX 10508 PATTERN : 0x0F 0xE7 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10509 OPERANDS : MEM0:w:q REG0=MMX_R():r:q 10510 } 10511 { 10512 ICLASS : PAVGB 10513 CPL : 3 10514 CATEGORY : SSE 10515 EXTENSION : SSE2 10516 EXCEPTIONS: SSE_TYPE_4 10517 ATTRIBUTES : REQUIRES_ALIGNMENT 10518 PATTERN : 0x0F 0xE0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10519 OPERANDS : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 10520 PATTERN : 0x0F 0xE0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10521 OPERANDS : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 10522 } 10523 10524 10525 { 10526 ICLASS : PSRAW 10527 CPL : 3 10528 CATEGORY : SSE 10529 EXTENSION : SSE2 10530 EXCEPTIONS: SSE_TYPE_4 10531 ATTRIBUTES : REQUIRES_ALIGNMENT 10532 PATTERN : 0x0F 0xE1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10533 OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:u64 10534 } 10535 { 10536 ICLASS : PSRAW 10537 CPL : 3 10538 CATEGORY : SSE 10539 EXTENSION : SSE2 10540 EXCEPTIONS: SSE_TYPE_7 10541 ATTRIBUTES : REQUIRES_ALIGNMENT 10542 PATTERN : 0x0F 0xE1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10543 OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:u64 10544 } 10545 10546 10547 10548 10549 { 10550 ICLASS : PSRAD 10551 CPL : 3 10552 CATEGORY : SSE 10553 EXTENSION : SSE2 10554 EXCEPTIONS: SSE_TYPE_4 10555 ATTRIBUTES : REQUIRES_ALIGNMENT 10556 PATTERN : 0x0F 0xE2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10557 OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:u64 10558 } 10559 { 10560 ICLASS : PSRAD 10561 CPL : 3 10562 CATEGORY : SSE 10563 EXTENSION : SSE2 10564 EXCEPTIONS: SSE_TYPE_7 10565 ATTRIBUTES : REQUIRES_ALIGNMENT 10566 PATTERN : 0x0F 0xE2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10567 OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:u64 10568 } 10569 10570 10571 10572 10573 { 10574 ICLASS : PAVGW 10575 CPL : 3 10576 CATEGORY : SSE 10577 EXTENSION : SSE2 10578 EXCEPTIONS: SSE_TYPE_4 10579 ATTRIBUTES : REQUIRES_ALIGNMENT 10580 PATTERN : 0x0F 0xE3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10581 OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16 10582 PATTERN : 0x0F 0xE3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10583 OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16 10584 } 10585 { 10586 ICLASS : PMULHUW 10587 CPL : 3 10588 CATEGORY : SSE 10589 EXTENSION : SSE2 10590 EXCEPTIONS: SSE_TYPE_4 10591 ATTRIBUTES : REQUIRES_ALIGNMENT 10592 PATTERN : 0x0F 0xE4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10593 OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16 10594 PATTERN : 0x0F 0xE4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10595 OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16 10596 } 10597 { 10598 ICLASS : PMULHW 10599 CPL : 3 10600 CATEGORY : SSE 10601 EXTENSION : SSE2 10602 EXCEPTIONS: SSE_TYPE_4 10603 ATTRIBUTES : REQUIRES_ALIGNMENT 10604 PATTERN : 0x0F 0xE5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10605 OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 10606 PATTERN : 0x0F 0xE5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10607 OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 10608 } 10609 { 10610 ICLASS : CVTTPD2DQ 10611 CPL : 3 10612 CATEGORY : CONVERT 10613 EXTENSION : SSE2 10614 EXCEPTIONS: SSE_TYPE_2 10615 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 10616 PATTERN : 0x0F 0xE6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10617 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64 10618 PATTERN : 0x0F 0xE6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10619 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64 10620 } 10621 { 10622 ICLASS : MOVNTDQ 10623 ATTRIBUTES: REQUIRES_ALIGNMENT NOTSX 10624 CPL : 3 10625 CATEGORY : DATAXFER 10626 EXTENSION : SSE2 10627 EXCEPTIONS: SSE_TYPE_1 10628 PATTERN : 0x0F 0xE7 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10629 OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq 10630 } 10631 { 10632 ICLASS : CVTDQ2PD 10633 CPL : 3 10634 CATEGORY : CONVERT 10635 EXTENSION : SSE2 10636 EXCEPTIONS: SSE_TYPE_5 10637 ATTRIBUTES : MXCSR 10638 PATTERN : 0x0F 0xE6 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 10639 OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32 10640 PATTERN : 0x0F 0xE6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 10641 OPERANDS : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:i32 10642 } 10643 { 10644 ICLASS : CVTPD2DQ 10645 CPL : 3 10646 CATEGORY : CONVERT 10647 EXTENSION : SSE2 10648 EXCEPTIONS: SSE_TYPE_2 10649 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 10650 PATTERN : 0x0F 0xE6 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 10651 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64 10652 PATTERN : 0x0F 0xE6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 10653 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64 10654 } 10655 { 10656 ICLASS : PSLLW 10657 EXCEPTIONS: mmx-mem 10658 ATTRIBUTES: NOTSX 10659 CPL : 3 10660 CATEGORY : MMX 10661 EXTENSION : MMX 10662 ISA_SET : PENTIUMMMX 10663 PATTERN : 0x0F 0xF1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10664 OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q 10665 PATTERN : 0x0F 0xF1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10666 OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q 10667 } 10668 { 10669 ICLASS : PSLLD 10670 EXCEPTIONS: mmx-mem 10671 ATTRIBUTES: NOTSX 10672 CPL : 3 10673 CATEGORY : MMX 10674 EXTENSION : MMX 10675 ISA_SET : PENTIUMMMX 10676 PATTERN : 0x0F 0xF2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10677 OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q 10678 PATTERN : 0x0F 0xF2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10679 OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q 10680 } 10681 { 10682 ICLASS : PSLLQ 10683 EXCEPTIONS: mmx-mem 10684 ATTRIBUTES: NOTSX 10685 CPL : 3 10686 CATEGORY : MMX 10687 EXTENSION : MMX 10688 ISA_SET : PENTIUMMMX 10689 PATTERN : 0x0F 0xF3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10690 OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q 10691 PATTERN : 0x0F 0xF3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10692 OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q 10693 } 10694 { 10695 ICLASS : PMULUDQ 10696 EXCEPTIONS: mmx-mem 10697 ATTRIBUTES: NOTSX 10698 CPL : 3 10699 CATEGORY : MMX 10700 EXTENSION : SSE2 10701 PATTERN : 0x0F 0xF4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10702 OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q:u32 10703 PATTERN : 0x0F 0xF4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10704 OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q:u32 10705 } 10706 { 10707 ICLASS : PMADDWD 10708 EXCEPTIONS: mmx-mem 10709 CPL : 3 10710 CATEGORY : MMX 10711 EXTENSION : MMX 10712 ISA_SET : PENTIUMMMX 10713 ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX 10714 PATTERN : 0x0F 0xF5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10715 OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 10716 PATTERN : 0x0F 0xF5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10717 OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 10718 } 10719 { 10720 ICLASS : PSADBW 10721 EXCEPTIONS: mmx-mem 10722 ATTRIBUTES: NOTSX 10723 CPL : 3 10724 CATEGORY : MMX 10725 EXTENSION : MMX 10726 ISA_SET : PENTIUMMMX 10727 PATTERN : 0x0F 0xF6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10728 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 10729 PATTERN : 0x0F 0xF6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10730 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 10731 } 10732 { 10733 ICLASS : MASKMOVQ 10734 EXCEPTIONS: mmx-nofp2 10735 CPL : 3 10736 CATEGORY : DATAXFER 10737 EXTENSION : MMX 10738 ISA_SET : PENTIUMMMX 10739 ATTRIBUTES : fixed_base0 maskop NOTSX 10740 PATTERN : 0x0F 0xF7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OVERRIDE_SEG0() 10741 OPERANDS : REG0=MMX_R():r:q:u8 REG1=MMX_B():r:q:i8 MEM0:w:q:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP 10742 } 10743 10744 10745 { 10746 ICLASS : PSLLW 10747 CPL : 3 10748 CATEGORY : SSE 10749 EXTENSION : SSE2 10750 EXCEPTIONS: SSE_TYPE_4 10751 ATTRIBUTES : REQUIRES_ALIGNMENT 10752 PATTERN : 0x0F 0xF1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10753 OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq 10754 } 10755 { 10756 ICLASS : PSLLW 10757 CPL : 3 10758 CATEGORY : SSE 10759 EXTENSION : SSE2 10760 EXCEPTIONS: SSE_TYPE_7 10761 ATTRIBUTES : REQUIRES_ALIGNMENT 10762 PATTERN : 0x0F 0xF1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10763 OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq 10764 } 10765 10766 10767 10768 { 10769 ICLASS : PSLLD 10770 CPL : 3 10771 CATEGORY : SSE 10772 EXTENSION : SSE2 10773 EXCEPTIONS: SSE_TYPE_4 10774 ATTRIBUTES : REQUIRES_ALIGNMENT 10775 PATTERN : 0x0F 0xF2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10776 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 10777 } 10778 { 10779 ICLASS : PSLLD 10780 CPL : 3 10781 CATEGORY : SSE 10782 EXTENSION : SSE2 10783 EXCEPTIONS: SSE_TYPE_7 10784 ATTRIBUTES : REQUIRES_ALIGNMENT 10785 PATTERN : 0x0F 0xF2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10786 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 10787 } 10788 10789 10790 10791 10792 10793 { 10794 ICLASS : PSLLQ 10795 CPL : 3 10796 CATEGORY : SSE 10797 EXTENSION : SSE2 10798 EXCEPTIONS: SSE_TYPE_4 10799 ATTRIBUTES : REQUIRES_ALIGNMENT 10800 PATTERN : 0x0F 0xF3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10801 OPERANDS : REG0=XMM_R():rw:dq:u64 MEM0:r:dq:u64 10802 } 10803 { 10804 ICLASS : PSLLQ 10805 CPL : 3 10806 CATEGORY : SSE 10807 EXTENSION : SSE2 10808 EXCEPTIONS: SSE_TYPE_7 10809 ATTRIBUTES : REQUIRES_ALIGNMENT 10810 PATTERN : 0x0F 0xF3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10811 OPERANDS : REG0=XMM_R():rw:dq:u64 REG1=XMM_B():r:dq:u64 10812 } 10813 10814 10815 10816 { 10817 ICLASS : PMULUDQ 10818 CPL : 3 10819 CATEGORY : SSE 10820 EXTENSION : SSE2 10821 EXCEPTIONS: SSE_TYPE_4 10822 ATTRIBUTES : REQUIRES_ALIGNMENT 10823 PATTERN : 0x0F 0xF4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10824 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 10825 PATTERN : 0x0F 0xF4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10826 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 10827 } 10828 { 10829 ICLASS : PMADDWD 10830 CPL : 3 10831 CATEGORY : SSE 10832 EXTENSION : SSE2 10833 EXCEPTIONS: SSE_TYPE_4 10834 ATTRIBUTES: REQUIRES_ALIGNMENT 10835 PATTERN : 0x0F 0xF5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10836 OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 10837 PATTERN : 0x0F 0xF5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10838 OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 10839 } 10840 { 10841 ICLASS : PSADBW 10842 CPL : 3 10843 CATEGORY : SSE 10844 EXTENSION : SSE2 10845 EXCEPTIONS: SSE_TYPE_4 10846 ATTRIBUTES : REQUIRES_ALIGNMENT 10847 PATTERN : 0x0F 0xF6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 10848 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 10849 PATTERN : 0x0F 0xF6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 10850 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 10851 } 10852 { 10853 ICLASS : MASKMOVDQU 10854 CPL : 3 10855 CATEGORY : DATAXFER 10856 EXTENSION : SSE2 10857 EXCEPTIONS: SSE_TYPE_4 10858 ATTRIBUTES : fixed_base0 maskop NOTSX 10859 PATTERN : 0x0F 0xF7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() OVERRIDE_SEG0() 10860 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq MEM0:w:dq:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP 10861 } 10862 { 10863 ICLASS : LDDQU 10864 CPL : 3 10865 CATEGORY : SSE 10866 EXTENSION : SSE3 10867 EXCEPTIONS: SSE_TYPE_4 10868 ATTRIBUTES : 10869 PATTERN : 0x0F 0xF0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() f2_refining_prefix 10870 OPERANDS : REG0=XMM_R():w:pd MEM0:r:dq 10871 } 10872 { 10873 ICLASS : INVD 10874 CPL : 0 10875 CATEGORY : SYSTEM 10876 EXTENSION : BASE 10877 ISA_SET : I486REAL 10878 ATTRIBUTES : RING0 NOTSX 10879 PATTERN : 0x0F 0x08 10880 OPERANDS : 10881 } 10882 { 10883 ICLASS : WBINVD 10884 CPL : 0 10885 CATEGORY : SYSTEM 10886 EXTENSION : BASE 10887 ISA_SET : I486REAL 10888 ATTRIBUTES : RING0 NOTSX 10889 PATTERN : 0x0F 0x09 10890 OPERANDS : 10891 } 10892 { 10893 ICLASS : UD2 10894 CPL : 3 10895 CATEGORY : MISC 10896 EXTENSION : BASE 10897 ISA_SET : PPRO 10898 ATTRIBUTES: NOTSX 10899 PATTERN : 0x0F 0x0B 10900 OPERANDS : 10901 } 10902 { 10903 ICLASS : MOVAPS 10904 CPL : 3 10905 CATEGORY : DATAXFER 10906 EXTENSION : SSE 10907 EXCEPTIONS: SSE_TYPE_1 10908 ATTRIBUTES : REQUIRES_ALIGNMENT 10909 PATTERN : 0x0F 0x28 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10910 OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps 10911 10912 PATTERN : 0x0F 0x28 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10913 OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps 10914 IFORM : MOVAPS_XMMps_XMMps_0F28 10915 10916 PATTERN : 0x0F 0x29 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10917 OPERANDS : MEM0:w:ps REG0=XMM_R():r:ps 10918 10919 PATTERN : 0x0F 0x29 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10920 OPERANDS : REG0=XMM_B():w:ps REG1=XMM_R():r:ps 10921 IFORM : MOVAPS_XMMps_XMMps_0F29 10922 } 10923 10924 { 10925 ICLASS : CVTPI2PS 10926 EXCEPTIONS: mmx-fp 10927 CPL : 3 10928 CATEGORY : CONVERT 10929 EXTENSION : SSE 10930 ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX 10931 PATTERN : 0x0F 0x2A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10932 OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:i32 10933 PATTERN : 0x0F 0x2A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10934 OPERANDS : REG0=XMM_R():w:q:f32 REG1=MMX_B():r:q:i32 10935 } 10936 { 10937 ICLASS : MOVNTPS 10938 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT 10939 CPL : 3 10940 CATEGORY : DATAXFER 10941 EXTENSION : SSE 10942 EXCEPTIONS: SSE_TYPE_1 10943 PATTERN : 0x0F 0x2B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10944 OPERANDS : MEM0:w:dq REG0=XMM_R():r:ps 10945 } 10946 { 10947 ICLASS : CVTTPS2PI 10948 EXCEPTIONS: mmx-fp 10949 CPL : 3 10950 CATEGORY : CONVERT 10951 EXTENSION : SSE 10952 ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX 10953 PATTERN : 0x0F 0x2C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10954 OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:q:f32 10955 PATTERN : 0x0F 0x2C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10956 OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32 10957 } 10958 { 10959 ICLASS : CVTPS2PI 10960 EXCEPTIONS: mmx-fp 10961 CPL : 3 10962 CATEGORY : CONVERT 10963 EXTENSION : SSE 10964 ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX 10965 PATTERN : 0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10966 OPERANDS : REG0=MMX_R():w:q:f32 MEM0:r:q:i32 10967 PATTERN : 0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10968 OPERANDS : REG0=MMX_R():w:q:f32 REG1=XMM_B():r:q:i32 10969 } 10970 { 10971 ICLASS : UCOMISS 10972 CPL : 3 10973 ATTRIBUTES : simd_scalar MXCSR 10974 CATEGORY : SSE 10975 EXTENSION : SSE 10976 EXCEPTIONS: SSE_TYPE_3 10977 FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] 10978 PATTERN : 0x0F 0x2E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10979 OPERANDS : REG0=XMM_R():r:ss MEM0:r:ss 10980 PATTERN : 0x0F 0x2E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10981 OPERANDS : REG0=XMM_R():r:ss REG1=XMM_B():r:ss 10982 } 10983 { 10984 ICLASS : COMISS 10985 CPL : 3 10986 ATTRIBUTES : simd_scalar MXCSR 10987 CATEGORY : SSE 10988 EXTENSION : SSE 10989 EXCEPTIONS: SSE_TYPE_3 10990 FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] 10991 PATTERN : 0x0F 0x2F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10992 OPERANDS : REG0=XMM_R():r:ss MEM0:r:ss 10993 PATTERN : 0x0F 0x2F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10994 OPERANDS : REG0=XMM_R():r:ss REG1=XMM_B():r:ss 10995 } 10996 { 10997 ICLASS : CVTSI2SS 10998 CPL : 3 10999 ATTRIBUTES : simd_scalar MXCSR 11000 CATEGORY : CONVERT 11001 EXTENSION : SSE 11002 EXCEPTIONS: SSE_TYPE_3 11003 PATTERN : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() 11004 OPERANDS : REG0=XMM_R():w:ss:f32 MEM0:r:d:i32 11005 PATTERN : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix 11006 OPERANDS : REG0=XMM_R():w:ss:f32 REG1=GPR32_B():r:d:i32 11007 PATTERN : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() 11008 OPERANDS : REG0=XMM_R():w:ss:f32 MEM0:r:q:i32 11009 PATTERN : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix 11010 OPERANDS : REG0=XMM_R():w:ss:f32 REG1=GPR64_B():r:q:i32 11011 } 11012 { 11013 ICLASS : CVTTSS2SI 11014 CPL : 3 11015 ATTRIBUTES : simd_scalar MXCSR 11016 CATEGORY : CONVERT 11017 EXTENSION : SSE 11018 EXCEPTIONS: SSE_TYPE_3 11019 PATTERN : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() 11020 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32 11021 PATTERN : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix 11022 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32 11023 PATTERN : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() 11024 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32 11025 PATTERN : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix 11026 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32 11027 } 11028 { 11029 ICLASS : CVTSS2SI 11030 CPL : 3 11031 ATTRIBUTES : simd_scalar MXCSR 11032 CATEGORY : CONVERT 11033 EXTENSION : SSE 11034 EXCEPTIONS: SSE_TYPE_3 11035 PATTERN : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() 11036 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32 11037 PATTERN : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix 11038 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32 11039 PATTERN : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() 11040 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32 11041 PATTERN : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix 11042 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32 11043 } 11044 { 11045 ICLASS : MOVAPD 11046 CPL : 3 11047 CATEGORY : DATAXFER 11048 EXTENSION : SSE2 11049 EXCEPTIONS: SSE_TYPE_1 11050 ATTRIBUTES : REQUIRES_ALIGNMENT 11051 PATTERN : 0x0F 0x28 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11052 OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd 11053 11054 PATTERN : 0x0F 0x28 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11055 OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd 11056 IFORM : MOVAPD_XMMpd_XMMpd_0F28 11057 11058 PATTERN : 0x0F 0x29 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11059 OPERANDS : MEM0:w:pd REG0=XMM_R():r:pd 11060 11061 PATTERN : 0x0F 0x29 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11062 OPERANDS : REG0=XMM_B():w:pd REG1=XMM_R():r:pd 11063 IFORM : MOVAPD_XMMpd_XMMpd_0F29 11064 } 11065 { 11066 ICLASS : CVTPI2PD 11067 EXCEPTIONS: mmx-nofp 11068 CPL : 3 11069 CATEGORY : CONVERT 11070 EXTENSION : SSE2 11071 ATTRIBUTES: MXCSR MMX_EXCEPT NOTSX 11072 PATTERN : 0x0F 0x2A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11073 OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32 11074 PATTERN : 0x0F 0x2A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11075 OPERANDS : REG0=XMM_R():w:pd:f64 REG1=MMX_B():r:q:i32 11076 } 11077 { 11078 ICLASS : MOVNTPD 11079 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT 11080 CPL : 3 11081 CATEGORY : DATAXFER 11082 EXTENSION : SSE2 11083 EXCEPTIONS: SSE_TYPE_1 11084 PATTERN : 0x0F 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11085 OPERANDS : MEM0:w:dq REG0=XMM_R():r:pd 11086 } 11087 { 11088 ICLASS : CVTTPD2PI 11089 EXCEPTIONS: mmx-fp-16align 11090 CPL : 3 11091 CATEGORY : CONVERT 11092 EXTENSION : SSE2 11093 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX 11094 PATTERN : 0x0F 0x2C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11095 OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64 11096 PATTERN : 0x0F 0x2C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11097 OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64 11098 } 11099 { 11100 ICLASS : CVTPD2PI 11101 EXCEPTIONS: mmx-fp-16align 11102 CPL : 3 11103 CATEGORY : CONVERT 11104 EXTENSION : SSE2 11105 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX 11106 PATTERN : 0x0F 0x2D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11107 OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64 11108 PATTERN : 0x0F 0x2D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11109 OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64 11110 } 11111 { 11112 ICLASS : UCOMISD 11113 CPL : 3 11114 ATTRIBUTES : simd_scalar MXCSR 11115 CATEGORY : SSE 11116 EXTENSION : SSE2 11117 EXCEPTIONS: SSE_TYPE_3 11118 FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] 11119 PATTERN : 0x0F 0x2E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11120 OPERANDS : REG0=XMM_R():r:sd MEM0:r:sd 11121 PATTERN : 0x0F 0x2E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11122 OPERANDS : REG0=XMM_R():r:sd REG1=XMM_B():r:sd 11123 } 11124 { 11125 ICLASS : COMISD 11126 CPL : 3 11127 ATTRIBUTES : simd_scalar MXCSR 11128 CATEGORY : SSE 11129 EXTENSION : SSE2 11130 EXCEPTIONS: SSE_TYPE_3 11131 FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] 11132 PATTERN : 0x0F 0x2F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11133 OPERANDS : REG0=XMM_R():r:sd MEM0:r:sd 11134 PATTERN : 0x0F 0x2F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11135 OPERANDS : REG0=XMM_R():r:sd REG1=XMM_B():r:sd 11136 } 11137 { 11138 ICLASS : CVTSI2SD 11139 CPL : 3 11140 ATTRIBUTES : simd_scalar MXCSR 11141 CATEGORY : CONVERT 11142 EXTENSION : SSE2 11143 EXCEPTIONS: SSE_TYPE_3 11144 PATTERN : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() 11145 OPERANDS : REG0=XMM_R():w:sd:f64 MEM0:r:d:i32 11146 PATTERN : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix 11147 OPERANDS : REG0=XMM_R():w:sd:f64 REG1=GPR32_B():r:d:i32 11148 PATTERN : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() 11149 OPERANDS : REG0=XMM_R():w:sd:f64 MEM0:r:q:i64 11150 PATTERN : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix 11151 OPERANDS : REG0=XMM_R():w:sd:f64 REG1=GPR64_B():r:q:i64 11152 } 11153 { 11154 ICLASS : CVTTSD2SI 11155 CPL : 3 11156 ATTRIBUTES : simd_scalar MXCSR 11157 CATEGORY : CONVERT 11158 EXTENSION : SSE2 11159 EXCEPTIONS: SSE_TYPE_3 11160 PATTERN : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() 11161 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64 11162 PATTERN : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix 11163 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64 11164 PATTERN : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() 11165 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64 11166 PATTERN : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix 11167 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64 11168 } 11169 { 11170 ICLASS : CVTSD2SI 11171 CPL : 3 11172 ATTRIBUTES : simd_scalar MXCSR 11173 CATEGORY : CONVERT 11174 EXTENSION : SSE2 11175 EXCEPTIONS: SSE_TYPE_3 11176 PATTERN : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() 11177 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64 11178 PATTERN : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix 11179 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64 11180 PATTERN : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() 11181 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64 11182 PATTERN : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix 11183 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64 11184 } 11185 { 11186 ICLASS : CMOVS 11187 CPL : 3 11188 CATEGORY : CMOV 11189 EXTENSION : BASE 11190 ISA_SET : PPRO 11191 FLAGS : READONLY [ sf-tst ] 11192 PATTERN : 0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11193 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 11194 } 11195 { 11196 ICLASS : CMOVS 11197 CPL : 3 11198 CATEGORY : CMOV 11199 EXTENSION : BASE 11200 ISA_SET : PPRO 11201 FLAGS : READONLY [ sf-tst ] 11202 PATTERN : 0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11203 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 11204 } 11205 { 11206 ICLASS : CMOVNS 11207 CPL : 3 11208 CATEGORY : CMOV 11209 EXTENSION : BASE 11210 ISA_SET : PPRO 11211 FLAGS : READONLY [ sf-tst ] 11212 PATTERN : 0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11213 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 11214 } 11215 { 11216 ICLASS : CMOVNS 11217 CPL : 3 11218 CATEGORY : CMOV 11219 EXTENSION : BASE 11220 ISA_SET : PPRO 11221 FLAGS : READONLY [ sf-tst ] 11222 PATTERN : 0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11223 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 11224 } 11225 { 11226 ICLASS : CMOVP 11227 CPL : 3 11228 CATEGORY : CMOV 11229 EXTENSION : BASE 11230 ISA_SET : PPRO 11231 FLAGS : READONLY [ pf-tst ] 11232 PATTERN : 0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11233 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 11234 } 11235 { 11236 ICLASS : CMOVP 11237 CPL : 3 11238 CATEGORY : CMOV 11239 EXTENSION : BASE 11240 ISA_SET : PPRO 11241 FLAGS : READONLY [ pf-tst ] 11242 PATTERN : 0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11243 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 11244 } 11245 { 11246 ICLASS : CMOVNP 11247 CPL : 3 11248 CATEGORY : CMOV 11249 EXTENSION : BASE 11250 ISA_SET : PPRO 11251 FLAGS : READONLY [ pf-tst ] 11252 PATTERN : 0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11253 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 11254 } 11255 { 11256 ICLASS : CMOVNP 11257 CPL : 3 11258 CATEGORY : CMOV 11259 EXTENSION : BASE 11260 ISA_SET : PPRO 11261 FLAGS : READONLY [ pf-tst ] 11262 PATTERN : 0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11263 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 11264 } 11265 { 11266 ICLASS : CMOVL 11267 CPL : 3 11268 CATEGORY : CMOV 11269 EXTENSION : BASE 11270 ISA_SET : PPRO 11271 FLAGS : READONLY [ sf-tst of-tst ] 11272 PATTERN : 0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11273 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 11274 } 11275 { 11276 ICLASS : CMOVL 11277 CPL : 3 11278 CATEGORY : CMOV 11279 EXTENSION : BASE 11280 ISA_SET : PPRO 11281 FLAGS : READONLY [ sf-tst of-tst ] 11282 PATTERN : 0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11283 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 11284 } 11285 { 11286 ICLASS : CMOVNL 11287 CPL : 3 11288 CATEGORY : CMOV 11289 EXTENSION : BASE 11290 ISA_SET : PPRO 11291 FLAGS : READONLY [ sf-tst of-tst ] 11292 PATTERN : 0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11293 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 11294 } 11295 { 11296 ICLASS : CMOVNL 11297 CPL : 3 11298 CATEGORY : CMOV 11299 EXTENSION : BASE 11300 ISA_SET : PPRO 11301 FLAGS : READONLY [ sf-tst of-tst ] 11302 PATTERN : 0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11303 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 11304 } 11305 { 11306 ICLASS : CMOVLE 11307 CPL : 3 11308 CATEGORY : CMOV 11309 EXTENSION : BASE 11310 ISA_SET : PPRO 11311 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 11312 PATTERN : 0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11313 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 11314 } 11315 { 11316 ICLASS : CMOVLE 11317 CPL : 3 11318 CATEGORY : CMOV 11319 EXTENSION : BASE 11320 ISA_SET : PPRO 11321 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 11322 PATTERN : 0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11323 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 11324 } 11325 { 11326 ICLASS : CMOVNLE 11327 CPL : 3 11328 CATEGORY : CMOV 11329 EXTENSION : BASE 11330 ISA_SET : PPRO 11331 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 11332 PATTERN : 0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11333 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 11334 } 11335 { 11336 ICLASS : CMOVNLE 11337 CPL : 3 11338 CATEGORY : CMOV 11339 EXTENSION : BASE 11340 ISA_SET : PPRO 11341 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 11342 PATTERN : 0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11343 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 11344 } 11345 { 11346 ICLASS : ADDPS 11347 CPL : 3 11348 CATEGORY : SSE 11349 EXTENSION : SSE 11350 EXCEPTIONS: SSE_TYPE_2 11351 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11352 PATTERN : 0x0F 0x58 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11353 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 11354 PATTERN : 0x0F 0x58 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11355 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 11356 } 11357 { 11358 ICLASS : MULPS 11359 CPL : 3 11360 CATEGORY : SSE 11361 EXTENSION : SSE 11362 EXCEPTIONS: SSE_TYPE_2 11363 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11364 PATTERN : 0x0F 0x59 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11365 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 11366 PATTERN : 0x0F 0x59 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11367 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 11368 } 11369 { 11370 ICLASS : CVTPS2PD 11371 CPL : 3 11372 CATEGORY : CONVERT 11373 EXTENSION : SSE2 11374 EXCEPTIONS: SSE_TYPE_3 11375 ATTRIBUTES: MXCSR 11376 PATTERN : 0x0F 0x5A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11377 OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:f32 11378 PATTERN : 0x0F 0x5A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11379 OPERANDS : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:f32 11380 } 11381 { 11382 ICLASS : CVTDQ2PS 11383 CPL : 3 11384 CATEGORY : CONVERT 11385 EXTENSION : SSE2 11386 EXCEPTIONS: SSE_TYPE_2 11387 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11388 PATTERN : 0x0F 0x5B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11389 OPERANDS : REG0=XMM_R():w:ps:f32 MEM0:r:dq:i32 11390 PATTERN : 0x0F 0x5B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11391 OPERANDS : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:dq:i32 11392 } 11393 { 11394 ICLASS : SUBPS 11395 CPL : 3 11396 CATEGORY : SSE 11397 EXTENSION : SSE 11398 EXCEPTIONS: SSE_TYPE_2 11399 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11400 PATTERN : 0x0F 0x5C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11401 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 11402 PATTERN : 0x0F 0x5C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11403 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 11404 } 11405 { 11406 ICLASS : MINPS 11407 CPL : 3 11408 CATEGORY : SSE 11409 EXTENSION : SSE 11410 EXCEPTIONS: SSE_TYPE_2 11411 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11412 PATTERN : 0x0F 0x5D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11413 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 11414 PATTERN : 0x0F 0x5D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11415 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 11416 } 11417 { 11418 ICLASS : DIVPS 11419 CPL : 3 11420 CATEGORY : SSE 11421 EXTENSION : SSE 11422 EXCEPTIONS: SSE_TYPE_2 11423 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11424 PATTERN : 0x0F 0x5E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11425 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 11426 PATTERN : 0x0F 0x5E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11427 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 11428 } 11429 { 11430 ICLASS : MAXPS 11431 CPL : 3 11432 CATEGORY : SSE 11433 EXTENSION : SSE 11434 EXCEPTIONS: SSE_TYPE_2 11435 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11436 PATTERN : 0x0F 0x5F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11437 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 11438 PATTERN : 0x0F 0x5F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11439 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 11440 } 11441 { 11442 ICLASS : ADDSS 11443 CPL : 3 11444 ATTRIBUTES : simd_scalar MXCSR 11445 CATEGORY : SSE 11446 EXTENSION : SSE 11447 EXCEPTIONS: SSE_TYPE_3 11448 PATTERN : 0x0F 0x58 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11449 OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss 11450 PATTERN : 0x0F 0x58 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11451 OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss 11452 } 11453 { 11454 ICLASS : MULSS 11455 CPL : 3 11456 ATTRIBUTES : simd_scalar MXCSR 11457 CATEGORY : SSE 11458 EXTENSION : SSE 11459 EXCEPTIONS: SSE_TYPE_3 11460 PATTERN : 0x0F 0x59 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11461 OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss 11462 PATTERN : 0x0F 0x59 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11463 OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss 11464 } 11465 { 11466 ICLASS : CVTSS2SD 11467 CPL : 3 11468 ATTRIBUTES : simd_scalar MXCSR 11469 CATEGORY : CONVERT 11470 EXTENSION : SSE2 11471 EXCEPTIONS: SSE_TYPE_3 11472 PATTERN : 0x0F 0x5A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11473 OPERANDS : REG0=XMM_R():w:sd:f64 MEM0:r:ss:f32 11474 PATTERN : 0x0F 0x5A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11475 OPERANDS : REG0=XMM_R():w:sd:f64 REG1=XMM_B():r:ss:f32 11476 } 11477 { 11478 ICLASS : CVTTPS2DQ 11479 CPL : 3 11480 CATEGORY : CONVERT 11481 EXTENSION : SSE2 11482 EXCEPTIONS: SSE_TYPE_2 11483 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11484 PATTERN : 0x0F 0x5B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11485 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32 11486 PATTERN : 0x0F 0x5B f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11487 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32 11488 } 11489 { 11490 ICLASS : SUBSS 11491 CPL : 3 11492 ATTRIBUTES : simd_scalar MXCSR 11493 CATEGORY : SSE 11494 EXTENSION : SSE 11495 EXCEPTIONS: SSE_TYPE_3 11496 PATTERN : 0x0F 0x5C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11497 OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss 11498 PATTERN : 0x0F 0x5C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11499 OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss 11500 } 11501 { 11502 ICLASS : MINSS 11503 CPL : 3 11504 ATTRIBUTES : simd_scalar MXCSR 11505 CATEGORY : SSE 11506 EXTENSION : SSE 11507 EXCEPTIONS: SSE_TYPE_3 11508 PATTERN : 0x0F 0x5D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11509 OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss 11510 PATTERN : 0x0F 0x5D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11511 OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss 11512 } 11513 { 11514 ICLASS : DIVSS 11515 CPL : 3 11516 ATTRIBUTES : simd_scalar MXCSR 11517 CATEGORY : SSE 11518 EXTENSION : SSE 11519 EXCEPTIONS: SSE_TYPE_3 11520 PATTERN : 0x0F 0x5E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11521 OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss 11522 PATTERN : 0x0F 0x5E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11523 OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss 11524 } 11525 { 11526 ICLASS : MAXSS 11527 CPL : 3 11528 ATTRIBUTES : simd_scalar MXCSR 11529 CATEGORY : SSE 11530 EXTENSION : SSE 11531 EXCEPTIONS: SSE_TYPE_3 11532 PATTERN : 0x0F 0x5F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11533 OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss 11534 PATTERN : 0x0F 0x5F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11535 OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss 11536 } 11537 { 11538 ICLASS : ADDPD 11539 CPL : 3 11540 CATEGORY : SSE 11541 EXTENSION : SSE2 11542 EXCEPTIONS: SSE_TYPE_2 11543 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11544 PATTERN : 0x0F 0x58 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11545 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 11546 PATTERN : 0x0F 0x58 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11547 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 11548 } 11549 { 11550 ICLASS : MULPD 11551 CPL : 3 11552 CATEGORY : SSE 11553 EXTENSION : SSE2 11554 EXCEPTIONS: SSE_TYPE_2 11555 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11556 PATTERN : 0x0F 0x59 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11557 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 11558 PATTERN : 0x0F 0x59 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11559 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 11560 } 11561 { 11562 ICLASS : CVTPD2PS 11563 CPL : 3 11564 CATEGORY : CONVERT 11565 EXTENSION : SSE2 11566 EXCEPTIONS: SSE_TYPE_2 11567 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11568 PATTERN : 0x0F 0x5A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11569 OPERANDS : REG0=XMM_R():w:ps:f32 MEM0:r:pd:f64 11570 PATTERN : 0x0F 0x5A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11571 OPERANDS : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:pd:f64 11572 } 11573 { 11574 ICLASS : CVTPS2DQ 11575 CPL : 3 11576 CATEGORY : CONVERT 11577 EXTENSION : SSE2 11578 EXCEPTIONS: SSE_TYPE_2 11579 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11580 PATTERN : 0x0F 0x5B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11581 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32 11582 PATTERN : 0x0F 0x5B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11583 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32 11584 } 11585 { 11586 ICLASS : SUBPD 11587 CPL : 3 11588 CATEGORY : SSE 11589 EXTENSION : SSE2 11590 EXCEPTIONS: SSE_TYPE_2 11591 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11592 PATTERN : 0x0F 0x5C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11593 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 11594 PATTERN : 0x0F 0x5C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11595 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 11596 } 11597 { 11598 ICLASS : MINPD 11599 CPL : 3 11600 CATEGORY : SSE 11601 EXTENSION : SSE2 11602 EXCEPTIONS: SSE_TYPE_2 11603 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11604 PATTERN : 0x0F 0x5D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11605 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 11606 PATTERN : 0x0F 0x5D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11607 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 11608 } 11609 { 11610 ICLASS : DIVPD 11611 CPL : 3 11612 CATEGORY : SSE 11613 EXTENSION : SSE2 11614 EXCEPTIONS: SSE_TYPE_2 11615 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 11616 PATTERN : 0x0F 0x5E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11617 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 11618 PATTERN : 0x0F 0x5E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11619 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 11620 } 11621 { 11622 ICLASS : MAXPD 11623 CPL : 3 11624 CATEGORY : SSE 11625 EXTENSION : SSE2 11626 EXCEPTIONS: SSE_TYPE_2 11627 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MXCSR 11628 PATTERN : 0x0F 0x5F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11629 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 11630 PATTERN : 0x0F 0x5F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11631 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 11632 } 11633 { 11634 ICLASS : ADDSD 11635 CPL : 3 11636 ATTRIBUTES : simd_scalar MXCSR 11637 CATEGORY : SSE 11638 EXTENSION : SSE2 11639 EXCEPTIONS: SSE_TYPE_3 11640 PATTERN : 0x0F 0x58 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11641 OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd 11642 PATTERN : 0x0F 0x58 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11643 OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd 11644 } 11645 { 11646 ICLASS : MULSD 11647 CPL : 3 11648 ATTRIBUTES : simd_scalar MXCSR 11649 CATEGORY : SSE 11650 EXTENSION : SSE2 11651 EXCEPTIONS: SSE_TYPE_3 11652 PATTERN : 0x0F 0x59 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11653 OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd 11654 PATTERN : 0x0F 0x59 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11655 OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd 11656 } 11657 { 11658 ICLASS : CVTSD2SS 11659 CPL : 3 11660 ATTRIBUTES : simd_scalar MXCSR 11661 CATEGORY : CONVERT 11662 EXTENSION : SSE2 11663 EXCEPTIONS: SSE_TYPE_3 11664 PATTERN : 0x0F 0x5A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11665 OPERANDS : REG0=XMM_R():w:ss:f32 MEM0:r:sd:f64 11666 PATTERN : 0x0F 0x5A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11667 OPERANDS : REG0=XMM_R():w:ss:f32 REG1=XMM_B():r:sd:f64 11668 } 11669 { 11670 ICLASS : SUBSD 11671 CPL : 3 11672 ATTRIBUTES : simd_scalar MXCSR 11673 CATEGORY : SSE 11674 EXTENSION : SSE2 11675 EXCEPTIONS: SSE_TYPE_3 11676 PATTERN : 0x0F 0x5C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11677 OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd 11678 PATTERN : 0x0F 0x5C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11679 OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd 11680 } 11681 { 11682 ICLASS : MINSD 11683 CPL : 3 11684 ATTRIBUTES : simd_scalar MXCSR 11685 CATEGORY : SSE 11686 EXTENSION : SSE2 11687 EXCEPTIONS: SSE_TYPE_3 11688 PATTERN : 0x0F 0x5D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11689 OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd 11690 PATTERN : 0x0F 0x5D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11691 OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd 11692 } 11693 { 11694 ICLASS : DIVSD 11695 CPL : 3 11696 ATTRIBUTES : simd_scalar MXCSR 11697 CATEGORY : SSE 11698 EXTENSION : SSE2 11699 EXCEPTIONS: SSE_TYPE_3 11700 PATTERN : 0x0F 0x5E f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11701 OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd 11702 PATTERN : 0x0F 0x5E f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11703 OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd 11704 } 11705 { 11706 ICLASS : MAXSD 11707 CPL : 3 11708 ATTRIBUTES : simd_scalar MXCSR 11709 CATEGORY : SSE 11710 EXTENSION : SSE2 11711 EXCEPTIONS: SSE_TYPE_3 11712 PATTERN : 0x0F 0x5F f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11713 OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd 11714 PATTERN : 0x0F 0x5F f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11715 OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd 11716 } 11717 { 11718 ICLASS : PUNPCKHBW 11719 EXCEPTIONS: mmx-mem 11720 CPL : 3 11721 CATEGORY : MMX 11722 EXTENSION : MMX 11723 ISA_SET : PENTIUMMMX 11724 ATTRIBUTES : SKIPLOW32 NOTSX 11725 PATTERN : 0x0F 0x68 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11726 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 11727 PATTERN : 0x0F 0x68 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11728 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d 11729 } 11730 { 11731 ICLASS : PUNPCKHWD 11732 EXCEPTIONS: mmx-mem 11733 CPL : 3 11734 CATEGORY : MMX 11735 EXTENSION : MMX 11736 ISA_SET : PENTIUMMMX 11737 ATTRIBUTES : SKIPLOW32 NOTSX 11738 PATTERN : 0x0F 0x69 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11739 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 11740 PATTERN : 0x0F 0x69 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11741 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d 11742 } 11743 { 11744 ICLASS : PUNPCKHDQ 11745 EXCEPTIONS: mmx-mem 11746 CPL : 3 11747 CATEGORY : MMX 11748 EXTENSION : MMX 11749 ISA_SET : PENTIUMMMX 11750 ATTRIBUTES : SKIPLOW32 NOTSX 11751 PATTERN : 0x0F 0x6A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11752 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 11753 PATTERN : 0x0F 0x6A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11754 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d 11755 } 11756 { 11757 ICLASS : PACKSSDW 11758 EXCEPTIONS: mmx-mem 11759 CPL : 3 11760 CATEGORY : MMX 11761 EXTENSION : MMX 11762 ISA_SET : PENTIUMMMX 11763 ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX 11764 PATTERN : 0x0F 0x6B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11765 OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 11766 } 11767 { 11768 ICLASS : PACKSSDW 11769 CPL : 3 11770 CATEGORY : MMX 11771 EXTENSION : MMX 11772 ISA_SET : PENTIUMMMX 11773 ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX 11774 PATTERN : 0x0F 0x6B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11775 OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 11776 } 11777 { 11778 ICLASS : MOVD 11779 CPL : 3 11780 CATEGORY : DATAXFER 11781 EXTENSION : SSE2 11782 EXCEPTIONS: SSE_TYPE_5 11783 ATTRIBUTES : 11784 PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM() 11785 OPERANDS : REG0=XMM_R():w:dq MEM0:r:d 11786 PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix 11787 OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r 11788 PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() 11789 OPERANDS : REG0=XMM_R():w:dq MEM0:r:d 11790 PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64 11791 OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r 11792 11793 11794 PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM() 11795 OPERANDS : MEM0:w:d REG0=XMM_R():r:d 11796 PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix 11797 OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:d 11798 PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() 11799 OPERANDS : MEM0:w:d REG0=XMM_R():r:d 11800 PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64 11801 OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:d 11802 } 11803 { 11804 ICLASS : MOVD 11805 CPL : 3 11806 CATEGORY : DATAXFER 11807 EXTENSION : MMX 11808 ISA_SET : PENTIUMMMX 11809 ATTRIBUTES : NOTSX 11810 PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() 11811 OPERANDS : REG0=MMX_R():w:q MEM0:r:d 11812 11813 PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix 11814 OPERANDS : REG0=MMX_R():w:q REG1=GPR32_B():r 11815 11816 PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() 11817 OPERANDS : REG0=MMX_R():w:q MEM0:r:d 11818 11819 PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 11820 OPERANDS : REG0=MMX_R():w:q REG1=GPR32_B():r 11821 11822 11823 PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() 11824 OPERANDS : MEM0:w:d REG0=MMX_R():r:d 11825 11826 PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix 11827 OPERANDS : REG0=GPR32_B():w REG1=MMX_R():r:d 11828 11829 PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() 11830 OPERANDS : MEM0:w:d REG0=MMX_R():r:d 11831 11832 PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 11833 OPERANDS : REG0=GPR32_B():w REG1=MMX_R():r:d 11834 } 11835 11836 11837 { 11838 ICLASS : MOVQ 11839 CPL : 3 11840 CATEGORY : DATAXFER 11841 EXTENSION : SSE2 11842 EXCEPTIONS: SSE_TYPE_5 11843 ATTRIBUTES : 11844 PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM() 11845 OPERANDS : REG0=XMM_R():w:dq MEM0:r:q 11846 IFORM : MOVQ_XMMdq_MEMq_0F6E 11847 11848 PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix 11849 OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r 11850 11851 PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM() 11852 OPERANDS : MEM0:w:q REG0=XMM_R():r:q 11853 IFORM : MOVQ_MEMq_XMMq_0F7E 11854 11855 PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix 11856 OPERANDS : REG0=GPR64_B():w REG1=XMM_R():r:q 11857 11858 PATTERN : 0x0F 0xD6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11859 OPERANDS : MEM0:w:q REG0=XMM_R():r:q 11860 IFORM : MOVQ_MEMq_XMMq_0FD6 11861 11862 PATTERN : 0x0F 0xD6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11863 OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q 11864 IFORM : MOVQ_XMMdq_XMMq_0FD6 11865 11866 PATTERN : 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11867 OPERANDS : REG0=XMM_R():w:dq MEM0:r:q 11868 IFORM : MOVQ_XMMdq_MEMq_0F7E 11869 11870 PATTERN : 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 11871 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q 11872 IFORM : MOVQ_XMMdq_XMMq_0F7E 11873 } 11874 11875 11876 { 11877 ICLASS : MOVQ 11878 EXCEPTIONS: mmx-nofp2 # FIXME guessing here... 11879 ATTRIBUTES: NOTSX 11880 CPL : 3 11881 CATEGORY : DATAXFER 11882 EXTENSION : MMX 11883 ISA_SET : PENTIUMMMX 11884 11885 PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() 11886 OPERANDS : REG0=MMX_R():w:q MEM0:r:q 11887 IFORM : MOVQ_MMXq_MEMq_0F6E 11888 11889 PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix 11890 OPERANDS : REG0=MMX_R():w:q REG1=GPR64_B():r 11891 11892 PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() 11893 OPERANDS : MEM0:w:q REG0=MMX_R():r:q 11894 IFORM : MOVQ_MEMq_MMXq_0F7E 11895 11896 PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix 11897 OPERANDS : REG0=GPR64_B():w REG1=MMX_R():r:q 11898 11899 PATTERN : 0x0F 0x6F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11900 OPERANDS : REG0=MMX_R():w:q MEM0:r:q 11901 IFORM : MOVQ_MMXq_MEMq_0F6F 11902 11903 PATTERN : 0x0F 0x6F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11904 OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q 11905 IFORM : MOVQ_MMXq_MMXq_0F6F 11906 11907 PATTERN : 0x0F 0x7F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 11908 OPERANDS : MEM0:w:q REG0=MMX_R():r:q 11909 IFORM : MOVQ_MEMq_MMXq_0F7F 11910 11911 PATTERN : 0x0F 0x7F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 11912 OPERANDS : REG0=MMX_B():w:q REG1=MMX_R():r:q 11913 IFORM : MOVQ_MMXq_MMXq_0F7F 11914 } 11915 11916 { 11917 ICLASS : PUNPCKHBW 11918 CPL : 3 11919 CATEGORY : SSE 11920 EXTENSION : SSE2 11921 EXCEPTIONS: SSE_TYPE_4 11922 ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT 11923 PATTERN : 0x0F 0x68 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11924 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 11925 PATTERN : 0x0F 0x68 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11926 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q 11927 } 11928 { 11929 ICLASS : PUNPCKHWD 11930 CPL : 3 11931 CATEGORY : SSE 11932 EXTENSION : SSE2 11933 EXCEPTIONS: SSE_TYPE_4 11934 ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT 11935 PATTERN : 0x0F 0x69 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11936 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 11937 PATTERN : 0x0F 0x69 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11938 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q 11939 } 11940 { 11941 ICLASS : PUNPCKHDQ 11942 CPL : 3 11943 CATEGORY : SSE 11944 EXTENSION : SSE2 11945 EXCEPTIONS: SSE_TYPE_4 11946 ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT 11947 PATTERN : 0x0F 0x6A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11948 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 11949 PATTERN : 0x0F 0x6A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11950 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q 11951 } 11952 { 11953 ICLASS : PACKSSDW 11954 CPL : 3 11955 CATEGORY : SSE 11956 EXTENSION : SSE2 11957 EXCEPTIONS: SSE_TYPE_4 11958 ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT 11959 PATTERN : 0x0F 0x6B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11960 OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 11961 PATTERN : 0x0F 0x6B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11962 OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 11963 } 11964 { 11965 ICLASS : PUNPCKLQDQ 11966 CPL : 3 11967 CATEGORY : SSE 11968 EXTENSION : SSE2 11969 EXCEPTIONS: SSE_TYPE_4 11970 ATTRIBUTES : REQUIRES_ALIGNMENT 11971 COMMENT : mem form only uses q portion of the dq load. See SDM. 11972 PATTERN : 0x0F 0x6C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11973 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 11974 PATTERN : 0x0F 0x6C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11975 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q 11976 } 11977 { 11978 ICLASS : PUNPCKHQDQ 11979 CPL : 3 11980 CATEGORY : SSE 11981 EXTENSION : SSE2 11982 EXCEPTIONS: SSE_TYPE_4 11983 ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT 11984 PATTERN : 0x0F 0x6D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 11985 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 11986 PATTERN : 0x0F 0x6D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 11987 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q 11988 } 11989 { 11990 ICLASS : MOVDQU 11991 CPL : 3 11992 CATEGORY : DATAXFER 11993 EXTENSION : SSE2 11994 EXCEPTIONS: SSE_TYPE_4M 11995 ATTRIBUTES : 11996 PATTERN : 0x0F 0x6F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 11997 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 11998 11999 PATTERN : 0x0F 0x6F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 12000 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 12001 IFORM : MOVDQU_XMMdq_XMMdq_0F6F 12002 12003 PATTERN : 0x0F 0x7F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 12004 OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq 12005 12006 PATTERN : 0x0F 0x7F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 12007 OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq 12008 IFORM : MOVDQU_XMMdq_XMMdq_0F7F 12009 } 12010 { 12011 ICLASS : VMREAD 12012 CPL : 3 12013 CATEGORY : VTX 12014 EXTENSION : VTX 12015 PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() 12016 OPERANDS : MEM0:rw:q REG0=GPR64_R():r 12017 12018 PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() 12019 OPERANDS : REG0=GPR64_B():rw REG1=GPR64_R():r 12020 12021 PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() 12022 OPERANDS : MEM0:rw:d REG0=GPR32_R():r 12023 12024 PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() 12025 OPERANDS : REG0=GPR32_B():rw REG1=GPR32_R():r 12026 } 12027 { 12028 ICLASS : VMWRITE 12029 CPL : 3 12030 CATEGORY : VTX 12031 EXTENSION : VTX 12032 PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() 12033 OPERANDS : REG0=GPR64_R():r MEM0:r:q 12034 12035 PATTERN : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() 12036 OPERANDS : REG0=GPR64_R():r REG1=GPR64_B():r 12037 12038 PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() 12039 OPERANDS : REG0=GPR32_R():r MEM0:r:d 12040 12041 PATTERN : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() 12042 OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r 12043 } 12044 { 12045 ICLASS : HADDPD 12046 CPL : 3 12047 CATEGORY : SSE 12048 EXTENSION : SSE3 12049 EXCEPTIONS: SSE_TYPE_2 12050 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 12051 PATTERN : 0x0F 0x7C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12052 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 12053 PATTERN : 0x0F 0x7C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12054 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 12055 } 12056 { 12057 ICLASS : HSUBPD 12058 CPL : 3 12059 CATEGORY : SSE 12060 EXTENSION : SSE3 12061 EXCEPTIONS: SSE_TYPE_2 12062 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 12063 PATTERN : 0x0F 0x7D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12064 OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd 12065 PATTERN : 0x0F 0x7D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12066 OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd 12067 } 12068 { 12069 ICLASS : MOVDQA 12070 CPL : 3 12071 CATEGORY : DATAXFER 12072 EXTENSION : SSE2 12073 EXCEPTIONS: SSE_TYPE_1 12074 ATTRIBUTES : REQUIRES_ALIGNMENT 12075 PATTERN : 0x0F 0x7F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12076 OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq 12077 12078 PATTERN : 0x0F 0x7F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12079 OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq 12080 IFORM : MOVDQA_XMMdq_XMMdq_0F7F 12081 12082 PATTERN : 0x0F 0x6F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12083 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 12084 12085 PATTERN : 0x0F 0x6F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12086 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 12087 IFORM : MOVDQA_XMMdq_XMMdq_0F6F 12088 } 12089 { 12090 ICLASS : HADDPS 12091 CPL : 3 12092 CATEGORY : SSE 12093 EXTENSION : SSE3 12094 EXCEPTIONS: SSE_TYPE_2 12095 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 12096 PATTERN : 0x0F 0x7C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 12097 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 12098 PATTERN : 0x0F 0x7C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 12099 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 12100 } 12101 { 12102 ICLASS : HSUBPS 12103 CPL : 3 12104 CATEGORY : SSE 12105 EXTENSION : SSE3 12106 EXCEPTIONS: SSE_TYPE_2 12107 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 12108 PATTERN : 0x0F 0x7D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 12109 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps 12110 PATTERN : 0x0F 0x7D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 12111 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps 12112 } 12113 { 12114 ICLASS : JS 12115 CPL : 3 12116 CATEGORY : COND_BR 12117 EXTENSION : BASE 12118 ISA_SET : I86 12119 FLAGS : READONLY [ sf-tst ] 12120 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 12121 PATTERN : 0x0F 0x88 not64 BRANCH_HINT() BRDISPz() 12122 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 12123 } 12124 { 12125 ICLASS : JS 12126 CPL : 3 12127 CATEGORY : COND_BR 12128 EXTENSION : BASE 12129 ISA_SET : I86 12130 FLAGS : READONLY [ sf-tst ] 12131 ATTRIBUTES: MPX_PREFIX_ABLE 12132 12133 PATTERN : 0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32() 12134 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 12135 } 12136 12137 12138 { 12139 ICLASS : JNS 12140 CPL : 3 12141 CATEGORY : COND_BR 12142 EXTENSION : BASE 12143 ISA_SET : I86 12144 FLAGS : READONLY [ sf-tst ] 12145 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 12146 PATTERN : 0x0F 0x89 not64 BRANCH_HINT() BRDISPz() 12147 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 12148 } 12149 { 12150 ICLASS : JNS 12151 CPL : 3 12152 CATEGORY : COND_BR 12153 EXTENSION : BASE 12154 ISA_SET : I86 12155 FLAGS : READONLY [ sf-tst ] 12156 ATTRIBUTES: MPX_PREFIX_ABLE 12157 12158 PATTERN : 0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32() 12159 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 12160 } 12161 12162 12163 12164 { 12165 ICLASS : JP 12166 CPL : 3 12167 CATEGORY : COND_BR 12168 EXTENSION : BASE 12169 ISA_SET : I86 12170 FLAGS : READONLY [ pf-tst ] 12171 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 12172 PATTERN : 0x0F 0x8A not64 BRANCH_HINT() BRDISPz() 12173 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 12174 } 12175 { 12176 ICLASS : JP 12177 CPL : 3 12178 CATEGORY : COND_BR 12179 EXTENSION : BASE 12180 ISA_SET : I86 12181 FLAGS : READONLY [ pf-tst ] 12182 ATTRIBUTES: MPX_PREFIX_ABLE 12183 12184 PATTERN : 0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32() 12185 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 12186 } 12187 12188 12189 { 12190 ICLASS : JNP 12191 CPL : 3 12192 CATEGORY : COND_BR 12193 EXTENSION : BASE 12194 ISA_SET : I86 12195 FLAGS : READONLY [ pf-tst ] 12196 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 12197 PATTERN : 0x0F 0x8B not64 BRANCH_HINT() BRDISPz() 12198 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 12199 } 12200 { 12201 ICLASS : JNP 12202 CPL : 3 12203 CATEGORY : COND_BR 12204 EXTENSION : BASE 12205 ISA_SET : I86 12206 FLAGS : READONLY [ pf-tst ] 12207 ATTRIBUTES: MPX_PREFIX_ABLE 12208 12209 PATTERN : 0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32() 12210 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 12211 } 12212 12213 12214 { 12215 ICLASS : JL 12216 CPL : 3 12217 CATEGORY : COND_BR 12218 EXTENSION : BASE 12219 ISA_SET : I86 12220 FLAGS : READONLY [ sf-tst of-tst ] 12221 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 12222 PATTERN : 0x0F 0x8C not64 BRANCH_HINT() BRDISPz() 12223 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 12224 } 12225 { 12226 ICLASS : JL 12227 CPL : 3 12228 CATEGORY : COND_BR 12229 EXTENSION : BASE 12230 ISA_SET : I86 12231 FLAGS : READONLY [ sf-tst of-tst ] 12232 ATTRIBUTES: MPX_PREFIX_ABLE 12233 12234 PATTERN : 0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32() 12235 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 12236 } 12237 12238 12239 12240 { 12241 ICLASS : JNL 12242 CPL : 3 12243 CATEGORY : COND_BR 12244 EXTENSION : BASE 12245 ISA_SET : I86 12246 FLAGS : READONLY [ sf-tst of-tst ] 12247 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 12248 PATTERN : 0x0F 0x8D not64 BRANCH_HINT() BRDISPz() 12249 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 12250 } 12251 { 12252 ICLASS : JNL 12253 CPL : 3 12254 CATEGORY : COND_BR 12255 EXTENSION : BASE 12256 ISA_SET : I86 12257 FLAGS : READONLY [ sf-tst of-tst ] 12258 ATTRIBUTES: MPX_PREFIX_ABLE 12259 12260 PATTERN : 0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32() 12261 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 12262 } 12263 12264 12265 12266 { 12267 ICLASS : JLE 12268 CPL : 3 12269 CATEGORY : COND_BR 12270 EXTENSION : BASE 12271 ISA_SET : I86 12272 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 12273 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 12274 PATTERN : 0x0F 0x8E not64 BRANCH_HINT() BRDISPz() 12275 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 12276 } 12277 { 12278 ICLASS : JLE 12279 CPL : 3 12280 CATEGORY : COND_BR 12281 EXTENSION : BASE 12282 ISA_SET : I86 12283 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 12284 ATTRIBUTES: MPX_PREFIX_ABLE 12285 12286 PATTERN : 0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32() 12287 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 12288 } 12289 12290 12291 12292 { 12293 ICLASS : JNLE 12294 CPL : 3 12295 CATEGORY : COND_BR 12296 EXTENSION : BASE 12297 ISA_SET : I86 12298 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 12299 ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE 12300 PATTERN : 0x0F 0x8F not64 BRANCH_HINT() BRDISPz() 12301 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP 12302 } 12303 { 12304 ICLASS : JNLE 12305 CPL : 3 12306 CATEGORY : COND_BR 12307 EXTENSION : BASE 12308 ISA_SET : I86 12309 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 12310 ATTRIBUTES: MPX_PREFIX_ABLE 12311 12312 PATTERN : 0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32() 12313 OPERANDS : RELBR:r:d REG0=rIP():rw:SUPP 12314 } 12315 12316 12317 { 12318 ICLASS : SETS 12319 CPL : 3 12320 CATEGORY : SETCC 12321 EXTENSION : BASE 12322 ISA_SET : I386 12323 ATTRIBUTES : BYTEOP 12324 FLAGS : READONLY [ sf-tst ] 12325 PATTERN : 0x0F 0x98 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12326 OPERANDS : MEM0:w:b 12327 PATTERN : 0x0F 0x98 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12328 OPERANDS : REG0=GPR8_B():w 12329 } 12330 { 12331 ICLASS : SETNS 12332 CPL : 3 12333 CATEGORY : SETCC 12334 EXTENSION : BASE 12335 ISA_SET : I386 12336 ATTRIBUTES : BYTEOP 12337 FLAGS : READONLY [ sf-tst ] 12338 PATTERN : 0x0F 0x99 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12339 OPERANDS : MEM0:w:b 12340 PATTERN : 0x0F 0x99 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12341 OPERANDS : REG0=GPR8_B():w 12342 } 12343 { 12344 ICLASS : SETP 12345 CPL : 3 12346 CATEGORY : SETCC 12347 EXTENSION : BASE 12348 ISA_SET : I386 12349 ATTRIBUTES : BYTEOP 12350 FLAGS : READONLY [ pf-tst ] 12351 PATTERN : 0x0F 0x9A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12352 OPERANDS : MEM0:w:b 12353 PATTERN : 0x0F 0x9A MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12354 OPERANDS : REG0=GPR8_B():w 12355 } 12356 { 12357 ICLASS : SETNP 12358 CPL : 3 12359 CATEGORY : SETCC 12360 EXTENSION : BASE 12361 ISA_SET : I386 12362 ATTRIBUTES : BYTEOP 12363 FLAGS : READONLY [ pf-tst ] 12364 PATTERN : 0x0F 0x9B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12365 OPERANDS : MEM0:w:b 12366 PATTERN : 0x0F 0x9B MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12367 OPERANDS : REG0=GPR8_B():w 12368 } 12369 { 12370 ICLASS : SETL 12371 CPL : 3 12372 CATEGORY : SETCC 12373 EXTENSION : BASE 12374 ISA_SET : I386 12375 ATTRIBUTES : BYTEOP 12376 FLAGS : READONLY [ sf-tst of-tst ] 12377 PATTERN : 0x0F 0x9C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12378 OPERANDS : MEM0:w:b 12379 PATTERN : 0x0F 0x9C MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12380 OPERANDS : REG0=GPR8_B():w 12381 } 12382 { 12383 ICLASS : SETNL 12384 CPL : 3 12385 CATEGORY : SETCC 12386 EXTENSION : BASE 12387 ISA_SET : I386 12388 ATTRIBUTES : BYTEOP 12389 FLAGS : READONLY [ sf-tst of-tst ] 12390 PATTERN : 0x0F 0x9D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12391 OPERANDS : MEM0:w:b 12392 PATTERN : 0x0F 0x9D MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12393 OPERANDS : REG0=GPR8_B():w 12394 } 12395 { 12396 ICLASS : SETLE 12397 CPL : 3 12398 CATEGORY : SETCC 12399 EXTENSION : BASE 12400 ISA_SET : I386 12401 ATTRIBUTES : BYTEOP 12402 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 12403 PATTERN : 0x0F 0x9E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12404 OPERANDS : MEM0:w:b 12405 PATTERN : 0x0F 0x9E MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12406 OPERANDS : REG0=GPR8_B():w 12407 } 12408 { 12409 ICLASS : SETNLE 12410 CPL : 3 12411 CATEGORY : SETCC 12412 EXTENSION : BASE 12413 ISA_SET : I386 12414 ATTRIBUTES : BYTEOP 12415 FLAGS : READONLY [ sf-tst of-tst zf-tst ] 12416 PATTERN : 0x0F 0x9F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12417 OPERANDS : MEM0:w:b 12418 PATTERN : 0x0F 0x9F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12419 OPERANDS : REG0=GPR8_B():w 12420 } 12421 { 12422 ICLASS : PUSH 12423 CPL : 3 12424 CATEGORY : PUSH 12425 EXTENSION : BASE 12426 ISA_SET : I86 12427 PATTERN : 0x0F 0xA8 DF64() 12428 OPERANDS : REG0=XED_REG_GS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP 12429 } 12430 { 12431 ICLASS : POP 12432 CPL : 3 12433 CATEGORY : POP 12434 EXTENSION : BASE 12435 ISA_SET : I86 12436 ATTRIBUTES: NOTSX 12437 PATTERN : 0x0F 0xA9 DF64() 12438 OPERANDS : REG0=XED_REG_GS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP 12439 } 12440 { 12441 ICLASS : RSM 12442 CPL : 3 12443 CATEGORY : SYSRET 12444 EXTENSION : BASE 12445 ISA_SET : I486 12446 ATTRIBUTES: NOTSX 12447 FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-mod rf-mod nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 12448 PATTERN : 0x0F 0xAA 12449 OPERANDS : REG0=rIP():w:SUPP 12450 } 12451 12452 { 12453 ICLASS : BTS_LOCK 12454 DISASM : bts 12455 CPL : 3 12456 CATEGORY : BITBYTE 12457 EXTENSION : BASE 12458 ISA_SET : I386 12459 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 12460 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 12461 PATTERN : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 12462 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 12463 } 12464 { 12465 ICLASS : BTS 12466 CPL : 3 12467 CATEGORY : BITBYTE 12468 EXTENSION : BASE 12469 ISA_SET : I386 12470 ATTRIBUTES : LOCKABLE 12471 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 12472 PATTERN : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 12473 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 12474 } 12475 { 12476 ICLASS : BTS 12477 CPL : 3 12478 CATEGORY : BITBYTE 12479 EXTENSION : BASE 12480 ISA_SET : I386 12481 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 12482 PATTERN : 0x0F 0xAB MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12483 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r 12484 } 12485 12486 12487 12488 { 12489 ICLASS : SHRD 12490 CPL : 3 12491 CATEGORY : SHIFT 12492 EXTENSION : BASE 12493 ISA_SET : I386 12494 FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 12495 PATTERN : 0x0F 0xAC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 12496 OPERANDS : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b 12497 12498 PATTERN : 0x0F 0xAC MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 12499 OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b 12500 } 12501 { 12502 ICLASS : SHRD 12503 CPL : 3 12504 CATEGORY : SHIFT 12505 EXTENSION : BASE 12506 ISA_SET : I386 12507 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 12508 PATTERN : 0x0F 0xAD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12509 OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL 12510 12511 PATTERN : 0x0F 0xAD MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12512 OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL 12513 } 12514 12515 { 12516 ICLASS : SHLD 12517 CPL : 3 12518 CATEGORY : SHIFT 12519 EXTENSION : BASE 12520 ISA_SET : I386 12521 FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 12522 PATTERN : 0x0F 0xA4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 12523 OPERANDS : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b 12524 12525 PATTERN : 0x0F 0xA4 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 12526 OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b 12527 } 12528 12529 { 12530 ICLASS : SHLD 12531 CPL : 3 12532 CATEGORY : SHIFT 12533 EXTENSION : BASE 12534 ISA_SET : I386 12535 FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] 12536 PATTERN : 0x0F 0xA5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12537 OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL 12538 12539 PATTERN : 0x0F 0xA5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12540 OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL 12541 } 12542 12543 { 12544 ICLASS : IMUL 12545 CPL : 3 12546 CATEGORY : BINARY 12547 EXTENSION : BASE 12548 ISA_SET : I86 12549 FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] 12550 PATTERN : 0x0F 0xAF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12551 OPERANDS : REG0=GPRv_R():rw MEM0:r:v 12552 12553 PATTERN : 0x0F 0xAF MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12554 OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r 12555 } 12556 12557 { 12558 ICLASS : BTC_LOCK 12559 DISASM : btc 12560 CPL : 3 12561 CATEGORY : BITBYTE 12562 EXTENSION : BASE 12563 ISA_SET : I386 12564 ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE 12565 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 12566 12567 PATTERN : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix 12568 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 12569 } 12570 { 12571 ICLASS : BTC 12572 CPL : 3 12573 CATEGORY : BITBYTE 12574 EXTENSION : BASE 12575 ISA_SET : I386 12576 ATTRIBUTES : LOCKABLE 12577 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 12578 12579 PATTERN : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix 12580 OPERANDS : MEM0:rw:v REG0=GPRv_R():r 12581 } 12582 { 12583 ICLASS : BTC 12584 CPL : 3 12585 CATEGORY : BITBYTE 12586 EXTENSION : BASE 12587 ISA_SET : I386 12588 FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] 12589 12590 PATTERN : 0x0F 0xBB MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12591 OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r 12592 } 12593 12594 12595 { 12596 ICLASS : BSF 12597 CPL : 3 12598 CATEGORY : BITBYTE 12599 EXTENSION : BASE 12600 ISA_SET : I386 12601 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] 12602 COMMENT : replaced in the HSW builds 12603 PATTERN : 0x0F 0xBC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12604 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 12605 12606 PATTERN : 0x0F 0xBC MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12607 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 12608 } 12609 { 12610 ICLASS : BSR 12611 CPL : 3 12612 CATEGORY : BITBYTE 12613 EXTENSION : BASE 12614 ISA_SET : I386 12615 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] 12616 COMMENT : replaced in the HSW builds 12617 PATTERN : 0x0F 0xBD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12618 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 12619 12620 PATTERN : 0x0F 0xBD MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12621 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 12622 } 12623 { 12624 ICLASS : MOVSX 12625 CPL : 3 12626 CATEGORY : DATAXFER 12627 EXTENSION : BASE 12628 ISA_SET : I386 12629 PATTERN : 0x0F 0xBE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12630 OPERANDS : REG0=GPRv_R():w MEM0:r:b 12631 } 12632 { 12633 ICLASS : MOVSX 12634 CPL : 3 12635 CATEGORY : DATAXFER 12636 EXTENSION : BASE 12637 ISA_SET : I386 12638 PATTERN : 0x0F 0xBE MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12639 OPERANDS : REG0=GPRv_R():w REG1=GPR8_B():r 12640 } 12641 { 12642 ICLASS : MOVSX 12643 CPL : 3 12644 CATEGORY : DATAXFER 12645 EXTENSION : BASE 12646 ISA_SET : I386 12647 PATTERN : 0x0F 0xBF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12648 OPERANDS : REG0=GPRv_R():w MEM0:r:w 12649 } 12650 { 12651 ICLASS : MOVSX 12652 CPL : 3 12653 CATEGORY : DATAXFER 12654 EXTENSION : BASE 12655 ISA_SET : I386 12656 PATTERN : 0x0F 0xBF MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12657 OPERANDS : REG0=GPRv_R():w REG1=GPR16_B():r 12658 } 12659 { 12660 ICLASS : BSWAP 12661 CPL : 3 12662 CATEGORY : DATAXFER 12663 EXTENSION : BASE 12664 ISA_SET : I486REAL 12665 PATTERN : 0x0F 0b1100_1 SRM[rrr] 12666 OPERANDS : REG0=GPRv_SB():rw 12667 } 12668 { 12669 ICLASS : PSUBUSB 12670 EXCEPTIONS: mmx-mem 12671 ATTRIBUTES: NOTSX 12672 CPL : 3 12673 CATEGORY : MMX 12674 EXTENSION : MMX 12675 ISA_SET : PENTIUMMMX 12676 PATTERN : 0x0F 0xD8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12677 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12678 } 12679 { 12680 ICLASS : PSUBUSB 12681 EXCEPTIONS: mmx-mem 12682 ATTRIBUTES: NOTSX 12683 CPL : 3 12684 CATEGORY : MMX 12685 EXTENSION : MMX 12686 ISA_SET : PENTIUMMMX 12687 PATTERN : 0x0F 0xD8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12688 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12689 } 12690 { 12691 ICLASS : PSUBUSW 12692 EXCEPTIONS: mmx-mem 12693 ATTRIBUTES: NOTSX 12694 CPL : 3 12695 CATEGORY : MMX 12696 EXTENSION : MMX 12697 ISA_SET : PENTIUMMMX 12698 PATTERN : 0x0F 0xD9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12699 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12700 } 12701 { 12702 ICLASS : PSUBUSW 12703 EXCEPTIONS: mmx-mem 12704 ATTRIBUTES: NOTSX 12705 CPL : 3 12706 CATEGORY : MMX 12707 EXTENSION : MMX 12708 ISA_SET : PENTIUMMMX 12709 PATTERN : 0x0F 0xD9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12710 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12711 } 12712 { 12713 ICLASS : PMINUB 12714 EXCEPTIONS: mmx-mem 12715 ATTRIBUTES: NOTSX 12716 CPL : 3 12717 CATEGORY : MMX 12718 EXTENSION : MMX 12719 ISA_SET : PENTIUMMMX 12720 PATTERN : 0x0F 0xDA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12721 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12722 } 12723 { 12724 ICLASS : PMINUB 12725 ATTRIBUTES: NOTSX 12726 CPL : 3 12727 CATEGORY : MMX 12728 EXTENSION : MMX 12729 ISA_SET : PENTIUMMMX 12730 PATTERN : 0x0F 0xDA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12731 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12732 } 12733 { 12734 ICLASS : PAND 12735 EXCEPTIONS: mmx-mem 12736 ATTRIBUTES: NOTSX 12737 CPL : 3 12738 CATEGORY : LOGICAL 12739 EXTENSION : MMX 12740 ISA_SET : PENTIUMMMX 12741 PATTERN : 0x0F 0xDB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12742 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12743 } 12744 { 12745 ICLASS : PAND 12746 ATTRIBUTES: NOTSX 12747 CPL : 3 12748 CATEGORY : LOGICAL 12749 EXTENSION : MMX 12750 ISA_SET : PENTIUMMMX 12751 PATTERN : 0x0F 0xDB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12752 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12753 } 12754 { 12755 ICLASS : PADDUSB 12756 EXCEPTIONS: mmx-mem 12757 ATTRIBUTES: NOTSX 12758 CPL : 3 12759 CATEGORY : MMX 12760 EXTENSION : MMX 12761 ISA_SET : PENTIUMMMX 12762 PATTERN : 0x0F 0xDC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12763 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12764 } 12765 { 12766 ICLASS : PADDUSB 12767 ATTRIBUTES: NOTSX 12768 CPL : 3 12769 CATEGORY : MMX 12770 EXTENSION : MMX 12771 ISA_SET : PENTIUMMMX 12772 PATTERN : 0x0F 0xDC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12773 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12774 } 12775 { 12776 ICLASS : PADDUSW 12777 EXCEPTIONS: mmx-mem 12778 ATTRIBUTES: NOTSX 12779 CPL : 3 12780 CATEGORY : MMX 12781 EXTENSION : MMX 12782 ISA_SET : PENTIUMMMX 12783 PATTERN : 0x0F 0xDD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12784 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12785 } 12786 { 12787 ICLASS : PADDUSW 12788 ATTRIBUTES: NOTSX 12789 CPL : 3 12790 CATEGORY : MMX 12791 EXTENSION : MMX 12792 ISA_SET : PENTIUMMMX 12793 PATTERN : 0x0F 0xDD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12794 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12795 } 12796 { 12797 ICLASS : PMAXUB 12798 EXCEPTIONS: mmx-mem 12799 ATTRIBUTES: NOTSX 12800 CPL : 3 12801 CATEGORY : MMX 12802 EXTENSION : MMX 12803 ISA_SET : PENTIUMMMX 12804 PATTERN : 0x0F 0xDE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12805 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12806 } 12807 { 12808 ICLASS : PMAXUB 12809 ATTRIBUTES: NOTSX 12810 CPL : 3 12811 CATEGORY : MMX 12812 EXTENSION : MMX 12813 ISA_SET : PENTIUMMMX 12814 PATTERN : 0x0F 0xDE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12815 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12816 } 12817 { 12818 ICLASS : PANDN 12819 EXCEPTIONS: mmx-mem 12820 ATTRIBUTES: NOTSX 12821 CPL : 3 12822 CATEGORY : LOGICAL 12823 EXTENSION : MMX 12824 ISA_SET : PENTIUMMMX 12825 PATTERN : 0x0F 0xDF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12826 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12827 } 12828 { 12829 ICLASS : PANDN 12830 ATTRIBUTES: NOTSX 12831 CPL : 3 12832 CATEGORY : LOGICAL 12833 EXTENSION : MMX 12834 ISA_SET : PENTIUMMMX 12835 PATTERN : 0x0F 0xDF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12836 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12837 } 12838 { 12839 ICLASS : PSUBUSB 12840 CPL : 3 12841 CATEGORY : SSE 12842 EXTENSION : SSE2 12843 EXCEPTIONS : SSE_TYPE_4 12844 ATTRIBUTES : REQUIRES_ALIGNMENT 12845 PATTERN : 0x0F 0xD8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12846 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 12847 PATTERN : 0x0F 0xD8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12848 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 12849 } 12850 { 12851 ICLASS : PSUBUSW 12852 CPL : 3 12853 CATEGORY : SSE 12854 EXTENSION : SSE2 12855 EXCEPTIONS : SSE_TYPE_4 12856 ATTRIBUTES : REQUIRES_ALIGNMENT 12857 PATTERN : 0x0F 0xD9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12858 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 12859 PATTERN : 0x0F 0xD9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12860 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 12861 } 12862 { 12863 ICLASS : PMINUB 12864 CPL : 3 12865 CATEGORY : SSE 12866 EXTENSION : SSE2 12867 EXCEPTIONS: SSE_TYPE_4 12868 ATTRIBUTES : REQUIRES_ALIGNMENT 12869 PATTERN : 0x0F 0xDA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12870 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 12871 PATTERN : 0x0F 0xDA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12872 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 12873 } 12874 { 12875 ICLASS : PAND 12876 CPL : 3 12877 CATEGORY : LOGICAL 12878 EXTENSION : SSE2 12879 EXCEPTIONS: SSE_TYPE_4 12880 ATTRIBUTES : REQUIRES_ALIGNMENT 12881 PATTERN : 0x0F 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12882 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 12883 PATTERN : 0x0F 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12884 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 12885 } 12886 { 12887 ICLASS : PADDUSB 12888 CPL : 3 12889 CATEGORY : SSE 12890 EXTENSION : SSE2 12891 EXCEPTIONS: SSE_TYPE_4 12892 ATTRIBUTES : REQUIRES_ALIGNMENT 12893 PATTERN : 0x0F 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12894 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 12895 PATTERN : 0x0F 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12896 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 12897 } 12898 { 12899 ICLASS : PADDUSW 12900 CPL : 3 12901 CATEGORY : SSE 12902 EXTENSION : SSE2 12903 EXCEPTIONS: SSE_TYPE_4 12904 ATTRIBUTES : REQUIRES_ALIGNMENT 12905 PATTERN : 0x0F 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12906 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 12907 PATTERN : 0x0F 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12908 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 12909 } 12910 { 12911 ICLASS : PMAXUB 12912 CPL : 3 12913 CATEGORY : SSE 12914 EXTENSION : SSE2 12915 EXCEPTIONS: SSE_TYPE_4 12916 ATTRIBUTES : REQUIRES_ALIGNMENT 12917 PATTERN : 0x0F 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12918 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 12919 PATTERN : 0x0F 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12920 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 12921 } 12922 { 12923 ICLASS : PANDN 12924 CPL : 3 12925 CATEGORY : LOGICAL 12926 EXTENSION : SSE2 12927 EXCEPTIONS: SSE_TYPE_4 12928 ATTRIBUTES : REQUIRES_ALIGNMENT 12929 PATTERN : 0x0F 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 12930 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 12931 PATTERN : 0x0F 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 12932 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 12933 } 12934 { 12935 ICLASS : PSUBSB 12936 EXCEPTIONS: mmx-mem 12937 ATTRIBUTES: NOTSX 12938 CPL : 3 12939 CATEGORY : MMX 12940 EXTENSION : MMX 12941 ISA_SET : PENTIUMMMX 12942 PATTERN : 0x0F 0xE8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12943 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12944 PATTERN : 0x0F 0xE8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12945 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12946 } 12947 { 12948 ICLASS : PSUBSW 12949 EXCEPTIONS: mmx-mem 12950 ATTRIBUTES: NOTSX 12951 CPL : 3 12952 CATEGORY : MMX 12953 EXTENSION : MMX 12954 ISA_SET : PENTIUMMMX 12955 PATTERN : 0x0F 0xE9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12956 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12957 PATTERN : 0x0F 0xE9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12958 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12959 } 12960 { 12961 ICLASS : PMINSW 12962 EXCEPTIONS: mmx-mem 12963 ATTRIBUTES: NOTSX 12964 CPL : 3 12965 CATEGORY : MMX 12966 EXTENSION : MMX 12967 ISA_SET : PENTIUMMMX 12968 PATTERN : 0x0F 0xEA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12969 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12970 PATTERN : 0x0F 0xEA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12971 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12972 } 12973 { 12974 ICLASS : POR 12975 ATTRIBUTES: NOTSX 12976 CPL : 3 12977 CATEGORY : LOGICAL 12978 EXTENSION : MMX 12979 ISA_SET : PENTIUMMMX 12980 PATTERN : 0x0F 0xEB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12981 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12982 PATTERN : 0x0F 0xEB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12983 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12984 } 12985 { 12986 ICLASS : PADDSB 12987 EXCEPTIONS: mmx-mem 12988 ATTRIBUTES: NOTSX 12989 CPL : 3 12990 CATEGORY : MMX 12991 EXTENSION : MMX 12992 ISA_SET : PENTIUMMMX 12993 PATTERN : 0x0F 0xEC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 12994 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 12995 PATTERN : 0x0F 0xEC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 12996 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 12997 } 12998 { 12999 ICLASS : PADDSW 13000 EXCEPTIONS: mmx-mem 13001 ATTRIBUTES: NOTSX 13002 CPL : 3 13003 CATEGORY : MMX 13004 EXTENSION : MMX 13005 ISA_SET : PENTIUMMMX 13006 PATTERN : 0x0F 0xED no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13007 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13008 PATTERN : 0x0F 0xED no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13009 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13010 } 13011 { 13012 ICLASS : PMAXSW 13013 EXCEPTIONS: mmx-mem 13014 ATTRIBUTES: NOTSX 13015 CPL : 3 13016 CATEGORY : MMX 13017 EXTENSION : MMX 13018 ISA_SET : PENTIUMMMX 13019 PATTERN : 0x0F 0xEE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13020 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13021 PATTERN : 0x0F 0xEE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13022 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13023 } 13024 { 13025 ICLASS : PXOR 13026 EXCEPTIONS: mmx-mem 13027 ATTRIBUTES: NOTSX 13028 CPL : 3 13029 CATEGORY : LOGICAL 13030 EXTENSION : MMX 13031 ISA_SET : PENTIUMMMX 13032 PATTERN : 0x0F 0xEF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13033 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13034 PATTERN : 0x0F 0xEF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13035 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13036 } 13037 { 13038 ICLASS : PSUBSB 13039 CPL : 3 13040 CATEGORY : SSE 13041 EXTENSION : SSE2 13042 EXCEPTIONS: SSE_TYPE_4 13043 ATTRIBUTES : REQUIRES_ALIGNMENT 13044 PATTERN : 0x0F 0xE8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13045 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13046 PATTERN : 0x0F 0xE8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13047 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13048 } 13049 { 13050 ICLASS : PSUBSW 13051 CPL : 3 13052 CATEGORY : SSE 13053 EXTENSION : SSE2 13054 EXCEPTIONS: SSE_TYPE_4 13055 ATTRIBUTES : REQUIRES_ALIGNMENT 13056 PATTERN : 0x0F 0xE9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13057 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13058 PATTERN : 0x0F 0xE9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13059 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13060 } 13061 { 13062 ICLASS : PMINSW 13063 CPL : 3 13064 CATEGORY : SSE 13065 EXTENSION : SSE2 13066 EXCEPTIONS: SSE_TYPE_4 13067 ATTRIBUTES : REQUIRES_ALIGNMENT 13068 PATTERN : 0x0F 0xEA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13069 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13070 PATTERN : 0x0F 0xEA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13071 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13072 } 13073 { 13074 ICLASS : POR 13075 CPL : 3 13076 CATEGORY : LOGICAL 13077 EXTENSION : SSE2 13078 EXCEPTIONS: SSE_TYPE_4 13079 ATTRIBUTES : REQUIRES_ALIGNMENT 13080 PATTERN : 0x0F 0xEB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13081 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13082 PATTERN : 0x0F 0xEB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13083 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13084 } 13085 { 13086 ICLASS : PADDSB 13087 CPL : 3 13088 CATEGORY : SSE 13089 EXTENSION : SSE2 13090 EXCEPTIONS: SSE_TYPE_4 13091 ATTRIBUTES : REQUIRES_ALIGNMENT 13092 PATTERN : 0x0F 0xEC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13093 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13094 PATTERN : 0x0F 0xEC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13095 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13096 } 13097 { 13098 ICLASS : PADDSW 13099 CPL : 3 13100 CATEGORY : SSE 13101 EXTENSION : SSE2 13102 EXCEPTIONS: SSE_TYPE_4 13103 ATTRIBUTES : REQUIRES_ALIGNMENT 13104 PATTERN : 0x0F 0xED osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13105 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13106 PATTERN : 0x0F 0xED osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13107 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13108 } 13109 { 13110 ICLASS : PMAXSW 13111 CPL : 3 13112 CATEGORY : SSE 13113 EXTENSION : SSE2 13114 EXCEPTIONS: SSE_TYPE_4 13115 ATTRIBUTES : REQUIRES_ALIGNMENT 13116 PATTERN : 0x0F 0xEE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13117 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13118 PATTERN : 0x0F 0xEE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13119 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13120 } 13121 { 13122 ICLASS : PXOR 13123 CPL : 3 13124 CATEGORY : LOGICAL 13125 EXTENSION : SSE2 13126 EXCEPTIONS: SSE_TYPE_4 13127 ATTRIBUTES : REQUIRES_ALIGNMENT 13128 PATTERN : 0x0F 0xEF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13129 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13130 PATTERN : 0x0F 0xEF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13131 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13132 } 13133 { 13134 ICLASS : PSUBB 13135 EXCEPTIONS: mmx-mem 13136 ATTRIBUTES: NOTSX 13137 CPL : 3 13138 CATEGORY : MMX 13139 EXTENSION : MMX 13140 ISA_SET : PENTIUMMMX 13141 PATTERN : 0x0F 0xF8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13142 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13143 PATTERN : 0x0F 0xF8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13144 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13145 } 13146 { 13147 ICLASS : PSUBW 13148 EXCEPTIONS: mmx-mem 13149 ATTRIBUTES: NOTSX 13150 CPL : 3 13151 CATEGORY : MMX 13152 EXTENSION : MMX 13153 ISA_SET : PENTIUMMMX 13154 PATTERN : 0x0F 0xF9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13155 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13156 PATTERN : 0x0F 0xF9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13157 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13158 } 13159 { 13160 ICLASS : PSUBD 13161 EXCEPTIONS: mmx-mem 13162 ATTRIBUTES: NOTSX 13163 CPL : 3 13164 CATEGORY : MMX 13165 EXTENSION : MMX 13166 ISA_SET : PENTIUMMMX 13167 PATTERN : 0x0F 0xFA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13168 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13169 PATTERN : 0x0F 0xFA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13170 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13171 } 13172 { 13173 ICLASS : PSUBQ 13174 EXCEPTIONS: mmx-mem 13175 ATTRIBUTES: NOTSX 13176 CPL : 3 13177 CATEGORY : MMX 13178 EXTENSION : SSE2 13179 PATTERN : 0x0F 0xFB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13180 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13181 PATTERN : 0x0F 0xFB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13182 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13183 } 13184 { 13185 ICLASS : PADDB 13186 EXCEPTIONS: mmx-mem 13187 ATTRIBUTES: NOTSX 13188 CPL : 3 13189 CATEGORY : MMX 13190 EXTENSION : MMX 13191 ISA_SET : PENTIUMMMX 13192 PATTERN : 0x0F 0xFC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13193 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13194 PATTERN : 0x0F 0xFC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13195 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13196 } 13197 { 13198 ICLASS : PADDW 13199 EXCEPTIONS: mmx-mem 13200 ATTRIBUTES: NOTSX 13201 CPL : 3 13202 CATEGORY : MMX 13203 EXTENSION : MMX 13204 ISA_SET : PENTIUMMMX 13205 PATTERN : 0x0F 0xFD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13206 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13207 PATTERN : 0x0F 0xFD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13208 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13209 } 13210 { 13211 ICLASS : PADDD 13212 EXCEPTIONS: mmx-mem 13213 ATTRIBUTES: NOTSX 13214 CPL : 3 13215 CATEGORY : MMX 13216 EXTENSION : MMX 13217 ISA_SET : PENTIUMMMX 13218 PATTERN : 0x0F 0xFE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13219 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13220 PATTERN : 0x0F 0xFE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13221 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13222 } 13223 { 13224 ICLASS : PSUBB 13225 CPL : 3 13226 CATEGORY : SSE 13227 EXTENSION : SSE2 13228 EXCEPTIONS: SSE_TYPE_4 13229 ATTRIBUTES : REQUIRES_ALIGNMENT 13230 PATTERN : 0x0F 0xF8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13231 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13232 PATTERN : 0x0F 0xF8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13233 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13234 } 13235 { 13236 ICLASS : PSUBW 13237 CPL : 3 13238 CATEGORY : SSE 13239 EXTENSION : SSE2 13240 EXCEPTIONS: SSE_TYPE_4 13241 ATTRIBUTES : REQUIRES_ALIGNMENT 13242 PATTERN : 0x0F 0xF9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13243 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13244 PATTERN : 0x0F 0xF9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13245 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13246 } 13247 { 13248 ICLASS : PSUBD 13249 CPL : 3 13250 CATEGORY : SSE 13251 EXTENSION : SSE2 13252 EXCEPTIONS: SSE_TYPE_4 13253 ATTRIBUTES : REQUIRES_ALIGNMENT 13254 PATTERN : 0x0F 0xFA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13255 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13256 PATTERN : 0x0F 0xFA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13257 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13258 } 13259 { 13260 ICLASS : PSUBQ 13261 CPL : 3 13262 CATEGORY : SSE 13263 EXTENSION : SSE2 13264 EXCEPTIONS: SSE_TYPE_4 13265 ATTRIBUTES : REQUIRES_ALIGNMENT 13266 PATTERN : 0x0F 0xFB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13267 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13268 PATTERN : 0x0F 0xFB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13269 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13270 } 13271 { 13272 ICLASS : PADDB 13273 CPL : 3 13274 CATEGORY : SSE 13275 EXTENSION : SSE2 13276 EXCEPTIONS: SSE_TYPE_4 13277 ATTRIBUTES : REQUIRES_ALIGNMENT 13278 PATTERN : 0x0F 0xFC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13279 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13280 PATTERN : 0x0F 0xFC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13281 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13282 } 13283 { 13284 ICLASS : PADDW 13285 CPL : 3 13286 CATEGORY : SSE 13287 EXTENSION : SSE2 13288 EXCEPTIONS: SSE_TYPE_4 13289 ATTRIBUTES : REQUIRES_ALIGNMENT 13290 PATTERN : 0x0F 0xFD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13291 OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 13292 PATTERN : 0x0F 0xFD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13293 OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 13294 } 13295 { 13296 ICLASS : PADDD 13297 CPL : 3 13298 CATEGORY : SSE 13299 EXTENSION : SSE2 13300 EXCEPTIONS: SSE_TYPE_4 13301 ATTRIBUTES : REQUIRES_ALIGNMENT 13302 PATTERN : 0x0F 0xFE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13303 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13304 PATTERN : 0x0F 0xFE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13305 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13306 } 13307 { 13308 ICLASS : PHADDW 13309 EXCEPTIONS: mmx-mem 13310 ATTRIBUTES: NOTSX 13311 CPL : 3 13312 CATEGORY : MMX 13313 EXTENSION : SSSE3 13314 PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13315 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13316 PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13317 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13318 } 13319 { 13320 ICLASS : PHADDW 13321 CPL : 3 13322 CATEGORY : SSE 13323 EXTENSION : SSSE3 13324 EXCEPTIONS: SSE_TYPE_4 13325 ATTRIBUTES : REQUIRES_ALIGNMENT 13326 PATTERN : 0x0F 0x38 0x01 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13327 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13328 PATTERN : 0x0F 0x38 0x01 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13329 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13330 } 13331 { 13332 ICLASS : PHADDD 13333 EXCEPTIONS: mmx-mem 13334 ATTRIBUTES: NOTSX 13335 CPL : 3 13336 CATEGORY : MMX 13337 EXTENSION : SSSE3 13338 PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13339 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13340 PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13341 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13342 } 13343 { 13344 ICLASS : PHADDD 13345 CPL : 3 13346 CATEGORY : SSE 13347 EXTENSION : SSSE3 13348 EXCEPTIONS: SSE_TYPE_4 13349 ATTRIBUTES : REQUIRES_ALIGNMENT 13350 PATTERN : 0x0F 0x38 0x02 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13351 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13352 PATTERN : 0x0F 0x38 0x02 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13353 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13354 } 13355 { 13356 ICLASS : PHADDSW 13357 EXCEPTIONS: mmx-mem 13358 ATTRIBUTES: NOTSX 13359 CPL : 3 13360 CATEGORY : MMX 13361 EXTENSION : SSSE3 13362 PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13363 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13364 PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13365 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13366 } 13367 { 13368 ICLASS : PHADDSW 13369 CPL : 3 13370 CATEGORY : SSE 13371 EXTENSION : SSSE3 13372 EXCEPTIONS: SSE_TYPE_4 13373 ATTRIBUTES : REQUIRES_ALIGNMENT 13374 PATTERN : 0x0F 0x38 0x03 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13375 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13376 PATTERN : 0x0F 0x38 0x03 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13377 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13378 } 13379 { 13380 ICLASS : PHSUBW 13381 EXCEPTIONS: mmx-mem 13382 ATTRIBUTES: NOTSX 13383 CPL : 3 13384 CATEGORY : MMX 13385 EXTENSION : SSSE3 13386 PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13387 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13388 PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13389 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13390 } 13391 { 13392 ICLASS : PHSUBW 13393 CPL : 3 13394 CATEGORY : SSE 13395 EXTENSION : SSSE3 13396 EXCEPTIONS: SSE_TYPE_4 13397 ATTRIBUTES : REQUIRES_ALIGNMENT 13398 PATTERN : 0x0F 0x38 0x05 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13399 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13400 PATTERN : 0x0F 0x38 0x05 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13401 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13402 } 13403 { 13404 ICLASS : PHSUBD 13405 EXCEPTIONS: mmx-mem 13406 ATTRIBUTES: NOTSX 13407 CPL : 3 13408 CATEGORY : MMX 13409 EXTENSION : SSSE3 13410 PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13411 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13412 PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13413 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13414 } 13415 { 13416 ICLASS : PHSUBD 13417 CPL : 3 13418 CATEGORY : SSE 13419 EXTENSION : SSSE3 13420 EXCEPTIONS: SSE_TYPE_4 13421 ATTRIBUTES : REQUIRES_ALIGNMENT 13422 PATTERN : 0x0F 0x38 0x06 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13423 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13424 PATTERN : 0x0F 0x38 0x06 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13425 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13426 } 13427 { 13428 ICLASS : PHSUBSW 13429 EXCEPTIONS: mmx-mem 13430 ATTRIBUTES: NOTSX 13431 CPL : 3 13432 CATEGORY : MMX 13433 EXTENSION : SSSE3 13434 PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13435 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13436 PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13437 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13438 } 13439 { 13440 ICLASS : PHSUBSW 13441 CPL : 3 13442 CATEGORY : SSE 13443 EXTENSION : SSSE3 13444 EXCEPTIONS: SSE_TYPE_4 13445 ATTRIBUTES : REQUIRES_ALIGNMENT 13446 PATTERN : 0x0F 0x38 0x07 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13447 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13448 PATTERN : 0x0F 0x38 0x07 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13449 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13450 } 13451 { 13452 ICLASS : PMADDUBSW 13453 EXCEPTIONS: mmx-mem 13454 CPL : 3 13455 CATEGORY : MMX 13456 EXTENSION : SSSE3 13457 ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX 13458 PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13459 OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 13460 PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13461 OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 13462 } 13463 { 13464 ICLASS : PMADDUBSW 13465 CPL : 3 13466 CATEGORY : SSE 13467 EXTENSION : SSSE3 13468 EXCEPTIONS: SSE_TYPE_4 13469 ATTRIBUTES : REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT 13470 PATTERN : 0x0F 0x38 0x04 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13471 OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 13472 PATTERN : 0x0F 0x38 0x04 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13473 OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 13474 } 13475 { 13476 ICLASS : PMULHRSW 13477 EXCEPTIONS: mmx-mem 13478 ATTRIBUTES: NOTSX 13479 CPL : 3 13480 CATEGORY : MMX 13481 EXTENSION : SSSE3 13482 PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13483 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13484 PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13485 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13486 } 13487 { 13488 ICLASS : PMULHRSW 13489 CPL : 3 13490 CATEGORY : SSE 13491 EXTENSION : SSSE3 13492 EXCEPTIONS: SSE_TYPE_4 13493 ATTRIBUTES : REQUIRES_ALIGNMENT 13494 PATTERN : 0x0F 0x38 0x0B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13495 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13496 PATTERN : 0x0F 0x38 0x0B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13497 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13498 } 13499 { 13500 ICLASS : PSHUFB 13501 EXCEPTIONS: mmx-mem 13502 ATTRIBUTES: NOTSX 13503 CPL : 3 13504 CATEGORY : MMX 13505 EXTENSION : SSSE3 13506 PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13507 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13508 PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13509 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13510 } 13511 { 13512 ICLASS : PSHUFB 13513 CPL : 3 13514 CATEGORY : SSE 13515 EXTENSION : SSSE3 13516 EXCEPTIONS: SSE_TYPE_4 13517 ATTRIBUTES : REQUIRES_ALIGNMENT 13518 PATTERN : 0x0F 0x38 0x00 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13519 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13520 PATTERN : 0x0F 0x38 0x00 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13521 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13522 } 13523 { 13524 ICLASS : PSIGNB 13525 EXCEPTIONS: mmx-mem 13526 ATTRIBUTES: NOTSX 13527 CPL : 3 13528 CATEGORY : MMX 13529 EXTENSION : SSSE3 13530 PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13531 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13532 PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13533 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13534 } 13535 { 13536 ICLASS : PSIGNB 13537 CPL : 3 13538 CATEGORY : SSE 13539 EXTENSION : SSSE3 13540 EXCEPTIONS: SSE_TYPE_4 13541 ATTRIBUTES : REQUIRES_ALIGNMENT 13542 PATTERN : 0x0F 0x38 0x08 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13543 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13544 PATTERN : 0x0F 0x38 0x08 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13545 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13546 } 13547 { 13548 ICLASS : PSIGNW 13549 EXCEPTIONS: mmx-mem 13550 ATTRIBUTES: NOTSX 13551 CPL : 3 13552 CATEGORY : MMX 13553 EXTENSION : SSSE3 13554 PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13555 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13556 PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13557 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13558 } 13559 { 13560 ICLASS : PSIGNW 13561 CPL : 3 13562 CATEGORY : SSE 13563 EXTENSION : SSSE3 13564 EXCEPTIONS: SSE_TYPE_4 13565 ATTRIBUTES : REQUIRES_ALIGNMENT 13566 PATTERN : 0x0F 0x38 0x09 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13567 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13568 PATTERN : 0x0F 0x38 0x09 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13569 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13570 } 13571 { 13572 ICLASS : PSIGND 13573 ATTRIBUTES: NOTSX 13574 CPL : 3 13575 CATEGORY : MMX 13576 EXTENSION : SSSE3 13577 EXCEPTIONS: mmx-mem 13578 PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13579 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 13580 PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13581 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 13582 } 13583 { 13584 ICLASS : PSIGND 13585 CPL : 3 13586 CATEGORY : SSE 13587 EXTENSION : SSSE3 13588 EXCEPTIONS: SSE_TYPE_4 13589 ATTRIBUTES : REQUIRES_ALIGNMENT 13590 PATTERN : 0x0F 0x38 0x0A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13591 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13592 PATTERN : 0x0F 0x38 0x0A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13593 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13594 } 13595 { 13596 ICLASS : PALIGNR 13597 EXCEPTIONS: mmx-mem 13598 ATTRIBUTES: NOTSX 13599 CPL : 3 13600 CATEGORY : MMX 13601 EXTENSION : SSSE3 13602 PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13603 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q IMM0:r:b 13604 PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13605 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q IMM0:r:b 13606 } 13607 { 13608 ICLASS : PALIGNR 13609 CPL : 3 13610 CATEGORY : SSE 13611 EXTENSION : SSSE3 13612 EXCEPTIONS: SSE_TYPE_4 13613 ATTRIBUTES : REQUIRES_ALIGNMENT 13614 PATTERN : 0x0F 0x3A 0x0F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() 13615 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b 13616 PATTERN : 0x0F 0x3A 0x0F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() 13617 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b 13618 } 13619 { 13620 ICLASS : PABSB 13621 EXCEPTIONS: mmx-mem 13622 ATTRIBUTES: NOTSX 13623 CPL : 3 13624 CATEGORY : MMX 13625 EXTENSION : SSSE3 13626 PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13627 OPERANDS : REG0=MMX_R():w:q MEM0:r:q 13628 PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13629 OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q 13630 } 13631 { 13632 ICLASS : PABSB 13633 CPL : 3 13634 CATEGORY : SSE 13635 EXTENSION : SSSE3 13636 EXCEPTIONS: SSE_TYPE_4 13637 ATTRIBUTES : REQUIRES_ALIGNMENT 13638 PATTERN : 0x0F 0x38 0x1C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13639 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 13640 PATTERN : 0x0F 0x38 0x1C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13641 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 13642 } 13643 { 13644 ICLASS : PABSW 13645 EXCEPTIONS: mmx-mem 13646 ATTRIBUTES: NOTSX 13647 CPL : 3 13648 CATEGORY : MMX 13649 EXTENSION : SSSE3 13650 PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13651 OPERANDS : REG0=MMX_R():w:q MEM0:r:q 13652 PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13653 OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q 13654 } 13655 { 13656 ICLASS : PABSW 13657 CPL : 3 13658 CATEGORY : SSE 13659 EXTENSION : SSSE3 13660 EXCEPTIONS: SSE_TYPE_4 13661 ATTRIBUTES : REQUIRES_ALIGNMENT 13662 PATTERN : 0x0F 0x38 0x1D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13663 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 13664 PATTERN : 0x0F 0x38 0x1D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13665 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 13666 } 13667 { 13668 ICLASS : PABSD 13669 EXCEPTIONS: mmx-mem 13670 CPL : 3 13671 ATTRIBUTES : simd_scalar NOTSX 13672 CATEGORY : MMX 13673 EXTENSION : SSSE3 13674 PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13675 OPERANDS : REG0=MMX_R():w:q MEM0:r:q 13676 } 13677 { 13678 ICLASS : PABSD 13679 CPL : 3 13680 ATTRIBUTES : simd_scalar NOTSX 13681 CATEGORY : MMX 13682 EXTENSION : SSSE3 13683 PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13684 OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q 13685 } 13686 { 13687 ICLASS : PABSD 13688 CPL : 3 13689 ATTRIBUTES : simd_scalar REQUIRES_ALIGNMENT 13690 CATEGORY : SSE 13691 EXTENSION : SSSE3 13692 EXCEPTIONS: SSE_TYPE_4 13693 PATTERN : 0x0F 0x38 0x1E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13694 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 13695 } 13696 { 13697 ICLASS : PABSD 13698 CPL : 3 13699 ATTRIBUTES : simd_scalar 13700 CATEGORY : SSE 13701 EXTENSION : SSSE3 13702 EXCEPTIONS: SSE_TYPE_4 13703 PATTERN : 0x0F 0x38 0x1E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13704 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 13705 } 13706 13707 #################################################################################### 13708 { 13709 ICLASS : POPCNT 13710 CPL : 3 13711 CATEGORY : SSE 13712 EXTENSION : SSE4 13713 ISA_SET : POPCNT 13714 ATTRIBUTES: IGNORES_OSFXSR 13715 # 2009-02-20: not using IGNORE66 on this because we need the 66 prefix 13716 # to get to the 16b form 32b and 64b modes. 13717 FLAGS : MUST [ cf-0 zf-mod of-0 af-0 pf-0 sf-0 ] 13718 PATTERN : 0x0F 0xB8 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13719 OPERANDS : REG0=GPRv_R():w:v MEM0:r:v 13720 PATTERN : 0x0F 0xB8 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13721 OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v 13722 } 13723 #################################################################################### 13724 { 13725 ICLASS : PCMPGTQ 13726 CPL : 3 13727 CATEGORY : SSE 13728 EXTENSION : SSE4 13729 ISA_SET : SSE42 13730 EXCEPTIONS: SSE_TYPE_4 13731 ATTRIBUTES : REQUIRES_ALIGNMENT 13732 PATTERN : 0x0F 0x38 0x37 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 13733 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13734 PATTERN : 0x0F 0x38 0x37 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 13735 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13736 } 13737 #################################################################################### 13738 { 13739 ICLASS : CRC32 13740 CPL : 3 13741 CATEGORY : SSE 13742 EXTENSION : SSE4 13743 ISA_SET : SSE42 13744 ATTRIBUTES : IGNORES_OSFXSR 13745 # 2009-02-20: not using IGNORE66 on this because we need the 66 prefix 13746 # to get to the 16b form 32b and 64b modes. 13747 13748 COMMENT: The dest min size is 32b, even for EOSZ 16b. 13749 13750 # The byte-readers 13751 13752 PATTERN : 0x0F 0x38 0xF0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13753 OPERANDS : REG0=GPRy_R():rw:y MEM0:r:b 13754 PATTERN : 0x0F 0x38 0xF0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13755 OPERANDS : REG0=GPRy_R():rw:y REG1=GPR8_B():r:b 13756 13757 13758 # The scalable readers 13759 13760 PATTERN : 0x0F 0x38 0xF1 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13761 OPERANDS : REG0=GPRy_R():rw:y MEM0:r:v 13762 PATTERN : 0x0F 0x38 0xF1 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13763 OPERANDS : REG0=GPRy_R():rw:y REG1=GPRv_B():r:v 13764 13765 } 13766 13767 13768 13769 { 13770 ICLASS : BLENDPD 13771 CPL : 3 13772 CATEGORY : SSE 13773 EXTENSION : SSE4 13774 EXCEPTIONS: SSE_TYPE_4 13775 ATTRIBUTES : REQUIRES_ALIGNMENT 13776 PATTERN : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13777 OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b 13778 13779 PATTERN : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13780 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b 13781 } 13782 { 13783 ICLASS : BLENDPS 13784 CPL : 3 13785 CATEGORY : SSE 13786 EXTENSION : SSE4 13787 EXCEPTIONS: SSE_TYPE_4 13788 ATTRIBUTES : REQUIRES_ALIGNMENT 13789 PATTERN : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13790 OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b 13791 13792 PATTERN : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13793 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b 13794 } 13795 #######################################################################33 13796 { 13797 ICLASS : BLENDVPD 13798 CPL : 3 13799 CATEGORY : SSE 13800 EXTENSION : SSE4 13801 EXCEPTIONS: SSE_TYPE_4 13802 ATTRIBUTES : REQUIRES_ALIGNMENT 13803 PATTERN : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13804 OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 REG1=XED_REG_XMM0:r:SUPP:dq:u64 13805 13806 PATTERN : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13807 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 REG2=XED_REG_XMM0:r:SUPP:dq:u64 13808 } 13809 13810 { 13811 ICLASS : BLENDVPS 13812 CPL : 3 13813 CATEGORY : SSE 13814 EXTENSION : SSE4 13815 EXCEPTIONS: SSE_TYPE_4 13816 ATTRIBUTES : REQUIRES_ALIGNMENT 13817 PATTERN : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13818 OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 REG1=XED_REG_XMM0:r:SUPP:dq:u32 13819 13820 PATTERN : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13821 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 REG2=XED_REG_XMM0:r:SUPP:dq:u32 13822 } 13823 #################################################################################### 13824 { 13825 ICLASS : PCMPEQQ 13826 CPL : 3 13827 CATEGORY : SSE 13828 EXTENSION : SSE4 13829 EXCEPTIONS: SSE_TYPE_4 13830 ATTRIBUTES : REQUIRES_ALIGNMENT 13831 PATTERN : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13832 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 13833 13834 PATTERN : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13835 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 13836 } 13837 #################################################################################### 13838 { 13839 ICLASS : DPPD 13840 CPL : 3 13841 CATEGORY : SSE 13842 EXTENSION : SSE4 13843 EXCEPTIONS: SSE_TYPE_2D 13844 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 13845 PATTERN : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13846 OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b 13847 13848 PATTERN : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13849 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b 13850 } 13851 { 13852 ICLASS : DPPS 13853 CPL : 3 13854 CATEGORY : SSE 13855 EXTENSION : SSE4 13856 EXCEPTIONS: SSE_TYPE_2D 13857 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 13858 PATTERN : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13859 OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b 13860 13861 PATTERN : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13862 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b 13863 } 13864 #################################################################################### 13865 { 13866 ICLASS : MOVNTDQA 13867 CPL : 3 13868 CATEGORY : SSE 13869 EXTENSION : SSE4 13870 EXCEPTIONS: SSE_TYPE_1 13871 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX 13872 PATTERN : 0x0F 0x38 0x2A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13873 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 13874 } 13875 #################################################################################### 13876 { 13877 ICLASS : EXTRACTPS 13878 CPL : 3 13879 CATEGORY : SSE 13880 EXTENSION : SSE4 13881 EXCEPTIONS: SSE_TYPE_5 13882 ATTRIBUTES : 13883 PATTERN : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13884 OPERANDS : MEM0:w:d REG0=XMM_R():r:ps IMM0:r:b 13885 13886 PATTERN : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13887 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b 13888 } 13889 #################################################################################### 13890 { 13891 ICLASS : INSERTPS 13892 CPL : 3 13893 CATEGORY : SSE 13894 EXTENSION : SSE4 13895 EXCEPTIONS: SSE_TYPE_5 13896 ATTRIBUTES : 13897 PATTERN : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13898 OPERANDS : REG0=XMM_R():rw:ps MEM0:r:d IMM0:r:b 13899 13900 PATTERN : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13901 OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b 13902 } 13903 ############################################################################ 13904 { 13905 ICLASS : MPSADBW 13906 CPL : 3 13907 CATEGORY : SSE 13908 EXTENSION : SSE4 13909 EXCEPTIONS: SSE_TYPE_4 13910 ATTRIBUTES : REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT 13911 PATTERN : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13912 OPERANDS : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 IMM0:r:b 13913 13914 PATTERN : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13915 OPERANDS : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b 13916 } 13917 ############################################################################ 13918 { 13919 ICLASS : PACKUSDW 13920 CPL : 3 13921 CATEGORY : SSE 13922 EXTENSION : SSE4 13923 EXCEPTIONS: SSE_TYPE_4 13924 ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT 13925 PATTERN : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13926 OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 13927 13928 PATTERN : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13929 OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 13930 } 13931 ############################################################################ 13932 { 13933 ICLASS : PBLENDW 13934 CPL : 3 13935 CATEGORY : SSE 13936 EXTENSION : SSE4 13937 EXCEPTIONS: SSE_TYPE_4 13938 ATTRIBUTES : REQUIRES_ALIGNMENT 13939 PATTERN : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13940 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b 13941 13942 PATTERN : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13943 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b 13944 } 13945 ############################################################################ 13946 { 13947 ICLASS : PBLENDVB 13948 CPL : 3 13949 CATEGORY : SSE 13950 EXTENSION : SSE4 13951 EXCEPTIONS: SSE_TYPE_4 13952 ATTRIBUTES : REQUIRES_ALIGNMENT 13953 PATTERN : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 13954 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq REG1=XED_REG_XMM0:r:dq:SUPP 13955 13956 PATTERN : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 13957 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq REG2=XED_REG_XMM0:r:dq:SUPP 13958 } 13959 ############################################################################ 13960 { 13961 ICLASS : PEXTRB 13962 CPL : 3 13963 CATEGORY : SSE 13964 EXTENSION : SSE4 13965 EXCEPTIONS: SSE_TYPE_5 13966 ATTRIBUTES : 13967 PATTERN : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13968 OPERANDS : MEM0:w:b REG0=XMM_R():r:dq IMM0:r:b 13969 # FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b??? 13970 PATTERN : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13971 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b 13972 } 13973 ############################################################################ 13974 { 13975 ICLASS : PEXTRW_SSE4 13976 DISASM_INTEL: pextrw 13977 DISASM_ATTSV: pextrw 13978 CPL : 3 13979 CATEGORY : SSE 13980 EXTENSION : SSE4 13981 EXCEPTIONS: SSE_TYPE_5 13982 ATTRIBUTES : 13983 # this one aliases with the SSE2 version so we made a new name 13984 13985 PATTERN : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 13986 OPERANDS : MEM0:w:w REG0=XMM_R():r:dq IMM0:r:b 13987 IFORM : PEXTRW_SSE4_MEMw_XMMdq_IMMb 13988 13989 # this one aliases with the SSE2 version so we made a new name 13990 PATTERN : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 13991 OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq IMM0:r:b 13992 IFORM : PEXTRW_SSE4_GPR32_XMMdq_IMMb 13993 } 13994 13995 ############################################################################ 13996 { 13997 ICLASS : PEXTRQ 13998 CPL : 3 13999 CATEGORY : SSE 14000 EXTENSION : SSE4 14001 EXCEPTIONS: SSE_TYPE_5 14002 ATTRIBUTES : 14003 PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14004 OPERANDS : MEM0:w:q REG0=XMM_R():r:dq IMM0:r:b 14005 PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14006 OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq IMM0:r:b 14007 } 14008 ############################################################################ 14009 { 14010 ICLASS : PEXTRD 14011 CPL : 3 14012 CATEGORY : SSE 14013 EXTENSION : SSE4 14014 EXCEPTIONS: SSE_TYPE_5 14015 ATTRIBUTES : 14016 PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14017 OPERANDS : MEM0:w:d REG0=XMM_R():r:dq IMM0:r:b 14018 # FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b??? 14019 PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14020 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b 14021 } 14022 ############################################################################ 14023 { 14024 ICLASS : PINSRB 14025 CPL : 3 14026 CATEGORY : SSE 14027 EXTENSION : SSE4 14028 EXCEPTIONS: SSE_TYPE_5 14029 ATTRIBUTES : 14030 PATTERN : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14031 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:b IMM0:r:b 14032 14033 PATTERN : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14034 OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d IMM0:r:b 14035 } 14036 ############################################################################ 14037 { 14038 ICLASS : PINSRD 14039 CPL : 3 14040 CATEGORY : SSE 14041 EXTENSION : SSE4 14042 EXCEPTIONS: SSE_TYPE_5 14043 ATTRIBUTES : 14044 PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14045 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:d IMM0:r:b 14046 14047 PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14048 OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d IMM0:r:b 14049 } 14050 ############################################################################ 14051 { 14052 ICLASS : PINSRQ 14053 CPL : 3 14054 CATEGORY : SSE 14055 EXTENSION : SSE4 14056 EXCEPTIONS: SSE_TYPE_5 14057 ATTRIBUTES : 14058 PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14059 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:q IMM0:r:b 14060 14061 PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14062 OPERANDS : REG0=XMM_R():rw:dq REG1=GPR64_B():r:q IMM0:r:b 14063 } 14064 ############################################################################ 14065 { 14066 ICLASS : ROUNDPD 14067 CPL : 3 14068 CATEGORY : SSE 14069 EXTENSION : SSE4 14070 EXCEPTIONS: SSE_TYPE_2 14071 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 14072 PATTERN : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14073 OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd IMM0:r:b 14074 PATTERN : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14075 OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd IMM0:r:b 14076 } 14077 ############################################################################ 14078 { 14079 ICLASS : ROUNDPS 14080 CPL : 3 14081 CATEGORY : SSE 14082 EXTENSION : SSE4 14083 EXCEPTIONS: SSE_TYPE_2 14084 ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR 14085 PATTERN : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14086 OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps IMM0:r:b 14087 PATTERN : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14088 OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps IMM0:r:b 14089 } 14090 ############################################################################ 14091 { 14092 ICLASS : ROUNDSD 14093 CPL : 3 14094 ATTRIBUTES : simd_scalar MXCSR 14095 CATEGORY : SSE 14096 EXTENSION : SSE4 14097 EXCEPTIONS: SSE_TYPE_3 14098 PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14099 OPERANDS : REG0=XMM_R():w:q MEM0:r:q IMM0:r:b 14100 PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14101 OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b 14102 } 14103 ############################################################################ 14104 { 14105 ICLASS : ROUNDSS 14106 CPL : 3 14107 ATTRIBUTES : simd_scalar MXCSR 14108 CATEGORY : SSE 14109 EXTENSION : SSE4 14110 EXCEPTIONS: SSE_TYPE_3 14111 PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14112 OPERANDS : REG0=XMM_R():w:d MEM0:r:d IMM0:r:b 14113 PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14114 OPERANDS : REG0=XMM_R():w:d REG1=XMM_B():r:d IMM0:r:b 14115 } 14116 ############################################################################ 14117 { 14118 ICLASS : PTEST 14119 CPL : 3 14120 CATEGORY : LOGICAL 14121 EXTENSION : SSE4 14122 EXCEPTIONS: SSE_TYPE_4 14123 ATTRIBUTES : REQUIRES_ALIGNMENT 14124 FLAGS : MUST [ cf-mod zf-mod of-0 af-0 pf-0 sf-0 ] 14125 PATTERN : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14126 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq 14127 PATTERN : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14128 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq 14129 } 14130 ############################################################################ 14131 { 14132 ICLASS : PHMINPOSUW 14133 CPL : 3 14134 CATEGORY : SSE 14135 EXTENSION : SSE4 14136 EXCEPTIONS: SSE_TYPE_4 14137 ATTRIBUTES : REQUIRES_ALIGNMENT 14138 PATTERN : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14139 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 14140 PATTERN : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14141 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 14142 } 14143 14144 14145 { 14146 ICLASS : PMAXSB 14147 CPL : 3 14148 CATEGORY : SSE 14149 EXTENSION : SSE4 14150 EXCEPTIONS: SSE_TYPE_4 14151 ATTRIBUTES : REQUIRES_ALIGNMENT 14152 PATTERN : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14153 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14154 PATTERN : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14155 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14156 } 14157 { 14158 ICLASS : PMAXSD 14159 CPL : 3 14160 CATEGORY : SSE 14161 EXTENSION : SSE4 14162 EXCEPTIONS: SSE_TYPE_4 14163 ATTRIBUTES : REQUIRES_ALIGNMENT 14164 PATTERN : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14165 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14166 PATTERN : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14167 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14168 } 14169 { 14170 ICLASS : PMAXUD 14171 CPL : 3 14172 CATEGORY : SSE 14173 EXTENSION : SSE4 14174 EXCEPTIONS: SSE_TYPE_4 14175 ATTRIBUTES : REQUIRES_ALIGNMENT 14176 PATTERN : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14177 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14178 PATTERN : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14179 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14180 } 14181 { 14182 ICLASS : PMAXUW 14183 CPL : 3 14184 CATEGORY : SSE 14185 EXTENSION : SSE4 14186 EXCEPTIONS: SSE_TYPE_4 14187 ATTRIBUTES : REQUIRES_ALIGNMENT 14188 PATTERN : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14189 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14190 PATTERN : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14191 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14192 } 14193 14194 { 14195 ICLASS : PMINSB 14196 CPL : 3 14197 CATEGORY : SSE 14198 EXTENSION : SSE4 14199 EXCEPTIONS: SSE_TYPE_4 14200 ATTRIBUTES : REQUIRES_ALIGNMENT 14201 PATTERN : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14202 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14203 PATTERN : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14204 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14205 } 14206 { 14207 ICLASS : PMINSD 14208 CPL : 3 14209 CATEGORY : SSE 14210 EXTENSION : SSE4 14211 EXCEPTIONS: SSE_TYPE_4 14212 ATTRIBUTES : REQUIRES_ALIGNMENT 14213 PATTERN : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14214 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14215 PATTERN : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14216 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14217 } 14218 { 14219 ICLASS : PMINUD 14220 CPL : 3 14221 CATEGORY : SSE 14222 EXTENSION : SSE4 14223 EXCEPTIONS: SSE_TYPE_4 14224 ATTRIBUTES : REQUIRES_ALIGNMENT 14225 PATTERN : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14226 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14227 PATTERN : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14228 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14229 } 14230 { 14231 ICLASS : PMINUW 14232 CPL : 3 14233 CATEGORY : SSE 14234 EXTENSION : SSE4 14235 EXCEPTIONS: SSE_TYPE_4 14236 ATTRIBUTES : REQUIRES_ALIGNMENT 14237 PATTERN : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14238 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14239 PATTERN : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14240 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14241 } 14242 14243 { 14244 ICLASS : PMULLD 14245 CPL : 3 14246 CATEGORY : SSE 14247 EXTENSION : SSE4 14248 EXCEPTIONS: SSE_TYPE_4 14249 ATTRIBUTES : REQUIRES_ALIGNMENT 14250 PATTERN : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14251 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14252 PATTERN : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14253 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14254 } 14255 { 14256 ICLASS : PMULDQ 14257 CPL : 3 14258 CATEGORY : SSE 14259 EXTENSION : SSE4 14260 EXCEPTIONS: SSE_TYPE_4 14261 ATTRIBUTES : REQUIRES_ALIGNMENT 14262 PATTERN : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14263 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14264 PATTERN : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14265 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14266 } 14267 14268 14269 14270 14271 14272 { 14273 ICLASS : PMOVSXBW 14274 CPL : 3 14275 CATEGORY : SSE 14276 EXTENSION : SSE4 14277 EXCEPTIONS: SSE_TYPE_5 14278 ATTRIBUTES : 14279 PATTERN : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14280 OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8 14281 PATTERN : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14282 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8 14283 } 14284 { 14285 ICLASS : PMOVSXBD 14286 CPL : 3 14287 CATEGORY : SSE 14288 EXTENSION : SSE4 14289 EXCEPTIONS: SSE_TYPE_5 14290 ATTRIBUTES : 14291 PATTERN : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14292 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8 14293 PATTERN : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14294 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8 14295 } 14296 { 14297 ICLASS : PMOVSXBQ 14298 CPL : 3 14299 CATEGORY : SSE 14300 EXTENSION : SSE4 14301 EXCEPTIONS: SSE_TYPE_5 14302 ATTRIBUTES : 14303 PATTERN : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14304 OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8 14305 PATTERN : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14306 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8 14307 } 14308 14309 { 14310 ICLASS : PMOVSXWD 14311 CPL : 3 14312 CATEGORY : SSE 14313 EXTENSION : SSE4 14314 EXCEPTIONS: SSE_TYPE_5 14315 ATTRIBUTES : 14316 PATTERN : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14317 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16 14318 PATTERN : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14319 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16 14320 } 14321 { 14322 ICLASS : PMOVSXWQ 14323 CPL : 3 14324 CATEGORY : SSE 14325 EXTENSION : SSE4 14326 EXCEPTIONS: SSE_TYPE_5 14327 ATTRIBUTES : 14328 PATTERN : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14329 OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16 14330 PATTERN : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14331 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16 14332 } 14333 { 14334 ICLASS : PMOVSXDQ 14335 CPL : 3 14336 CATEGORY : SSE 14337 EXTENSION : SSE4 14338 EXCEPTIONS: SSE_TYPE_5 14339 ATTRIBUTES : 14340 PATTERN : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14341 OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32 14342 PATTERN : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14343 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32 14344 } 14345 14346 { 14347 ICLASS : PMOVZXBW 14348 CPL : 3 14349 CATEGORY : SSE 14350 EXTENSION : SSE4 14351 EXCEPTIONS: SSE_TYPE_5 14352 ATTRIBUTES : 14353 PATTERN : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14354 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8 14355 PATTERN : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14356 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8 14357 } 14358 { 14359 ICLASS : PMOVZXBD 14360 CPL : 3 14361 CATEGORY : SSE 14362 EXTENSION : SSE4 14363 EXCEPTIONS: SSE_TYPE_5 14364 ATTRIBUTES : 14365 PATTERN : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14366 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8 14367 PATTERN : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14368 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8 14369 } 14370 { 14371 ICLASS : PMOVZXBQ 14372 CPL : 3 14373 CATEGORY : SSE 14374 EXTENSION : SSE4 14375 EXCEPTIONS: SSE_TYPE_5 14376 ATTRIBUTES : 14377 PATTERN : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14378 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8 14379 PATTERN : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14380 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8 14381 } 14382 14383 { 14384 ICLASS : PMOVZXWD 14385 CPL : 3 14386 CATEGORY : SSE 14387 EXTENSION : SSE4 14388 EXCEPTIONS: SSE_TYPE_5 14389 ATTRIBUTES : 14390 PATTERN : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14391 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16 14392 PATTERN : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14393 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16 14394 } 14395 { 14396 ICLASS : PMOVZXWQ 14397 CPL : 3 14398 CATEGORY : SSE 14399 EXTENSION : SSE4 14400 EXCEPTIONS: SSE_TYPE_5 14401 ATTRIBUTES : 14402 PATTERN : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14403 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16 14404 PATTERN : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14405 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16 14406 } 14407 { 14408 ICLASS : PMOVZXDQ 14409 CPL : 3 14410 CATEGORY : SSE 14411 EXTENSION : SSE4 14412 EXCEPTIONS: SSE_TYPE_5 14413 ATTRIBUTES : 14414 PATTERN : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14415 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32 14416 PATTERN : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14417 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32 14418 } 14419 14420 14421 14422 14423 14424 14425 14426 { 14427 ICLASS : PCMPESTRI 14428 CPL : 3 14429 CATEGORY : SSE 14430 EXTENSION : SSE4 14431 ISA_SET : SSE42 14432 EXCEPTIONS: SSE_TYPE_4 14433 ATTRIBUTES: 14434 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 14435 14436 PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14437 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP 14438 14439 PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14440 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP 14441 14442 PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14443 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP 14444 14445 PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14446 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP 14447 } 14448 { 14449 ICLASS : PCMPISTRI 14450 CPL : 3 14451 CATEGORY : SSE 14452 EXTENSION : SSE4 14453 ISA_SET : SSE42 14454 EXCEPTIONS: SSE_TYPE_4 14455 ATTRIBUTES: 14456 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 14457 14458 PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14459 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP 14460 14461 PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14462 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP 14463 14464 PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14465 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP 14466 14467 PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14468 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP 14469 } 14470 14471 { 14472 ICLASS : PCMPESTRM 14473 CPL : 3 14474 CATEGORY : SSE 14475 EXTENSION : SSE4 14476 ISA_SET : SSE42 14477 EXCEPTIONS: SSE_TYPE_4 14478 ATTRIBUTES: 14479 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 14480 14481 PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14482 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP 14483 14484 PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14485 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP 14486 14487 PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14488 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP 14489 14490 PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14491 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP 14492 14493 } 14494 { 14495 ICLASS : PCMPISTRM 14496 CPL : 3 14497 CATEGORY : SSE 14498 EXTENSION : SSE4 14499 ISA_SET : SSE42 14500 EXCEPTIONS: SSE_TYPE_4 14501 ATTRIBUTES: 14502 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 14503 PATTERN : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 14504 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP 14505 14506 PATTERN : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 14507 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP 14508 } 14509 #################################################################################### 14510 { 14511 ICLASS : XGETBV 14512 CPL : 3 14513 CATEGORY : XSAVE 14514 EXTENSION : XSAVE 14515 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix 14516 OPERANDS : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_EAX:w:SUPP REG3=XED_REG_XCR0:r:SUPP 14517 } 14518 14519 { 14520 ICLASS : XSETBV 14521 CPL : 0 14522 CATEGORY : XSAVE 14523 EXTENSION : XSAVE 14524 ATTRIBUTES : RING0 NOTSX 14525 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix 14526 OPERANDS : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_XCR0:w:SUPP 14527 } 14528 14529 14530 { 14531 ICLASS : XSAVE 14532 CPL : 3 14533 CATEGORY : XSAVE 14534 EXTENSION : XSAVE 14535 COMMENT : variable length store 14536 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED 14537 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM() 14538 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR 14539 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 14540 } 14541 { 14542 ICLASS : XRSTOR 14543 CPL : 3 14544 CATEGORY : XSAVE 14545 EXTENSION : XSAVE 14546 COMMENT : variable length load and conditianal reg write 14547 ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED 14548 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM() 14549 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR 14550 OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 14551 } 14552 14553 14554 { 14555 ICLASS : XSAVE64 14556 CPL : 3 14557 CATEGORY : XSAVE 14558 EXTENSION : XSAVE 14559 COMMENT : variable length store 14560 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED 14561 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM() 14562 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR 14563 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 14564 } 14565 14566 { 14567 ICLASS : XRSTOR64 14568 CPL : 3 14569 CATEGORY : XSAVE 14570 EXTENSION : XSAVE 14571 COMMENT : variable length load and conditianal reg write 14572 ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED 14573 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM() 14574 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR 14575 OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 14576 } 14577 14578 14579 14580 14581 14582 #################################################################################### 14583 14584 { 14585 ICLASS : MOVBE 14586 CPL : 3 14587 CATEGORY : DATAXFER 14588 EXTENSION : MOVBE 14589 COMMENT : Intro on Atom Silverthorne. Intercepted by Haswell. 14590 # 14591 # must allow 66 prefix. So "not_refning" gives us REFINING=0 which suffices to exclude F2/F3 prefixes. 14592 # 14593 PATTERN : 0x0F 0x38 0xF0 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14594 OPERANDS : REG0=GPRv_R():w MEM0:r:v 14595 PATTERN : 0x0F 0x38 0xF1 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 14596 OPERANDS : MEM0:w:v REG0=GPRv_R():r 14597 } 14598 14599 14600 { 14601 ICLASS : GETSEC 14602 CPL : 3 14603 CATEGORY : SYSTEM 14604 ATTRIBUTES: PROTECTED_MODE NOTSX 14605 EXTENSION : SMX 14606 PATTERN : 0x0F 0x37 14607 OPERANDS : REG0=XED_REG_EAX:rcw:SUPP REG1=XED_REG_EBX:r:SUPP 14608 } 14609 14610 14611 #################################################################################### 14612 { 14613 ICLASS : AESKEYGENASSIST 14614 CPL : 3 14615 CATEGORY : AES 14616 EXTENSION : AES 14617 EXCEPTIONS: SSE_TYPE_4 14618 ATTRIBUTES : REQUIRES_ALIGNMENT 14619 PATTERN : 0x0F 0x3A 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() 14620 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b 14621 PATTERN : 0x0F 0x3A 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() 14622 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b 14623 } 14624 { 14625 ICLASS : AESENC 14626 CPL : 3 14627 CATEGORY : AES 14628 EXTENSION : AES 14629 EXCEPTIONS: SSE_TYPE_4 14630 ATTRIBUTES : REQUIRES_ALIGNMENT 14631 PATTERN : 0x0F 0x38 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 14632 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14633 PATTERN : 0x0F 0x38 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 14634 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14635 } 14636 { 14637 ICLASS : AESENCLAST 14638 CPL : 3 14639 CATEGORY : AES 14640 EXTENSION : AES 14641 EXCEPTIONS: SSE_TYPE_4 14642 ATTRIBUTES : REQUIRES_ALIGNMENT 14643 PATTERN : 0x0F 0x38 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 14644 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14645 PATTERN : 0x0F 0x38 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 14646 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14647 } 14648 { 14649 ICLASS : AESDEC 14650 CPL : 3 14651 CATEGORY : AES 14652 EXTENSION : AES 14653 EXCEPTIONS: SSE_TYPE_4 14654 ATTRIBUTES : REQUIRES_ALIGNMENT 14655 PATTERN : 0x0F 0x38 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 14656 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14657 PATTERN : 0x0F 0x38 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 14658 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14659 } 14660 { 14661 ICLASS : AESDECLAST 14662 CPL : 3 14663 CATEGORY : AES 14664 EXTENSION : AES 14665 EXCEPTIONS: SSE_TYPE_4 14666 ATTRIBUTES : REQUIRES_ALIGNMENT 14667 PATTERN : 0x0F 0x38 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 14668 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq 14669 PATTERN : 0x0F 0x38 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 14670 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq 14671 } 14672 { 14673 ICLASS : AESIMC 14674 CPL : 3 14675 CATEGORY : AES 14676 EXTENSION : AES 14677 EXCEPTIONS: SSE_TYPE_4 14678 ATTRIBUTES : REQUIRES_ALIGNMENT 14679 PATTERN : 0x0F 0x38 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() 14680 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 14681 PATTERN : 0x0F 0x38 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() 14682 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 14683 } 14684 #################################################################################### 14685 { 14686 ICLASS : PCLMULQDQ 14687 CPL : 3 14688 CATEGORY : PCLMULQDQ 14689 EXTENSION : PCLMULQDQ 14690 EXCEPTIONS: SSE_TYPE_4 14691 ATTRIBUTES : REQUIRES_ALIGNMENT 14692 PATTERN : 0x0F 0x3A 0x44 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() 14693 OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b 14694 PATTERN : 0x0F 0x3A 0x44 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() 14695 OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b 14696 } 14697 14698 14699 ####################################################################### 14700 { 14701 ICLASS : INVEPT 14702 CPL : 0 14703 CATEGORY : VTX 14704 EXTENSION : VTX 14705 ATTRIBUTES : RING0 NOTSX 14706 PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() 14707 OPERANDS : REG0=GPR64_R():r MEM0:r:dq 14708 PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode32 MODRM() CR_WIDTH() 14709 OPERANDS : REG0=GPR32_R():r MEM0:r:dq 14710 COMMENT : SDM rev 27 14711 } 14712 { 14713 ICLASS : INVVPID 14714 CPL : 0 14715 CATEGORY : VTX 14716 EXTENSION : VTX 14717 ATTRIBUTES : RING0 NOTSX 14718 PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() 14719 OPERANDS : REG0=GPR64_R():r MEM0:r:dq 14720 PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode32 MODRM() CR_WIDTH() 14721 OPERANDS : REG0=GPR32_R():r MEM0:r:dq 14722 COMMENT : SDM rev 27 14723 } 14724 14725 14726 14727 14728 14729 14730 ###FILE: ../xed/datafiles/xed-amd-prefetch.txt 14731 14732 #BEGIN_LEGAL 14733 # 14734 #Copyright (c) 2016 Intel Corporation 14735 # 14736 # Licensed under the Apache License, Version 2.0 (the "License"); 14737 # you may not use this file except in compliance with the License. 14738 # You may obtain a copy of the License at 14739 # 14740 # http://www.apache.org/licenses/LICENSE-2.0 14741 # 14742 # Unless required by applicable law or agreed to in writing, software 14743 # distributed under the License is distributed on an "AS IS" BASIS, 14744 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14745 # See the License for the specific language governing permissions and 14746 # limitations under the License. 14747 # 14748 #END_LEGAL 14749 14750 INSTRUCTIONS():: 14751 { 14752 ICLASS : NOP 14753 UNAME : NOP0F0D_reg 14754 CPL : 3 14755 CATEGORY : WIDENOP 14756 EXTENSION : BASE 14757 ISA_SET : PREFETCH_NOP 14758 COMMENT : AMD 3DNOW prefetches that do not touch memory. This is the reg/reg form. 14759 14760 PATTERN : 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn] 14761 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 14762 IFORM : NOP_GPRv_GPRv_0F0D 14763 } 14764 14765 # The rest are all mem forms (MODRM.MOD!=3) 14766 14767 { 14768 ICLASS : PREFETCH_EXCLUSIVE 14769 CPL : 3 14770 ATTRIBUTES: PREFETCH 14771 CATEGORY : PREFETCH 14772 EXTENSION : 3DNOW 14773 ISA_SET : PREFETCH_NOP 14774 PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() 14775 OPERANDS : MEM0:r:mprefetch 14776 } 14777 { 14778 ICLASS : PREFETCHW 14779 CPL : 3 14780 ATTRIBUTES: PREFETCH 14781 CATEGORY : PREFETCH 14782 EXTENSION : 3DNOW 14783 COMMENT: : was PREFETCH_MODIFIED, prefetch on >=broadwell and >=silvermont 14784 ISA_SET : PREFETCH_NOP 14785 PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 14786 OPERANDS : MEM0:r:mprefetch 14787 IFORM : PREFETCHW_0F0Dr1 14788 } 14789 { 14790 ICLASS : PREFETCH_RESERVED 14791 CPL : 3 14792 ATTRIBUTES: PREFETCH 14793 CATEGORY : PREFETCH 14794 EXTENSION : 3DNOW 14795 ISA_SET : PREFETCH_NOP 14796 PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 14797 OPERANDS : MEM0:r:mprefetch 14798 IFORM : PREFETCH_RESERVED_0F0Dr2 14799 UNAME : PREFETCH_RESERVED_0F0Dr2 14800 } 14801 { 14802 ICLASS : PREFETCHW 14803 CPL : 3 14804 ATTRIBUTES: PREFETCH 14805 CATEGORY : PREFETCH 14806 EXTENSION : 3DNOW 14807 COMMENT: : was PREFETCH_MODIFIED 14808 ISA_SET : PREFETCH_NOP 14809 PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 14810 OPERANDS : MEM0:r:mprefetch 14811 IFORM : PREFETCHW_0F0Dr3 14812 } 14813 { 14814 ICLASS : PREFETCH_RESERVED 14815 CPL : 3 14816 ATTRIBUTES: PREFETCH 14817 CATEGORY : PREFETCH 14818 EXTENSION : 3DNOW 14819 ISA_SET : PREFETCH_NOP 14820 PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 14821 OPERANDS : MEM0:r:mprefetch 14822 IFORM : PREFETCH_RESERVED_0F0Dr4 14823 14824 PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 14825 OPERANDS : MEM0:r:mprefetch 14826 IFORM : PREFETCH_RESERVED_0F0Dr5 14827 14828 PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 14829 OPERANDS : MEM0:r:mprefetch 14830 IFORM : PREFETCH_RESERVED_0F0Dr6 14831 14832 PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 14833 OPERANDS : MEM0:r:mprefetch 14834 IFORM : PREFETCH_RESERVED_0F0Dr7 14835 } 14836 14837 14838 14839 ###FILE: ../xed/datafiles/xed-nops.txt 14840 14841 #BEGIN_LEGAL 14842 # 14843 #Copyright (c) 2016 Intel Corporation 14844 # 14845 # Licensed under the Apache License, Version 2.0 (the "License"); 14846 # you may not use this file except in compliance with the License. 14847 # You may obtain a copy of the License at 14848 # 14849 # http://www.apache.org/licenses/LICENSE-2.0 14850 # 14851 # Unless required by applicable law or agreed to in writing, software 14852 # distributed under the License is distributed on an "AS IS" BASIS, 14853 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14854 # See the License for the specific language governing permissions and 14855 # limitations under the License. 14856 # 14857 #END_LEGAL 14858 #################################################################### 14859 # SPECIFIC WIDE NOPS RECOMMENDED BY THE PROGRAMMERS REFERENCE MANUAL 14860 #################################################################### 14861 #{ 14862 #ICLASS : NOP1 14863 #CPL : 3 14864 #CATEGORY : WIDENOP 14865 #EXTENSION : BASE 14866 #PATTERN : 90 14867 #OPERANDS : 14868 #} 14869 { 14870 ICLASS : NOP2 14871 CPL : 3 14872 CATEGORY : WIDENOP 14873 EXTENSION : BASE 14874 PATTERN : 0x66 0x90 14875 OPERANDS : 14876 } 14877 { 14878 ICLASS : NOP3 14879 CPL : 3 14880 CATEGORY : WIDENOP 14881 EXTENSION : BASE 14882 PATTERN : 0x0F 0x1F 0x00 14883 OPERANDS : 14884 } 14885 { 14886 ICLASS : NOP4 14887 CPL : 3 14888 CATEGORY : WIDENOP 14889 EXTENSION : BASE 14890 PATTERN : 0x0F 0x1F 0x40 0x00 14891 OPERANDS : 14892 } 14893 { 14894 ICLASS : NOP5 14895 CPL : 3 14896 CATEGORY : WIDENOP 14897 EXTENSION : BASE 14898 PATTERN : 0x0F 0x1F 0x44 0x00 0x00 14899 OPERANDS : 14900 } 14901 { 14902 ICLASS : NOP6 14903 CPL : 3 14904 CATEGORY : WIDENOP 14905 EXTENSION : BASE 14906 PATTERN : 0x66 0x0F 0x1F 0x44 0x00 0x00 14907 OPERANDS : 14908 } 14909 { 14910 ICLASS : NOP7 14911 CPL : 3 14912 CATEGORY : WIDENOP 14913 EXTENSION : BASE 14914 PATTERN : 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 14915 OPERANDS : 14916 } 14917 { 14918 ICLASS : NOP8 14919 CPL : 3 14920 CATEGORY : WIDENOP 14921 EXTENSION : BASE 14922 PATTERN : 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 14923 OPERANDS : 14924 } 14925 { 14926 ICLASS : NOP9 14927 CPL : 3 14928 CATEGORY : WIDENOP 14929 EXTENSION : BASE 14930 PATTERN : 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 14931 OPERANDS : 14932 } 14933 14934 14935 ###FILE: ../xed/datafiles/xed-amd-3dnow.txt 14936 14937 #BEGIN_LEGAL 14938 # 14939 #Copyright (c) 2016 Intel Corporation 14940 # 14941 # Licensed under the Apache License, Version 2.0 (the "License"); 14942 # you may not use this file except in compliance with the License. 14943 # You may obtain a copy of the License at 14944 # 14945 # http://www.apache.org/licenses/LICENSE-2.0 14946 # 14947 # Unless required by applicable law or agreed to in writing, software 14948 # distributed under the License is distributed on an "AS IS" BASIS, 14949 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14950 # See the License for the specific language governing permissions and 14951 # limitations under the License. 14952 # 14953 #END_LEGAL 14954 14955 INSTRUCTIONS():: 14956 { 14957 ICLASS : FEMMS 14958 CPL : 3 14959 CATEGORY : MMX 14960 EXTENSION : 3DNOW 14961 ATTRIBUTES : x87_mmx_state_w 14962 PATTERN : 0x0F 0x0E 14963 OPERANDS : 14964 } 14965 { 14966 ICLASS : PI2FW 14967 CPL : 3 14968 CATEGORY : 3DNOW 14969 EXTENSION : 3DNOW 14970 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0C 14971 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 14972 } 14973 { 14974 ICLASS : PI2FW 14975 CPL : 3 14976 CATEGORY : 3DNOW 14977 EXTENSION : 3DNOW 14978 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0C 14979 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 14980 } 14981 { 14982 ICLASS : PI2FD 14983 CPL : 3 14984 CATEGORY : 3DNOW 14985 EXTENSION : 3DNOW 14986 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0D 14987 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 14988 } 14989 { 14990 ICLASS : PI2FD 14991 CPL : 3 14992 CATEGORY : 3DNOW 14993 EXTENSION : 3DNOW 14994 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0D 14995 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 14996 } 14997 { 14998 ICLASS : PF2IW 14999 CPL : 3 15000 CATEGORY : 3DNOW 15001 EXTENSION : 3DNOW 15002 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1C 15003 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15004 } 15005 { 15006 ICLASS : PF2IW 15007 CPL : 3 15008 CATEGORY : 3DNOW 15009 EXTENSION : 3DNOW 15010 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1C 15011 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15012 } 15013 { 15014 ICLASS : PF2ID 15015 CPL : 3 15016 CATEGORY : 3DNOW 15017 EXTENSION : 3DNOW 15018 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1D 15019 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15020 } 15021 { 15022 ICLASS : PF2ID 15023 CPL : 3 15024 CATEGORY : 3DNOW 15025 EXTENSION : 3DNOW 15026 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1D 15027 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15028 } 15029 { 15030 ICLASS : PFNACC 15031 CPL : 3 15032 CATEGORY : 3DNOW 15033 EXTENSION : 3DNOW 15034 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8A 15035 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15036 } 15037 { 15038 ICLASS : PFNACC 15039 CPL : 3 15040 CATEGORY : 3DNOW 15041 EXTENSION : 3DNOW 15042 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8A 15043 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15044 } 15045 { 15046 ICLASS : PFPNACC 15047 CPL : 3 15048 CATEGORY : 3DNOW 15049 EXTENSION : 3DNOW 15050 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8E 15051 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15052 } 15053 { 15054 ICLASS : PFPNACC 15055 CPL : 3 15056 CATEGORY : 3DNOW 15057 EXTENSION : 3DNOW 15058 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8E 15059 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15060 } 15061 { 15062 ICLASS : PFCMPGE 15063 CPL : 3 15064 CATEGORY : 3DNOW 15065 EXTENSION : 3DNOW 15066 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x90 15067 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15068 } 15069 { 15070 ICLASS : PFCMPGE 15071 CPL : 3 15072 CATEGORY : 3DNOW 15073 EXTENSION : 3DNOW 15074 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x90 15075 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15076 } 15077 { 15078 ICLASS : PFMIN 15079 CPL : 3 15080 CATEGORY : 3DNOW 15081 EXTENSION : 3DNOW 15082 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x94 15083 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15084 } 15085 { 15086 ICLASS : PFMIN 15087 CPL : 3 15088 CATEGORY : 3DNOW 15089 EXTENSION : 3DNOW 15090 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x94 15091 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15092 } 15093 { 15094 ICLASS : PFRCP 15095 CPL : 3 15096 CATEGORY : 3DNOW 15097 EXTENSION : 3DNOW 15098 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x96 15099 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15100 } 15101 { 15102 ICLASS : PFRCP 15103 CPL : 3 15104 CATEGORY : 3DNOW 15105 EXTENSION : 3DNOW 15106 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x96 15107 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15108 } 15109 { 15110 ICLASS : PFSQRT 15111 CPL : 3 15112 CATEGORY : 3DNOW 15113 EXTENSION : 3DNOW 15114 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x97 15115 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15116 } 15117 { 15118 ICLASS : PFSQRT 15119 CPL : 3 15120 CATEGORY : 3DNOW 15121 EXTENSION : 3DNOW 15122 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x97 15123 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15124 } 15125 { 15126 ICLASS : PFSUB 15127 CPL : 3 15128 CATEGORY : 3DNOW 15129 EXTENSION : 3DNOW 15130 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9A 15131 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15132 } 15133 { 15134 ICLASS : PFSUB 15135 CPL : 3 15136 CATEGORY : 3DNOW 15137 EXTENSION : 3DNOW 15138 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9A 15139 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15140 } 15141 { 15142 ICLASS : PFADD 15143 CPL : 3 15144 CATEGORY : 3DNOW 15145 EXTENSION : 3DNOW 15146 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9E 15147 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15148 } 15149 { 15150 ICLASS : PFADD 15151 CPL : 3 15152 CATEGORY : 3DNOW 15153 EXTENSION : 3DNOW 15154 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9E 15155 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15156 } 15157 { 15158 ICLASS : PFCMPGT 15159 CPL : 3 15160 CATEGORY : 3DNOW 15161 EXTENSION : 3DNOW 15162 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA0 15163 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15164 } 15165 { 15166 ICLASS : PFCMPGT 15167 CPL : 3 15168 CATEGORY : 3DNOW 15169 EXTENSION : 3DNOW 15170 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA0 15171 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15172 } 15173 { 15174 ICLASS : PFMAX 15175 CPL : 3 15176 CATEGORY : 3DNOW 15177 EXTENSION : 3DNOW 15178 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA4 15179 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15180 } 15181 { 15182 ICLASS : PFMAX 15183 CPL : 3 15184 CATEGORY : 3DNOW 15185 EXTENSION : 3DNOW 15186 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA4 15187 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15188 } 15189 { 15190 ICLASS : PFCPIT1 15191 CPL : 3 15192 CATEGORY : 3DNOW 15193 EXTENSION : 3DNOW 15194 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA6 15195 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15196 } 15197 { 15198 ICLASS : PFCPIT1 15199 CPL : 3 15200 CATEGORY : 3DNOW 15201 EXTENSION : 3DNOW 15202 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA6 15203 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15204 } 15205 { 15206 ICLASS : PFRSQIT1 15207 CPL : 3 15208 CATEGORY : 3DNOW 15209 EXTENSION : 3DNOW 15210 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA7 15211 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15212 } 15213 { 15214 ICLASS : PFRSQIT1 15215 CPL : 3 15216 CATEGORY : 3DNOW 15217 EXTENSION : 3DNOW 15218 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA7 15219 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15220 } 15221 { 15222 ICLASS : PFSUBR 15223 CPL : 3 15224 CATEGORY : 3DNOW 15225 EXTENSION : 3DNOW 15226 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAA 15227 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15228 } 15229 { 15230 ICLASS : PFSUBR 15231 CPL : 3 15232 CATEGORY : 3DNOW 15233 EXTENSION : 3DNOW 15234 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAA 15235 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15236 } 15237 { 15238 ICLASS : PFACC 15239 CPL : 3 15240 CATEGORY : 3DNOW 15241 EXTENSION : 3DNOW 15242 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAE 15243 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15244 } 15245 { 15246 ICLASS : PFACC 15247 CPL : 3 15248 CATEGORY : 3DNOW 15249 EXTENSION : 3DNOW 15250 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAE 15251 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15252 } 15253 { 15254 ICLASS : PFCMPEQ 15255 CPL : 3 15256 CATEGORY : 3DNOW 15257 EXTENSION : 3DNOW 15258 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB0 15259 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15260 } 15261 { 15262 ICLASS : PFCMPEQ 15263 CPL : 3 15264 CATEGORY : 3DNOW 15265 EXTENSION : 3DNOW 15266 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB0 15267 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15268 } 15269 { 15270 ICLASS : PFMUL 15271 CPL : 3 15272 CATEGORY : 3DNOW 15273 EXTENSION : 3DNOW 15274 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB4 15275 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15276 } 15277 { 15278 ICLASS : PFMUL 15279 CPL : 3 15280 CATEGORY : 3DNOW 15281 EXTENSION : 3DNOW 15282 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB4 15283 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15284 } 15285 { 15286 ICLASS : PFRCPIT2 15287 CPL : 3 15288 CATEGORY : 3DNOW 15289 EXTENSION : 3DNOW 15290 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB6 15291 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15292 } 15293 { 15294 ICLASS : PFRCPIT2 15295 CPL : 3 15296 CATEGORY : 3DNOW 15297 EXTENSION : 3DNOW 15298 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB6 15299 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15300 } 15301 { 15302 ICLASS : PMULHRW 15303 CPL : 3 15304 CATEGORY : 3DNOW 15305 EXTENSION : 3DNOW 15306 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB7 15307 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15308 } 15309 { 15310 ICLASS : PMULHRW 15311 CPL : 3 15312 CATEGORY : 3DNOW 15313 EXTENSION : 3DNOW 15314 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB7 15315 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15316 } 15317 { 15318 ICLASS : PSWAPD 15319 CPL : 3 15320 CATEGORY : 3DNOW 15321 EXTENSION : 3DNOW 15322 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBB 15323 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15324 } 15325 { 15326 ICLASS : PSWAPD 15327 CPL : 3 15328 CATEGORY : 3DNOW 15329 EXTENSION : 3DNOW 15330 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBB 15331 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15332 } 15333 { 15334 ICLASS : PAVGUSB 15335 CPL : 3 15336 CATEGORY : 3DNOW 15337 EXTENSION : 3DNOW 15338 PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBF 15339 OPERANDS : REG0=MMX_R():rw:q MEM0:r:q 15340 } 15341 { 15342 ICLASS : PAVGUSB 15343 CPL : 3 15344 CATEGORY : 3DNOW 15345 EXTENSION : 3DNOW 15346 PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBF 15347 OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q 15348 } 15349 15350 15351 ###FILE: ../xed/datafiles/xed-amd-base.txt 15352 15353 #BEGIN_LEGAL 15354 # 15355 #Copyright (c) 2016 Intel Corporation 15356 # 15357 # Licensed under the Apache License, Version 2.0 (the "License"); 15358 # you may not use this file except in compliance with the License. 15359 # You may obtain a copy of the License at 15360 # 15361 # http://www.apache.org/licenses/LICENSE-2.0 15362 # 15363 # Unless required by applicable law or agreed to in writing, software 15364 # distributed under the License is distributed on an "AS IS" BASIS, 15365 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15366 # See the License for the specific language governing permissions and 15367 # limitations under the License. 15368 # 15369 #END_LEGAL 15370 # file: xed-amd-base.txt 15371 15372 INSTRUCTIONS():: 15373 # SYSCALL and SYSRET are supported in 32b mode only on AMD chips 15374 15375 { 15376 ICLASS : SYSCALL_AMD 15377 DISASM : syscall 15378 CPL : 3 15379 CATEGORY : SYSCALL 15380 EXTENSION : BASE 15381 ISA_SET : AMD 15382 FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 15383 PATTERN : 0x0F 0x05 not64 IGNORE66() 15384 OPERANDS : REG0=rIP():w:SUPP 15385 } 15386 15387 15388 { 15389 ICLASS : SYSRET_AMD 15390 DISASM : sysret 15391 CPL : 0 15392 CATEGORY : SYSRET 15393 ATTRIBUTES: PROTECTED_MODE RING0 15394 EXTENSION : BASE 15395 ISA_SET : AMD 15396 FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] 15397 PATTERN : 0x0F 0x07 not64 15398 OPERANDS : REG0=XED_REG_EIP:w:SUPP 15399 } 15400 15401 15402 ###FILE: ../xed/datafiles/xed-amd-svm.txt 15403 15404 #BEGIN_LEGAL 15405 # 15406 #Copyright (c) 2016 Intel Corporation 15407 # 15408 # Licensed under the Apache License, Version 2.0 (the "License"); 15409 # you may not use this file except in compliance with the License. 15410 # You may obtain a copy of the License at 15411 # 15412 # http://www.apache.org/licenses/LICENSE-2.0 15413 # 15414 # Unless required by applicable law or agreed to in writing, software 15415 # distributed under the License is distributed on an "AS IS" BASIS, 15416 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15417 # See the License for the specific language governing permissions and 15418 # limitations under the License. 15419 # 15420 #END_LEGAL 15421 INSTRUCTIONS():: 15422 { 15423 ICLASS : VMRUN 15424 CPL : 3 15425 CATEGORY : SYSTEM 15426 EXTENSION : SVM 15427 ATTRIBUTES: PROTECTED_MODE 15428 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000] 15429 OPERANDS : REG0=OrAX():r:IMPL 15430 } 15431 { 15432 ICLASS : VMMCALL 15433 CPL : 3 15434 CATEGORY : SYSTEM 15435 EXTENSION : SVM 15436 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001] 15437 OPERANDS : 15438 } 15439 { 15440 ICLASS : VMLOAD 15441 CPL : 3 15442 CATEGORY : SYSTEM 15443 EXTENSION : SVM 15444 ATTRIBUTES: PROTECTED_MODE 15445 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010] 15446 OPERANDS : REG0=OrAX():r:IMPL 15447 } 15448 { 15449 ICLASS : VMSAVE 15450 CPL : 3 15451 CATEGORY : SYSTEM 15452 EXTENSION : SVM 15453 ATTRIBUTES: PROTECTED_MODE 15454 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011] 15455 OPERANDS : 15456 } 15457 { 15458 ICLASS : STGI 15459 CPL : 3 15460 CATEGORY : SYSTEM 15461 EXTENSION : SVM 15462 ATTRIBUTES: PROTECTED_MODE 15463 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100] 15464 OPERANDS : 15465 } 15466 { 15467 ICLASS : CLGI 15468 CPL : 3 15469 CATEGORY : SYSTEM 15470 EXTENSION : SVM 15471 ATTRIBUTES: PROTECTED_MODE 15472 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101] 15473 OPERANDS : 15474 } 15475 { 15476 ICLASS : SKINIT 15477 CPL : 3 15478 CATEGORY : SYSTEM 15479 EXTENSION : SVM 15480 ATTRIBUTES: PROTECTED_MODE 15481 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110] 15482 OPERANDS : REG0=XED_REG_EAX:r:IMPL 15483 } 15484 { 15485 ICLASS : INVLPGA 15486 CPL : 0 15487 CATEGORY : SYSTEM 15488 EXTENSION : SVM 15489 ATTRIBUTES: PROTECTED_MODE 15490 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111] 15491 OPERANDS : REG0=OrAX():r:IMPL REG1=XED_REG_ECX:r:IMPL 15492 } 15493 15494 15495 ###FILE: ../xed/datafiles/xed-amd-sse4a.txt 15496 15497 #BEGIN_LEGAL 15498 # 15499 #Copyright (c) 2016 Intel Corporation 15500 # 15501 # Licensed under the Apache License, Version 2.0 (the "License"); 15502 # you may not use this file except in compliance with the License. 15503 # You may obtain a copy of the License at 15504 # 15505 # http://www.apache.org/licenses/LICENSE-2.0 15506 # 15507 # Unless required by applicable law or agreed to in writing, software 15508 # distributed under the License is distributed on an "AS IS" BASIS, 15509 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15510 # See the License for the specific language governing permissions and 15511 # limitations under the License. 15512 # 15513 #END_LEGAL 15514 # EXTRQ xmm:w:q, imm8, imm8 66 0F 78 /0 ib ib 15515 # EXTRQ xmm:w:q, xmm:r:w 66 0F 79 /r 15516 15517 { 15518 ICLASS : EXTRQ 15519 CPL : 3 15520 CATEGORY : BITBYTE 15521 EXTENSION : SSE4a 15522 ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION 15523 PATTERN : 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1() 15524 OPERANDS : REG0=XMM_R():w:q IMM0:r:b IMM1:r:b 15525 PATTERN : 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 15526 OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq 15527 } 15528 15529 # INSERTQ xmm:w:q xmm:r:q, imm8, imm8 f2 0f 78 /r ib ib 15530 # INSERTQ xmm:w:q xmm:r:dq, f2 0f 79 /r 15531 15532 { 15533 ICLASS : INSERTQ 15534 CPL : 3 15535 CATEGORY : BITBYTE 15536 EXTENSION : SSE4a 15537 ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION 15538 PATTERN : 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1() 15539 OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b IMM1:r:b 15540 PATTERN : 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 15541 OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq 15542 } 15543 15544 15545 # MOVNTSD mem64:w:q, xmm:r:q f2 0f 2b /r 15546 # MOVNTSS mem32:w:d, xmm:r:d f3 0f 2b /r 15547 15548 { 15549 ICLASS : MOVNTSD 15550 CPL : 3 15551 CATEGORY : DATAXFER 15552 EXTENSION : SSE4a 15553 PATTERN : 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 15554 OPERANDS : MEM0:w:q REG0=XMM_R():r:q 15555 } 15556 { 15557 ICLASS : MOVNTSS 15558 CPL : 3 15559 CATEGORY : DATAXFER 15560 EXTENSION : SSE4a 15561 PATTERN : 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 15562 OPERANDS : MEM0:w:d REG0=XMM_R():r:d 15563 } 15564 15565 ######################################################################################################### 15566 # These next one is not part of SSE4a or SSE5. 15567 15568 # LZCNT reg16, reg/mem16 F30FBD /r 15569 # LZCNT reg32, reg/mem32 F30FBD /r 15570 # LZCNT reg64, reg/mem64 F30FBD /r 15571 15572 { 15573 ICLASS : LZCNT 15574 CPL : 3 15575 CATEGORY : BITBYTE 15576 EXTENSION : AMD 15577 FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] 15578 PATTERN : 0x0F 0xBD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 15579 OPERANDS : REG0=GPRv_R():w:v MEM0:r:v 15580 PATTERN : 0x0F 0xBD f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 15581 OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v 15582 } 15583 15584 15585 { 15586 ICLASS : BSR 15587 VERSION : 1 15588 COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR 15589 CPL : 3 15590 CATEGORY : BITBYTE 15591 EXTENSION : BASE 15592 ISA_SET : I386 15593 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] 15594 PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 15595 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 15596 15597 PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 15598 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 15599 } 15600 15601 15602 ###FILE: ../xed/datafiles/xed-amd-clzero.txt 15603 15604 #BEGIN_LEGAL 15605 # 15606 #Copyright (c) 2016 Intel Corporation 15607 # 15608 # Licensed under the Apache License, Version 2.0 (the "License"); 15609 # you may not use this file except in compliance with the License. 15610 # You may obtain a copy of the License at 15611 # 15612 # http://www.apache.org/licenses/LICENSE-2.0 15613 # 15614 # Unless required by applicable law or agreed to in writing, software 15615 # distributed under the License is distributed on an "AS IS" BASIS, 15616 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15617 # See the License for the specific language governing permissions and 15618 # limitations under the License. 15619 # 15620 #END_LEGAL 15621 INSTRUCTIONS():: 15622 { 15623 ICLASS : CLZERO 15624 CPL : 3 15625 CATEGORY : CLZERO 15626 EXTENSION : CLZERO 15627 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100] 15628 OPERANDS : REG0=OrAX():r:IMPL 15629 COMMENT : AMD "Zen" ~2016 (expected) CPU 15630 } 15631 15632 15633 ###FILE: ../xed/datafiles/amdxop/amd-xop-isa.txt 15634 15635 #BEGIN_LEGAL 15636 # 15637 #Copyright (c) 2016 Intel Corporation 15638 # 15639 # Licensed under the Apache License, Version 2.0 (the "License"); 15640 # you may not use this file except in compliance with the License. 15641 # You may obtain a copy of the License at 15642 # 15643 # http://www.apache.org/licenses/LICENSE-2.0 15644 # 15645 # Unless required by applicable law or agreed to in writing, software 15646 # distributed under the License is distributed on an "AS IS" BASIS, 15647 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15648 # See the License for the specific language governing permissions and 15649 # limitations under the License. 15650 # 15651 #END_LEGAL 15652 15653 XOP_INSTRUCTIONS():: 15654 { 15655 ICLASS: VPMACSSWW 15656 CPL: 3 15657 CATEGORY: XOP 15658 ISA_SET: XOP 15659 EXTENSION: XOP 15660 15661 PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15662 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 15663 15664 PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15665 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 15666 } 15667 15668 { 15669 ICLASS: VPMACSSWD 15670 CPL: 3 15671 CATEGORY: XOP 15672 ISA_SET: XOP 15673 EXTENSION: XOP 15674 15675 PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15676 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 15677 15678 PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15679 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 15680 } 15681 15682 { 15683 ICLASS: VPMACSSDQL 15684 CPL: 3 15685 CATEGORY: XOP 15686 ISA_SET: XOP 15687 EXTENSION: XOP 15688 15689 PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15690 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 15691 15692 PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15693 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 15694 } 15695 15696 { 15697 ICLASS: VPMACSWW 15698 CPL: 3 15699 CATEGORY: XOP 15700 ISA_SET: XOP 15701 EXTENSION: XOP 15702 15703 PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15704 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 15705 15706 PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15707 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 15708 } 15709 15710 { 15711 ICLASS: VPMACSWD 15712 CPL: 3 15713 CATEGORY: XOP 15714 ISA_SET: XOP 15715 EXTENSION: XOP 15716 15717 PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15718 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 15719 15720 PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15721 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 15722 } 15723 15724 { 15725 ICLASS: VPMACSDQL 15726 CPL: 3 15727 CATEGORY: XOP 15728 ISA_SET: XOP 15729 EXTENSION: XOP 15730 15731 PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15732 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 15733 15734 PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15735 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 15736 } 15737 15738 { 15739 ICLASS: VPCMOV 15740 CPL: 3 15741 CATEGORY: XOP 15742 ISA_SET: XOP 15743 EXTENSION: XOP 15744 15745 PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15746 OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 MEM0:r:dq:i1 REG2=XMM_SE():r:dq:i1 15747 15748 PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15749 OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_B():r:dq:i1 REG3=XMM_SE():r:dq:i1 15750 15751 PATTERN: XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15752 OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 MEM0:r:dq:i1 15753 15754 PATTERN: XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15755 OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 REG3=XMM_B():r:dq:i1 15756 15757 PATTERN: XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15758 OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 MEM0:r:qq:i1 REG2=YMM_SE():r:qq:i1 15759 15760 PATTERN: XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15761 OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_B():r:qq:i1 REG3=YMM_SE():r:qq:i1 15762 15763 PATTERN: XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15764 OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 MEM0:r:qq:i1 15765 15766 PATTERN: XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15767 OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 REG3=YMM_B():r:qq:i1 15768 } 15769 15770 { 15771 ICLASS: VPPERM 15772 CPL: 3 15773 CATEGORY: XOP 15774 ISA_SET: XOP 15775 EXTENSION: XOP 15776 15777 PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15778 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 15779 15780 PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15781 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 15782 15783 PATTERN: XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15784 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 MEM0:r:dq:i16 15785 15786 PATTERN: XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15787 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 REG3=XMM_B():r:dq:i16 15788 } 15789 15790 { 15791 ICLASS: VPMADCSSWD 15792 CPL: 3 15793 CATEGORY: XOP 15794 ISA_SET: XOP 15795 EXTENSION: XOP 15796 15797 PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15798 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 15799 15800 PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15801 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 15802 } 15803 15804 { 15805 ICLASS: VPMADCSWD 15806 CPL: 3 15807 CATEGORY: XOP 15808 ISA_SET: XOP 15809 EXTENSION: XOP 15810 15811 PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15812 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 15813 15814 PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15815 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 15816 } 15817 15818 { 15819 ICLASS: VPROTB 15820 CPL: 3 15821 CATEGORY: XOP 15822 ISA_SET: XOP 15823 EXTENSION: XOP 15824 15825 PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 15826 OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8 15827 15828 PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 15829 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b:u8 15830 } 15831 15832 { 15833 ICLASS: VPROTW 15834 CPL: 3 15835 CATEGORY: XOP 15836 ISA_SET: XOP 15837 EXTENSION: XOP 15838 15839 PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 15840 OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u16 15841 15842 PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 15843 OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b:u16 15844 } 15845 15846 { 15847 ICLASS: VPROTD 15848 CPL: 3 15849 CATEGORY: XOP 15850 ISA_SET: XOP 15851 EXTENSION: XOP 15852 15853 PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 15854 OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u32 15855 15856 PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 15857 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b:u32 15858 } 15859 15860 { 15861 ICLASS: VPROTQ 15862 CPL: 3 15863 CATEGORY: XOP 15864 ISA_SET: XOP 15865 EXTENSION: XOP 15866 15867 PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 15868 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u64 15869 15870 PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 15871 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b:u64 15872 } 15873 15874 { 15875 ICLASS: VPMACSSDD 15876 CPL: 3 15877 CATEGORY: XOP 15878 ISA_SET: XOP 15879 EXTENSION: XOP 15880 15881 PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15882 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32 15883 15884 PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15885 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32 15886 } 15887 15888 { 15889 ICLASS: VPMACSSDQH 15890 CPL: 3 15891 CATEGORY: XOP 15892 ISA_SET: XOP 15893 EXTENSION: XOP 15894 15895 PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15896 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 15897 15898 PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15899 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 15900 } 15901 15902 { 15903 ICLASS: VPMACSDD 15904 CPL: 3 15905 CATEGORY: XOP 15906 ISA_SET: XOP 15907 EXTENSION: XOP 15908 15909 PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15910 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32 15911 15912 PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15913 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32 15914 } 15915 15916 { 15917 ICLASS: VPMACSDQH 15918 CPL: 3 15919 CATEGORY: XOP 15920 ISA_SET: XOP 15921 EXTENSION: XOP 15922 15923 PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 15924 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 15925 15926 PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15927 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 15928 } 15929 15930 { 15931 ICLASS: VPCOMB 15932 CPL: 3 15933 CATEGORY: XOP 15934 ISA_SET: XOP 15935 EXTENSION: XOP 15936 15937 PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 15938 OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b:i8 15939 15940 PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 15941 OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 IMM0:r:b:i8 15942 } 15943 15944 { 15945 ICLASS: VPCOMW 15946 CPL: 3 15947 CATEGORY: XOP 15948 ISA_SET: XOP 15949 EXTENSION: XOP 15950 15951 PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 15952 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b:i16 15953 15954 PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 15955 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 IMM0:r:b:i16 15956 } 15957 15958 { 15959 ICLASS: VPCOMD 15960 CPL: 3 15961 CATEGORY: XOP 15962 ISA_SET: XOP 15963 EXTENSION: XOP 15964 15965 PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 15966 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 IMM0:r:b:i32 15967 15968 PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 15969 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 IMM0:r:b:i32 15970 } 15971 15972 { 15973 ICLASS: VPCOMQ 15974 CPL: 3 15975 CATEGORY: XOP 15976 ISA_SET: XOP 15977 EXTENSION: XOP 15978 15979 PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 15980 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 IMM0:r:b:i64 15981 15982 PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 15983 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 IMM0:r:b:i64 15984 } 15985 15986 { 15987 ICLASS: VPCOMUB 15988 CPL: 3 15989 CATEGORY: XOP 15990 ISA_SET: XOP 15991 EXTENSION: XOP 15992 15993 PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 15994 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8 15995 15996 PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 15997 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b:u8 15998 } 15999 16000 { 16001 ICLASS: VPCOMUW 16002 CPL: 3 16003 CATEGORY: XOP 16004 ISA_SET: XOP 16005 EXTENSION: XOP 16006 16007 PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 16008 OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u16 16009 16010 PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 16011 OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b:u16 16012 } 16013 16014 { 16015 ICLASS: VPCOMUD 16016 CPL: 3 16017 CATEGORY: XOP 16018 ISA_SET: XOP 16019 EXTENSION: XOP 16020 16021 PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 16022 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u32 16023 16024 PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 16025 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b:u32 16026 } 16027 16028 { 16029 ICLASS: VPCOMUQ 16030 CPL: 3 16031 CATEGORY: XOP 16032 ISA_SET: XOP 16033 EXTENSION: XOP 16034 16035 PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 16036 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u64 16037 16038 PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 16039 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b:u64 16040 } 16041 16042 { 16043 ICLASS: VFRCZPS 16044 CPL: 3 16045 CATEGORY: XOP 16046 ISA_SET: XOP 16047 EXTENSION: XOP 16048 ATTRIBUTES: MXCSR 16049 16050 PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16051 OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 16052 16053 PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16054 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 16055 16056 PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16057 OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 16058 16059 PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16060 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 16061 } 16062 16063 { 16064 ICLASS: VFRCZPD 16065 CPL: 3 16066 CATEGORY: XOP 16067 ISA_SET: XOP 16068 EXTENSION: XOP 16069 ATTRIBUTES: MXCSR 16070 16071 PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16072 OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 16073 16074 PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16075 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 16076 16077 PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16078 OPERANDS: REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 16079 16080 PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16081 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 16082 } 16083 16084 { 16085 ICLASS: VFRCZSS 16086 CPL: 3 16087 CATEGORY: XOP 16088 ISA_SET: XOP 16089 EXTENSION: XOP 16090 ATTRIBUTES: SIMD_SCALAR MXCSR 16091 16092 PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16093 OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 16094 16095 PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16096 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:d:f32 16097 } 16098 16099 { 16100 ICLASS: VFRCZSD 16101 CPL: 3 16102 CATEGORY: XOP 16103 ISA_SET: XOP 16104 EXTENSION: XOP 16105 ATTRIBUTES: SIMD_SCALAR MXCSR 16106 16107 PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16108 OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 16109 16110 PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16111 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f64 16112 } 16113 16114 { 16115 ICLASS: VPROTB 16116 CPL: 3 16117 CATEGORY: XOP 16118 ISA_SET: XOP 16119 EXTENSION: XOP 16120 16121 PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16122 OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8 16123 16124 PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16125 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8 16126 16127 PATTERN: XOPV 0x90 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16128 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 16129 16130 PATTERN: XOPV 0x90 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16131 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 16132 } 16133 16134 { 16135 ICLASS: VPROTW 16136 CPL: 3 16137 CATEGORY: XOP 16138 ISA_SET: XOP 16139 EXTENSION: XOP 16140 16141 PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16142 OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16 16143 16144 PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16145 OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16 16146 16147 PATTERN: XOPV 0x91 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16148 OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 16149 16150 PATTERN: XOPV 0x91 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16151 OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 16152 } 16153 16154 { 16155 ICLASS: VPROTD 16156 CPL: 3 16157 CATEGORY: XOP 16158 ISA_SET: XOP 16159 EXTENSION: XOP 16160 16161 PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16162 OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32 16163 16164 PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16165 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32 16166 16167 PATTERN: XOPV 0x92 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16168 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 16169 16170 PATTERN: XOPV 0x92 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16171 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 16172 } 16173 16174 { 16175 ICLASS: VPROTQ 16176 CPL: 3 16177 CATEGORY: XOP 16178 ISA_SET: XOP 16179 EXTENSION: XOP 16180 16181 PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16182 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64 16183 16184 PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16185 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64 16186 16187 PATTERN: XOPV 0x93 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16188 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 16189 16190 PATTERN: XOPV 0x93 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16191 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 16192 } 16193 16194 { 16195 ICLASS: VPSHLB 16196 CPL: 3 16197 CATEGORY: XOP 16198 ISA_SET: XOP 16199 EXTENSION: XOP 16200 16201 PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16202 OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8 16203 16204 PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16205 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8 16206 16207 PATTERN: XOPV 0x94 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16208 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 16209 16210 PATTERN: XOPV 0x94 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16211 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 16212 } 16213 16214 { 16215 ICLASS: VPSHLW 16216 CPL: 3 16217 CATEGORY: XOP 16218 ISA_SET: XOP 16219 EXTENSION: XOP 16220 16221 PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16222 OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16 16223 16224 PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16225 OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16 16226 16227 PATTERN: XOPV 0x95 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16228 OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 16229 16230 PATTERN: XOPV 0x95 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16231 OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 16232 } 16233 16234 { 16235 ICLASS: VPSHLD 16236 CPL: 3 16237 CATEGORY: XOP 16238 ISA_SET: XOP 16239 EXTENSION: XOP 16240 16241 PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16242 OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32 16243 16244 PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16245 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32 16246 16247 PATTERN: XOPV 0x96 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16248 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 16249 16250 PATTERN: XOPV 0x96 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16251 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 16252 } 16253 16254 { 16255 ICLASS: VPSHLQ 16256 CPL: 3 16257 CATEGORY: XOP 16258 ISA_SET: XOP 16259 EXTENSION: XOP 16260 16261 PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16262 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64 16263 16264 PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16265 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64 16266 16267 PATTERN: XOPV 0x97 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16268 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 16269 16270 PATTERN: XOPV 0x97 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16271 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 16272 } 16273 16274 { 16275 ICLASS: VPHADDBW 16276 CPL: 3 16277 CATEGORY: XOP 16278 ISA_SET: XOP 16279 EXTENSION: XOP 16280 16281 PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16282 OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 16283 16284 PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16285 OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8 16286 } 16287 16288 { 16289 ICLASS: VPHADDBD 16290 CPL: 3 16291 CATEGORY: XOP 16292 ISA_SET: XOP 16293 EXTENSION: XOP 16294 16295 PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16296 OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i8 16297 16298 PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16299 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i8 16300 } 16301 16302 { 16303 ICLASS: VPHADDBQ 16304 CPL: 3 16305 CATEGORY: XOP 16306 ISA_SET: XOP 16307 EXTENSION: XOP 16308 16309 PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16310 OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i8 16311 16312 PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16313 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i8 16314 } 16315 16316 { 16317 ICLASS: VPHADDWD 16318 CPL: 3 16319 CATEGORY: XOP 16320 ISA_SET: XOP 16321 EXTENSION: XOP 16322 16323 PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16324 OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16 16325 16326 PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16327 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16 16328 } 16329 16330 { 16331 ICLASS: VPHADDWQ 16332 CPL: 3 16333 CATEGORY: XOP 16334 ISA_SET: XOP 16335 EXTENSION: XOP 16336 16337 PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16338 OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i16 16339 16340 PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16341 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i16 16342 } 16343 16344 { 16345 ICLASS: VPHADDUBW 16346 CPL: 3 16347 CATEGORY: XOP 16348 ISA_SET: XOP 16349 EXTENSION: XOP 16350 16351 PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16352 OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u8 16353 16354 PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16355 OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u8 16356 } 16357 16358 { 16359 ICLASS: VPHADDUBD 16360 CPL: 3 16361 CATEGORY: XOP 16362 ISA_SET: XOP 16363 EXTENSION: XOP 16364 16365 PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16366 OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u8 16367 16368 PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16369 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u8 16370 } 16371 16372 { 16373 ICLASS: VPHADDUBQ 16374 CPL: 3 16375 CATEGORY: XOP 16376 ISA_SET: XOP 16377 EXTENSION: XOP 16378 16379 PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16380 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u8 16381 16382 PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16383 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u8 16384 } 16385 16386 { 16387 ICLASS: VPHADDUWD 16388 CPL: 3 16389 CATEGORY: XOP 16390 ISA_SET: XOP 16391 EXTENSION: XOP 16392 16393 PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16394 OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u16 16395 16396 PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16397 OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u16 16398 } 16399 16400 { 16401 ICLASS: VPHADDUWQ 16402 CPL: 3 16403 CATEGORY: XOP 16404 ISA_SET: XOP 16405 EXTENSION: XOP 16406 16407 PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16408 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u16 16409 16410 PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16411 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u16 16412 } 16413 16414 { 16415 ICLASS: VPHSUBBW 16416 CPL: 3 16417 CATEGORY: XOP 16418 ISA_SET: XOP 16419 EXTENSION: XOP 16420 16421 PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16422 OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i8 16423 16424 PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16425 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i8 16426 } 16427 16428 { 16429 ICLASS: VPHSUBWD 16430 CPL: 3 16431 CATEGORY: XOP 16432 ISA_SET: XOP 16433 EXTENSION: XOP 16434 16435 PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16436 OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16 16437 16438 PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16439 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16 16440 } 16441 16442 { 16443 ICLASS: VPHSUBDQ 16444 CPL: 3 16445 CATEGORY: XOP 16446 ISA_SET: XOP 16447 EXTENSION: XOP 16448 16449 PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16450 OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32 16451 16452 PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16453 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32 16454 } 16455 16456 { 16457 ICLASS: VPSHAB 16458 CPL: 3 16459 CATEGORY: XOP 16460 ISA_SET: XOP 16461 EXTENSION: XOP 16462 16463 PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16464 OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 REG1=XMM_N():r:dq:i8 16465 16466 PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16467 OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8 REG2=XMM_N():r:dq:i8 16468 16469 PATTERN: XOPV 0x98 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16470 OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 16471 16472 PATTERN: XOPV 0x98 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16473 OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 16474 } 16475 16476 { 16477 ICLASS: VPSHAW 16478 CPL: 3 16479 CATEGORY: XOP 16480 ISA_SET: XOP 16481 EXTENSION: XOP 16482 16483 PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16484 OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i16 REG1=XMM_N():r:dq:i16 16485 16486 PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16487 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i16 REG2=XMM_N():r:dq:i16 16488 16489 PATTERN: XOPV 0x99 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16490 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 16491 16492 PATTERN: XOPV 0x99 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16493 OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 16494 } 16495 16496 { 16497 ICLASS: VPSHAD 16498 CPL: 3 16499 CATEGORY: XOP 16500 ISA_SET: XOP 16501 EXTENSION: XOP 16502 16503 PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16504 OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i32 REG1=XMM_N():r:dq:i32 16505 16506 PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16507 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XMM_N():r:dq:i32 16508 16509 PATTERN: XOPV 0x9A VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16510 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 16511 16512 PATTERN: XOPV 0x9A VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16513 OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 16514 } 16515 16516 { 16517 ICLASS: VPSHAQ 16518 CPL: 3 16519 CATEGORY: XOP 16520 ISA_SET: XOP 16521 EXTENSION: XOP 16522 16523 PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16524 OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i64 REG1=XMM_N():r:dq:i64 16525 16526 PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16527 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i64 REG2=XMM_N():r:dq:i64 16528 16529 PATTERN: XOPV 0x9B VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16530 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 16531 16532 PATTERN: XOPV 0x9B VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16533 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 16534 } 16535 16536 { 16537 ICLASS: VPHADDDQ 16538 CPL: 3 16539 CATEGORY: XOP 16540 ISA_SET: XOP 16541 EXTENSION: XOP 16542 16543 PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16544 OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32 16545 16546 PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16547 OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32 16548 } 16549 16550 { 16551 ICLASS: VPHADDUDQ 16552 CPL: 3 16553 CATEGORY: XOP 16554 ISA_SET: XOP 16555 EXTENSION: XOP 16556 16557 PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 16558 OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u32 16559 16560 PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 16561 OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u32 16562 } 16563 16564 { 16565 ICLASS: BEXTR_XOP 16566 CPL: 3 16567 CATEGORY: TBM 16568 ISA_SET: TBM 16569 EXTENSION: TBM 16570 FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ] 16571 16572 PATTERN: XOPV 0x10 VNP W0 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() 16573 OPERANDS: REG0=GPRy_R():w:y MEM0:r:y IMM0:r:d 16574 16575 PATTERN: XOPV 0x10 VNP W0 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() 16576 OPERANDS: REG0=GPRy_R():w:y REG1=GPRy_B():r:y IMM0:r:d 16577 } 16578 16579 { 16580 ICLASS: BLCFILL 16581 CPL: 3 16582 CATEGORY: TBM 16583 ISA_SET: TBM 16584 EXTENSION: TBM 16585 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] 16586 16587 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 16588 OPERANDS: REG0=GPRy_N():w:y MEM0:r:y 16589 16590 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 16591 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y 16592 } 16593 16594 { 16595 ICLASS: BLSFILL 16596 CPL: 3 16597 CATEGORY: TBM 16598 ISA_SET: TBM 16599 EXTENSION: TBM 16600 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] 16601 16602 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 16603 OPERANDS: REG0=GPRy_N():w:y MEM0:r:y 16604 16605 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 16606 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y 16607 } 16608 16609 { 16610 ICLASS: BLCS 16611 CPL: 3 16612 CATEGORY: TBM 16613 ISA_SET: TBM 16614 EXTENSION: TBM 16615 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] 16616 16617 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 16618 OPERANDS: REG0=GPRy_N():w:y MEM0:r:y 16619 16620 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 16621 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y 16622 } 16623 16624 { 16625 ICLASS: TZMSK 16626 CPL: 3 16627 CATEGORY: TBM 16628 ISA_SET: TBM 16629 EXTENSION: TBM 16630 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] 16631 16632 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() 16633 OPERANDS: REG0=GPRy_N():w:y MEM0:r:y 16634 16635 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] 16636 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y 16637 } 16638 16639 { 16640 ICLASS: BLCIC 16641 CPL: 3 16642 CATEGORY: TBM 16643 ISA_SET: TBM 16644 EXTENSION: TBM 16645 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] 16646 16647 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() 16648 OPERANDS: REG0=GPRy_N():w:y MEM0:r:y 16649 16650 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] 16651 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y 16652 } 16653 16654 { 16655 ICLASS: BLSIC 16656 CPL: 3 16657 CATEGORY: TBM 16658 ISA_SET: TBM 16659 EXTENSION: TBM 16660 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] 16661 16662 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 16663 OPERANDS: REG0=GPRy_N():w:y MEM0:r:y 16664 16665 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] 16666 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y 16667 } 16668 16669 { 16670 ICLASS: T1MSKC 16671 CPL: 3 16672 CATEGORY: TBM 16673 ISA_SET: TBM 16674 EXTENSION: TBM 16675 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] 16676 16677 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() 16678 OPERANDS: REG0=GPRy_N():w:y MEM0:r:y 16679 16680 PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] 16681 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y 16682 } 16683 16684 { 16685 ICLASS: BLCMSK 16686 CPL: 3 16687 CATEGORY: TBM 16688 ISA_SET: TBM 16689 EXTENSION: TBM 16690 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] 16691 16692 PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 16693 OPERANDS: REG0=GPRy_N():w:y MEM0:r:y 16694 16695 PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 16696 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y 16697 } 16698 16699 { 16700 ICLASS: BLCI 16701 CPL: 3 16702 CATEGORY: TBM 16703 ISA_SET: TBM 16704 EXTENSION: TBM 16705 FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] 16706 16707 PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 16708 OPERANDS: REG0=GPRy_N():w:y MEM0:r:y 16709 16710 PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] 16711 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:y 16712 } 16713 16714 { 16715 ICLASS: LLWPCB 16716 CPL: 3 16717 CATEGORY: XOP 16718 ISA_SET: XOP 16719 EXTENSION: XOP 16720 16721 PATTERN: XOPV 0x12 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] 16722 OPERANDS: REG0=GPRy_B():w:y 16723 } 16724 16725 { 16726 ICLASS: SLWPCB 16727 CPL: 3 16728 CATEGORY: XOP 16729 ISA_SET: XOP 16730 EXTENSION: XOP 16731 16732 PATTERN: XOPV 0x12 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 16733 OPERANDS: REG0=GPRy_B():w:y 16734 } 16735 16736 { 16737 ICLASS: LWPINS 16738 CPL: 3 16739 CATEGORY: XOP 16740 ISA_SET: XOP 16741 EXTENSION: XOP 16742 FLAGS: MUST [ cf-mod ] 16743 16744 PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32() 16745 OPERANDS: REG0=GPRy_N():w:y MEM0:r:d IMM0:r:d 16746 16747 PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32() 16748 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d 16749 } 16750 16751 { 16752 ICLASS: LWPVAL 16753 CPL: 3 16754 CATEGORY: XOP 16755 ISA_SET: XOP 16756 EXTENSION: XOP 16757 16758 PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32() 16759 OPERANDS: REG0=GPRy_N():w:y MEM0:r:d IMM0:r:d 16760 16761 PATTERN: XOPV 0x12 VNP W0 VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32() 16762 OPERANDS: REG0=GPRy_N():w:y REG1=GPRv_B():r:d IMM0:r:d 16763 } 16764 16765 16766 ###FILE: ../xed/datafiles/amdxop/amd-fma4-isa.txt 16767 16768 #BEGIN_LEGAL 16769 # 16770 #Copyright (c) 2016 Intel Corporation 16771 # 16772 # Licensed under the Apache License, Version 2.0 (the "License"); 16773 # you may not use this file except in compliance with the License. 16774 # You may obtain a copy of the License at 16775 # 16776 # http://www.apache.org/licenses/LICENSE-2.0 16777 # 16778 # Unless required by applicable law or agreed to in writing, software 16779 # distributed under the License is distributed on an "AS IS" BASIS, 16780 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16781 # See the License for the specific language governing permissions and 16782 # limitations under the License. 16783 # 16784 #END_LEGAL 16785 16786 AVX_INSTRUCTIONS():: 16787 { 16788 ICLASS: VFMADDSUBPS 16789 CPL: 3 16790 CATEGORY: FMA4 16791 ISA_SET: FMA4 16792 EXTENSION: FMA4 16793 ATTRIBUTES: MXCSR 16794 16795 PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16796 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 16797 16798 PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16799 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 16800 16801 PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16802 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 16803 16804 PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16805 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 16806 16807 PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16808 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 16809 16810 PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16811 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 16812 16813 PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16814 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 16815 16816 PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16817 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 16818 } 16819 16820 { 16821 ICLASS: VFMADDSUBPD 16822 CPL: 3 16823 CATEGORY: FMA4 16824 ISA_SET: FMA4 16825 EXTENSION: FMA4 16826 ATTRIBUTES: MXCSR 16827 16828 PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16829 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 16830 16831 PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16832 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 16833 16834 PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16835 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 16836 16837 PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16838 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 16839 16840 PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16841 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 16842 16843 PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16844 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 16845 16846 PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16847 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 16848 16849 PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16850 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 16851 } 16852 16853 { 16854 ICLASS: VFMSUBADDPS 16855 CPL: 3 16856 CATEGORY: FMA4 16857 ISA_SET: FMA4 16858 EXTENSION: FMA4 16859 ATTRIBUTES: MXCSR 16860 16861 PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16862 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 16863 16864 PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16865 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 16866 16867 PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16868 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 16869 16870 PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16871 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 16872 16873 PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16874 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 16875 16876 PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16877 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 16878 16879 PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16880 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 16881 16882 PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16883 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 16884 } 16885 16886 { 16887 ICLASS: VFMSUBADDPD 16888 CPL: 3 16889 CATEGORY: FMA4 16890 ISA_SET: FMA4 16891 EXTENSION: FMA4 16892 ATTRIBUTES: MXCSR 16893 16894 PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16895 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 16896 16897 PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16898 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 16899 16900 PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16901 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 16902 16903 PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16904 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 16905 16906 PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16907 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 16908 16909 PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16910 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 16911 16912 PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16913 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 16914 16915 PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16916 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 16917 } 16918 16919 { 16920 ICLASS: VFMADDPS 16921 CPL: 3 16922 CATEGORY: FMA4 16923 ISA_SET: FMA4 16924 EXTENSION: FMA4 16925 ATTRIBUTES: MXCSR 16926 16927 PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16928 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 16929 16930 PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16931 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 16932 16933 PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16934 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 16935 16936 PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16937 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 16938 16939 PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16940 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 16941 16942 PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16943 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 16944 16945 PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16946 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 16947 16948 PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16949 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 16950 } 16951 16952 { 16953 ICLASS: VFMADDPD 16954 CPL: 3 16955 CATEGORY: FMA4 16956 ISA_SET: FMA4 16957 EXTENSION: FMA4 16958 ATTRIBUTES: MXCSR 16959 16960 PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16961 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 16962 16963 PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16964 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 16965 16966 PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16967 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 16968 16969 PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16970 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 16971 16972 PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16973 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 16974 16975 PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16976 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 16977 16978 PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16979 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 16980 16981 PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16982 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 16983 } 16984 16985 { 16986 ICLASS: VFMADDSS 16987 CPL: 3 16988 CATEGORY: FMA4 16989 ISA_SET: FMA4 16990 EXTENSION: FMA4 16991 ATTRIBUTES: SIMD_SCALAR MXCSR 16992 16993 PATTERN: VV1 0x6A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 16994 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 16995 16996 PATTERN: VV1 0x6A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 16997 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 16998 16999 PATTERN: VV1 0x6A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17000 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 17001 17002 PATTERN: VV1 0x6A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17003 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 17004 } 17005 17006 { 17007 ICLASS: VFMADDSD 17008 CPL: 3 17009 CATEGORY: FMA4 17010 ISA_SET: FMA4 17011 EXTENSION: FMA4 17012 ATTRIBUTES: SIMD_SCALAR MXCSR 17013 17014 PATTERN: VV1 0x6B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17015 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 17016 17017 PATTERN: VV1 0x6B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17018 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 17019 17020 PATTERN: VV1 0x6B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17021 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 17022 17023 PATTERN: VV1 0x6B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17024 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 17025 } 17026 17027 { 17028 ICLASS: VFMSUBPS 17029 CPL: 3 17030 CATEGORY: FMA4 17031 ISA_SET: FMA4 17032 EXTENSION: FMA4 17033 ATTRIBUTES: MXCSR 17034 17035 PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17036 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 17037 17038 PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17039 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 17040 17041 PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17042 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 17043 17044 PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17045 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 17046 17047 PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17048 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 17049 17050 PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17051 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 17052 17053 PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17054 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 17055 17056 PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17057 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 17058 } 17059 17060 { 17061 ICLASS: VFMSUBPD 17062 CPL: 3 17063 CATEGORY: FMA4 17064 ISA_SET: FMA4 17065 EXTENSION: FMA4 17066 ATTRIBUTES: MXCSR 17067 17068 PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17069 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 17070 17071 PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17072 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 17073 17074 PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17075 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 17076 17077 PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17078 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 17079 17080 PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17081 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 17082 17083 PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17084 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 17085 17086 PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17087 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 17088 17089 PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17090 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 17091 } 17092 17093 { 17094 ICLASS: VFMSUBSS 17095 CPL: 3 17096 CATEGORY: FMA4 17097 ISA_SET: FMA4 17098 EXTENSION: FMA4 17099 ATTRIBUTES: SIMD_SCALAR MXCSR 17100 17101 PATTERN: VV1 0x6E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17102 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 17103 17104 PATTERN: VV1 0x6E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17105 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 17106 17107 PATTERN: VV1 0x6E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17108 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 17109 17110 PATTERN: VV1 0x6E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17111 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 17112 } 17113 17114 { 17115 ICLASS: VFMSUBSD 17116 CPL: 3 17117 CATEGORY: FMA4 17118 ISA_SET: FMA4 17119 EXTENSION: FMA4 17120 ATTRIBUTES: SIMD_SCALAR MXCSR 17121 17122 PATTERN: VV1 0x6F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17123 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 17124 17125 PATTERN: VV1 0x6F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17126 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 17127 17128 PATTERN: VV1 0x6F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17129 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 17130 17131 PATTERN: VV1 0x6F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17132 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 17133 } 17134 17135 { 17136 ICLASS: VFNMADDPS 17137 CPL: 3 17138 CATEGORY: FMA4 17139 ISA_SET: FMA4 17140 EXTENSION: FMA4 17141 ATTRIBUTES: MXCSR 17142 17143 PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17144 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 17145 17146 PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17147 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 17148 17149 PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17150 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 17151 17152 PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17153 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 17154 17155 PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17156 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 17157 17158 PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17159 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 17160 17161 PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17162 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 17163 17164 PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17165 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 17166 } 17167 17168 { 17169 ICLASS: VFNMADDPD 17170 CPL: 3 17171 CATEGORY: FMA4 17172 ISA_SET: FMA4 17173 EXTENSION: FMA4 17174 ATTRIBUTES: MXCSR 17175 17176 PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17177 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 17178 17179 PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17180 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 17181 17182 PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17183 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 17184 17185 PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17186 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 17187 17188 PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17189 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 17190 17191 PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17192 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 17193 17194 PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17195 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 17196 17197 PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17198 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 17199 } 17200 17201 { 17202 ICLASS: VFNMADDSS 17203 CPL: 3 17204 CATEGORY: FMA4 17205 ISA_SET: FMA4 17206 EXTENSION: FMA4 17207 ATTRIBUTES: SIMD_SCALAR MXCSR 17208 17209 PATTERN: VV1 0x7A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17210 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 17211 17212 PATTERN: VV1 0x7A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17213 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 17214 17215 PATTERN: VV1 0x7A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17216 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 17217 17218 PATTERN: VV1 0x7A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17219 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 17220 } 17221 17222 { 17223 ICLASS: VFNMADDSD 17224 CPL: 3 17225 CATEGORY: FMA4 17226 ISA_SET: FMA4 17227 EXTENSION: FMA4 17228 ATTRIBUTES: SIMD_SCALAR MXCSR 17229 17230 PATTERN: VV1 0x7B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17231 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 17232 17233 PATTERN: VV1 0x7B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17234 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 17235 17236 PATTERN: VV1 0x7B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17237 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 17238 17239 PATTERN: VV1 0x7B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17240 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 17241 } 17242 17243 { 17244 ICLASS: VFNMSUBPS 17245 CPL: 3 17246 CATEGORY: FMA4 17247 ISA_SET: FMA4 17248 EXTENSION: FMA4 17249 ATTRIBUTES: MXCSR 17250 17251 PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17252 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 17253 17254 PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17255 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 17256 17257 PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17258 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 17259 17260 PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17261 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 17262 17263 PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17264 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 17265 17266 PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17267 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 17268 17269 PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17270 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 17271 17272 PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17273 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 17274 } 17275 17276 { 17277 ICLASS: VFNMSUBPD 17278 CPL: 3 17279 CATEGORY: FMA4 17280 ISA_SET: FMA4 17281 EXTENSION: FMA4 17282 ATTRIBUTES: MXCSR 17283 17284 PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17285 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 17286 17287 PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17288 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 17289 17290 PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17291 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 17292 17293 PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17294 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 17295 17296 PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17297 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 17298 17299 PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17300 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 17301 17302 PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17303 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 17304 17305 PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17306 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 17307 } 17308 17309 { 17310 ICLASS: VFNMSUBSS 17311 CPL: 3 17312 CATEGORY: FMA4 17313 ISA_SET: FMA4 17314 EXTENSION: FMA4 17315 ATTRIBUTES: SIMD_SCALAR MXCSR 17316 17317 PATTERN: VV1 0x7E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17318 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 17319 17320 PATTERN: VV1 0x7E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17321 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 17322 17323 PATTERN: VV1 0x7E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17324 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 17325 17326 PATTERN: VV1 0x7E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17327 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 17328 } 17329 17330 { 17331 ICLASS: VFNMSUBSD 17332 CPL: 3 17333 CATEGORY: FMA4 17334 ISA_SET: FMA4 17335 EXTENSION: FMA4 17336 ATTRIBUTES: SIMD_SCALAR MXCSR 17337 17338 PATTERN: VV1 0x7F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17339 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 17340 17341 PATTERN: VV1 0x7F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17342 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 17343 17344 PATTERN: VV1 0x7F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17345 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 17346 17347 PATTERN: VV1 0x7F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17348 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 17349 } 17350 17351 17352 ###FILE: ../xed/datafiles/amdxop/amd-vpermil2-isa.txt 17353 17354 #BEGIN_LEGAL 17355 # 17356 #Copyright (c) 2016 Intel Corporation 17357 # 17358 # Licensed under the Apache License, Version 2.0 (the "License"); 17359 # you may not use this file except in compliance with the License. 17360 # You may obtain a copy of the License at 17361 # 17362 # http://www.apache.org/licenses/LICENSE-2.0 17363 # 17364 # Unless required by applicable law or agreed to in writing, software 17365 # distributed under the License is distributed on an "AS IS" BASIS, 17366 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17367 # See the License for the specific language governing permissions and 17368 # limitations under the License. 17369 # 17370 #END_LEGAL 17371 17372 AVX_INSTRUCTIONS():: 17373 17374 17375 { 17376 ICLASS : VPERMIL2PS 17377 CPL : 3 17378 CATEGORY : XOP 17379 EXTENSION : XOP 17380 ISA_SET : XOP 17381 17382 # 128b W0 17383 PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17384 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 IMM0:r:b 17385 17386 PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17387 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 IMM0:r:b 17388 17389 # 256b W0 17390 PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17391 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 IMM0:r:b 17392 17393 PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17394 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 IMM0:r:b 17395 17396 # 128b W1 17397 PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17398 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b 17399 17400 PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17401 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 IMM0:r:b 17402 17403 # 256b W1 17404 PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17405 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b 17406 17407 PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17408 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 IMM0:r:b 17409 17410 } 17411 17412 17413 17414 { 17415 ICLASS : VPERMIL2PD 17416 CPL : 3 17417 CATEGORY : XOP 17418 EXTENSION : XOP 17419 ISA_SET : XOP 17420 17421 # 128b W0 17422 PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17423 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 IMM0:r:b 17424 17425 PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17426 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 IMM0:r:b 17427 17428 # 256b W0 17429 PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17430 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 IMM0:r:b 17431 17432 PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17433 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 IMM0:r:b 17434 17435 # 128b W1 17436 PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17437 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b 17438 17439 PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17440 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 IMM0:r:b 17441 17442 # 256b W1 17443 PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 17444 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b 17445 17446 PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 17447 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 IMM0:r:b 17448 17449 } 17450 17451 17452 17453 ###FILE: ../xed/datafiles/xsaveopt/xsaveopt-isa.txt 17454 17455 #BEGIN_LEGAL 17456 # 17457 #Copyright (c) 2016 Intel Corporation 17458 # 17459 # Licensed under the Apache License, Version 2.0 (the "License"); 17460 # you may not use this file except in compliance with the License. 17461 # You may obtain a copy of the License at 17462 # 17463 # http://www.apache.org/licenses/LICENSE-2.0 17464 # 17465 # Unless required by applicable law or agreed to in writing, software 17466 # distributed under the License is distributed on an "AS IS" BASIS, 17467 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17468 # See the License for the specific language governing permissions and 17469 # limitations under the License. 17470 # 17471 #END_LEGAL 17472 INSTRUCTIONS():: 17473 17474 { 17475 ICLASS : XSAVEOPT 17476 CPL : 3 17477 CATEGORY : XSAVEOPT 17478 EXTENSION : XSAVEOPT 17479 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX 17480 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM() 17481 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR 17482 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 17483 } 17484 17485 17486 { 17487 ICLASS : XSAVEOPT64 17488 CPL : 3 17489 CATEGORY : XSAVEOPT 17490 EXTENSION : XSAVEOPT 17491 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX 17492 17493 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM() 17494 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR 17495 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 17496 } 17497 17498 17499 17500 ###FILE: ../xed/datafiles/mpx/mpx-isa.txt 17501 17502 #BEGIN_LEGAL 17503 # 17504 #Copyright (c) 2016 Intel Corporation 17505 # 17506 # Licensed under the Apache License, Version 2.0 (the "License"); 17507 # you may not use this file except in compliance with the License. 17508 # You may obtain a copy of the License at 17509 # 17510 # http://www.apache.org/licenses/LICENSE-2.0 17511 # 17512 # Unless required by applicable law or agreed to in writing, software 17513 # distributed under the License is distributed on an "AS IS" BASIS, 17514 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17515 # See the License for the specific language governing permissions and 17516 # limitations under the License. 17517 # 17518 #END_LEGAL 17519 17520 17521 INSTRUCTIONS():: 17522 17523 17524 UDELETE: NOP0F1A 17525 UDELETE: NOP0F1B 17526 17527 17528 17529 { 17530 ICLASS: BNDMK 17531 EXTENSION: MPX 17532 CATEGORY: MPX 17533 ISA_SET: MPX 17534 ATTRIBUTES: NO_RIP_REL 17535 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix 17536 OPERANDS: REG0=BND_R():w AGEN:r 17537 } 17538 17539 17540 17541 17542 { 17543 ICLASS: BNDCL 17544 EXTENSION: MPX 17545 CATEGORY: MPX 17546 ISA_SET: MPX 17547 ATTRIBUTES: EXCEPTION_BR 17548 COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. 17549 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix 17550 OPERANDS: REG0=BND_R():r AGEN:r 17551 17552 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64 17553 OPERANDS: REG0=BND_R():r REG1=GPR64_B():r 17554 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64 17555 OPERANDS: REG0=BND_R():r REG1=GPR32_B():r 17556 } 17557 17558 { 17559 ICLASS: BNDCU 17560 EXTENSION: MPX 17561 CATEGORY: MPX 17562 ISA_SET: MPX 17563 ATTRIBUTES: EXCEPTION_BR 17564 COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. 17565 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix 17566 OPERANDS: REG0=BND_R():r AGEN:r 17567 17568 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 17569 OPERANDS: REG0=BND_R():r REG1=GPR64_B():r 17570 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 17571 OPERANDS: REG0=BND_R():r REG1=GPR32_B():r 17572 } 17573 17574 { 17575 ICLASS: BNDCN 17576 EXTENSION: MPX 17577 CATEGORY: MPX 17578 ISA_SET: MPX 17579 ATTRIBUTES: EXCEPTION_BR 17580 COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. 17581 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix 17582 OPERANDS: REG0=BND_R():r AGEN:r 17583 17584 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 17585 OPERANDS: REG0=BND_R():r REG1=GPR64_B():r 17586 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 17587 OPERANDS: REG0=BND_R():r REG1=GPR32_B():r 17588 17589 } 17590 17591 { 17592 ICLASS: BNDMOV 17593 EXTENSION: MPX 17594 CATEGORY: MPX 17595 ISA_SET: MPX 17596 ATTRIBUTES: 17597 COMMENT: load form 17598 17599 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() 17600 OPERANDS: REG0=BND_R():w REG1=BND_B():r 17601 17602 # 16b refs 64b memop (2x32b) but only if EASZ=32b! 17603 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 17604 OPERANDS: REG0=BND_R():w MEM0:r:q:u32 17605 17606 # 32b refs 64b memop (2x32b) 17607 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 17608 OPERANDS: REG0=BND_R():w MEM0:r:q:u32 17609 17610 # 64b refs 128b memop (2x64b) 17611 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 17612 OPERANDS: REG0=BND_R():w MEM0:r:dq:u64 17613 17614 17615 17616 } 17617 17618 { 17619 ICLASS: BNDMOV 17620 EXTENSION: MPX 17621 CATEGORY: MPX 17622 ISA_SET: MPX 17623 ATTRIBUTES: 17624 COMMENT: store form 17625 17626 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() 17627 OPERANDS: REG0=BND_B():w REG1=BND_R():r 17628 17629 # 16b refs 64b memop (2x32b) but only if EASZ=32b! 17630 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 17631 OPERANDS: MEM0:w:q:u32 REG0=BND_R():r 17632 17633 # 32b refs 64b memop (2x32b) 17634 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 17635 OPERANDS: MEM0:w:q:u32 REG0=BND_R():r 17636 17637 # 64b refs 128b memop (2x64b) 17638 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 17639 OPERANDS: MEM0:w:dq:u64 REG0=BND_R():r 17640 } 17641 17642 17643 { 17644 ICLASS: BNDLDX 17645 EXTENSION: MPX 17646 CATEGORY: MPX 17647 ISA_SET: MPX 17648 ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL 17649 COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only 17650 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 17651 OPERANDS: REG0=BND_R():w MEM0:r:bnd32 17652 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 17653 OPERANDS: REG0=BND_R():w MEM0:r:bnd64 17654 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 17655 OPERANDS: REG0=BND_R():w MEM0:r:bnd64 17656 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 17657 OPERANDS: REG0=BND_R():w MEM0:r:bnd64 17658 } 17659 17660 { 17661 ICLASS: BNDSTX 17662 EXTENSION: MPX 17663 CATEGORY: MPX 17664 ISA_SET: MPX 17665 ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL 17666 COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only 17667 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 17668 OPERANDS: MEM0:w:bnd32 REG0=BND_R():r 17669 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 17670 OPERANDS: MEM0:w:bnd64 REG0=BND_R():r 17671 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 17672 OPERANDS: MEM0:w:bnd64 REG0=BND_R():r 17673 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 17674 OPERANDS: MEM0:w:bnd64 REG0=BND_R():r 17675 } 17676 17677 { 17678 ICLASS : NOP 17679 CPL : 3 17680 CATEGORY : WIDENOP 17681 ATTRIBUTES: NOP 17682 EXTENSION : BASE 17683 ISA_SET : PPRO 17684 COMMENT : MPXMODE=1: some of the reg/reg forms of these NOPs are still NOPs. 17685 17686 PATTERN : 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 17687 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 17688 IFORM : NOP_GPRv_GPRv_0F1A 17689 17690 PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 17691 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 17692 IFORM : NOP_GPRv_GPRv_0F1B 17693 17694 PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix 17695 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 17696 IFORM : NOP_GPRv_GPRv_0F1B 17697 } 17698 17699 17700 { 17701 ICLASS : NOP 17702 CPL : 3 17703 CATEGORY : WIDENOP 17704 ATTRIBUTES: NOP 17705 EXTENSION : BASE 17706 ISA_SET : PPRO 17707 COMMENT : For MPXMODE=0 operation 17708 17709 PATTERN : 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 17710 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 17711 IFORM : NOP_GPRv_GPRv_0F1A 17712 17713 PATTERN : 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 17714 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 17715 IFORM : NOP_GPRv_GPRv_0F1B 17716 17717 PATTERN : 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 17718 OPERANDS : REG0=GPRv_B():r MEM0:r:v 17719 IFORM : NOP_GPRv_MEMv_0F1A 17720 17721 PATTERN : 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 17722 OPERANDS : REG0=GPRv_B():r MEM0:r:v 17723 IFORM : NOP_GPRv_MEM_0F1B 17724 } 17725 17726 17727 17728 17729 ###FILE: ../xed/datafiles/sha/sha-isa.xed.txt 17730 17731 #BEGIN_LEGAL 17732 # 17733 #Copyright (c) 2016 Intel Corporation 17734 # 17735 # Licensed under the Apache License, Version 2.0 (the "License"); 17736 # you may not use this file except in compliance with the License. 17737 # You may obtain a copy of the License at 17738 # 17739 # http://www.apache.org/licenses/LICENSE-2.0 17740 # 17741 # Unless required by applicable law or agreed to in writing, software 17742 # distributed under the License is distributed on an "AS IS" BASIS, 17743 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17744 # See the License for the specific language governing permissions and 17745 # limitations under the License. 17746 # 17747 #END_LEGAL 17748 # 17749 # 17750 # 17751 # ***** GENERATED FILE -- DO NOT EDIT! ***** 17752 # ***** GENERATED FILE -- DO NOT EDIT! ***** 17753 # ***** GENERATED FILE -- DO NOT EDIT! ***** 17754 # 17755 # 17756 # 17757 INSTRUCTIONS():: 17758 # EMITTING SHA1MSG1 (SHA1MSG1-N/A-1) 17759 { 17760 ICLASS: SHA1MSG1 17761 CPL: 3 17762 CATEGORY: SHA 17763 EXTENSION: SHA 17764 ISA_SET: SHA 17765 EXCEPTIONS: SSE_TYPE_4 17766 REAL_OPCODE: Y 17767 PATTERN: 0x0F 0x38 0xC9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 17768 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 17769 IFORM: SHA1MSG1_XMMi32_XMMi32_SHA 17770 } 17771 17772 { 17773 ICLASS: SHA1MSG1 17774 CPL: 3 17775 CATEGORY: SHA 17776 EXTENSION: SHA 17777 ISA_SET: SHA 17778 EXCEPTIONS: SSE_TYPE_4 17779 REAL_OPCODE: Y 17780 ATTRIBUTES: REQUIRES_ALIGNMENT 17781 PATTERN: 0x0F 0x38 0xC9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 17782 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 17783 IFORM: SHA1MSG1_XMMi32_MEMi32_SHA 17784 } 17785 17786 17787 # EMITTING SHA1MSG2 (SHA1MSG2-N/A-1) 17788 { 17789 ICLASS: SHA1MSG2 17790 CPL: 3 17791 CATEGORY: SHA 17792 EXTENSION: SHA 17793 ISA_SET: SHA 17794 EXCEPTIONS: SSE_TYPE_4 17795 REAL_OPCODE: Y 17796 PATTERN: 0x0F 0x38 0xCA MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 17797 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 17798 IFORM: SHA1MSG2_XMMi32_XMMi32_SHA 17799 } 17800 17801 { 17802 ICLASS: SHA1MSG2 17803 CPL: 3 17804 CATEGORY: SHA 17805 EXTENSION: SHA 17806 ISA_SET: SHA 17807 EXCEPTIONS: SSE_TYPE_4 17808 REAL_OPCODE: Y 17809 ATTRIBUTES: REQUIRES_ALIGNMENT 17810 PATTERN: 0x0F 0x38 0xCA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 17811 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 17812 IFORM: SHA1MSG2_XMMi32_MEMi32_SHA 17813 } 17814 17815 17816 # EMITTING SHA1NEXTE (SHA1NEXTE-N/A-1) 17817 { 17818 ICLASS: SHA1NEXTE 17819 CPL: 3 17820 CATEGORY: SHA 17821 EXTENSION: SHA 17822 ISA_SET: SHA 17823 EXCEPTIONS: SSE_TYPE_4 17824 REAL_OPCODE: Y 17825 PATTERN: 0x0F 0x38 0xC8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 17826 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 17827 IFORM: SHA1NEXTE_XMMi32_XMMi32_SHA 17828 } 17829 17830 { 17831 ICLASS: SHA1NEXTE 17832 CPL: 3 17833 CATEGORY: SHA 17834 EXTENSION: SHA 17835 ISA_SET: SHA 17836 EXCEPTIONS: SSE_TYPE_4 17837 REAL_OPCODE: Y 17838 ATTRIBUTES: REQUIRES_ALIGNMENT 17839 PATTERN: 0x0F 0x38 0xC8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 17840 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 17841 IFORM: SHA1NEXTE_XMMi32_MEMi32_SHA 17842 } 17843 17844 17845 # EMITTING SHA1RNDS4 (SHA1RNDS4-N/A-1) 17846 { 17847 ICLASS: SHA1RNDS4 17848 CPL: 3 17849 CATEGORY: SHA 17850 EXTENSION: SHA 17851 ISA_SET: SHA 17852 EXCEPTIONS: SSE_TYPE_4 17853 REAL_OPCODE: Y 17854 PATTERN: 0x0F 0x3A 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix UIMM8() 17855 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b 17856 IFORM: SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA 17857 } 17858 17859 { 17860 ICLASS: SHA1RNDS4 17861 CPL: 3 17862 CATEGORY: SHA 17863 EXTENSION: SHA 17864 ISA_SET: SHA 17865 EXCEPTIONS: SSE_TYPE_4 17866 REAL_OPCODE: Y 17867 ATTRIBUTES: REQUIRES_ALIGNMENT 17868 PATTERN: 0x0F 0x3A 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix UIMM8() 17869 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 IMM0:r:b 17870 IFORM: SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA 17871 } 17872 17873 17874 # EMITTING SHA256MSG1 (SHA256MSG1-N/A-1) 17875 { 17876 ICLASS: SHA256MSG1 17877 CPL: 3 17878 CATEGORY: SHA 17879 EXTENSION: SHA 17880 ISA_SET: SHA 17881 EXCEPTIONS: SSE_TYPE_4 17882 REAL_OPCODE: Y 17883 PATTERN: 0x0F 0x38 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 17884 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 17885 IFORM: SHA256MSG1_XMMi32_XMMi32_SHA 17886 } 17887 17888 { 17889 ICLASS: SHA256MSG1 17890 CPL: 3 17891 CATEGORY: SHA 17892 EXTENSION: SHA 17893 ISA_SET: SHA 17894 EXCEPTIONS: SSE_TYPE_4 17895 REAL_OPCODE: Y 17896 ATTRIBUTES: REQUIRES_ALIGNMENT 17897 PATTERN: 0x0F 0x38 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 17898 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 17899 IFORM: SHA256MSG1_XMMi32_MEMi32_SHA 17900 } 17901 17902 17903 # EMITTING SHA256MSG2 (SHA256MSG2-N/A-1) 17904 { 17905 ICLASS: SHA256MSG2 17906 CPL: 3 17907 CATEGORY: SHA 17908 EXTENSION: SHA 17909 ISA_SET: SHA 17910 EXCEPTIONS: SSE_TYPE_4 17911 REAL_OPCODE: Y 17912 PATTERN: 0x0F 0x38 0xCD MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 17913 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 17914 IFORM: SHA256MSG2_XMMi32_XMMi32_SHA 17915 } 17916 17917 { 17918 ICLASS: SHA256MSG2 17919 CPL: 3 17920 CATEGORY: SHA 17921 EXTENSION: SHA 17922 ISA_SET: SHA 17923 EXCEPTIONS: SSE_TYPE_4 17924 REAL_OPCODE: Y 17925 ATTRIBUTES: REQUIRES_ALIGNMENT 17926 PATTERN: 0x0F 0x38 0xCD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 17927 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 17928 IFORM: SHA256MSG2_XMMi32_MEMi32_SHA 17929 } 17930 17931 17932 # EMITTING SHA256RNDS2 (SHA256RNDS2-N/A-1) 17933 { 17934 ICLASS: SHA256RNDS2 17935 CPL: 3 17936 CATEGORY: SHA 17937 EXTENSION: SHA 17938 ISA_SET: SHA 17939 EXCEPTIONS: SSE_TYPE_4 17940 REAL_OPCODE: Y 17941 PATTERN: 0x0F 0x38 0xCB MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 17942 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XED_REG_XMM0:r:SUPP:dq:u8 17943 IFORM: SHA256RNDS2_XMMi32_XMMi32_SHA 17944 } 17945 17946 { 17947 ICLASS: SHA256RNDS2 17948 CPL: 3 17949 CATEGORY: SHA 17950 EXTENSION: SHA 17951 ISA_SET: SHA 17952 EXCEPTIONS: SSE_TYPE_4 17953 REAL_OPCODE: Y 17954 ATTRIBUTES: REQUIRES_ALIGNMENT 17955 PATTERN: 0x0F 0x38 0xCB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 17956 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 REG1=XED_REG_XMM0:r:SUPP:dq:u8 17957 IFORM: SHA256RNDS2_XMMi32_MEMi32_SHA 17958 } 17959 17960 17961 17962 17963 ###FILE: ../xed/datafiles/ivbint/ivb-int-isa.txt 17964 17965 #BEGIN_LEGAL 17966 # 17967 #Copyright (c) 2016 Intel Corporation 17968 # 17969 # Licensed under the Apache License, Version 2.0 (the "License"); 17970 # you may not use this file except in compliance with the License. 17971 # You may obtain a copy of the License at 17972 # 17973 # http://www.apache.org/licenses/LICENSE-2.0 17974 # 17975 # Unless required by applicable law or agreed to in writing, software 17976 # distributed under the License is distributed on an "AS IS" BASIS, 17977 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17978 # See the License for the specific language governing permissions and 17979 # limitations under the License. 17980 # 17981 #END_LEGAL 17982 INSTRUCTIONS():: 17983 17984 { 17985 ICLASS : RDRAND 17986 CPL : 3 17987 CATEGORY : RDRAND 17988 EXTENSION : RDRAND 17989 ISA_SET : RDRAND 17990 FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] 17991 PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining 17992 OPERANDS : REG0=GPRv_B():w 17993 } 17994 17995 17996 17997 ###FILE: ../xed/datafiles/ivbint/fsgsbase-isa.txt 17998 17999 #BEGIN_LEGAL 18000 # 18001 #Copyright (c) 2016 Intel Corporation 18002 # 18003 # Licensed under the Apache License, Version 2.0 (the "License"); 18004 # you may not use this file except in compliance with the License. 18005 # You may obtain a copy of the License at 18006 # 18007 # http://www.apache.org/licenses/LICENSE-2.0 18008 # 18009 # Unless required by applicable law or agreed to in writing, software 18010 # distributed under the License is distributed on an "AS IS" BASIS, 18011 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 18012 # See the License for the specific language governing permissions and 18013 # limitations under the License. 18014 # 18015 #END_LEGAL 18016 INSTRUCTIONS():: 18017 18018 18019 { 18020 ICLASS : RDFSBASE 18021 CPL : 3 18022 CATEGORY : RDWRFSGS 18023 EXTENSION : RDWRFSGS 18024 18025 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix no66_prefix 18026 OPERANDS : REG0=GPRy_B():w REG1=XED_REG_FSBASE:r:SUPP:y 18027 18028 } 18029 { 18030 ICLASS : RDGSBASE 18031 CPL : 3 18032 CATEGORY : RDWRFSGS 18033 EXTENSION : RDWRFSGS 18034 18035 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix no66_prefix 18036 OPERANDS : REG0=GPRy_B():w REG1=XED_REG_GSBASE:r:SUPP:y 18037 18038 } 18039 18040 18041 18042 { 18043 ICLASS : WRFSBASE 18044 CPL : 3 18045 CATEGORY : RDWRFSGS 18046 EXTENSION : RDWRFSGS 18047 ATTRIBUTES: NOTSX 18048 18049 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix no66_prefix 18050 OPERANDS : REG0=GPRy_B():r REG1=XED_REG_FSBASE:w:SUPP:y 18051 18052 } 18053 { 18054 ICLASS : WRGSBASE 18055 CPL : 3 18056 CATEGORY : RDWRFSGS 18057 EXTENSION : RDWRFSGS 18058 ATTRIBUTES: NOTSX 18059 18060 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix no66_prefix 18061 OPERANDS : REG0=GPRy_B():r REG1=XED_REG_GSBASE:w:SUPP:y 18062 18063 } 18064 18065 18066 ###FILE: ../xed/datafiles/xsaves/xsaves-isa.txt 18067 18068 #BEGIN_LEGAL 18069 # 18070 #Copyright (c) 2016 Intel Corporation 18071 # 18072 # Licensed under the Apache License, Version 2.0 (the "License"); 18073 # you may not use this file except in compliance with the License. 18074 # You may obtain a copy of the License at 18075 # 18076 # http://www.apache.org/licenses/LICENSE-2.0 18077 # 18078 # Unless required by applicable law or agreed to in writing, software 18079 # distributed under the License is distributed on an "AS IS" BASIS, 18080 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 18081 # See the License for the specific language governing permissions and 18082 # limitations under the License. 18083 # 18084 #END_LEGAL 18085 INSTRUCTIONS():: 18086 18087 { 18088 ICLASS : XSAVES 18089 CPL : 0 18090 CATEGORY : XSAVE 18091 EXTENSION : XSAVES 18092 COMMENT : variable length load and conditianal reg write 18093 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED 18094 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix 18095 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 18096 } 18097 18098 18099 { 18100 ICLASS : XSAVES64 18101 CPL : 0 18102 CATEGORY : XSAVE 18103 EXTENSION : XSAVES 18104 COMMENT : variable length load and conditianal reg write 18105 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED 18106 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix 18107 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 18108 } 18109 18110 18111 18112 18113 18114 { 18115 ICLASS : XRSTORS 18116 CPL : 0 18117 CATEGORY : XSAVE 18118 EXTENSION : XSAVES 18119 COMMENT : variable length load and conditianal reg write 18120 ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED 18121 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix 18122 OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 18123 } 18124 18125 18126 { 18127 ICLASS : XRSTORS64 18128 CPL : 0 18129 CATEGORY : XSAVE 18130 EXTENSION : XSAVES 18131 COMMENT : variable length load and conditianal reg write 18132 ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED 18133 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix 18134 OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 18135 } 18136 18137 18138 18139 ###FILE: ../xed/datafiles/xsavec/xsavec-isa.txt 18140 18141 #BEGIN_LEGAL 18142 # 18143 #Copyright (c) 2016 Intel Corporation 18144 # 18145 # Licensed under the Apache License, Version 2.0 (the "License"); 18146 # you may not use this file except in compliance with the License. 18147 # You may obtain a copy of the License at 18148 # 18149 # http://www.apache.org/licenses/LICENSE-2.0 18150 # 18151 # Unless required by applicable law or agreed to in writing, software 18152 # distributed under the License is distributed on an "AS IS" BASIS, 18153 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 18154 # See the License for the specific language governing permissions and 18155 # limitations under the License. 18156 # 18157 #END_LEGAL 18158 INSTRUCTIONS():: 18159 18160 { 18161 ICLASS : XSAVEC 18162 CPL : 3 18163 CATEGORY : XSAVE 18164 EXTENSION : XSAVEC 18165 COMMENT : variable length store 18166 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED 18167 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix 18168 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 18169 } 18170 18171 18172 18173 { 18174 ICLASS : XSAVEC64 18175 CPL : 3 18176 CATEGORY : XSAVE 18177 EXTENSION : XSAVEC 18178 COMMENT : variable length store 18179 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED 18180 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix 18181 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 18182 } 18183 18184 18185 18186 18187 ###FILE: ../xed/datafiles/avx/avx-isa.txt 18188 18189 #BEGIN_LEGAL 18190 # 18191 #Copyright (c) 2016 Intel Corporation 18192 # 18193 # Licensed under the Apache License, Version 2.0 (the "License"); 18194 # you may not use this file except in compliance with the License. 18195 # You may obtain a copy of the License at 18196 # 18197 # http://www.apache.org/licenses/LICENSE-2.0 18198 # 18199 # Unless required by applicable law or agreed to in writing, software 18200 # distributed under the License is distributed on an "AS IS" BASIS, 18201 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 18202 # See the License for the specific language governing permissions and 18203 # limitations under the License. 18204 # 18205 #END_LEGAL 18206 18207 # The neat thing is we can just end a nonterminal by starting a new one. 18208 18209 AVX_INSTRUCTIONS():: 18210 { 18211 ICLASS : VADDPD 18212 EXCEPTIONS: avx-type-2 18213 CPL : 3 18214 CATEGORY : AVX 18215 EXTENSION : AVX 18216 ATTRIBUTES: MXCSR 18217 PATTERN : VV1 0x58 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18218 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 18219 18220 PATTERN : VV1 0x58 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18221 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 18222 18223 PATTERN : VV1 0x58 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18224 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 18225 18226 PATTERN : VV1 0x58 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18227 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 18228 } 18229 18230 18231 { 18232 ICLASS : VADDPS 18233 EXCEPTIONS: avx-type-2 18234 CPL : 3 18235 CATEGORY : AVX 18236 EXTENSION : AVX 18237 ATTRIBUTES: MXCSR 18238 PATTERN : VV1 0x58 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18239 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 18240 18241 PATTERN : VV1 0x58 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18242 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 18243 18244 PATTERN : VV1 0x58 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18245 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 18246 18247 PATTERN : VV1 0x58 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18248 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 18249 } 18250 18251 18252 { 18253 ICLASS : VADDSD 18254 EXCEPTIONS: avx-type-3 18255 CPL : 3 18256 ATTRIBUTES : simd_scalar MXCSR 18257 CATEGORY : AVX 18258 EXTENSION : AVX 18259 PATTERN : VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18260 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 18261 18262 PATTERN : VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18263 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 18264 } 18265 18266 { 18267 ICLASS : VADDSS 18268 EXCEPTIONS: avx-type-3 18269 CPL : 3 18270 ATTRIBUTES : simd_scalar MXCSR 18271 CATEGORY : AVX 18272 EXTENSION : AVX 18273 PATTERN : VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18274 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 18275 18276 PATTERN : VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18277 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 18278 } 18279 18280 18281 { 18282 ICLASS : VADDSUBPD 18283 EXCEPTIONS: avx-type-2 18284 CPL : 3 18285 CATEGORY : AVX 18286 EXTENSION : AVX 18287 ATTRIBUTES: MXCSR 18288 PATTERN : VV1 0xD0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18289 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 18290 18291 PATTERN : VV1 0xD0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18292 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 18293 18294 PATTERN : VV1 0xD0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18295 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 18296 18297 PATTERN : VV1 0xD0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18298 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 18299 } 18300 18301 { 18302 ICLASS : VADDSUBPS 18303 EXCEPTIONS: avx-type-2 18304 CPL : 3 18305 CATEGORY : AVX 18306 EXTENSION : AVX 18307 ATTRIBUTES: MXCSR 18308 PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18309 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 18310 18311 PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18312 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 18313 18314 PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18315 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 18316 18317 PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18318 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 18319 } 18320 18321 18322 { 18323 ICLASS : VANDPD 18324 EXCEPTIONS: avx-type-4 18325 CPL : 3 18326 CATEGORY : LOGICAL_FP 18327 EXTENSION : AVX 18328 PATTERN : VV1 0x54 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18329 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 18330 18331 PATTERN : VV1 0x54 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18332 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 18333 18334 PATTERN : VV1 0x54 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18335 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 18336 18337 PATTERN : VV1 0x54 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18338 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 18339 } 18340 18341 18342 18343 { 18344 ICLASS : VANDPS 18345 EXCEPTIONS: avx-type-4 18346 CPL : 3 18347 CATEGORY : LOGICAL_FP 18348 EXTENSION : AVX 18349 PATTERN : VV1 0x54 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18350 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 18351 18352 PATTERN : VV1 0x54 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18353 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 18354 18355 PATTERN : VV1 0x54 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18356 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 18357 18358 PATTERN : VV1 0x54 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18359 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 18360 } 18361 18362 18363 { 18364 ICLASS : VANDNPD 18365 EXCEPTIONS: avx-type-4 18366 CPL : 3 18367 CATEGORY : LOGICAL_FP 18368 EXTENSION : AVX 18369 PATTERN : VV1 0x55 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18370 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 18371 18372 PATTERN : VV1 0x55 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18373 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 18374 18375 PATTERN : VV1 0x55 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18376 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 18377 18378 PATTERN : VV1 0x55 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18379 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 18380 } 18381 18382 18383 18384 { 18385 ICLASS : VANDNPS 18386 EXCEPTIONS: avx-type-4 18387 CPL : 3 18388 CATEGORY : LOGICAL_FP 18389 EXTENSION : AVX 18390 PATTERN : VV1 0x55 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18391 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 18392 18393 PATTERN : VV1 0x55 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18394 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 18395 18396 PATTERN : VV1 0x55 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18397 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 18398 18399 PATTERN : VV1 0x55 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18400 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 18401 } 18402 18403 18404 18405 { 18406 ICLASS : VBLENDPD 18407 EXCEPTIONS: avx-type-4 18408 CPL : 3 18409 CATEGORY : AVX 18410 EXTENSION : AVX 18411 PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 18412 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b 18413 18414 PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 18415 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b 18416 18417 PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 18418 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b 18419 18420 PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 18421 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b 18422 } 18423 18424 18425 { 18426 ICLASS : VBLENDPS 18427 EXCEPTIONS: avx-type-4 18428 CPL : 3 18429 CATEGORY : AVX 18430 EXTENSION : AVX 18431 PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 18432 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b 18433 18434 PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 18435 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b 18436 18437 PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 18438 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b 18439 18440 PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 18441 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b 18442 } 18443 18444 18445 18446 18447 18448 18449 { 18450 ICLASS : VCMPPD 18451 EXCEPTIONS: avx-type-2 18452 CPL : 3 18453 CATEGORY : AVX 18454 EXTENSION : AVX 18455 ATTRIBUTES: MXCSR 18456 PATTERN : VV1 0xC2 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 18457 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b 18458 18459 PATTERN : VV1 0xC2 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 18460 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b 18461 18462 PATTERN : VV1 0xC2 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 18463 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b 18464 18465 PATTERN : VV1 0xC2 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 18466 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b 18467 } 18468 18469 18470 18471 { 18472 ICLASS : VCMPPS 18473 EXCEPTIONS: avx-type-2 18474 CPL : 3 18475 CATEGORY : AVX 18476 EXTENSION : AVX 18477 ATTRIBUTES: MXCSR 18478 PATTERN : VV1 0xC2 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 18479 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b 18480 18481 PATTERN : VV1 0xC2 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 18482 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b 18483 18484 PATTERN : VV1 0xC2 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 18485 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b 18486 18487 PATTERN : VV1 0xC2 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 18488 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b 18489 } 18490 18491 18492 18493 { 18494 ICLASS : VCMPSD 18495 EXCEPTIONS: avx-type-3 18496 CPL : 3 18497 CATEGORY : AVX 18498 EXTENSION : AVX 18499 ATTRIBUTES : simd_scalar MXCSR 18500 PATTERN : VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 18501 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 18502 18503 PATTERN : VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 18504 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b 18505 } 18506 18507 18508 18509 { 18510 ICLASS : VCMPSS 18511 EXCEPTIONS: avx-type-3 18512 CPL : 3 18513 CATEGORY : AVX 18514 EXTENSION : AVX 18515 18516 ATTRIBUTES : simd_scalar MXCSR 18517 18518 PATTERN : VV1 0xC2 VF3 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 18519 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 18520 18521 PATTERN : VV1 0xC2 VF3 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 18522 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b 18523 } 18524 18525 18526 { 18527 ICLASS : VCOMISD 18528 EXCEPTIONS: avx-type-3 18529 CPL : 3 18530 CATEGORY : AVX 18531 EXTENSION : AVX 18532 ATTRIBUTES : simd_scalar MXCSR 18533 18534 FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] 18535 PATTERN : VV1 0x2F V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18536 OPERANDS : REG0=XMM_R():r:q:f64 MEM0:r:q:f64 18537 18538 PATTERN : VV1 0x2F V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18539 OPERANDS : REG0=XMM_R():r:q:f64 REG1=XMM_B():r:q:f64 18540 } 18541 18542 { 18543 ICLASS : VCOMISS 18544 EXCEPTIONS: avx-type-3 18545 CPL : 3 18546 CATEGORY : AVX 18547 EXTENSION : AVX 18548 ATTRIBUTES : simd_scalar MXCSR 18549 18550 FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] 18551 PATTERN : VV1 0x2F VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18552 OPERANDS : REG0=XMM_R():r:d:f32 MEM0:r:d:f32 18553 18554 PATTERN : VV1 0x2F VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18555 OPERANDS : REG0=XMM_R():r:d:f32 REG1=XMM_B():r:d:f32 18556 } 18557 18558 18559 { 18560 ICLASS : VCVTDQ2PD 18561 EXCEPTIONS: avx-type-5 18562 CPL : 3 18563 CATEGORY : CONVERT 18564 EXTENSION : AVX 18565 ATTRIBUTES: MXCSR 18566 PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18567 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:i32 18568 18569 PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18570 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:i32 18571 18572 PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18573 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:i32 18574 18575 PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18576 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:i32 18577 } 18578 18579 { 18580 ICLASS : VCVTDQ2PS 18581 EXCEPTIONS: avx-type-2 18582 CPL : 3 18583 CATEGORY : CONVERT 18584 EXTENSION : AVX 18585 ATTRIBUTES: MXCSR 18586 PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18587 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:i32 18588 18589 PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18590 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:i32 18591 18592 PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18593 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:i32 18594 18595 PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18596 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:i32 18597 } 18598 18599 { 18600 ICLASS : VCVTPD2DQ 18601 EXCEPTIONS: avx-type-2 18602 CPL : 3 18603 CATEGORY : CONVERT 18604 EXTENSION : AVX 18605 ATTRIBUTES: MXCSR 18606 PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18607 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 18608 18609 PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18610 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 18611 18612 PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18613 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 18614 18615 PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18616 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64 18617 } 18618 18619 18620 { 18621 ICLASS : VCVTTPD2DQ 18622 EXCEPTIONS: avx-type-2 18623 CPL : 3 18624 CATEGORY : CONVERT 18625 EXTENSION : AVX 18626 ATTRIBUTES: MXCSR 18627 PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18628 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 18629 18630 PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18631 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 18632 18633 PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18634 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 18635 18636 PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18637 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64 18638 } 18639 18640 18641 { 18642 ICLASS : VCVTPD2PS 18643 EXCEPTIONS: avx-type-2 18644 CPL : 3 18645 CATEGORY : CONVERT 18646 EXTENSION : AVX 18647 ATTRIBUTES: MXCSR 18648 PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18649 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f64 18650 18651 PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18652 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f64 18653 18654 PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18655 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:qq:f64 18656 18657 PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18658 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=YMM_B():r:qq:f64 18659 } 18660 18661 { 18662 ICLASS : VCVTPS2DQ 18663 EXCEPTIONS: avx-type-2 18664 CPL : 3 18665 CATEGORY : CONVERT 18666 EXTENSION : AVX 18667 ATTRIBUTES: MXCSR 18668 PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18669 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32 18670 18671 PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18672 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32 18673 18674 PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18675 OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32 18676 18677 PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18678 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32 18679 } 18680 18681 { 18682 ICLASS : VCVTTPS2DQ 18683 EXCEPTIONS: avx-type-2 18684 CPL : 3 18685 CATEGORY : CONVERT 18686 EXTENSION : AVX 18687 ATTRIBUTES: MXCSR 18688 PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18689 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32 18690 18691 PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18692 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32 18693 18694 PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18695 OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32 18696 18697 PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18698 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32 18699 } 18700 18701 { 18702 ICLASS : VCVTPS2PD 18703 EXCEPTIONS: avx-type-3 18704 CPL : 3 18705 CATEGORY : CONVERT 18706 EXTENSION : AVX 18707 ATTRIBUTES: MXCSR 18708 PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18709 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f32 18710 18711 PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18712 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f32 18713 18714 PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18715 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f32 18716 18717 PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18718 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f32 18719 } 18720 18721 18722 18723 18724 { 18725 ICLASS : VCVTSD2SI 18726 EXCEPTIONS: avx-type-3 18727 CPL : 3 18728 CATEGORY : CONVERT 18729 EXTENSION : AVX 18730 ATTRIBUTES : simd_scalar MXCSR 18731 18732 PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18733 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 18734 18735 PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18736 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 18737 18738 18739 PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18740 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 18741 18742 PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18743 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 18744 18745 18746 18747 PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18748 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 18749 18750 PATTERN : VV1 0x2D VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18751 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 18752 } 18753 18754 { 18755 ICLASS : VCVTTSD2SI 18756 EXCEPTIONS: avx-type-3 18757 CPL : 3 18758 CATEGORY : CONVERT 18759 EXTENSION : AVX 18760 ATTRIBUTES : simd_scalar MXCSR 18761 18762 PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18763 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 18764 18765 PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18766 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 18767 18768 18769 18770 PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18771 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 18772 18773 PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18774 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 18775 18776 18777 18778 PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18779 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 18780 18781 PATTERN : VV1 0x2C VF2 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18782 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 18783 } 18784 18785 18786 18787 18788 { 18789 ICLASS : VCVTSS2SI 18790 EXCEPTIONS: avx-type-3 18791 CPL : 3 18792 CATEGORY : CONVERT 18793 EXTENSION : AVX 18794 ATTRIBUTES : simd_scalar MXCSR 18795 18796 PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18797 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 18798 18799 PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18800 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 18801 18802 18803 18804 PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18805 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 18806 18807 PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18808 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 18809 18810 18811 PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18812 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 18813 18814 PATTERN : VV1 0x2D VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18815 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 18816 } 18817 18818 { 18819 ICLASS : VCVTTSS2SI 18820 EXCEPTIONS: avx-type-3 18821 CPL : 3 18822 CATEGORY : CONVERT 18823 EXTENSION : AVX 18824 ATTRIBUTES : simd_scalar MXCSR 18825 18826 PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18827 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 18828 18829 PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18830 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 18831 18832 18833 18834 PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18835 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 18836 18837 PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18838 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 18839 18840 18841 18842 18843 PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18844 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 18845 18846 PATTERN : VV1 0x2C VF3 V0F VL128 NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18847 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 18848 } 18849 18850 18851 18852 18853 { 18854 ICLASS : VCVTSD2SS 18855 EXCEPTIONS: avx-type-3 18856 CPL : 3 18857 CATEGORY : CONVERT 18858 EXTENSION : AVX 18859 ATTRIBUTES : simd_scalar MXCSR 18860 18861 PATTERN : VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18862 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f64 18863 18864 PATTERN : VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18865 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:q:f64 18866 18867 } 18868 18869 18870 { 18871 ICLASS : VCVTSI2SD 18872 EXCEPTIONS: avx-type-3 18873 CPL : 3 18874 CATEGORY : CONVERT 18875 EXTENSION : AVX 18876 ATTRIBUTES : simd_scalar MXCSR 18877 18878 PATTERN : VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18879 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32 18880 18881 PATTERN : VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18882 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32 18883 18884 18885 18886 PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18887 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32 18888 18889 PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18890 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32 18891 18892 18893 18894 PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18895 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:i64 18896 18897 PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18898 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR64_B():r:q:i64 18899 } 18900 18901 18902 { 18903 ICLASS : VCVTSI2SS 18904 EXCEPTIONS: avx-type-3 18905 CPL : 3 18906 CATEGORY : CONVERT 18907 EXTENSION : AVX 18908 ATTRIBUTES : simd_scalar MXCSR 18909 18910 PATTERN : VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18911 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 18912 18913 PATTERN : VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18914 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32 18915 18916 18917 18918 PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18919 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 18920 18921 PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18922 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32 18923 18924 18925 18926 PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18927 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:i64 18928 18929 PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18930 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR64_B():r:q:i64 18931 } 18932 18933 18934 { 18935 ICLASS : VCVTSS2SD 18936 EXCEPTIONS: avx-type-3 18937 CPL : 3 18938 CATEGORY : CONVERT 18939 EXTENSION : AVX 18940 ATTRIBUTES : simd_scalar MXCSR 18941 18942 PATTERN : VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18943 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:f32 18944 18945 PATTERN : VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18946 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:d:f32 18947 } 18948 18949 18950 { 18951 ICLASS : VDIVPD 18952 EXCEPTIONS: avx-type-2 18953 CPL : 3 18954 CATEGORY : AVX 18955 EXTENSION : AVX 18956 ATTRIBUTES: MXCSR 18957 PATTERN : VV1 0x5E V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18958 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 18959 18960 PATTERN : VV1 0x5E V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18961 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 18962 18963 PATTERN : VV1 0x5E V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18964 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 18965 18966 PATTERN : VV1 0x5E V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18967 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 18968 } 18969 18970 18971 { 18972 ICLASS : VDIVPS 18973 EXCEPTIONS: avx-type-2 18974 CPL : 3 18975 CATEGORY : AVX 18976 EXTENSION : AVX 18977 ATTRIBUTES: MXCSR 18978 PATTERN : VV1 0x5E VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18979 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 18980 18981 PATTERN : VV1 0x5E VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18982 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 18983 18984 PATTERN : VV1 0x5E VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 18985 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 18986 18987 PATTERN : VV1 0x5E VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 18988 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 18989 } 18990 18991 18992 18993 { 18994 ICLASS : VDIVSD 18995 EXCEPTIONS: avx-type-3 18996 CPL : 3 18997 CATEGORY : AVX 18998 EXTENSION : AVX 18999 ATTRIBUTES : simd_scalar MXCSR 19000 19001 PATTERN : VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19002 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 19003 19004 PATTERN : VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19005 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 19006 } 19007 19008 { 19009 ICLASS : VDIVSS 19010 EXCEPTIONS: avx-type-3 19011 CPL : 3 19012 CATEGORY : AVX 19013 EXTENSION : AVX 19014 ATTRIBUTES : simd_scalar MXCSR 19015 19016 PATTERN : VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19017 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 19018 19019 PATTERN : VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19020 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 19021 } 19022 19023 19024 { 19025 ICLASS : VEXTRACTF128 19026 EXCEPTIONS: avx-type-6 19027 CPL : 3 19028 CATEGORY : AVX 19029 EXTENSION : AVX 19030 PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19031 OPERANDS : MEM0:w:dq:f64 REG0=YMM_R():r:dq:f64 IMM0:r:b 19032 19033 PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19034 OPERANDS : REG0=XMM_B():w:dq:f64 REG1=YMM_R():r:dq:f64 IMM0:r:b 19035 } 19036 19037 19038 19039 { 19040 ICLASS : VDPPD 19041 EXCEPTIONS: avx-type-2D 19042 CPL : 3 19043 CATEGORY : AVX 19044 EXTENSION : AVX 19045 ATTRIBUTES: MXCSR 19046 PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19047 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b 19048 19049 PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19050 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b 19051 } 19052 19053 { 19054 ICLASS : VDPPS 19055 EXCEPTIONS: avx-type-2D 19056 CPL : 3 19057 CATEGORY : AVX 19058 EXTENSION : AVX 19059 ATTRIBUTES: MXCSR 19060 PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19061 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b 19062 19063 PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19064 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b 19065 19066 PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19067 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b 19068 19069 PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19070 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b 19071 } 19072 19073 19074 { 19075 ICLASS : VEXTRACTPS 19076 EXCEPTIONS: avx-type-5 19077 CPL : 3 19078 CATEGORY : AVX 19079 EXTENSION : AVX 19080 PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19081 OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:dq:f32 IMM0:r:b 19082 19083 PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19084 OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq:f32 IMM0:r:b 19085 } 19086 19087 19088 { 19089 ICLASS : VZEROALL 19090 EXCEPTIONS: avx-type-8 19091 CPL : 3 19092 CATEGORY : AVX 19093 EXTENSION : AVX 19094 ATTRIBUTES : xmm_state_w 19095 19096 PATTERN : VV1 0x77 VNP V0F VL256 NOVSR 19097 OPERANDS: 19098 19099 } 19100 19101 # FIXME: how to denote partial upper clobber! 19102 { 19103 ICLASS : VZEROUPPER 19104 EXCEPTIONS: avx-type-8 19105 CPL : 3 19106 CATEGORY : AVX 19107 EXTENSION : AVX 19108 ATTRIBUTES : xmm_state_w NOTSX # FIXME: should be ymm_state_w? 19109 19110 PATTERN : VV1 0x77 VNP V0F VL128 NOVSR 19111 OPERANDS: 19112 } 19113 19114 19115 { 19116 ICLASS : VHADDPD 19117 EXCEPTIONS: avx-type-2 19118 CPL : 3 19119 CATEGORY : AVX 19120 EXTENSION : AVX 19121 ATTRIBUTES: MXCSR 19122 PATTERN : VV1 0x7C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19123 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 19124 19125 PATTERN : VV1 0x7C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19126 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 19127 19128 PATTERN : VV1 0x7C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19129 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 19130 19131 PATTERN : VV1 0x7C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19132 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 19133 } 19134 19135 19136 { 19137 ICLASS : VHADDPS 19138 EXCEPTIONS: avx-type-2 19139 CPL : 3 19140 CATEGORY : AVX 19141 EXTENSION : AVX 19142 ATTRIBUTES: MXCSR 19143 PATTERN : VV1 0x7C VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19144 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 19145 19146 PATTERN : VV1 0x7C VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19147 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 19148 19149 PATTERN : VV1 0x7C VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19150 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 19151 19152 PATTERN : VV1 0x7C VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19153 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 19154 } 19155 19156 19157 { 19158 ICLASS : VHSUBPD 19159 EXCEPTIONS: avx-type-2 19160 CPL : 3 19161 CATEGORY : AVX 19162 EXTENSION : AVX 19163 ATTRIBUTES: MXCSR 19164 PATTERN : VV1 0x7D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19165 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 19166 19167 PATTERN : VV1 0x7D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19168 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 19169 19170 PATTERN : VV1 0x7D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19171 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 19172 19173 PATTERN : VV1 0x7D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19174 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 19175 } 19176 19177 19178 { 19179 ICLASS : VHSUBPS 19180 EXCEPTIONS: avx-type-2 19181 CPL : 3 19182 CATEGORY : AVX 19183 EXTENSION : AVX 19184 ATTRIBUTES: MXCSR 19185 PATTERN : VV1 0x7D VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19186 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 19187 19188 PATTERN : VV1 0x7D VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19189 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 19190 19191 PATTERN : VV1 0x7D VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19192 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 19193 19194 PATTERN : VV1 0x7D VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19195 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 19196 } 19197 19198 19199 19200 { 19201 ICLASS : VPERMILPD 19202 EXCEPTIONS: avx-type-6 19203 CPL : 3 19204 CATEGORY : AVX 19205 EXTENSION : AVX 19206 # 2008-02-01 moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPD 19207 PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19208 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:u64 19209 19210 PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19211 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:u64 19212 19213 PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19214 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:u64 19215 19216 PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19217 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:u64 19218 19219 ######################################## 19220 # IMMEDIATE FORM 19221 ######################################## 19222 19223 # 2008-02-01 moved norexw_prefix to after V0F3A to avoid a graph build conflict with VPHSUBW 19224 PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19225 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b 19226 19227 PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19228 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b 19229 19230 PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19231 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b 19232 19233 PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19234 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b 19235 } 19236 19237 19238 { 19239 ICLASS : VPERMILPS 19240 EXCEPTIONS: avx-type-6 19241 CPL : 3 19242 CATEGORY : AVX 19243 EXTENSION : AVX 19244 # moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPS 19245 PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19246 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:u32 19247 19248 PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19249 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:u32 19250 19251 PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19252 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:u32 19253 19254 PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19255 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:u32 19256 19257 ######################################## 19258 # IMMEDIATE FORM 19259 ######################################## 19260 19261 # 2008-02-01: moved norexw_prefix after V0F3A due to graph-build collision with VPMADDUBSW 19262 PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19263 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b 19264 19265 PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19266 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b 19267 19268 PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19269 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b 19270 19271 PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19272 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b 19273 } 19274 19275 19276 { 19277 ICLASS : VPERM2F128 19278 EXCEPTIONS: avx-type-6 19279 CPL : 3 19280 CATEGORY : AVX 19281 EXTENSION : AVX 19282 19283 # 2008-02-01 moved norexw_prefix to after V0F3A to avoid conflict with VPHSUBD 19284 PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19285 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b 19286 19287 PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19288 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b 19289 } 19290 19291 19292 19293 { 19294 ICLASS : VBROADCASTSS 19295 EXCEPTIONS: avx-type-6 19296 CPL : 3 19297 CATEGORY : BROADCAST 19298 EXTENSION : AVX 19299 PATTERN : VV1 0x18 norexw_prefix VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19300 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 19301 19302 PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19303 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 19304 } 19305 { 19306 ICLASS : VBROADCASTSD 19307 EXCEPTIONS: avx-type-6 19308 CPL : 3 19309 CATEGORY : BROADCAST 19310 EXTENSION : AVX 19311 PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19312 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 19313 } 19314 19315 { 19316 ICLASS : VBROADCASTF128 19317 EXCEPTIONS: avx-type-6 19318 CPL : 3 19319 CATEGORY : BROADCAST 19320 EXTENSION : AVX 19321 COMMENT : There is no F128 type. I just set these to f64 for lack of anything better. 19322 PATTERN : VV1 0x1A norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19323 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 19324 } 19325 19326 19327 { 19328 ICLASS : VINSERTF128 19329 EXCEPTIONS: avx-type-6 19330 CPL : 3 19331 CATEGORY : AVX 19332 EXTENSION : AVX 19333 PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19334 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64 19335 19336 PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19337 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64 19338 } 19339 19340 { 19341 ICLASS : VINSERTPS 19342 EXCEPTIONS: avx-type-5 19343 CPL : 3 19344 CATEGORY : AVX 19345 EXTENSION : AVX 19346 PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 19347 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 19348 19349 PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 19350 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b 19351 } 19352 19353 19354 19355 19356 19357 { 19358 ICLASS : VLDDQU 19359 EXCEPTIONS: avx-type-4 19360 CPL : 3 19361 CATEGORY : AVX 19362 EXTENSION : AVX 19363 PATTERN : VV1 0xF0 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19364 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 19365 19366 PATTERN : VV1 0xF0 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19367 OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq 19368 } 19369 19370 19371 19372 19373 19374 19375 { 19376 ICLASS : VMASKMOVPS 19377 EXCEPTIONS: avx-type-6 19378 CPL : 3 19379 CATEGORY : AVX 19380 EXTENSION : AVX 19381 ATTRIBUTES : maskop 19382 # load forms 19383 PATTERN : VV1 0x2C V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19384 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq MEM0:r:dq:f32 19385 19386 PATTERN : VV1 0x2C V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19387 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq MEM0:r:qq:f32 19388 19389 # store forms 19390 PATTERN : VV1 0x2E V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19391 OPERANDS : MEM0:w:dq:f32 REG0=XMM_N():r:dq REG1=XMM_R():r:dq:f32 19392 19393 PATTERN : VV1 0x2E V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19394 OPERANDS : MEM0:w:qq:f32 REG0=YMM_N():r:qq REG1=YMM_R():r:qq:f32 19395 } 19396 19397 { 19398 ICLASS : VMASKMOVPD 19399 EXCEPTIONS: avx-type-6 19400 CPL : 3 19401 CATEGORY : AVX 19402 EXTENSION : AVX 19403 ATTRIBUTES : maskop 19404 # load forms 19405 PATTERN : VV1 0x2D V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19406 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:f64 19407 19408 PATTERN : VV1 0x2D V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19409 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:f64 19410 19411 # store forms 19412 PATTERN : VV1 0x2F V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19413 OPERANDS : MEM0:w:dq:f64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:f64 19414 19415 PATTERN : VV1 0x2F V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19416 OPERANDS : MEM0:w:qq:f64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:f64 19417 } 19418 19419 { 19420 ICLASS : VPTEST 19421 EXCEPTIONS: avx-type-4 19422 CPL : 3 19423 CATEGORY : LOGICAL 19424 EXTENSION : AVX 19425 FLAGS : MUST [ zf-mod cf-mod ] 19426 PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19427 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq 19428 19429 PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19430 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq 19431 19432 PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19433 OPERANDS : REG0=YMM_R():r:qq MEM0:r:qq 19434 19435 PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19436 OPERANDS : REG0=YMM_R():r:qq REG1=YMM_B():r:qq 19437 } 19438 19439 { 19440 ICLASS : VTESTPS 19441 EXCEPTIONS: avx-type-4 19442 CPL : 3 19443 CATEGORY : LOGICAL_FP 19444 EXTENSION : AVX 19445 FLAGS : MUST [ zf-mod cf-mod ] 19446 PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19447 OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:dq:f32 19448 19449 PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19450 OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:dq:f32 19451 19452 PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19453 OPERANDS : REG0=YMM_R():r:qq:f32 MEM0:r:qq:f32 19454 19455 PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19456 OPERANDS : REG0=YMM_R():r:qq:f32 REG1=YMM_B():r:qq:f32 19457 } 19458 19459 { 19460 ICLASS : VTESTPD 19461 EXCEPTIONS: avx-type-4 19462 CPL : 3 19463 CATEGORY : LOGICAL_FP 19464 EXTENSION : AVX 19465 FLAGS : MUST [ zf-mod cf-mod ] 19466 PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19467 OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:dq:f64 19468 19469 PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19470 OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:dq:f64 19471 19472 PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19473 OPERANDS : REG0=YMM_R():r:qq:f64 MEM0:r:qq:f64 19474 19475 PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19476 OPERANDS : REG0=YMM_R():r:qq:f64 REG1=YMM_B():r:qq:f64 19477 } 19478 19479 19480 { 19481 ICLASS : VMAXPD 19482 EXCEPTIONS: avx-type-2 19483 CPL : 3 19484 CATEGORY : AVX 19485 EXTENSION : AVX 19486 ATTRIBUTES: MXCSR 19487 PATTERN : VV1 0x5F V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19488 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 19489 19490 PATTERN : VV1 0x5F V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19491 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 19492 19493 PATTERN : VV1 0x5F V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19494 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 19495 19496 PATTERN : VV1 0x5F V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19497 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 19498 } 19499 19500 { 19501 ICLASS : VMAXPS 19502 EXCEPTIONS: avx-type-2 19503 CPL : 3 19504 CATEGORY : AVX 19505 EXTENSION : AVX 19506 ATTRIBUTES: MXCSR 19507 PATTERN : VV1 0x5F VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19508 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 19509 19510 PATTERN : VV1 0x5F VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19511 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 19512 19513 PATTERN : VV1 0x5F VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19514 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 19515 19516 PATTERN : VV1 0x5F VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19517 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 19518 } 19519 19520 19521 19522 { 19523 ICLASS : VMAXSD 19524 EXCEPTIONS: avx-type-3 19525 CPL : 3 19526 CATEGORY : AVX 19527 EXTENSION : AVX 19528 ATTRIBUTES : simd_scalar MXCSR 19529 19530 PATTERN : VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19531 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 19532 19533 PATTERN : VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19534 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 19535 } 19536 19537 { 19538 ICLASS : VMAXSS 19539 EXCEPTIONS: avx-type-3 19540 CPL : 3 19541 CATEGORY : AVX 19542 EXTENSION : AVX 19543 ATTRIBUTES : simd_scalar MXCSR 19544 19545 PATTERN : VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19546 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 19547 19548 PATTERN : VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19549 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 19550 } 19551 19552 { 19553 ICLASS : VMINPD 19554 EXCEPTIONS: avx-type-2 19555 CPL : 3 19556 CATEGORY : AVX 19557 EXTENSION : AVX 19558 ATTRIBUTES: MXCSR 19559 PATTERN : VV1 0x5D V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19560 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 19561 19562 PATTERN : VV1 0x5D V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19563 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 19564 19565 PATTERN : VV1 0x5D V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19566 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 19567 19568 PATTERN : VV1 0x5D V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19569 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 19570 } 19571 19572 { 19573 ICLASS : VMINPS 19574 EXCEPTIONS: avx-type-2 19575 CPL : 3 19576 CATEGORY : AVX 19577 EXTENSION : AVX 19578 ATTRIBUTES: MXCSR 19579 PATTERN : VV1 0x5D VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19580 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 19581 19582 PATTERN : VV1 0x5D VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19583 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 19584 19585 PATTERN : VV1 0x5D VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19586 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 19587 19588 PATTERN : VV1 0x5D VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19589 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 19590 } 19591 19592 19593 19594 { 19595 ICLASS : VMINSD 19596 EXCEPTIONS: avx-type-3 19597 CPL : 3 19598 CATEGORY : AVX 19599 EXTENSION : AVX 19600 ATTRIBUTES : simd_scalar MXCSR 19601 19602 PATTERN : VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19603 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 19604 19605 PATTERN : VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19606 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 19607 } 19608 19609 { 19610 ICLASS : VMINSS 19611 EXCEPTIONS: avx-type-3 19612 CPL : 3 19613 CATEGORY : AVX 19614 EXTENSION : AVX 19615 ATTRIBUTES : simd_scalar MXCSR 19616 19617 PATTERN : VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19618 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 19619 19620 PATTERN : VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19621 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 19622 } 19623 19624 19625 { 19626 ICLASS : VMOVAPD 19627 EXCEPTIONS: avx-type-1 19628 CPL : 3 19629 CATEGORY : DATAXFER 19630 EXTENSION : AVX 19631 ATTRIBUTES : REQUIRES_ALIGNMENT 19632 19633 # 128b load 19634 19635 PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19636 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 19637 19638 PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19639 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 19640 IFORM : VMOVAPD_XMMdq_XMMdq_28 19641 19642 # 128b store 19643 19644 PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19645 OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 19646 19647 PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19648 OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 19649 IFORM : VMOVAPD_XMMdq_XMMdq_29 19650 19651 # 256b load 19652 19653 PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19654 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 19655 19656 PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19657 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 19658 IFORM : VMOVAPD_YMMqq_YMMqq_28 19659 19660 # 256b store 19661 19662 PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19663 OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 19664 19665 PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19666 OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64 19667 IFORM : VMOVAPD_YMMqq_YMMqq_29 19668 } 19669 19670 19671 19672 { 19673 ICLASS : VMOVAPS 19674 EXCEPTIONS: avx-type-1 19675 CPL : 3 19676 CATEGORY : DATAXFER 19677 EXTENSION : AVX 19678 ATTRIBUTES : REQUIRES_ALIGNMENT 19679 19680 # 128b load 19681 19682 PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19683 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 19684 19685 PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19686 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 19687 IFORM : VMOVAPS_XMMdq_XMMdq_28 19688 # 128b store 19689 19690 PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19691 OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 19692 19693 PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19694 OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 19695 IFORM : VMOVAPS_XMMdq_XMMdq_29 19696 19697 # 256b load 19698 19699 PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19700 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 19701 19702 PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19703 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 19704 IFORM : VMOVAPS_YMMqq_YMMqq_28 19705 19706 # 256b store 19707 19708 PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19709 OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 19710 19711 PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19712 OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32 19713 IFORM : VMOVAPS_YMMqq_YMMqq_29 19714 } 19715 19716 19717 19718 { 19719 ICLASS : VMOVD 19720 EXCEPTIONS: avx-type-5 19721 CPL : 3 19722 CATEGORY : DATAXFER 19723 EXTENSION : AVX 19724 19725 # 32b load 19726 PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19727 OPERANDS : REG0=XMM_R():w:dq MEM0:r:d 19728 19729 PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19730 OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d 19731 19732 # 32b store 19733 PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19734 OPERANDS : MEM0:w:d REG0=XMM_R():r:d 19735 19736 PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19737 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d 19738 19739 19740 19741 # 32b load 19742 PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19743 OPERANDS : REG0=XMM_R():w:dq MEM0:r:d 19744 19745 PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19746 OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d 19747 19748 # 32b store 19749 PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19750 OPERANDS : MEM0:w:d REG0=XMM_R():r:d 19751 19752 PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19753 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d 19754 19755 19756 } 19757 19758 { 19759 ICLASS : VMOVQ 19760 EXCEPTIONS: avx-type-5 19761 CPL : 3 19762 CATEGORY : DATAXFER 19763 EXTENSION : AVX 19764 19765 # 64b load 19766 PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19767 OPERANDS : REG0=XMM_R():w:dq MEM0:r:q 19768 IFORM : VMOVQ_XMMdq_MEMq_6E 19769 19770 PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19771 OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r:q 19772 19773 # 64b store 19774 PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19775 OPERANDS : MEM0:w:q REG0=XMM_R():r:q 19776 IFORM : VMOVQ_MEMq_XMMq_7E 19777 19778 PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19779 OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:q 19780 19781 19782 # 2nd page of MOVQ forms 19783 PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19784 OPERANDS : REG0=XMM_R():w:dq MEM0:r:q 19785 IFORM : VMOVQ_XMMdq_MEMq_7E 19786 19787 PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19788 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q 19789 IFORM : VMOVQ_XMMdq_XMMq_7E 19790 19791 PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19792 OPERANDS : MEM0:w:q REG0=XMM_R():r:q 19793 IFORM : VMOVQ_MEMq_XMMq_D6 19794 19795 PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19796 OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q 19797 IFORM : VMOVQ_XMMdq_XMMq_D6 19798 19799 } 19800 19801 19802 19803 19804 { 19805 ICLASS : VMOVDDUP 19806 EXCEPTIONS: avx-type-5 19807 CPL : 3 19808 CATEGORY : DATAXFER 19809 EXTENSION : AVX 19810 19811 PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19812 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 19813 19814 PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19815 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 19816 19817 19818 PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19819 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 19820 19821 PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19822 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 19823 } 19824 19825 19826 19827 { 19828 ICLASS : VMOVDQA 19829 EXCEPTIONS: avx-type-1 19830 CPL : 3 19831 CATEGORY : DATAXFER 19832 EXTENSION : AVX 19833 ATTRIBUTES : REQUIRES_ALIGNMENT 19834 19835 # LOAD XMM 19836 19837 PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19838 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 19839 19840 PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19841 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 19842 IFORM : VMOVDQA_XMMdq_XMMdq_6F 19843 19844 # STORE XMM 19845 19846 PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19847 OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq 19848 19849 PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19850 OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq 19851 IFORM : VMOVDQA_XMMdq_XMMdq_7F 19852 19853 # LOAD YMM 19854 19855 PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19856 OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq 19857 19858 PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19859 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq 19860 IFORM : VMOVDQA_YMMqq_YMMqq_6F 19861 19862 19863 # STORE YMM 19864 19865 PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19866 OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq 19867 19868 PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19869 OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq 19870 IFORM : VMOVDQA_YMMqq_YMMqq_7F 19871 } 19872 19873 19874 { 19875 ICLASS : VMOVDQU 19876 EXCEPTIONS: avx-type-4M 19877 CPL : 3 19878 CATEGORY : DATAXFER 19879 EXTENSION : AVX 19880 19881 # LOAD XMM 19882 19883 PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19884 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 19885 19886 PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19887 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 19888 IFORM : VMOVDQU_XMMdq_XMMdq_6F 19889 19890 # LOAD YMM 19891 19892 PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19893 OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq 19894 19895 PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19896 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq 19897 IFORM : VMOVDQU_YMMqq_YMMqq_6F 19898 19899 # STORE XMM 19900 19901 PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19902 OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq 19903 19904 PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19905 OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq 19906 IFORM : VMOVDQU_XMMdq_XMMdq_7F 19907 19908 # STORE YMM 19909 19910 PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19911 OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq 19912 19913 PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19914 OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq 19915 IFORM : VMOVDQU_YMMqq_YMMqq_7F 19916 } 19917 19918 ################################################# 19919 ## skipping to the end 19920 ################################################# 19921 19922 ################################################# 19923 ## MACROS 19924 ################################################# 19925 { 19926 ICLASS : VMOVSHDUP 19927 EXCEPTIONS: avx-type-4 19928 CPL : 3 19929 CATEGORY : DATAXFER 19930 EXTENSION : AVX 19931 PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19932 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 19933 19934 PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19935 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 19936 19937 PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19938 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 19939 19940 PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19941 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 19942 } 19943 { 19944 ICLASS : VMOVSLDUP 19945 EXCEPTIONS: avx-type-4 19946 CPL : 3 19947 CATEGORY : DATAXFER 19948 EXTENSION : AVX 19949 PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19950 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 19951 19952 PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19953 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 19954 19955 PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19956 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 19957 19958 PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19959 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 19960 } 19961 19962 19963 19964 { 19965 ICLASS : VPOR 19966 EXCEPTIONS: avx-type-4 19967 CPL : 3 19968 CATEGORY : LOGICAL 19969 EXTENSION : AVX 19970 PATTERN : VV1 0xEB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19971 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 19972 19973 PATTERN : VV1 0xEB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19974 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 19975 } 19976 { 19977 ICLASS : VPAND 19978 EXCEPTIONS: avx-type-4 19979 CPL : 3 19980 CATEGORY : LOGICAL 19981 EXTENSION : AVX 19982 PATTERN : VV1 0xDB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19983 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 19984 19985 PATTERN : VV1 0xDB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19986 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 19987 } 19988 { 19989 ICLASS : VPANDN 19990 EXCEPTIONS: avx-type-4 19991 CPL : 3 19992 CATEGORY : LOGICAL 19993 EXTENSION : AVX 19994 PATTERN : VV1 0xDF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 19995 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 19996 19997 PATTERN : VV1 0xDF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 19998 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 19999 } 20000 { 20001 ICLASS : VPXOR 20002 EXCEPTIONS: avx-type-4 20003 CPL : 3 20004 CATEGORY : LOGICAL 20005 EXTENSION : AVX 20006 PATTERN : VV1 0xEF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20007 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 20008 20009 PATTERN : VV1 0xEF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20010 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 20011 } 20012 20013 20014 { 20015 ICLASS : VPABSB 20016 EXCEPTIONS: avx-type-4 20017 CPL : 3 20018 CATEGORY : AVX 20019 EXTENSION : AVX 20020 PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20021 OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:dq:i8 20022 20023 PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20024 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:i8 20025 } 20026 { 20027 ICLASS : VPABSW 20028 EXCEPTIONS: avx-type-4 20029 CPL : 3 20030 CATEGORY : AVX 20031 EXTENSION : AVX 20032 PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20033 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:i16 20034 20035 PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20036 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:i16 20037 } 20038 { 20039 ICLASS : VPABSD 20040 EXCEPTIONS: avx-type-4 20041 CPL : 3 20042 CATEGORY : AVX 20043 EXTENSION : AVX 20044 PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20045 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:i32 20046 20047 PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20048 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:i32 20049 } 20050 20051 { 20052 ICLASS : VPHMINPOSUW 20053 EXCEPTIONS: avx-type-4 20054 CPL : 3 20055 CATEGORY : AVX 20056 EXTENSION : AVX 20057 PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20058 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 20059 20060 PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20061 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 20062 } 20063 20064 20065 20066 20067 20068 20069 20070 20071 20072 20073 { 20074 ICLASS : VPSHUFD 20075 EXCEPTIONS: avx-type-4 20076 CPL : 3 20077 CATEGORY : AVX 20078 EXTENSION : AVX 20079 PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 20080 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b 20081 20082 PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 20083 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b 20084 } 20085 { 20086 ICLASS : VPSHUFHW 20087 EXCEPTIONS: avx-type-4 20088 CPL : 3 20089 CATEGORY : AVX 20090 EXTENSION : AVX 20091 PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 20092 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b 20093 20094 PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 20095 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b 20096 } 20097 { 20098 ICLASS : VPSHUFLW 20099 EXCEPTIONS: avx-type-4 20100 CPL : 3 20101 CATEGORY : AVX 20102 EXTENSION : AVX 20103 PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 20104 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b 20105 20106 PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 20107 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b 20108 } 20109 20110 20111 20112 20113 20114 20115 20116 20117 20118 20119 20120 20121 20122 { 20123 ICLASS : VPACKSSWB 20124 EXCEPTIONS: avx-type-4 20125 CPL : 3 20126 CATEGORY : AVX 20127 EXTENSION : AVX 20128 PATTERN : VV1 0x63 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20129 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20130 20131 PATTERN : VV1 0x63 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20132 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20133 } 20134 { 20135 ICLASS : VPACKSSDW 20136 EXCEPTIONS: avx-type-4 20137 CPL : 3 20138 CATEGORY : AVX 20139 EXTENSION : AVX 20140 PATTERN : VV1 0x6B VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20141 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 20142 20143 PATTERN : VV1 0x6B VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20144 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 20145 } 20146 { 20147 ICLASS : VPACKUSWB 20148 EXCEPTIONS: avx-type-4 20149 CPL : 3 20150 CATEGORY : AVX 20151 EXTENSION : AVX 20152 PATTERN : VV1 0x67 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20153 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20154 20155 PATTERN : VV1 0x67 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20156 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20157 } 20158 { 20159 ICLASS : VPACKUSDW 20160 EXCEPTIONS: avx-type-4 20161 CPL : 3 20162 CATEGORY : AVX 20163 EXTENSION : AVX 20164 PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20165 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 20166 20167 PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20168 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 20169 } 20170 20171 { 20172 ICLASS : VPSLLW 20173 EXCEPTIONS: avx-type-7 20174 CPL : 3 20175 CATEGORY : AVX 20176 EXTENSION : AVX 20177 PATTERN : VV1 0xF1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20178 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64 20179 20180 PATTERN : VV1 0xF1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20181 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64 20182 } 20183 { 20184 ICLASS : VPSLLD 20185 EXCEPTIONS: avx-type-7 20186 CPL : 3 20187 CATEGORY : AVX 20188 EXTENSION : AVX 20189 PATTERN : VV1 0xF2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20190 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 20191 20192 PATTERN : VV1 0xF2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20193 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64 20194 } 20195 { 20196 ICLASS : VPSLLQ 20197 EXCEPTIONS: avx-type-7 20198 CPL : 3 20199 CATEGORY : AVX 20200 EXTENSION : AVX 20201 PATTERN : VV1 0xF3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20202 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 20203 20204 PATTERN : VV1 0xF3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20205 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 20206 } 20207 20208 { 20209 ICLASS : VPSRLW 20210 EXCEPTIONS: avx-type-7 20211 CPL : 3 20212 CATEGORY : AVX 20213 EXTENSION : AVX 20214 PATTERN : VV1 0xD1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20215 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64 20216 20217 PATTERN : VV1 0xD1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20218 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64 20219 } 20220 { 20221 ICLASS : VPSRLD 20222 EXCEPTIONS: avx-type-7 20223 CPL : 3 20224 CATEGORY : AVX 20225 EXTENSION : AVX 20226 PATTERN : VV1 0xD2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20227 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 20228 20229 PATTERN : VV1 0xD2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20230 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64 20231 } 20232 { 20233 ICLASS : VPSRLQ 20234 EXCEPTIONS: avx-type-7 20235 CPL : 3 20236 CATEGORY : AVX 20237 EXTENSION : AVX 20238 PATTERN : VV1 0xD3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20239 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 20240 20241 PATTERN : VV1 0xD3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20242 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 20243 } 20244 20245 { 20246 ICLASS : VPSRAW 20247 EXCEPTIONS: avx-type-7 20248 CPL : 3 20249 CATEGORY : AVX 20250 EXTENSION : AVX 20251 PATTERN : VV1 0xE1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20252 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:u64 20253 20254 PATTERN : VV1 0xE1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20255 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:u64 20256 } 20257 { 20258 ICLASS : VPSRAD 20259 EXCEPTIONS: avx-type-7 20260 CPL : 3 20261 CATEGORY : AVX 20262 EXTENSION : AVX 20263 PATTERN : VV1 0xE2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20264 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:u64 20265 20266 PATTERN : VV1 0xE2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20267 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:u64 20268 } 20269 20270 { 20271 ICLASS : VPADDB 20272 EXCEPTIONS: avx-type-4 20273 CPL : 3 20274 CATEGORY : AVX 20275 EXTENSION : AVX 20276 PATTERN : VV1 0xFC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20277 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 20278 20279 PATTERN : VV1 0xFC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20280 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 20281 } 20282 { 20283 ICLASS : VPADDW 20284 EXCEPTIONS: avx-type-4 20285 CPL : 3 20286 CATEGORY : AVX 20287 EXTENSION : AVX 20288 PATTERN : VV1 0xFD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20289 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20290 20291 PATTERN : VV1 0xFD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20292 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20293 } 20294 { 20295 ICLASS : VPADDD 20296 EXCEPTIONS: avx-type-4 20297 CPL : 3 20298 CATEGORY : AVX 20299 EXTENSION : AVX 20300 PATTERN : VV1 0xFE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20301 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 20302 20303 PATTERN : VV1 0xFE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20304 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 20305 } 20306 { 20307 ICLASS : VPADDQ 20308 EXCEPTIONS: avx-type-4 20309 CPL : 3 20310 CATEGORY : AVX 20311 EXTENSION : AVX 20312 PATTERN : VV1 0xD4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20313 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 20314 20315 PATTERN : VV1 0xD4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20316 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 20317 } 20318 20319 { 20320 ICLASS : VPADDSB 20321 EXCEPTIONS: avx-type-4 20322 CPL : 3 20323 CATEGORY : AVX 20324 EXTENSION : AVX 20325 PATTERN : VV1 0xEC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20326 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 20327 20328 PATTERN : VV1 0xEC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20329 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 20330 } 20331 { 20332 ICLASS : VPADDSW 20333 EXCEPTIONS: avx-type-4 20334 CPL : 3 20335 CATEGORY : AVX 20336 EXTENSION : AVX 20337 PATTERN : VV1 0xED VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20338 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20339 20340 PATTERN : VV1 0xED VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20341 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20342 } 20343 20344 { 20345 ICLASS : VPADDUSB 20346 EXCEPTIONS: avx-type-4 20347 CPL : 3 20348 CATEGORY : AVX 20349 EXTENSION : AVX 20350 PATTERN : VV1 0xDC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20351 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 20352 20353 PATTERN : VV1 0xDC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20354 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 20355 } 20356 { 20357 ICLASS : VPADDUSW 20358 EXCEPTIONS: avx-type-4 20359 CPL : 3 20360 CATEGORY : AVX 20361 EXTENSION : AVX 20362 PATTERN : VV1 0xDD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20363 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 20364 20365 PATTERN : VV1 0xDD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20366 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 20367 } 20368 20369 { 20370 ICLASS : VPAVGB 20371 EXCEPTIONS: avx-type-4 20372 CPL : 3 20373 CATEGORY : AVX 20374 EXTENSION : AVX 20375 PATTERN : VV1 0xE0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20376 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 20377 20378 PATTERN : VV1 0xE0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20379 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 20380 } 20381 { 20382 ICLASS : VPAVGW 20383 EXCEPTIONS: avx-type-4 20384 CPL : 3 20385 CATEGORY : AVX 20386 EXTENSION : AVX 20387 PATTERN : VV1 0xE3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20388 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 20389 20390 PATTERN : VV1 0xE3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20391 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 20392 } 20393 20394 { 20395 ICLASS : VPCMPEQB 20396 EXCEPTIONS: avx-type-4 20397 CPL : 3 20398 CATEGORY : AVX 20399 EXTENSION : AVX 20400 PATTERN : VV1 0x74 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20401 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 20402 20403 PATTERN : VV1 0x74 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20404 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 20405 } 20406 { 20407 ICLASS : VPCMPEQW 20408 EXCEPTIONS: avx-type-4 20409 CPL : 3 20410 CATEGORY : AVX 20411 EXTENSION : AVX 20412 PATTERN : VV1 0x75 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20413 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 20414 20415 PATTERN : VV1 0x75 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20416 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 20417 } 20418 { 20419 ICLASS : VPCMPEQD 20420 EXCEPTIONS: avx-type-4 20421 CPL : 3 20422 CATEGORY : AVX 20423 EXTENSION : AVX 20424 PATTERN : VV1 0x76 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20425 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 20426 20427 PATTERN : VV1 0x76 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20428 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 20429 } 20430 { 20431 ICLASS : VPCMPEQQ 20432 EXCEPTIONS: avx-type-4 20433 CPL : 3 20434 CATEGORY : AVX 20435 EXTENSION : AVX 20436 PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20437 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 20438 20439 PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20440 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 20441 } 20442 20443 { 20444 ICLASS : VPCMPGTB 20445 EXCEPTIONS: avx-type-4 20446 CPL : 3 20447 CATEGORY : AVX 20448 EXTENSION : AVX 20449 PATTERN : VV1 0x64 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20450 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 20451 20452 PATTERN : VV1 0x64 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20453 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 20454 } 20455 { 20456 ICLASS : VPCMPGTW 20457 EXCEPTIONS: avx-type-4 20458 CPL : 3 20459 CATEGORY : AVX 20460 EXTENSION : AVX 20461 PATTERN : VV1 0x65 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20462 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20463 20464 PATTERN : VV1 0x65 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20465 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20466 } 20467 { 20468 ICLASS : VPCMPGTD 20469 EXCEPTIONS: avx-type-4 20470 CPL : 3 20471 CATEGORY : AVX 20472 EXTENSION : AVX 20473 PATTERN : VV1 0x66 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20474 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 20475 20476 PATTERN : VV1 0x66 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20477 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 20478 } 20479 { 20480 ICLASS : VPCMPGTQ 20481 EXCEPTIONS: avx-type-4 20482 CPL : 3 20483 CATEGORY : AVX 20484 EXTENSION : AVX 20485 PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20486 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 20487 20488 PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20489 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 20490 } 20491 20492 { 20493 ICLASS : VPHADDW 20494 EXCEPTIONS: avx-type-4 20495 CPL : 3 20496 CATEGORY : AVX 20497 EXTENSION : AVX 20498 PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20499 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20500 20501 PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20502 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20503 } 20504 { 20505 ICLASS : VPHADDD 20506 EXCEPTIONS: avx-type-4 20507 CPL : 3 20508 CATEGORY : AVX 20509 EXTENSION : AVX 20510 PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20511 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 20512 20513 PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20514 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 20515 } 20516 { 20517 ICLASS : VPHADDSW 20518 EXCEPTIONS: avx-type-4 20519 CPL : 3 20520 CATEGORY : AVX 20521 EXTENSION : AVX 20522 PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20523 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20524 20525 PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20526 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20527 } 20528 { 20529 ICLASS : VPHSUBW 20530 EXCEPTIONS: avx-type-4 20531 CPL : 3 20532 CATEGORY : AVX 20533 EXTENSION : AVX 20534 PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20535 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20536 20537 PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20538 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20539 } 20540 { 20541 ICLASS : VPHSUBD 20542 EXCEPTIONS: avx-type-4 20543 CPL : 3 20544 CATEGORY : AVX 20545 EXTENSION : AVX 20546 PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20547 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 20548 20549 PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20550 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 20551 } 20552 { 20553 ICLASS : VPHSUBSW 20554 EXCEPTIONS: avx-type-4 20555 CPL : 3 20556 CATEGORY : AVX 20557 EXTENSION : AVX 20558 PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20559 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20560 20561 PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20562 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20563 } 20564 20565 { 20566 ICLASS : VPMULHUW 20567 EXCEPTIONS: avx-type-4 20568 CPL : 3 20569 CATEGORY : AVX 20570 EXTENSION : AVX 20571 PATTERN : VV1 0xE4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20572 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 20573 20574 PATTERN : VV1 0xE4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20575 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 20576 } 20577 { 20578 ICLASS : VPMULHRSW 20579 EXCEPTIONS: avx-type-4 20580 CPL : 3 20581 CATEGORY : AVX 20582 EXTENSION : AVX 20583 PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20584 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20585 20586 PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20587 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20588 } 20589 { 20590 ICLASS : VPMULHW 20591 EXCEPTIONS: avx-type-4 20592 CPL : 3 20593 CATEGORY : AVX 20594 EXTENSION : AVX 20595 PATTERN : VV1 0xE5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20596 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20597 20598 PATTERN : VV1 0xE5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20599 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20600 } 20601 { 20602 ICLASS : VPMULLW 20603 EXCEPTIONS: avx-type-4 20604 CPL : 3 20605 CATEGORY : AVX 20606 EXTENSION : AVX 20607 PATTERN : VV1 0xD5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20608 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20609 20610 PATTERN : VV1 0xD5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20611 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20612 } 20613 { 20614 ICLASS : VPMULLD 20615 EXCEPTIONS: avx-type-4 20616 CPL : 3 20617 CATEGORY : AVX 20618 EXTENSION : AVX 20619 PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20620 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 20621 20622 PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20623 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 20624 } 20625 20626 { 20627 ICLASS : VPMULUDQ 20628 EXCEPTIONS: avx-type-4 20629 CPL : 3 20630 CATEGORY : AVX 20631 EXTENSION : AVX 20632 PATTERN : VV1 0xF4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20633 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 20634 20635 PATTERN : VV1 0xF4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20636 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 20637 } 20638 { 20639 ICLASS : VPMULDQ 20640 EXCEPTIONS: avx-type-4 20641 CPL : 3 20642 CATEGORY : AVX 20643 EXTENSION : AVX 20644 PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20645 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 20646 20647 PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20648 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 20649 } 20650 20651 { 20652 ICLASS : VPSADBW 20653 EXCEPTIONS: avx-type-4 20654 CPL : 3 20655 CATEGORY : AVX 20656 EXTENSION : AVX 20657 PATTERN : VV1 0xF6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20658 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 20659 20660 PATTERN : VV1 0xF6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20661 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 20662 } 20663 { 20664 ICLASS : VPSHUFB 20665 EXCEPTIONS: avx-type-4 20666 CPL : 3 20667 CATEGORY : AVX 20668 EXTENSION : AVX 20669 PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20670 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 20671 20672 PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20673 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 20674 } 20675 20676 { 20677 ICLASS : VPSIGNB 20678 EXCEPTIONS: avx-type-4 20679 CPL : 3 20680 CATEGORY : AVX 20681 EXTENSION : AVX 20682 PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20683 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 20684 20685 PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20686 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 20687 } 20688 { 20689 ICLASS : VPSIGNW 20690 EXCEPTIONS: avx-type-4 20691 CPL : 3 20692 CATEGORY : AVX 20693 EXTENSION : AVX 20694 PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20695 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20696 20697 PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20698 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20699 } 20700 { 20701 ICLASS : VPSIGND 20702 EXCEPTIONS: avx-type-4 20703 CPL : 3 20704 CATEGORY : AVX 20705 EXTENSION : AVX 20706 PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20707 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 20708 20709 PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20710 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 20711 } 20712 20713 { 20714 ICLASS : VPSUBSB 20715 EXCEPTIONS: avx-type-4 20716 CPL : 3 20717 CATEGORY : AVX 20718 EXTENSION : AVX 20719 PATTERN : VV1 0xE8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20720 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 20721 20722 PATTERN : VV1 0xE8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20723 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 20724 } 20725 { 20726 ICLASS : VPSUBSW 20727 EXCEPTIONS: avx-type-4 20728 CPL : 3 20729 CATEGORY : AVX 20730 EXTENSION : AVX 20731 PATTERN : VV1 0xE9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20732 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20733 20734 PATTERN : VV1 0xE9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20735 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20736 } 20737 20738 { 20739 ICLASS : VPSUBUSB 20740 EXCEPTIONS: avx-type-4 20741 CPL : 3 20742 CATEGORY : AVX 20743 EXTENSION : AVX 20744 PATTERN : VV1 0xD8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20745 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 20746 20747 PATTERN : VV1 0xD8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20748 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 20749 } 20750 { 20751 ICLASS : VPSUBUSW 20752 EXCEPTIONS: avx-type-4 20753 CPL : 3 20754 CATEGORY : AVX 20755 EXTENSION : AVX 20756 PATTERN : VV1 0xD9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20757 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 20758 20759 PATTERN : VV1 0xD9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20760 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 20761 } 20762 20763 { 20764 ICLASS : VPSUBB 20765 EXCEPTIONS: avx-type-4 20766 CPL : 3 20767 CATEGORY : AVX 20768 EXTENSION : AVX 20769 PATTERN : VV1 0xF8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20770 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 20771 20772 PATTERN : VV1 0xF8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20773 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 20774 } 20775 { 20776 ICLASS : VPSUBW 20777 EXCEPTIONS: avx-type-4 20778 CPL : 3 20779 CATEGORY : AVX 20780 EXTENSION : AVX 20781 PATTERN : VV1 0xF9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20782 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 20783 20784 PATTERN : VV1 0xF9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20785 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 20786 } 20787 { 20788 ICLASS : VPSUBD 20789 EXCEPTIONS: avx-type-4 20790 CPL : 3 20791 CATEGORY : AVX 20792 EXTENSION : AVX 20793 PATTERN : VV1 0xFA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20794 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 20795 20796 PATTERN : VV1 0xFA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20797 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 20798 } 20799 { 20800 ICLASS : VPSUBQ 20801 EXCEPTIONS: avx-type-4 20802 CPL : 3 20803 CATEGORY : AVX 20804 EXTENSION : AVX 20805 PATTERN : VV1 0xFB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20806 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 20807 20808 PATTERN : VV1 0xFB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20809 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 20810 } 20811 20812 { 20813 ICLASS : VPUNPCKHBW 20814 EXCEPTIONS: avx-type-4 20815 CPL : 3 20816 CATEGORY : AVX 20817 EXTENSION : AVX 20818 PATTERN : VV1 0x68 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20819 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 20820 20821 PATTERN : VV1 0x68 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20822 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 20823 } 20824 { 20825 ICLASS : VPUNPCKHWD 20826 EXCEPTIONS: avx-type-4 20827 CPL : 3 20828 CATEGORY : AVX 20829 EXTENSION : AVX 20830 PATTERN : VV1 0x69 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20831 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 20832 20833 PATTERN : VV1 0x69 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20834 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 20835 } 20836 { 20837 ICLASS : VPUNPCKHDQ 20838 EXCEPTIONS: avx-type-4 20839 CPL : 3 20840 CATEGORY : AVX 20841 EXTENSION : AVX 20842 PATTERN : VV1 0x6A VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20843 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 20844 20845 PATTERN : VV1 0x6A VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20846 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 20847 } 20848 { 20849 ICLASS : VPUNPCKHQDQ 20850 EXCEPTIONS: avx-type-4 20851 CPL : 3 20852 CATEGORY : AVX 20853 EXTENSION : AVX 20854 PATTERN : VV1 0x6D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20855 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 20856 20857 PATTERN : VV1 0x6D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20858 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 20859 } 20860 20861 { 20862 ICLASS : VPUNPCKLBW 20863 EXCEPTIONS: avx-type-4 20864 CPL : 3 20865 CATEGORY : AVX 20866 EXTENSION : AVX 20867 PATTERN : VV1 0x60 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20868 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 20869 20870 PATTERN : VV1 0x60 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20871 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 20872 } 20873 { 20874 ICLASS : VPUNPCKLWD 20875 EXCEPTIONS: avx-type-4 20876 CPL : 3 20877 CATEGORY : AVX 20878 EXTENSION : AVX 20879 PATTERN : VV1 0x61 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20880 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 20881 20882 PATTERN : VV1 0x61 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20883 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 20884 } 20885 { 20886 ICLASS : VPUNPCKLDQ 20887 EXCEPTIONS: avx-type-4 20888 CPL : 3 20889 CATEGORY : AVX 20890 EXTENSION : AVX 20891 PATTERN : VV1 0x62 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20892 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 20893 20894 PATTERN : VV1 0x62 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20895 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 20896 } 20897 { 20898 ICLASS : VPUNPCKLQDQ 20899 EXCEPTIONS: avx-type-4 20900 CPL : 3 20901 CATEGORY : AVX 20902 EXTENSION : AVX 20903 PATTERN : VV1 0x6C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 20904 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 20905 20906 PATTERN : VV1 0x6C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20907 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 20908 } 20909 20910 20911 20912 { 20913 ICLASS : VPSRLDQ 20914 EXCEPTIONS: avx-type-7 20915 CPL : 3 20916 CATEGORY : AVX 20917 EXTENSION : AVX 20918 PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() 20919 OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD 20920 } 20921 { 20922 ICLASS : VPSLLDQ 20923 EXCEPTIONS: avx-type-7 20924 CPL : 3 20925 CATEGORY : AVX 20926 EXTENSION : AVX 20927 PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() 20928 OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD 20929 } 20930 20931 20932 20933 20934 20935 20936 20937 20938 20939 20940 20941 20942 20943 20944 20945 20946 20947 20948 20949 20950 { 20951 ICLASS : VMOVLHPS 20952 EXCEPTIONS: avx-type-7 20953 CPL : 3 20954 CATEGORY : DATAXFER 20955 EXTENSION : AVX 20956 PATTERN : VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20957 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 REG2=XMM_B():r:q:f32 20958 } 20959 { 20960 ICLASS : VMOVHLPS 20961 EXCEPTIONS: avx-type-7 20962 CPL : 3 20963 CATEGORY : DATAXFER 20964 EXTENSION : AVX 20965 PATTERN : VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 20966 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 20967 } 20968 20969 20970 20971 20972 20973 20974 20975 { 20976 ICLASS : VPALIGNR 20977 EXCEPTIONS: avx-type-4 20978 CPL : 3 20979 CATEGORY : AVX 20980 EXTENSION : AVX 20981 PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 20982 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b 20983 20984 PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 20985 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b 20986 } 20987 { 20988 ICLASS : VPBLENDW 20989 EXCEPTIONS: avx-type-4 20990 CPL : 3 20991 CATEGORY : AVX 20992 EXTENSION : AVX 20993 PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 20994 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b 20995 20996 PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 20997 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b 20998 } 20999 21000 21001 21002 21003 21004 21005 21006 21007 21008 21009 21010 21011 ############################################################ 21012 { 21013 ICLASS : VROUNDPD 21014 EXCEPTIONS: avx-type-2 21015 CPL : 3 21016 CATEGORY : AVX 21017 EXTENSION : AVX 21018 ATTRIBUTES: MXCSR 21019 PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21020 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b 21021 21022 PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21023 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b 21024 21025 PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21026 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b 21027 21028 PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21029 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b 21030 } 21031 { 21032 ICLASS : VROUNDPS 21033 EXCEPTIONS: avx-type-2 21034 CPL : 3 21035 CATEGORY : AVX 21036 EXTENSION : AVX 21037 ATTRIBUTES: MXCSR 21038 PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21039 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b 21040 21041 PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21042 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b 21043 21044 PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21045 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b 21046 21047 PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21048 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b 21049 } 21050 { 21051 ICLASS : VROUNDSD 21052 EXCEPTIONS: avx-type-3 21053 CPL : 3 21054 CATEGORY : AVX 21055 EXTENSION : AVX 21056 ATTRIBUTES: MXCSR simd_scalar 21057 PATTERN : VV1 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21058 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 21059 21060 PATTERN : VV1 0x0B V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21061 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b 21062 } 21063 { 21064 ICLASS : VROUNDSS 21065 EXCEPTIONS: avx-type-3 21066 CPL : 3 21067 CATEGORY : AVX 21068 EXTENSION : AVX 21069 ATTRIBUTES: MXCSR simd_scalar 21070 PATTERN : VV1 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21071 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 21072 21073 PATTERN : VV1 0x0A V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21074 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b 21075 } 21076 21077 { 21078 ICLASS : VSHUFPD 21079 EXCEPTIONS: avx-type-4 21080 CPL : 3 21081 CATEGORY : AVX 21082 EXTENSION : AVX 21083 PATTERN : VV1 0xC6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21084 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b 21085 21086 PATTERN : VV1 0xC6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21087 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b 21088 21089 PATTERN : VV1 0xC6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21090 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b 21091 21092 PATTERN : VV1 0xC6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21093 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b 21094 } 21095 { 21096 ICLASS : VSHUFPS 21097 EXCEPTIONS: avx-type-4 21098 CPL : 3 21099 CATEGORY : AVX 21100 EXTENSION : AVX 21101 PATTERN : VV1 0xC6 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21102 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b 21103 21104 PATTERN : VV1 0xC6 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21105 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b 21106 21107 PATTERN : VV1 0xC6 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21108 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b 21109 21110 PATTERN : VV1 0xC6 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21111 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b 21112 } 21113 21114 { 21115 ICLASS : VRCPPS 21116 EXCEPTIONS: avx-type-4 21117 CPL : 3 21118 CATEGORY : AVX 21119 EXTENSION : AVX 21120 PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21121 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 21122 21123 PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21124 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 21125 21126 PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21127 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 21128 21129 PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21130 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 21131 } 21132 { 21133 ICLASS : VRCPSS 21134 EXCEPTIONS: avx-type-5 21135 CPL : 3 21136 CATEGORY : AVX 21137 EXTENSION : AVX 21138 ATTRIBUTES: simd_scalar 21139 PATTERN : VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21140 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 21141 21142 PATTERN : VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21143 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 21144 } 21145 21146 { 21147 ICLASS : VRSQRTPS 21148 EXCEPTIONS: avx-type-4 21149 CPL : 3 21150 CATEGORY : AVX 21151 EXTENSION : AVX 21152 PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21153 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 21154 21155 PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21156 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 21157 21158 PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21159 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 21160 21161 PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21162 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 21163 } 21164 { 21165 ICLASS : VRSQRTSS 21166 EXCEPTIONS: avx-type-5 21167 CPL : 3 21168 CATEGORY : AVX 21169 EXTENSION : AVX 21170 ATTRIBUTES: simd_scalar 21171 PATTERN : VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21172 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 21173 21174 PATTERN : VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21175 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 21176 } 21177 21178 { 21179 ICLASS : VSQRTPD 21180 EXCEPTIONS: avx-type-2 21181 CPL : 3 21182 CATEGORY : AVX 21183 EXTENSION : AVX 21184 ATTRIBUTES: MXCSR 21185 PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21186 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 21187 21188 PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21189 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 21190 21191 PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21192 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 21193 21194 PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21195 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 21196 } 21197 { 21198 ICLASS : VSQRTPS 21199 EXCEPTIONS: avx-type-2 21200 CPL : 3 21201 CATEGORY : AVX 21202 EXTENSION : AVX 21203 ATTRIBUTES: MXCSR 21204 PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21205 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 21206 21207 PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21208 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 21209 21210 PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21211 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 21212 21213 PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21214 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 21215 } 21216 { 21217 ICLASS : VSQRTSD 21218 EXCEPTIONS: avx-type-3 21219 CPL : 3 21220 CATEGORY : AVX 21221 EXTENSION : AVX 21222 ATTRIBUTES : MXCSR simd_scalar 21223 PATTERN : VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21224 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 21225 21226 PATTERN : VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21227 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 21228 } 21229 { 21230 ICLASS : VSQRTSS 21231 EXCEPTIONS: avx-type-3 21232 CPL : 3 21233 CATEGORY : AVX 21234 EXTENSION : AVX 21235 ATTRIBUTES: MXCSR simd_scalar 21236 PATTERN : VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21237 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 21238 21239 PATTERN : VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21240 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 21241 } 21242 21243 21244 { 21245 ICLASS : VUNPCKHPD 21246 EXCEPTIONS: avx-type-4 21247 CPL : 3 21248 CATEGORY : AVX 21249 EXTENSION : AVX 21250 PATTERN : VV1 0x15 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21251 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 21252 21253 PATTERN : VV1 0x15 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21254 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 21255 21256 PATTERN : VV1 0x15 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21257 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 21258 21259 PATTERN : VV1 0x15 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21260 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 21261 } 21262 { 21263 ICLASS : VUNPCKHPS 21264 EXCEPTIONS: avx-type-4 21265 CPL : 3 21266 CATEGORY : AVX 21267 EXTENSION : AVX 21268 PATTERN : VV1 0x15 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21269 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 21270 21271 PATTERN : VV1 0x15 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21272 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 21273 21274 PATTERN : VV1 0x15 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21275 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 21276 21277 PATTERN : VV1 0x15 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21278 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 21279 } 21280 21281 21282 21283 { 21284 ICLASS : VSUBPD 21285 EXCEPTIONS: avx-type-2 21286 CPL : 3 21287 CATEGORY : AVX 21288 EXTENSION : AVX 21289 ATTRIBUTES: MXCSR 21290 PATTERN : VV1 0x5C V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21291 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 21292 21293 PATTERN : VV1 0x5C V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21294 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 21295 21296 PATTERN : VV1 0x5C V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21297 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 21298 21299 PATTERN : VV1 0x5C V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21300 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 21301 } 21302 { 21303 ICLASS : VSUBPS 21304 EXCEPTIONS: avx-type-2 21305 CPL : 3 21306 CATEGORY : AVX 21307 EXTENSION : AVX 21308 ATTRIBUTES: MXCSR 21309 PATTERN : VV1 0x5C VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21310 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 21311 21312 PATTERN : VV1 0x5C VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21313 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 21314 21315 PATTERN : VV1 0x5C VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21316 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 21317 21318 PATTERN : VV1 0x5C VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21319 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 21320 } 21321 { 21322 ICLASS : VSUBSD 21323 EXCEPTIONS: avx-type-3 21324 CPL : 3 21325 CATEGORY : AVX 21326 EXTENSION : AVX 21327 ATTRIBUTES : MXCSR SIMD_SCALAR 21328 PATTERN : VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21329 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 21330 21331 PATTERN : VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21332 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 21333 } 21334 { 21335 ICLASS : VSUBSS 21336 EXCEPTIONS: avx-type-3 21337 CPL : 3 21338 CATEGORY : AVX 21339 EXTENSION : AVX 21340 ATTRIBUTES: MXCSR simd_scalar 21341 PATTERN : VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21342 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 21343 21344 PATTERN : VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21345 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 21346 } 21347 21348 { 21349 ICLASS : VMULPD 21350 EXCEPTIONS: avx-type-2 21351 CPL : 3 21352 CATEGORY : AVX 21353 EXTENSION : AVX 21354 ATTRIBUTES: MXCSR 21355 PATTERN : VV1 0x59 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21356 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 21357 21358 PATTERN : VV1 0x59 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21359 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 21360 21361 PATTERN : VV1 0x59 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21362 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 21363 21364 PATTERN : VV1 0x59 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21365 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 21366 } 21367 { 21368 ICLASS : VMULPS 21369 EXCEPTIONS: avx-type-2 21370 CPL : 3 21371 CATEGORY : AVX 21372 EXTENSION : AVX 21373 ATTRIBUTES: MXCSR 21374 PATTERN : VV1 0x59 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21375 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 21376 21377 PATTERN : VV1 0x59 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21378 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 21379 21380 PATTERN : VV1 0x59 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21381 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 21382 21383 PATTERN : VV1 0x59 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21384 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 21385 } 21386 { 21387 ICLASS : VMULSD 21388 EXCEPTIONS: avx-type-3 21389 CPL : 3 21390 CATEGORY : AVX 21391 EXTENSION : AVX 21392 ATTRIBUTES : MXCSR simd_scalar 21393 PATTERN : VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21394 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 21395 21396 PATTERN : VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21397 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 21398 } 21399 { 21400 ICLASS : VMULSS 21401 EXCEPTIONS: avx-type-3 21402 CPL : 3 21403 CATEGORY : AVX 21404 EXTENSION : AVX 21405 ATTRIBUTES: MXCSR simd_scalar 21406 PATTERN : VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21407 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 21408 21409 PATTERN : VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21410 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 21411 } 21412 21413 { 21414 ICLASS : VORPD 21415 EXCEPTIONS: avx-type-4 21416 CPL : 3 21417 CATEGORY : LOGICAL_FP 21418 EXTENSION : AVX 21419 PATTERN : VV1 0x56 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21420 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 21421 21422 PATTERN : VV1 0x56 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21423 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 21424 21425 PATTERN : VV1 0x56 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21426 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 21427 21428 PATTERN : VV1 0x56 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21429 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 21430 } 21431 { 21432 ICLASS : VORPS 21433 EXCEPTIONS: avx-type-4 21434 CPL : 3 21435 CATEGORY : LOGICAL_FP 21436 EXTENSION : AVX 21437 PATTERN : VV1 0x56 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21438 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 21439 21440 PATTERN : VV1 0x56 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21441 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 21442 21443 PATTERN : VV1 0x56 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21444 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 21445 21446 PATTERN : VV1 0x56 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21447 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 21448 } 21449 21450 { 21451 ICLASS : VPMAXSB 21452 EXCEPTIONS: avx-type-4 21453 CPL : 3 21454 CATEGORY : AVX 21455 EXTENSION : AVX 21456 PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21457 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 21458 21459 PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21460 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 21461 } 21462 { 21463 ICLASS : VPMAXSW 21464 EXCEPTIONS: avx-type-4 21465 CPL : 3 21466 CATEGORY : AVX 21467 EXTENSION : AVX 21468 PATTERN : VV1 0xEE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21469 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 21470 21471 PATTERN : VV1 0xEE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21472 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 21473 } 21474 { 21475 ICLASS : VPMAXSD 21476 EXCEPTIONS: avx-type-4 21477 CPL : 3 21478 CATEGORY : AVX 21479 EXTENSION : AVX 21480 PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21481 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 21482 21483 PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21484 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 21485 } 21486 21487 { 21488 ICLASS : VPMAXUB 21489 EXCEPTIONS: avx-type-4 21490 CPL : 3 21491 CATEGORY : AVX 21492 EXTENSION : AVX 21493 PATTERN : VV1 0xDE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21494 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 21495 21496 PATTERN : VV1 0xDE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21497 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 21498 } 21499 { 21500 ICLASS : VPMAXUW 21501 EXCEPTIONS: avx-type-4 21502 CPL : 3 21503 CATEGORY : AVX 21504 EXTENSION : AVX 21505 PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21506 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 21507 21508 PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21509 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 21510 } 21511 { 21512 ICLASS : VPMAXUD 21513 EXCEPTIONS: avx-type-4 21514 CPL : 3 21515 CATEGORY : AVX 21516 EXTENSION : AVX 21517 PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21518 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 21519 21520 PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21521 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 21522 } 21523 21524 { 21525 ICLASS : VPMINSB 21526 EXCEPTIONS: avx-type-4 21527 CPL : 3 21528 CATEGORY : AVX 21529 EXTENSION : AVX 21530 PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21531 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 21532 21533 PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21534 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 21535 } 21536 { 21537 ICLASS : VPMINSW 21538 EXCEPTIONS: avx-type-4 21539 CPL : 3 21540 CATEGORY : AVX 21541 EXTENSION : AVX 21542 PATTERN : VV1 0xEA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21543 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 21544 21545 PATTERN : VV1 0xEA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21546 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 21547 } 21548 { 21549 ICLASS : VPMINSD 21550 EXCEPTIONS: avx-type-4 21551 CPL : 3 21552 CATEGORY : AVX 21553 EXTENSION : AVX 21554 PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21555 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 21556 21557 PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21558 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 21559 } 21560 21561 { 21562 ICLASS : VPMINUB 21563 EXCEPTIONS: avx-type-4 21564 CPL : 3 21565 CATEGORY : AVX 21566 EXTENSION : AVX 21567 PATTERN : VV1 0xDA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21568 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 21569 21570 PATTERN : VV1 0xDA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21571 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 21572 } 21573 { 21574 ICLASS : VPMINUW 21575 EXCEPTIONS: avx-type-4 21576 CPL : 3 21577 CATEGORY : AVX 21578 EXTENSION : AVX 21579 PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21580 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 21581 21582 PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21583 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 21584 } 21585 { 21586 ICLASS : VPMINUD 21587 EXCEPTIONS: avx-type-4 21588 CPL : 3 21589 CATEGORY : AVX 21590 EXTENSION : AVX 21591 PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21592 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 21593 21594 PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21595 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 21596 } 21597 21598 21599 { 21600 ICLASS : VPMADDWD 21601 EXCEPTIONS: avx-type-4 21602 CPL : 3 21603 CATEGORY : AVX 21604 EXTENSION : AVX 21605 PATTERN : VV1 0xF5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21606 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 21607 21608 PATTERN : VV1 0xF5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21609 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 21610 } 21611 { 21612 ICLASS : VPMADDUBSW 21613 EXCEPTIONS: avx-type-4 21614 CPL : 3 21615 CATEGORY : AVX 21616 EXTENSION : AVX 21617 PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21618 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:i8 21619 21620 PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21621 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:i8 21622 } 21623 21624 21625 { 21626 ICLASS : VMPSADBW 21627 EXCEPTIONS: avx-type-4 21628 CPL : 3 21629 CATEGORY : AVX 21630 EXTENSION : AVX 21631 PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 21632 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b 21633 21634 PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 21635 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b 21636 } 21637 21638 21639 ############################################################ 21640 { 21641 ICLASS : VPSLLW 21642 EXCEPTIONS: avx-type-7 21643 CPL : 3 21644 CATEGORY : AVX 21645 EXTENSION : AVX 21646 PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 21647 OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD 21648 } 21649 { 21650 ICLASS : VPSLLD 21651 EXCEPTIONS: avx-type-7 21652 CPL : 3 21653 CATEGORY : AVX 21654 EXTENSION : AVX 21655 PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 21656 OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b #NDD 21657 } 21658 { 21659 ICLASS : VPSLLQ 21660 EXCEPTIONS: avx-type-7 21661 CPL : 3 21662 CATEGORY : AVX 21663 EXTENSION : AVX 21664 PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 21665 OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD 21666 } 21667 21668 { 21669 ICLASS : VPSRAW 21670 EXCEPTIONS: avx-type-7 21671 CPL : 3 21672 CATEGORY : AVX 21673 EXTENSION : AVX 21674 PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 21675 OPERANDS : REG0=XMM_N():w:dq:i16 REG1=XMM_B():r:dq:i16 IMM0:r:b # NDD 21676 } 21677 { 21678 ICLASS : VPSRAD 21679 EXCEPTIONS: avx-type-7 21680 CPL : 3 21681 CATEGORY : AVX 21682 EXTENSION : AVX 21683 PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 21684 OPERANDS : REG0=XMM_N():w:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b # NDD 21685 } 21686 { 21687 ICLASS : VPSRLW 21688 EXCEPTIONS: avx-type-7 21689 CPL : 3 21690 CATEGORY : AVX 21691 EXTENSION : AVX 21692 PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 21693 OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD 21694 } 21695 { 21696 ICLASS : VPSRLD 21697 EXCEPTIONS: avx-type-7 21698 CPL : 3 21699 CATEGORY : AVX 21700 EXTENSION : AVX 21701 PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 21702 OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b # NDD 21703 } 21704 { 21705 ICLASS : VPSRLQ 21706 EXCEPTIONS: avx-type-7 21707 CPL : 3 21708 CATEGORY : AVX 21709 EXTENSION : AVX 21710 PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 21711 OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD 21712 } 21713 21714 21715 { 21716 ICLASS : VUCOMISD 21717 EXCEPTIONS: avx-type-3 21718 CPL : 3 21719 CATEGORY : AVX 21720 EXTENSION : AVX 21721 ATTRIBUTES : simd_scalar MXCSR 21722 21723 FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] 21724 21725 PATTERN : VV1 0x2E V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21726 OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:q:f64 21727 21728 PATTERN : VV1 0x2E V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21729 OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:q:f64 21730 } 21731 21732 { 21733 ICLASS : VUCOMISS 21734 EXCEPTIONS: avx-type-3 21735 CPL : 3 21736 CATEGORY : AVX 21737 EXTENSION : AVX 21738 ATTRIBUTES : simd_scalar MXCSR 21739 21740 FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] 21741 21742 PATTERN : VV1 0x2E VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21743 OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:d:f32 21744 21745 PATTERN : VV1 0x2E VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21746 OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:d:f32 21747 } 21748 21749 ############################################### 21750 21751 21752 { 21753 ICLASS : VUNPCKLPD 21754 EXCEPTIONS: avx-type-4 21755 CPL : 3 21756 CATEGORY : AVX 21757 EXTENSION : AVX 21758 PATTERN : VV1 0x14 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21759 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 21760 21761 PATTERN : VV1 0x14 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21762 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 21763 21764 PATTERN : VV1 0x14 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21765 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 21766 21767 PATTERN : VV1 0x14 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21768 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 21769 } 21770 21771 21772 { 21773 ICLASS : VUNPCKLPS 21774 EXCEPTIONS: avx-type-4 21775 CPL : 3 21776 CATEGORY : AVX 21777 EXTENSION : AVX 21778 PATTERN : VV1 0x14 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21779 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 21780 21781 PATTERN : VV1 0x14 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21782 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 21783 21784 PATTERN : VV1 0x14 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21785 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 21786 21787 PATTERN : VV1 0x14 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21788 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 21789 } 21790 21791 21792 21793 21794 { 21795 ICLASS : VXORPD 21796 EXCEPTIONS: avx-type-4 21797 CPL : 3 21798 CATEGORY : LOGICAL_FP 21799 EXTENSION : AVX 21800 PATTERN : VV1 0x57 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21801 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 21802 21803 PATTERN : VV1 0x57 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21804 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 21805 21806 PATTERN : VV1 0x57 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21807 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 21808 21809 PATTERN : VV1 0x57 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21810 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 21811 } 21812 21813 21814 { 21815 ICLASS : VXORPS 21816 EXCEPTIONS: avx-type-4 21817 CPL : 3 21818 CATEGORY : LOGICAL_FP 21819 EXTENSION : AVX 21820 PATTERN : VV1 0x57 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21821 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 21822 21823 PATTERN : VV1 0x57 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21824 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 21825 21826 PATTERN : VV1 0x57 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21827 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 21828 21829 PATTERN : VV1 0x57 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21830 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 21831 } 21832 21833 21834 ############################################################################ 21835 21836 { 21837 ICLASS : VMOVSS 21838 EXCEPTIONS: avx-type-5 21839 CPL : 3 21840 CATEGORY : DATAXFER 21841 EXTENSION : AVX 21842 ATTRIBUTES : simd_scalar 21843 21844 # NOTE: REG1 is ignored!!! 21845 PATTERN : VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() 21846 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 21847 21848 PATTERN : VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21849 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 21850 IFORM : VMOVSS_XMMdq_XMMdq_XMMd_10 21851 21852 PATTERN : VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() 21853 OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:d:f32 21854 21855 PATTERN : VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21856 OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_R():r:d:f32 21857 IFORM : VMOVSS_XMMdq_XMMdq_XMMd_11 21858 } 21859 ############################################################################ 21860 { 21861 ICLASS : VMOVSD 21862 EXCEPTIONS: avx-type-5 21863 CPL : 3 21864 CATEGORY : DATAXFER 21865 EXTENSION : AVX 21866 ATTRIBUTES : simd_scalar 21867 21868 # NOTE: REG1 is ignored!!! 21869 PATTERN : VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() 21870 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 21871 21872 PATTERN : VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21873 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 21874 IFORM : VMOVSD_XMMdq_XMMdq_XMMq_10 21875 21876 PATTERN : VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() 21877 OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64 21878 21879 PATTERN : VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21880 OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_R():r:q:f64 21881 IFORM : VMOVSD_XMMdq_XMMdq_XMMq_11 21882 } 21883 ############################################################################ 21884 { 21885 ICLASS : VMOVUPD 21886 EXCEPTIONS: avx-type-4M 21887 CPL : 3 21888 CATEGORY : DATAXFER 21889 EXTENSION : AVX 21890 21891 PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21892 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 21893 21894 PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21895 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 21896 IFORM : VMOVUPD_XMMdq_XMMdq_10 21897 21898 PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21899 OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 21900 21901 PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21902 OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 21903 IFORM : VMOVUPD_XMMdq_XMMdq_11 21904 21905 # 256b versions 21906 21907 PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21908 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 21909 21910 PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21911 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 21912 IFORM : VMOVUPD_YMMqq_YMMqq_10 21913 21914 PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21915 OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 21916 21917 PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21918 OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64 21919 IFORM : VMOVUPD_YMMqq_YMMqq_11 21920 } 21921 21922 ############################################################################ 21923 { 21924 ICLASS : VMOVUPS 21925 EXCEPTIONS: avx-type-4M 21926 CPL : 3 21927 CATEGORY : DATAXFER 21928 EXTENSION : AVX 21929 21930 PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21931 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 21932 21933 PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21934 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 21935 IFORM : VMOVUPS_XMMdq_XMMdq_10 21936 21937 PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21938 OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 21939 21940 PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21941 OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 21942 IFORM : VMOVUPS_XMMdq_XMMdq_11 21943 21944 # 256b versions 21945 21946 PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21947 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 21948 21949 PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21950 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 21951 IFORM : VMOVUPS_YMMqq_YMMqq_10 21952 21953 PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21954 OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 21955 21956 PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 21957 OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32 21958 IFORM : VMOVUPS_YMMqq_YMMqq_11 21959 } 21960 21961 21962 ############################################################################ 21963 { 21964 ICLASS : VMOVLPD 21965 EXCEPTIONS: avx-type-5 21966 CPL : 3 21967 CATEGORY : DATAXFER 21968 EXTENSION : AVX 21969 COMMENT: 3op version uses high part of XMM_N 21970 PATTERN : VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21971 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 21972 21973 PATTERN : VV1 0x13 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21974 OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64 21975 } 21976 21977 { 21978 ICLASS : VMOVLPS 21979 EXCEPTIONS: avx-type-5 21980 CPL : 3 21981 CATEGORY : DATAXFER 21982 EXTENSION : AVX 21983 21984 COMMENT: 3op version uses high part of XMM_N 21985 PATTERN : VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21986 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f32 21987 21988 PATTERN : VV1 0x13 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 21989 OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:q:f32 21990 } 21991 21992 { 21993 ICLASS : VMOVHPD 21994 EXCEPTIONS: avx-type-5 21995 CPL : 3 21996 CATEGORY : DATAXFER 21997 EXTENSION : AVX 21998 COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0 21999 PATTERN : VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22000 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 22001 22002 PATTERN : VV1 0x17 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22003 OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:dq:f64 22004 } 22005 22006 { 22007 ICLASS : VMOVHPS 22008 EXCEPTIONS: avx-type-5 22009 CPL : 3 22010 CATEGORY : DATAXFER 22011 EXTENSION : AVX 22012 22013 COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0 22014 PATTERN : VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22015 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 MEM0:r:q:f32 22016 22017 PATTERN : VV1 0x17 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22018 OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:dq:f32 22019 } 22020 ############################################################################ 22021 22022 { 22023 ICLASS : VMOVMSKPD 22024 EXCEPTIONS: avx-type-7 22025 CPL : 3 22026 CATEGORY : DATAXFER 22027 EXTENSION : AVX 22028 PATTERN : VV1 0x50 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22029 OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f64 22030 22031 # 256b versions 22032 22033 PATTERN : VV1 0x50 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22034 OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f64 22035 } 22036 22037 { 22038 ICLASS : VMOVMSKPS 22039 EXCEPTIONS: avx-type-7 22040 CPL : 3 22041 CATEGORY : DATAXFER 22042 EXTENSION : AVX 22043 PATTERN : VV1 0x50 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22044 OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f32 22045 22046 # 256b versions 22047 22048 PATTERN : VV1 0x50 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22049 OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f32 22050 } 22051 22052 ############################################################################ 22053 { 22054 ICLASS : VPMOVMSKB 22055 EXCEPTIONS: avx-type-7 22056 CPL : 3 22057 CATEGORY : AVX 22058 EXTENSION : AVX 22059 PATTERN : VV1 0xD7 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22060 OPERANDS : REG0=GPR32_R():w:d:u32 REG1=XMM_B():r:dq:i8 22061 } 22062 22063 ############################################################################ 22064 22065 ############################################################################ 22066 # SX versions 22067 ############################################################################ 22068 22069 { 22070 ICLASS : VPMOVSXBW 22071 EXCEPTIONS: avx-type-5 22072 CPL : 3 22073 CATEGORY : AVX 22074 EXTENSION : AVX 22075 PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22076 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8 22077 PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22078 OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8 22079 } 22080 22081 ############################################################################ 22082 { 22083 ICLASS : VPMOVSXBD 22084 EXCEPTIONS: avx-type-5 22085 CPL : 3 22086 CATEGORY : AVX 22087 EXTENSION : AVX 22088 PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22089 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8 22090 PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22091 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8 22092 } 22093 ############################################################################ 22094 { 22095 ICLASS : VPMOVSXBQ 22096 EXCEPTIONS: avx-type-5 22097 CPL : 3 22098 CATEGORY : AVX 22099 EXTENSION : AVX 22100 PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22101 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8 22102 PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22103 OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8 22104 } 22105 ############################################################################ 22106 { 22107 ICLASS : VPMOVSXWD 22108 EXCEPTIONS: avx-type-5 22109 CPL : 3 22110 CATEGORY : AVX 22111 EXTENSION : AVX 22112 PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22113 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16 22114 PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22115 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16 22116 } 22117 ############################################################################ 22118 { 22119 ICLASS : VPMOVSXWQ 22120 EXCEPTIONS: avx-type-5 22121 CPL : 3 22122 CATEGORY : AVX 22123 EXTENSION : AVX 22124 PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22125 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16 22126 PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22127 OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16 22128 } 22129 ############################################################################ 22130 { 22131 ICLASS : VPMOVSXDQ 22132 EXCEPTIONS: avx-type-5 22133 CPL : 3 22134 CATEGORY : AVX 22135 EXTENSION : AVX 22136 PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22137 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32 22138 PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22139 OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32 22140 } 22141 22142 22143 22144 22145 22146 ############################################################################ 22147 # ZX versions 22148 ############################################################################ 22149 22150 { 22151 ICLASS : VPMOVZXBW 22152 EXCEPTIONS: avx-type-5 22153 CPL : 3 22154 CATEGORY : AVX 22155 EXTENSION : AVX 22156 PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22157 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8 22158 PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22159 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8 22160 } 22161 22162 ############################################################################ 22163 { 22164 ICLASS : VPMOVZXBD 22165 EXCEPTIONS: avx-type-5 22166 CPL : 3 22167 CATEGORY : AVX 22168 EXTENSION : AVX 22169 PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22170 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8 22171 PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22172 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8 22173 } 22174 ############################################################################ 22175 { 22176 ICLASS : VPMOVZXBQ 22177 EXCEPTIONS: avx-type-5 22178 CPL : 3 22179 CATEGORY : AVX 22180 EXTENSION : AVX 22181 PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22182 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8 22183 PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22184 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8 22185 } 22186 ############################################################################ 22187 { 22188 ICLASS : VPMOVZXWD 22189 EXCEPTIONS: avx-type-5 22190 CPL : 3 22191 CATEGORY : AVX 22192 EXTENSION : AVX 22193 PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22194 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16 22195 PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22196 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16 22197 } 22198 ############################################################################ 22199 { 22200 ICLASS : VPMOVZXWQ 22201 EXCEPTIONS: avx-type-5 22202 CPL : 3 22203 CATEGORY : AVX 22204 EXTENSION : AVX 22205 PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22206 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16 22207 PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22208 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16 22209 } 22210 ############################################################################ 22211 { 22212 ICLASS : VPMOVZXDQ 22213 EXCEPTIONS: avx-type-5 22214 CPL : 3 22215 CATEGORY : AVX 22216 EXTENSION : AVX 22217 PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22218 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32 22219 PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22220 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32 22221 } 22222 22223 22224 22225 ############################################################################ 22226 ############################################################################ 22227 { 22228 ICLASS : VPEXTRB 22229 EXCEPTIONS: avx-type-5 22230 CPL : 3 22231 CATEGORY : AVX 22232 EXTENSION : AVX 22233 COMMENT: WIG 22234 PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22235 OPERANDS : MEM0:w:b REG0=XMM_R():r:dq:u8 IMM0:r:b 22236 22237 PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22238 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u8 IMM0:r:b 22239 } 22240 ############################################################################ 22241 { 22242 ICLASS : VPEXTRW 22243 EXCEPTIONS: avx-type-5 22244 CPL : 3 22245 CATEGORY : AVX 22246 EXTENSION : AVX 22247 COMMENT: WIG 22248 22249 PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22250 OPERANDS : MEM0:w:w REG0=XMM_R():r:dq:u16 IMM0:r:b 22251 22252 PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22253 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u16 IMM0:r:b 22254 IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_15 22255 22256 # special C5 reg-only versions from SSE2: 22257 22258 PATTERN : VV1 0xC5 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22259 OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:u16 IMM0:r:b 22260 IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_C5 22261 } 22262 ############################################################################ 22263 { 22264 ICLASS : VPEXTRQ 22265 EXCEPTIONS: avx-type-5 22266 CPL : 3 22267 CATEGORY : AVX 22268 EXTENSION : AVX 22269 PATTERN : VV1 0x16 VL128 V66 V0F3A rexw_prefix mode64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22270 OPERANDS : MEM0:w:q REG0=XMM_R():r:dq:u64 IMM0:r:b 22271 PATTERN : VV1 0x16 VL128 V66 V0F3A rexw_prefix mode64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22272 OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq:u64 IMM0:r:b 22273 } 22274 ############################################################################ 22275 { 22276 ICLASS : VPEXTRD 22277 EXCEPTIONS: avx-type-5 22278 CPL : 3 22279 CATEGORY : AVX 22280 EXTENSION : AVX 22281 PATTERN : VV1 0x16 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22282 OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b 22283 PATTERN : VV1 0x16 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22284 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b 22285 } 22286 ############################################################################ 22287 22288 22289 22290 22291 22292 22293 { 22294 ICLASS : VPINSRB 22295 EXCEPTIONS: avx-type-5 22296 CPL : 3 22297 CATEGORY : AVX 22298 EXTENSION : AVX 22299 COMMENT: WIG 22300 PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22301 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:b:u8 IMM0:r:b 22302 PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22303 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b 22304 } 22305 22306 { 22307 ICLASS : VPINSRW 22308 EXCEPTIONS: avx-type-5 22309 CPL : 3 22310 CATEGORY : AVX 22311 EXTENSION : AVX 22312 COMMENT : WIG 22313 PATTERN : VV1 0xC4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22314 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:w:u16 IMM0:r:b 22315 22316 PATTERN : VV1 0xC4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22317 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b 22318 } 22319 22320 { 22321 ICLASS : VPINSRD 22322 EXCEPTIONS: avx-type-5 22323 CPL : 3 22324 CATEGORY : AVX 22325 EXTENSION : AVX 22326 PATTERN : VV1 0x22 VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22327 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b 22328 PATTERN : VV1 0x22 VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22329 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b 22330 } 22331 { 22332 ICLASS : VPINSRQ 22333 EXCEPTIONS: avx-type-5 22334 CPL : 3 22335 CATEGORY : AVX 22336 EXTENSION : AVX 22337 PATTERN : VV1 0x22 VL128 V66 V0F3A rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22338 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:q:u64 IMM0:r:b 22339 PATTERN : VV1 0x22 VL128 V66 V0F3A rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22340 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b 22341 } 22342 22343 ############################################################################ 22344 22345 22346 22347 22348 22349 { 22350 ICLASS : VPCMPESTRI 22351 EXCEPTIONS: avx-type-4 22352 CPL : 3 22353 CATEGORY : STTNI 22354 EXTENSION : AVX 22355 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 22356 22357 # outside of 64b mode, vex.w is ignored for this instr 22358 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22359 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP 22360 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22361 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP 22362 22363 # in 64b mode, vex.w changes the behavior for GPRs 22364 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22365 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP 22366 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22367 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP 22368 22369 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22370 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP 22371 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22372 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP 22373 } 22374 { 22375 ICLASS : VPCMPISTRI 22376 EXCEPTIONS: avx-type-4 22377 CPL : 3 22378 CATEGORY : STTNI 22379 EXTENSION : AVX 22380 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 22381 22382 # outside of 64b mode, vex.w is ignored for this instr 22383 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22384 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP 22385 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22386 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP 22387 22388 # in 64b mode, vex.w changes the behavior for GPRs 22389 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22390 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP 22391 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22392 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP 22393 22394 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22395 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP 22396 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22397 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP 22398 } 22399 22400 { 22401 ICLASS : VPCMPESTRM 22402 EXCEPTIONS: avx-type-4 22403 CPL : 3 22404 CATEGORY : STTNI 22405 EXTENSION : AVX 22406 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 22407 22408 # outside of 64b mode, vex.w is ignored for this instr 22409 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22410 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP 22411 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22412 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP 22413 22414 # in 64b mode, vex.w changes the behavior for GPRs 22415 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22416 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP 22417 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22418 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP 22419 22420 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22421 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP 22422 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22423 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP 22424 } 22425 22426 { 22427 ICLASS : VPCMPISTRM 22428 EXCEPTIONS: avx-type-4 22429 CPL : 3 22430 CATEGORY : STTNI 22431 EXTENSION : AVX 22432 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 22433 PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22434 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP 22435 PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22436 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP 22437 } 22438 #################################################################################### 22439 22440 22441 22442 #################################################################################### 22443 { 22444 ICLASS : VMASKMOVDQU 22445 EXCEPTIONS: avx-type-4 22446 CPL : 3 22447 CATEGORY : AVX 22448 EXTENSION : AVX 22449 ATTRIBUTES : maskop fixed_base0 NOTSX 22450 PATTERN : VV1 0xF7 V0F V66 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22451 OPERANDS : REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 MEM0:w:SUPP:dq:u8 BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP 22452 } 22453 22454 #################################################################################### 22455 { 22456 ICLASS : VLDMXCSR 22457 EXCEPTIONS: avx-type-5L 22458 CPL : 3 22459 CATEGORY : AVX 22460 EXTENSION : AVX 22461 ATTRIBUTES: MXCSR 22462 PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM() 22463 OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP 22464 } 22465 { 22466 ICLASS : VSTMXCSR 22467 EXCEPTIONS: avx-type-5 22468 CPL : 3 22469 CATEGORY : AVX 22470 EXTENSION : AVX 22471 ATTRIBUTES: MXCSR_RD 22472 PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM() 22473 OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP 22474 } 22475 ####################################################################################### 22476 22477 { 22478 ICLASS : VPBLENDVB 22479 EXCEPTIONS: avx-type-4 22480 CPL : 3 22481 CATEGORY : AVX 22482 EXTENSION : AVX 22483 22484 # W0 (modrm.rm memory op 2nd to last) 22485 PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 22486 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 REG2=XMM_SE():r:dq:i8 22487 22488 PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 22489 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 REG3=XMM_SE():r:dq:i8 22490 } 22491 22492 { 22493 ICLASS : VBLENDVPD 22494 EXCEPTIONS: avx-type-4 22495 CPL : 3 22496 CATEGORY : AVX 22497 EXTENSION : AVX 22498 22499 # W0 (modrm.rm memory op 2nd to last) 22500 PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 22501 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:u64 22502 22503 PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 22504 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:u64 22505 22506 PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 22507 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:u64 22508 22509 PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 22510 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:u64 22511 22512 } 22513 22514 { 22515 ICLASS : VBLENDVPS 22516 EXCEPTIONS: avx-type-4 22517 CPL : 3 22518 CATEGORY : AVX 22519 EXTENSION : AVX 22520 22521 # W0 (modrm.rm memory op 2nd to last) 22522 PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 22523 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:u32 22524 22525 PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 22526 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:u32 22527 22528 PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 22529 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:u32 22530 22531 PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 22532 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:u32 22533 22534 22535 } 22536 22537 ####################################################################################### 22538 22539 22540 22541 { 22542 ICLASS : VMOVNTDQA 22543 EXCEPTIONS: avx-type-1 22544 CPL : 3 22545 CATEGORY : DATAXFER 22546 EXTENSION : AVX 22547 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX 22548 22549 PATTERN : VV1 0x2A V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22550 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 22551 } 22552 22553 22554 22555 22556 22557 { 22558 ICLASS : VMOVNTDQ 22559 EXCEPTIONS: avx-type-1 22560 CPL : 3 22561 CATEGORY : DATAXFER 22562 EXTENSION : AVX 22563 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX 22564 PATTERN : VV1 0xE7 V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22565 OPERANDS : MEM0:w:dq:i32 REG0=XMM_R():r:dq:i32 22566 22567 } 22568 { 22569 ICLASS : VMOVNTPD 22570 EXCEPTIONS: avx-type-1 22571 CPL : 3 22572 CATEGORY : DATAXFER 22573 EXTENSION : AVX 22574 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX 22575 PATTERN : VV1 0x2B V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22576 OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 22577 22578 } 22579 { 22580 ICLASS : VMOVNTPS 22581 EXCEPTIONS: avx-type-1 22582 CPL : 3 22583 CATEGORY : DATAXFER 22584 EXTENSION : AVX 22585 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX 22586 PATTERN : VV1 0x2B VNP V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22587 OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 22588 22589 } 22590 22591 22592 22593 ###FILE: ../xed/datafiles/avx/avx-movnt-store.txt 22594 22595 #BEGIN_LEGAL 22596 # 22597 #Copyright (c) 2016 Intel Corporation 22598 # 22599 # Licensed under the Apache License, Version 2.0 (the "License"); 22600 # you may not use this file except in compliance with the License. 22601 # You may obtain a copy of the License at 22602 # 22603 # http://www.apache.org/licenses/LICENSE-2.0 22604 # 22605 # Unless required by applicable law or agreed to in writing, software 22606 # distributed under the License is distributed on an "AS IS" BASIS, 22607 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22608 # See the License for the specific language governing permissions and 22609 # limitations under the License. 22610 # 22611 #END_LEGAL 22612 AVX_INSTRUCTIONS():: 22613 22614 22615 { 22616 ICLASS : VMOVNTDQ 22617 EXCEPTIONS: avx-type-1 22618 CPL : 3 22619 CATEGORY : DATAXFER 22620 EXTENSION : AVX 22621 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX 22622 PATTERN : VV1 0xE7 V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22623 OPERANDS : MEM0:w:qq:i32 REG0=YMM_R():r:qq:i32 22624 22625 } 22626 { 22627 ICLASS : VMOVNTPD 22628 EXCEPTIONS: avx-type-1 22629 CPL : 3 22630 CATEGORY : DATAXFER 22631 EXTENSION : AVX 22632 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX 22633 PATTERN : VV1 0x2B V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22634 OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 22635 22636 } 22637 { 22638 ICLASS : VMOVNTPS 22639 EXCEPTIONS: avx-type-1 22640 CPL : 3 22641 CATEGORY : DATAXFER 22642 EXTENSION : AVX 22643 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX 22644 PATTERN : VV1 0x2B VNP V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22645 OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 22646 22647 } 22648 22649 22650 22651 ###FILE: ../xed/datafiles/avx/avx-aes-isa.txt 22652 22653 #BEGIN_LEGAL 22654 # 22655 #Copyright (c) 2016 Intel Corporation 22656 # 22657 # Licensed under the Apache License, Version 2.0 (the "License"); 22658 # you may not use this file except in compliance with the License. 22659 # You may obtain a copy of the License at 22660 # 22661 # http://www.apache.org/licenses/LICENSE-2.0 22662 # 22663 # Unless required by applicable law or agreed to in writing, software 22664 # distributed under the License is distributed on an "AS IS" BASIS, 22665 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22666 # See the License for the specific language governing permissions and 22667 # limitations under the License. 22668 # 22669 #END_LEGAL 22670 AVX_INSTRUCTIONS():: 22671 22672 { 22673 ICLASS : VAESKEYGENASSIST 22674 EXCEPTIONS: avx-type-4 22675 CPL : 3 22676 CATEGORY : AES 22677 EXTENSION : AVXAES 22678 PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 22679 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b 22680 PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 22681 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b 22682 } 22683 { 22684 ICLASS : VAESENC 22685 EXCEPTIONS: avx-type-4 22686 CPL : 3 22687 CATEGORY : AES 22688 EXTENSION : AVXAES 22689 PATTERN : VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 22690 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 22691 PATTERN : VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 22692 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 22693 } 22694 { 22695 ICLASS : VAESENCLAST 22696 EXCEPTIONS: avx-type-4 22697 CPL : 3 22698 CATEGORY : AES 22699 EXTENSION : AVXAES 22700 PATTERN : VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 22701 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 22702 PATTERN : VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 22703 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 22704 } 22705 { 22706 ICLASS : VAESDEC 22707 EXCEPTIONS: avx-type-4 22708 CPL : 3 22709 CATEGORY : AES 22710 EXTENSION : AVXAES 22711 PATTERN : VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 22712 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 22713 PATTERN : VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 22714 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 22715 } 22716 { 22717 ICLASS : VAESDECLAST 22718 EXCEPTIONS: avx-type-4 22719 CPL : 3 22720 CATEGORY : AES 22721 EXTENSION : AVXAES 22722 PATTERN : VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 22723 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 22724 PATTERN : VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 22725 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 22726 } 22727 { 22728 ICLASS : VAESIMC 22729 EXCEPTIONS: avx-type-4 22730 CPL : 3 22731 CATEGORY : AES 22732 EXTENSION : AVXAES 22733 PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 22734 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 22735 PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 22736 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 22737 } 22738 22739 22740 22741 ###FILE: ../xed/datafiles/avx/avx-pclmul-isa.txt 22742 22743 #BEGIN_LEGAL 22744 # 22745 #Copyright (c) 2016 Intel Corporation 22746 # 22747 # Licensed under the Apache License, Version 2.0 (the "License"); 22748 # you may not use this file except in compliance with the License. 22749 # You may obtain a copy of the License at 22750 # 22751 # http://www.apache.org/licenses/LICENSE-2.0 22752 # 22753 # Unless required by applicable law or agreed to in writing, software 22754 # distributed under the License is distributed on an "AS IS" BASIS, 22755 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22756 # See the License for the specific language governing permissions and 22757 # limitations under the License. 22758 # 22759 #END_LEGAL 22760 AVX_INSTRUCTIONS():: 22761 { 22762 ICLASS : VPCLMULQDQ 22763 EXCEPTIONS: avx-type-4 22764 CPL : 3 22765 CATEGORY : AVX 22766 EXTENSION : AVX 22767 PATTERN : VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 UIMM8() 22768 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b 22769 PATTERN : VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 UIMM8() 22770 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b 22771 } 22772 22773 22774 ###FILE: ../xed/datafiles/ivbavx/fp16-isa.txt 22775 22776 #BEGIN_LEGAL 22777 # 22778 #Copyright (c) 2016 Intel Corporation 22779 # 22780 # Licensed under the Apache License, Version 2.0 (the "License"); 22781 # you may not use this file except in compliance with the License. 22782 # You may obtain a copy of the License at 22783 # 22784 # http://www.apache.org/licenses/LICENSE-2.0 22785 # 22786 # Unless required by applicable law or agreed to in writing, software 22787 # distributed under the License is distributed on an "AS IS" BASIS, 22788 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22789 # See the License for the specific language governing permissions and 22790 # limitations under the License. 22791 # 22792 #END_LEGAL 22793 AVX_INSTRUCTIONS():: 22794 { 22795 ICLASS : VCVTPH2PS 22796 COMMENT : UPCONVERT -- NO IMMEDIATE 22797 CPL : 3 22798 CATEGORY : CONVERT 22799 EXTENSION : F16C 22800 ATTRIBUTES : MXCSR 22801 EXCEPTIONS: avx-type-11 22802 # 128b form 22803 22804 PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 22805 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:q:f16 22806 22807 PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 22808 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:q:f16 22809 22810 22811 # 256b form 22812 22813 PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 22814 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:dq:f16 22815 22816 PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 22817 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f16 22818 } 22819 22820 22821 { 22822 ICLASS : VCVTPS2PH 22823 COMMENT : DOWNCONVERT -- HAS IMMEDIATE 22824 CPL : 3 22825 CATEGORY : CONVERT 22826 EXTENSION : F16C 22827 ATTRIBUTES : MXCSR 22828 EXCEPTIONS: avx-type-11 22829 # 128b imm8 form 22830 22831 PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 22832 OPERANDS : MEM0:w:q:f16 REG0=XMM_R():r:dq:f32 IMM0:r:b 22833 22834 PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 22835 OPERANDS : REG0=XMM_B():w:q:f16 REG1=XMM_R():r:dq:f32 IMM0:r:b 22836 22837 # 256b imm8 form 22838 22839 PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 22840 OPERANDS : MEM0:w:dq:f16 REG0=YMM_R():r:qq:f32 IMM0:r:b 22841 22842 PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 22843 OPERANDS : REG0=XMM_B():w:dq:f16 REG1=YMM_R():r:qq:f32 IMM0:r:b 22844 22845 } 22846 22847 22848 22849 ###FILE: ../xed/datafiles/avxhsw/gather-isa.txt 22850 22851 #BEGIN_LEGAL 22852 # 22853 #Copyright (c) 2016 Intel Corporation 22854 # 22855 # Licensed under the Apache License, Version 2.0 (the "License"); 22856 # you may not use this file except in compliance with the License. 22857 # You may obtain a copy of the License at 22858 # 22859 # http://www.apache.org/licenses/LICENSE-2.0 22860 # 22861 # Unless required by applicable law or agreed to in writing, software 22862 # distributed under the License is distributed on an "AS IS" BASIS, 22863 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22864 # See the License for the specific language governing permissions and 22865 # limitations under the License. 22866 # 22867 #END_LEGAL 22868 AVX_INSTRUCTIONS():: 22869 22870 22871 # DEST in MODRM.REG 22872 # BASE in SIB.base 22873 # INDEX in SIB.index 22874 # MASK in VEX.VVVV -- NOTE mask is a signed integer!!! 22875 22876 # VL = 128 VL = 256 22877 # dest/mask index memsz dest/mask index memsz 22878 # qps/qd xmm xmm 2*32=64b xmm* ymm* 4*32=128b 22879 # dps/dd xmm xmm 4*32=128b ymm ymm 8*32=256b 22880 # dpd/dq xmm xmm 2*64=128b ymm* xmm* 4*64=256b 22881 # qpd/qq xmm xmm 2*64=128b ymm ymm 4*64=256b 22882 22883 22884 22885 { 22886 ICLASS : VGATHERDPD 22887 CPL : 3 22888 CATEGORY : AVX2GATHER 22889 EXTENSION : AVX2GATHER 22890 ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED 22891 EXCEPTIONS: avx-type-12 22892 22893 22894 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 22895 PATTERN : VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 22896 OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:qq:f64 REG1=YMM_N():rw:qq:i64 22897 IFORM: VGATHERDPD_YMMf64_MEMqq_YMMi64_VL256 22898 22899 # VL = 128 - index, mask and dest are all XMMs 22900 PATTERN : VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 22901 OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:dq:f64 REG1=XMM_N():rw:dq:i64 22902 IFORM: VGATHERDPD_XMMf64_MEMdq_XMMi64_VL128 22903 22904 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 22905 } 22906 { 22907 ICLASS : VGATHERDPS 22908 CPL : 3 22909 CATEGORY : AVX2GATHER 22910 EXTENSION : AVX2GATHER 22911 ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED 22912 EXCEPTIONS: avx-type-12 22913 22914 22915 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 22916 PATTERN : VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 22917 OPERANDS : REG0=YMM_R():crw:qq:f32 MEM0:r:qq:f32 REG1=YMM_N():rw:qq:i32 22918 IFORM: VGATHERDPS_YMMf32_MEMqq_YMMi32_VL256 22919 22920 # VL = 128 - index, mask and dest are all XMMs 22921 PATTERN : VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 22922 OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:dq:f32 REG1=XMM_N():rw:dq:i32 22923 IFORM: VGATHERDPS_XMMf32_MEMdq_XMMi32_VL128 22924 22925 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 22926 } 22927 { 22928 ICLASS : VGATHERQPD 22929 CPL : 3 22930 CATEGORY : AVX2GATHER 22931 EXTENSION : AVX2GATHER 22932 ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED 22933 EXCEPTIONS: avx-type-12 22934 22935 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 22936 PATTERN : VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 22937 OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:qq:f64 REG1=YMM_N():rw:qq:i64 22938 IFORM: VGATHERQPD_YMMf64_MEMqq_YMMi64_VL256 22939 22940 # VL = 128 - index, mask and dest are all XMMs 22941 PATTERN : VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 22942 OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:dq:f64 REG1=XMM_N():rw:dq:i64 22943 IFORM: VGATHERQPD_XMMf64_MEMdq_XMMi64_VL128 22944 22945 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 22946 } 22947 { 22948 ICLASS : VGATHERQPS 22949 CPL : 3 22950 CATEGORY : AVX2GATHER 22951 EXTENSION : AVX2GATHER 22952 ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED 22953 EXCEPTIONS: avx-type-12 22954 22955 22956 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 22957 PATTERN : VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 22958 OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:dq:f32 REG1=XMM_N():rw:dq:i32 22959 IFORM: VGATHERQPS_XMMf32_MEMdq_XMMi32_VL256 22960 22961 # VL = 128 - index, mask and dest are all XMMs 22962 PATTERN : VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 22963 OPERANDS : REG0=XMM_R():crw:q:f32 MEM0:r:q:f32 REG1=XMM_N():rw:q:i32 22964 IFORM: VGATHERQPS_XMMf32_MEMq_XMMi32_VL128 22965 22966 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 22967 } 22968 22969 { 22970 ICLASS : VPGATHERDQ 22971 CPL : 3 22972 CATEGORY : AVX2GATHER 22973 EXTENSION : AVX2GATHER 22974 ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED 22975 EXCEPTIONS: avx-type-12 22976 22977 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 22978 PATTERN : VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 22979 OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:qq:u64 REG1=YMM_N():rw:qq:i64 22980 IFORM: VPGATHERDQ_YMMu64_MEMqq_YMMi64_VL256 22981 22982 # VL = 128 - index, mask and dest are all XMMs 22983 PATTERN : VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 22984 OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():rw:dq:i64 22985 IFORM: VPGATHERDQ_XMMu64_MEMdq_XMMi64_VL128 22986 22987 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 22988 } 22989 { 22990 ICLASS : VPGATHERDD 22991 CPL : 3 22992 CATEGORY : AVX2GATHER 22993 EXTENSION : AVX2GATHER 22994 ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED 22995 EXCEPTIONS: avx-type-12 22996 22997 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 22998 PATTERN : VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 22999 OPERANDS : REG0=YMM_R():crw:qq:u32 MEM0:r:qq:u32 REG1=YMM_N():rw:qq:i32 23000 IFORM: VPGATHERDD_YMMu32_MEMqq_YMMi32_VL256 23001 23002 # VL = 128 - index, mask and dest are all XMMs 23003 PATTERN : VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 23004 OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():rw:dq:i32 23005 IFORM: VPGATHERDD_XMMu32_MEMdq_XMMi32_VL128 23006 23007 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 23008 } 23009 { 23010 ICLASS : VPGATHERQQ 23011 CPL : 3 23012 CATEGORY : AVX2GATHER 23013 EXTENSION : AVX2GATHER 23014 ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED 23015 EXCEPTIONS: avx-type-12 23016 23017 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 23018 PATTERN : VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 23019 OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:qq:u64 REG1=YMM_N():rw:qq:i64 23020 IFORM: VPGATHERQQ_YMMu64_MEMqq_YMMi64_VL256 23021 23022 # VL = 128 - index, mask and dest are all XMMs 23023 PATTERN : VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 23024 OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():rw:dq:i64 23025 IFORM: VPGATHERQQ_XMMu64_MEMdq_XMMi64_VL128 23026 23027 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 23028 } 23029 { 23030 ICLASS : VPGATHERQD 23031 CPL : 3 23032 CATEGORY : AVX2GATHER 23033 EXTENSION : AVX2GATHER 23034 ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED 23035 EXCEPTIONS: avx-type-12 23036 23037 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 23038 PATTERN : VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 23039 OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():rw:dq:i32 23040 IFORM: VPGATHERQD_XMMu32_MEMdq_XMMi32_VL256 23041 23042 # VL = 128 - index, mask and dest are all XMMs 23043 PATTERN : VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 23044 OPERANDS : REG0=XMM_R():crw:q:u32 MEM0:r:q:u32 REG1=XMM_N():rw:q:i32 23045 IFORM: VPGATHERQD_XMMu32_MEMq_XMMi32_VL128 23046 23047 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 23048 } 23049 23050 23051 23052 ###FILE: ../xed/datafiles/avxhsw/hsw-int256-isa.txt 23053 23054 #BEGIN_LEGAL 23055 # 23056 #Copyright (c) 2016 Intel Corporation 23057 # 23058 # Licensed under the Apache License, Version 2.0 (the "License"); 23059 # you may not use this file except in compliance with the License. 23060 # You may obtain a copy of the License at 23061 # 23062 # http://www.apache.org/licenses/LICENSE-2.0 23063 # 23064 # Unless required by applicable law or agreed to in writing, software 23065 # distributed under the License is distributed on an "AS IS" BASIS, 23066 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23067 # See the License for the specific language governing permissions and 23068 # limitations under the License. 23069 # 23070 #END_LEGAL 23071 AVX_INSTRUCTIONS():: 23072 23073 23074 { 23075 ICLASS : VPABSB 23076 CPL : 3 23077 CATEGORY : AVX2 23078 EXTENSION : AVX2 23079 EXCEPTIONS: avx-type-4 23080 PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23081 OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:qq:i8 23082 23083 PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23084 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_B():r:qq:i8 23085 } 23086 { 23087 ICLASS : VPABSW 23088 CPL : 3 23089 CATEGORY : AVX2 23090 EXTENSION : AVX2 23091 EXCEPTIONS: avx-type-4 23092 PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23093 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:i16 23094 23095 PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23096 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:i16 23097 } 23098 { 23099 ICLASS : VPABSD 23100 CPL : 3 23101 CATEGORY : AVX2 23102 EXTENSION : AVX2 23103 EXCEPTIONS: avx-type-4 23104 PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23105 OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:i32 23106 23107 PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23108 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:i32 23109 } 23110 { 23111 ICLASS : VPHMINPOSUW 23112 CPL : 3 23113 CATEGORY : AVX2 23114 EXTENSION : AVX2 23115 EXCEPTIONS: avx-type-4 23116 PATTERN : VV1 0x41 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23117 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 23118 23119 PATTERN : VV1 0x41 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23120 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 23121 } 23122 23123 23124 23125 23126 23127 23128 23129 23130 23131 23132 { 23133 ICLASS : VPACKSSWB 23134 CPL : 3 23135 CATEGORY : AVX2 23136 EXTENSION : AVX2 23137 EXCEPTIONS: avx-type-4 23138 PATTERN : VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23139 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23140 23141 PATTERN : VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23142 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23143 } 23144 { 23145 ICLASS : VPACKSSDW 23146 CPL : 3 23147 CATEGORY : AVX2 23148 EXTENSION : AVX2 23149 EXCEPTIONS: avx-type-4 23150 PATTERN : VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23151 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23152 23153 PATTERN : VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23154 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23155 } 23156 { 23157 ICLASS : VPACKUSWB 23158 CPL : 3 23159 CATEGORY : AVX2 23160 EXTENSION : AVX2 23161 EXCEPTIONS: avx-type-4 23162 PATTERN : VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23163 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23164 23165 PATTERN : VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23166 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23167 } 23168 { 23169 ICLASS : VPACKUSDW 23170 CPL : 3 23171 CATEGORY : AVX2 23172 EXTENSION : AVX2 23173 EXCEPTIONS: avx-type-4 23174 PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23175 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23176 23177 PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23178 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23179 } 23180 23181 { 23182 ICLASS : VPSLLW 23183 CPL : 3 23184 CATEGORY : AVX2 23185 EXTENSION : AVX2 23186 EXCEPTIONS: avx-type-4 23187 PATTERN : VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23188 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 23189 23190 PATTERN : VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23191 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 23192 } 23193 { 23194 ICLASS : VPSLLD 23195 CPL : 3 23196 CATEGORY : AVX2 23197 EXTENSION : AVX2 23198 EXCEPTIONS: avx-type-4 23199 PATTERN : VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23200 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 23201 23202 PATTERN : VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23203 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 23204 } 23205 { 23206 ICLASS : VPSLLQ 23207 CPL : 3 23208 CATEGORY : AVX2 23209 EXTENSION : AVX2 23210 EXCEPTIONS: avx-type-4 23211 PATTERN : VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23212 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 23213 23214 PATTERN : VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23215 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 23216 } 23217 23218 { 23219 ICLASS : VPSRLW 23220 CPL : 3 23221 CATEGORY : AVX2 23222 EXTENSION : AVX2 23223 EXCEPTIONS: avx-type-4 23224 PATTERN : VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23225 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 23226 23227 PATTERN : VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23228 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 23229 } 23230 { 23231 ICLASS : VPSRLD 23232 CPL : 3 23233 CATEGORY : AVX2 23234 EXTENSION : AVX2 23235 EXCEPTIONS: avx-type-4 23236 PATTERN : VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23237 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 23238 23239 PATTERN : VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23240 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 23241 } 23242 { 23243 ICLASS : VPSRLQ 23244 CPL : 3 23245 CATEGORY : AVX2 23246 EXTENSION : AVX2 23247 EXCEPTIONS: avx-type-4 23248 PATTERN : VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23249 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 23250 23251 PATTERN : VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23252 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 23253 } 23254 23255 { 23256 ICLASS : VPSRAW 23257 CPL : 3 23258 CATEGORY : AVX2 23259 EXTENSION : AVX2 23260 EXCEPTIONS: avx-type-4 23261 PATTERN : VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23262 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:dq:u64 23263 23264 PATTERN : VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23265 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=XMM_B():r:q:u64 23266 } 23267 { 23268 ICLASS : VPSRAD 23269 CPL : 3 23270 CATEGORY : AVX2 23271 EXTENSION : AVX2 23272 EXCEPTIONS: avx-type-4 23273 PATTERN : VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23274 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:dq:u64 23275 23276 PATTERN : VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23277 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=XMM_B():r:q:u64 23278 } 23279 23280 23281 { 23282 ICLASS : VPADDB 23283 CPL : 3 23284 CATEGORY : AVX2 23285 EXTENSION : AVX2 23286 EXCEPTIONS: avx-type-4 23287 PATTERN : VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23288 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 23289 23290 PATTERN : VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23291 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 23292 } 23293 { 23294 ICLASS : VPADDW 23295 CPL : 3 23296 CATEGORY : AVX2 23297 EXTENSION : AVX2 23298 EXCEPTIONS: avx-type-4 23299 PATTERN : VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23300 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23301 23302 PATTERN : VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23303 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23304 } 23305 { 23306 ICLASS : VPADDD 23307 CPL : 3 23308 CATEGORY : AVX2 23309 EXTENSION : AVX2 23310 EXCEPTIONS: avx-type-4 23311 PATTERN : VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23312 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23313 23314 PATTERN : VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23315 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23316 } 23317 { 23318 ICLASS : VPADDQ 23319 CPL : 3 23320 CATEGORY : AVX2 23321 EXTENSION : AVX2 23322 EXCEPTIONS: avx-type-4 23323 PATTERN : VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23324 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 23325 23326 PATTERN : VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23327 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 23328 } 23329 23330 { 23331 ICLASS : VPADDSB 23332 CPL : 3 23333 CATEGORY : AVX2 23334 EXTENSION : AVX2 23335 EXCEPTIONS: avx-type-4 23336 PATTERN : VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23337 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 23338 23339 PATTERN : VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23340 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 23341 } 23342 { 23343 ICLASS : VPADDSW 23344 CPL : 3 23345 CATEGORY : AVX2 23346 EXTENSION : AVX2 23347 EXCEPTIONS: avx-type-4 23348 PATTERN : VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23349 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23350 23351 PATTERN : VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23352 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23353 } 23354 23355 { 23356 ICLASS : VPADDUSB 23357 CPL : 3 23358 CATEGORY : AVX2 23359 EXTENSION : AVX2 23360 EXCEPTIONS: avx-type-4 23361 PATTERN : VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23362 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 23363 23364 PATTERN : VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23365 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 23366 } 23367 { 23368 ICLASS : VPADDUSW 23369 CPL : 3 23370 CATEGORY : AVX2 23371 EXTENSION : AVX2 23372 EXCEPTIONS: avx-type-4 23373 PATTERN : VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23374 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 23375 23376 PATTERN : VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23377 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 23378 } 23379 23380 { 23381 ICLASS : VPAVGB 23382 CPL : 3 23383 CATEGORY : AVX2 23384 EXTENSION : AVX2 23385 EXCEPTIONS: avx-type-4 23386 PATTERN : VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23387 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 23388 23389 PATTERN : VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23390 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 23391 } 23392 { 23393 ICLASS : VPAVGW 23394 CPL : 3 23395 CATEGORY : AVX2 23396 EXTENSION : AVX2 23397 EXCEPTIONS: avx-type-4 23398 PATTERN : VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23399 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 23400 23401 PATTERN : VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23402 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 23403 } 23404 23405 23406 { 23407 ICLASS : VPCMPEQB 23408 CPL : 3 23409 CATEGORY : AVX2 23410 EXTENSION : AVX2 23411 EXCEPTIONS: avx-type-4 23412 PATTERN : VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23413 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 23414 23415 PATTERN : VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23416 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 23417 } 23418 { 23419 ICLASS : VPCMPEQW 23420 CPL : 3 23421 CATEGORY : AVX2 23422 EXTENSION : AVX2 23423 EXCEPTIONS: avx-type-4 23424 PATTERN : VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23425 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 23426 23427 PATTERN : VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23428 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 23429 } 23430 { 23431 ICLASS : VPCMPEQD 23432 CPL : 3 23433 CATEGORY : AVX2 23434 EXTENSION : AVX2 23435 EXCEPTIONS: avx-type-4 23436 PATTERN : VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23437 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 23438 23439 PATTERN : VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23440 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 23441 } 23442 { 23443 ICLASS : VPCMPEQQ 23444 CPL : 3 23445 CATEGORY : AVX2 23446 EXTENSION : AVX2 23447 EXCEPTIONS: avx-type-4 23448 PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23449 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 23450 23451 PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23452 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 23453 } 23454 23455 { 23456 ICLASS : VPCMPGTB 23457 CPL : 3 23458 CATEGORY : AVX2 23459 EXTENSION : AVX2 23460 EXCEPTIONS: avx-type-4 23461 PATTERN : VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23462 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 23463 23464 PATTERN : VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23465 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 23466 } 23467 { 23468 ICLASS : VPCMPGTW 23469 CPL : 3 23470 CATEGORY : AVX2 23471 EXTENSION : AVX2 23472 EXCEPTIONS: avx-type-4 23473 PATTERN : VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23474 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23475 23476 PATTERN : VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23477 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23478 } 23479 { 23480 ICLASS : VPCMPGTD 23481 CPL : 3 23482 CATEGORY : AVX2 23483 EXTENSION : AVX2 23484 EXCEPTIONS: avx-type-4 23485 PATTERN : VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23486 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23487 23488 PATTERN : VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23489 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23490 } 23491 { 23492 ICLASS : VPCMPGTQ 23493 CPL : 3 23494 CATEGORY : AVX2 23495 EXTENSION : AVX2 23496 EXCEPTIONS: avx-type-4 23497 PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23498 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 23499 23500 PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23501 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 23502 } 23503 23504 23505 { 23506 ICLASS : VPHADDW 23507 CPL : 3 23508 CATEGORY : AVX2 23509 EXTENSION : AVX2 23510 EXCEPTIONS: avx-type-4 23511 PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23512 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23513 23514 PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23515 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23516 } 23517 { 23518 ICLASS : VPHADDD 23519 CPL : 3 23520 CATEGORY : AVX2 23521 EXTENSION : AVX2 23522 EXCEPTIONS: avx-type-4 23523 PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23524 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23525 23526 PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23527 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23528 } 23529 { 23530 ICLASS : VPHADDSW 23531 CPL : 3 23532 CATEGORY : AVX2 23533 EXTENSION : AVX2 23534 EXCEPTIONS: avx-type-4 23535 PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23536 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23537 23538 PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23539 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23540 } 23541 { 23542 ICLASS : VPHSUBW 23543 CPL : 3 23544 CATEGORY : AVX2 23545 EXTENSION : AVX2 23546 EXCEPTIONS: avx-type-4 23547 PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23548 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23549 23550 PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23551 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23552 } 23553 { 23554 ICLASS : VPHSUBD 23555 CPL : 3 23556 CATEGORY : AVX2 23557 EXTENSION : AVX2 23558 EXCEPTIONS: avx-type-4 23559 PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23560 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23561 23562 PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23563 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23564 } 23565 { 23566 ICLASS : VPHSUBSW 23567 CPL : 3 23568 CATEGORY : AVX2 23569 EXTENSION : AVX2 23570 EXCEPTIONS: avx-type-4 23571 PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23572 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23573 23574 PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23575 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23576 } 23577 23578 { 23579 ICLASS : VPMADDWD 23580 CPL : 3 23581 CATEGORY : AVX2 23582 EXTENSION : AVX2 23583 EXCEPTIONS: avx-type-4 23584 PATTERN : VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23585 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23586 23587 PATTERN : VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23588 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23589 } 23590 { 23591 ICLASS : VPMADDUBSW 23592 CPL : 3 23593 CATEGORY : AVX2 23594 EXTENSION : AVX2 23595 EXCEPTIONS: avx-type-4 23596 PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23597 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:i8 23598 23599 PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23600 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:i8 23601 } 23602 23603 { 23604 ICLASS : VPMAXSB 23605 CPL : 3 23606 CATEGORY : AVX2 23607 EXTENSION : AVX2 23608 EXCEPTIONS: avx-type-4 23609 PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23610 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 23611 23612 PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23613 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 23614 } 23615 { 23616 ICLASS : VPMAXSW 23617 CPL : 3 23618 CATEGORY : AVX2 23619 EXTENSION : AVX2 23620 EXCEPTIONS: avx-type-4 23621 PATTERN : VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23622 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23623 23624 PATTERN : VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23625 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23626 } 23627 { 23628 ICLASS : VPMAXSD 23629 CPL : 3 23630 CATEGORY : AVX2 23631 EXTENSION : AVX2 23632 EXCEPTIONS: avx-type-4 23633 PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23634 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23635 23636 PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23637 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23638 } 23639 23640 { 23641 ICLASS : VPMAXUB 23642 CPL : 3 23643 CATEGORY : AVX2 23644 EXTENSION : AVX2 23645 EXCEPTIONS: avx-type-4 23646 PATTERN : VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23647 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 23648 23649 PATTERN : VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23650 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 23651 } 23652 { 23653 ICLASS : VPMAXUW 23654 CPL : 3 23655 CATEGORY : AVX2 23656 EXTENSION : AVX2 23657 EXCEPTIONS: avx-type-4 23658 PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23659 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 23660 23661 PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23662 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 23663 } 23664 { 23665 ICLASS : VPMAXUD 23666 CPL : 3 23667 CATEGORY : AVX2 23668 EXTENSION : AVX2 23669 EXCEPTIONS: avx-type-4 23670 PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23671 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 23672 23673 PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23674 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 23675 } 23676 23677 { 23678 ICLASS : VPMINSB 23679 CPL : 3 23680 CATEGORY : AVX2 23681 EXTENSION : AVX2 23682 EXCEPTIONS: avx-type-4 23683 PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23684 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 23685 23686 PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23687 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 23688 } 23689 { 23690 ICLASS : VPMINSW 23691 CPL : 3 23692 CATEGORY : AVX2 23693 EXTENSION : AVX2 23694 EXCEPTIONS: avx-type-4 23695 PATTERN : VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23696 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23697 23698 PATTERN : VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23699 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23700 } 23701 { 23702 ICLASS : VPMINSD 23703 CPL : 3 23704 CATEGORY : AVX2 23705 EXTENSION : AVX2 23706 EXCEPTIONS: avx-type-4 23707 PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23708 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23709 23710 PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23711 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23712 } 23713 23714 { 23715 ICLASS : VPMINUB 23716 CPL : 3 23717 CATEGORY : AVX2 23718 EXTENSION : AVX2 23719 EXCEPTIONS: avx-type-4 23720 PATTERN : VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23721 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 23722 23723 PATTERN : VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23724 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 23725 } 23726 { 23727 ICLASS : VPMINUW 23728 CPL : 3 23729 CATEGORY : AVX2 23730 EXTENSION : AVX2 23731 EXCEPTIONS: avx-type-4 23732 PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23733 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 23734 23735 PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23736 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 23737 } 23738 { 23739 ICLASS : VPMINUD 23740 CPL : 3 23741 CATEGORY : AVX2 23742 EXTENSION : AVX2 23743 EXCEPTIONS: avx-type-4 23744 PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23745 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 23746 23747 PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23748 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 23749 } 23750 23751 { 23752 ICLASS : VPMULHUW 23753 CPL : 3 23754 CATEGORY : AVX2 23755 EXTENSION : AVX2 23756 EXCEPTIONS: avx-type-4 23757 PATTERN : VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23758 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 23759 23760 PATTERN : VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23761 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 23762 } 23763 { 23764 ICLASS : VPMULHRSW 23765 CPL : 3 23766 CATEGORY : AVX2 23767 EXTENSION : AVX2 23768 EXCEPTIONS: avx-type-4 23769 PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23770 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23771 23772 PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23773 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23774 } 23775 23776 { 23777 ICLASS : VPMULHW 23778 CPL : 3 23779 CATEGORY : AVX2 23780 EXTENSION : AVX2 23781 EXCEPTIONS: avx-type-4 23782 PATTERN : VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23783 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23784 23785 PATTERN : VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23786 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23787 } 23788 { 23789 ICLASS : VPMULLW 23790 CPL : 3 23791 CATEGORY : AVX2 23792 EXTENSION : AVX2 23793 EXCEPTIONS: avx-type-4 23794 PATTERN : VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23795 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23796 23797 PATTERN : VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23798 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23799 } 23800 { 23801 ICLASS : VPMULLD 23802 CPL : 3 23803 CATEGORY : AVX2 23804 EXTENSION : AVX2 23805 EXCEPTIONS: avx-type-4 23806 PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23807 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23808 23809 PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23810 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23811 } 23812 23813 { 23814 ICLASS : VPMULUDQ 23815 CPL : 3 23816 CATEGORY : AVX2 23817 EXTENSION : AVX2 23818 EXCEPTIONS: avx-type-4 23819 PATTERN : VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23820 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 23821 23822 PATTERN : VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23823 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 23824 } 23825 { 23826 ICLASS : VPMULDQ 23827 CPL : 3 23828 CATEGORY : AVX2 23829 EXTENSION : AVX2 23830 EXCEPTIONS: avx-type-4 23831 PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23832 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23833 23834 PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23835 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23836 } 23837 23838 { 23839 ICLASS : VPSADBW 23840 CPL : 3 23841 CATEGORY : AVX2 23842 EXTENSION : AVX2 23843 EXCEPTIONS: avx-type-4 23844 PATTERN : VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23845 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 23846 23847 PATTERN : VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23848 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 23849 } 23850 { 23851 ICLASS : VPSHUFB 23852 CPL : 3 23853 CATEGORY : AVX2 23854 EXTENSION : AVX2 23855 EXCEPTIONS: avx-type-4 23856 PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23857 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 23858 23859 PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23860 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 23861 } 23862 23863 { 23864 ICLASS : VPSIGNB 23865 CPL : 3 23866 CATEGORY : AVX2 23867 EXTENSION : AVX2 23868 EXCEPTIONS: avx-type-4 23869 PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23870 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 23871 23872 PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23873 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 23874 } 23875 { 23876 ICLASS : VPSIGNW 23877 CPL : 3 23878 CATEGORY : AVX2 23879 EXTENSION : AVX2 23880 EXCEPTIONS: avx-type-4 23881 PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23882 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23883 23884 PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23885 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23886 } 23887 { 23888 ICLASS : VPSIGND 23889 CPL : 3 23890 CATEGORY : AVX2 23891 EXTENSION : AVX2 23892 EXCEPTIONS: avx-type-4 23893 PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23894 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23895 23896 PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23897 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23898 } 23899 23900 23901 { 23902 ICLASS : VPSUBSB 23903 CPL : 3 23904 CATEGORY : AVX2 23905 EXTENSION : AVX2 23906 EXCEPTIONS: avx-type-4 23907 PATTERN : VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23908 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 23909 23910 PATTERN : VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23911 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 23912 } 23913 { 23914 ICLASS : VPSUBSW 23915 CPL : 3 23916 CATEGORY : AVX2 23917 EXTENSION : AVX2 23918 EXCEPTIONS: avx-type-4 23919 PATTERN : VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23920 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23921 23922 PATTERN : VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23923 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23924 } 23925 23926 { 23927 ICLASS : VPSUBUSB 23928 CPL : 3 23929 CATEGORY : AVX2 23930 EXTENSION : AVX2 23931 EXCEPTIONS: avx-type-4 23932 PATTERN : VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23933 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 23934 23935 PATTERN : VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23936 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 23937 } 23938 { 23939 ICLASS : VPSUBUSW 23940 CPL : 3 23941 CATEGORY : AVX2 23942 EXTENSION : AVX2 23943 EXCEPTIONS: avx-type-4 23944 PATTERN : VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23945 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 23946 23947 PATTERN : VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23948 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 23949 } 23950 23951 { 23952 ICLASS : VPSUBB 23953 CPL : 3 23954 CATEGORY : AVX2 23955 EXTENSION : AVX2 23956 EXCEPTIONS: avx-type-4 23957 PATTERN : VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23958 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 23959 23960 PATTERN : VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23961 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 23962 } 23963 { 23964 ICLASS : VPSUBW 23965 CPL : 3 23966 CATEGORY : AVX2 23967 EXTENSION : AVX2 23968 EXCEPTIONS: avx-type-4 23969 PATTERN : VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23970 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 23971 23972 PATTERN : VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23973 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 23974 } 23975 { 23976 ICLASS : VPSUBD 23977 CPL : 3 23978 CATEGORY : AVX2 23979 EXTENSION : AVX2 23980 EXCEPTIONS: avx-type-4 23981 PATTERN : VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23982 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 23983 23984 PATTERN : VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23985 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 23986 } 23987 { 23988 ICLASS : VPSUBQ 23989 CPL : 3 23990 CATEGORY : AVX2 23991 EXTENSION : AVX2 23992 EXCEPTIONS: avx-type-4 23993 PATTERN : VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 23994 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 23995 23996 PATTERN : VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 23997 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 23998 } 23999 24000 { 24001 ICLASS : VPUNPCKHBW 24002 CPL : 3 24003 CATEGORY : AVX2 24004 EXTENSION : AVX2 24005 EXCEPTIONS: avx-type-4 24006 PATTERN : VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24007 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 24008 24009 PATTERN : VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24010 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 24011 } 24012 { 24013 ICLASS : VPUNPCKHWD 24014 CPL : 3 24015 CATEGORY : AVX2 24016 EXTENSION : AVX2 24017 EXCEPTIONS: avx-type-4 24018 PATTERN : VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24019 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 24020 24021 PATTERN : VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24022 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 24023 } 24024 { 24025 ICLASS : VPUNPCKHDQ 24026 CPL : 3 24027 CATEGORY : AVX2 24028 EXTENSION : AVX2 24029 EXCEPTIONS: avx-type-4 24030 PATTERN : VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24031 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 24032 24033 PATTERN : VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24034 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 24035 } 24036 { 24037 ICLASS : VPUNPCKHQDQ 24038 CPL : 3 24039 CATEGORY : AVX2 24040 EXTENSION : AVX2 24041 EXCEPTIONS: avx-type-4 24042 PATTERN : VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24043 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 24044 24045 PATTERN : VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24046 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 24047 } 24048 24049 { 24050 ICLASS : VPUNPCKLBW 24051 CPL : 3 24052 CATEGORY : AVX2 24053 EXTENSION : AVX2 24054 EXCEPTIONS: avx-type-4 24055 PATTERN : VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24056 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 24057 24058 PATTERN : VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24059 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 24060 } 24061 { 24062 ICLASS : VPUNPCKLWD 24063 CPL : 3 24064 CATEGORY : AVX2 24065 EXTENSION : AVX2 24066 EXCEPTIONS: avx-type-4 24067 PATTERN : VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24068 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 24069 24070 PATTERN : VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24071 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 24072 } 24073 { 24074 ICLASS : VPUNPCKLDQ 24075 CPL : 3 24076 CATEGORY : AVX2 24077 EXTENSION : AVX2 24078 EXCEPTIONS: avx-type-4 24079 PATTERN : VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24080 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 24081 24082 PATTERN : VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24083 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 24084 } 24085 { 24086 ICLASS : VPUNPCKLQDQ 24087 CPL : 3 24088 CATEGORY : AVX2 24089 EXTENSION : AVX2 24090 EXCEPTIONS: avx-type-4 24091 PATTERN : VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24092 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 24093 24094 PATTERN : VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24095 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 24096 } 24097 24098 24099 { 24100 ICLASS : VPALIGNR 24101 CPL : 3 24102 CATEGORY : AVX2 24103 EXTENSION : AVX2 24104 EXCEPTIONS: avx-type-4 24105 PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24106 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b 24107 24108 PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24109 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b 24110 } 24111 { 24112 ICLASS : VPBLENDW 24113 CPL : 3 24114 CATEGORY : AVX2 24115 EXTENSION : AVX2 24116 EXCEPTIONS: avx-type-4 24117 PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24118 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b 24119 24120 PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24121 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 IMM0:r:b 24122 } 24123 { 24124 ICLASS : VMPSADBW 24125 CPL : 3 24126 CATEGORY : AVX2 24127 EXTENSION : AVX2 24128 EXCEPTIONS: avx-type-4 24129 PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24130 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b 24131 24132 PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24133 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b 24134 } 24135 24136 24137 24138 { 24139 ICLASS : VPOR 24140 CPL : 3 24141 CATEGORY : LOGICAL 24142 EXTENSION : AVX2 24143 EXCEPTIONS: avx-type-4 24144 PATTERN : VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24145 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 24146 24147 PATTERN : VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24148 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 24149 } 24150 { 24151 ICLASS : VPAND 24152 CPL : 3 24153 CATEGORY : LOGICAL 24154 EXTENSION : AVX2 24155 EXCEPTIONS: avx-type-4 24156 PATTERN : VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24157 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 24158 24159 PATTERN : VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24160 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 24161 } 24162 { 24163 ICLASS : VPANDN 24164 CPL : 3 24165 CATEGORY : LOGICAL 24166 EXTENSION : AVX2 24167 EXCEPTIONS: avx-type-4 24168 PATTERN : VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24169 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 24170 24171 PATTERN : VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24172 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 24173 } 24174 { 24175 ICLASS : VPXOR 24176 CPL : 3 24177 CATEGORY : LOGICAL 24178 EXTENSION : AVX2 24179 EXCEPTIONS: avx-type-4 24180 PATTERN : VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24181 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 24182 24183 PATTERN : VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24184 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 24185 } 24186 24187 24188 24189 { 24190 ICLASS : VPBLENDVB 24191 CPL : 3 24192 CATEGORY : AVX2 24193 EXTENSION : AVX2 24194 EXCEPTIONS: avx-type-4 24195 PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 24196 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 REG2=YMM_SE():r:qq:u8 24197 24198 PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 24199 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 REG3=YMM_SE():r:qq:u8 24200 } 24201 24202 24203 24204 24205 { 24206 ICLASS : VPMOVMSKB 24207 CPL : 3 24208 CATEGORY : AVX2 24209 EXTENSION : AVX2 24210 EXCEPTIONS: avx-type-7 24211 PATTERN : VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24212 OPERANDS : REG0=GPR32_R():w:d:u32 REG1=YMM_B():r:qq:i8 24213 } 24214 24215 24216 24217 { 24218 ICLASS : VPSHUFD 24219 CPL : 3 24220 CATEGORY : AVX2 24221 EXTENSION : AVX2 24222 EXCEPTIONS: avx-type-4 24223 PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24224 OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:u32 IMM0:r:b 24225 24226 PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24227 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b 24228 } 24229 { 24230 ICLASS : VPSHUFHW 24231 CPL : 3 24232 CATEGORY : AVX2 24233 EXTENSION : AVX2 24234 EXCEPTIONS: avx-type-4 24235 PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24236 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b 24237 24238 PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24239 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b 24240 } 24241 { 24242 ICLASS : VPSHUFLW 24243 CPL : 3 24244 CATEGORY : AVX2 24245 EXTENSION : AVX2 24246 EXCEPTIONS: avx-type-4 24247 PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24248 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b 24249 24250 PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24251 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b 24252 } 24253 24254 24255 24256 { 24257 ICLASS : VPSRLDQ 24258 CPL : 3 24259 CATEGORY : AVX2 24260 EXTENSION : AVX2 24261 EXCEPTIONS: avx-type-7 24262 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() 24263 OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD 24264 } 24265 { 24266 ICLASS : VPSLLDQ 24267 CPL : 3 24268 CATEGORY : AVX2 24269 EXTENSION : AVX2 24270 EXCEPTIONS: avx-type-7 24271 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() 24272 OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD 24273 } 24274 24275 ############################################## 24276 24277 { 24278 ICLASS : VPSLLW 24279 CPL : 3 24280 CATEGORY : AVX2 24281 EXTENSION : AVX2 24282 EXCEPTIONS: avx-type-7 24283 PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 24284 OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD 24285 } 24286 { 24287 ICLASS : VPSLLD 24288 CPL : 3 24289 CATEGORY : AVX2 24290 EXTENSION : AVX2 24291 EXCEPTIONS: avx-type-7 24292 PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 24293 OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b #NDD 24294 } 24295 { 24296 ICLASS : VPSLLQ 24297 CPL : 3 24298 CATEGORY : AVX2 24299 EXTENSION : AVX2 24300 EXCEPTIONS: avx-type-7 24301 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 24302 OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD 24303 } 24304 24305 { 24306 ICLASS : VPSRAW 24307 CPL : 3 24308 CATEGORY : AVX2 24309 EXTENSION : AVX2 24310 EXCEPTIONS: avx-type-7 24311 PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 24312 OPERANDS : REG0=YMM_N():w:qq:i16 REG1=YMM_B():r:qq:i16 IMM0:r:b # NDD 24313 } 24314 { 24315 ICLASS : VPSRAD 24316 CPL : 3 24317 CATEGORY : AVX2 24318 EXTENSION : AVX2 24319 EXCEPTIONS: avx-type-7 24320 PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 24321 OPERANDS : REG0=YMM_N():w:qq:i32 REG1=YMM_B():r:qq:i32 IMM0:r:b # NDD 24322 } 24323 { 24324 ICLASS : VPSRLW 24325 CPL : 3 24326 CATEGORY : AVX2 24327 EXTENSION : AVX2 24328 EXCEPTIONS: avx-type-7 24329 PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 24330 OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD 24331 } 24332 { 24333 ICLASS : VPSRLD 24334 CPL : 3 24335 CATEGORY : AVX2 24336 EXTENSION : AVX2 24337 EXCEPTIONS: avx-type-7 24338 24339 PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 24340 OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b # NDD 24341 } 24342 { 24343 ICLASS : VPSRLQ 24344 CPL : 3 24345 CATEGORY : AVX2 24346 EXTENSION : AVX2 24347 EXCEPTIONS: avx-type-7 24348 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 24349 OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD 24350 } 24351 24352 24353 24354 ############################################################################ 24355 # SX versions 24356 ############################################################################ 24357 24358 { 24359 ICLASS : VPMOVSXBW 24360 CPL : 3 24361 CATEGORY : AVX2 24362 EXTENSION : AVX2 24363 EXCEPTIONS: avx-type-5 24364 PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24365 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=XMM_B():r:dq:i8 24366 PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24367 OPERANDS : REG0=YMM_R():w:qq:i16 MEM0:r:dq:i8 24368 } 24369 24370 ############################################################################ 24371 { 24372 ICLASS : VPMOVSXBD 24373 CPL : 3 24374 CATEGORY : AVX2 24375 EXTENSION : AVX2 24376 EXCEPTIONS: avx-type-5 24377 PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24378 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:q:i8 24379 PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24380 OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:q:i8 24381 } 24382 ############################################################################ 24383 { 24384 ICLASS : VPMOVSXBQ 24385 CPL : 3 24386 CATEGORY : AVX2 24387 EXTENSION : AVX2 24388 EXCEPTIONS: avx-type-5 24389 PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24390 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:d:i8 24391 PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24392 OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:d:i8 24393 } 24394 ############################################################################ 24395 { 24396 ICLASS : VPMOVSXWD 24397 CPL : 3 24398 CATEGORY : AVX2 24399 EXTENSION : AVX2 24400 EXCEPTIONS: avx-type-5 24401 PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24402 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:dq:i16 24403 PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24404 OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:dq:i16 24405 } 24406 ############################################################################ 24407 { 24408 ICLASS : VPMOVSXWQ 24409 CPL : 3 24410 CATEGORY : AVX2 24411 EXTENSION : AVX2 24412 EXCEPTIONS: avx-type-5 24413 PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24414 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:q:i16 24415 PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24416 OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:q:i16 24417 } 24418 ############################################################################ 24419 { 24420 ICLASS : VPMOVSXDQ 24421 CPL : 3 24422 CATEGORY : AVX2 24423 EXTENSION : AVX2 24424 EXCEPTIONS: avx-type-5 24425 PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24426 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:dq:i32 24427 PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24428 OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:dq:i32 24429 } 24430 24431 24432 24433 24434 24435 ############################################################################ 24436 # ZX versions 24437 ############################################################################ 24438 24439 { 24440 ICLASS : VPMOVZXBW 24441 CPL : 3 24442 CATEGORY : AVX2 24443 EXTENSION : AVX2 24444 EXCEPTIONS: avx-type-5 24445 PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24446 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:dq:u8 24447 PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24448 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:dq:u8 24449 } 24450 24451 ############################################################################ 24452 { 24453 ICLASS : VPMOVZXBD 24454 CPL : 3 24455 CATEGORY : AVX2 24456 EXTENSION : AVX2 24457 EXCEPTIONS: avx-type-5 24458 PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24459 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:q:u8 24460 PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24461 OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:q:u8 24462 } 24463 ############################################################################ 24464 { 24465 ICLASS : VPMOVZXBQ 24466 CPL : 3 24467 CATEGORY : AVX2 24468 EXTENSION : AVX2 24469 EXCEPTIONS: avx-type-5 24470 PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24471 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:d:u8 24472 PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24473 OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:d:u8 24474 } 24475 ############################################################################ 24476 { 24477 ICLASS : VPMOVZXWD 24478 CPL : 3 24479 CATEGORY : AVX2 24480 EXTENSION : AVX2 24481 EXCEPTIONS: avx-type-5 24482 PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24483 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:dq:u16 24484 PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24485 OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:dq:u16 24486 } 24487 ############################################################################ 24488 { 24489 ICLASS : VPMOVZXWQ 24490 CPL : 3 24491 CATEGORY : AVX2 24492 EXTENSION : AVX2 24493 EXCEPTIONS: avx-type-5 24494 PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24495 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u16 24496 PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24497 OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u16 24498 } 24499 ############################################################################ 24500 { 24501 ICLASS : VPMOVZXDQ 24502 CPL : 3 24503 CATEGORY : AVX2 24504 EXTENSION : AVX2 24505 EXCEPTIONS: avx-type-5 24506 PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24507 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:dq:u32 24508 PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24509 OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:dq:u32 24510 } 24511 24512 24513 ################################## 24514 # newer stuff 2009-08-14 24515 24516 24517 { 24518 ICLASS : VINSERTI128 24519 CPL : 3 24520 CATEGORY : AVX2 24521 EXTENSION : AVX2 24522 EXCEPTIONS: avx-type-6 24523 PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24524 OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:dq:u128 IMM0:r:b 24525 24526 PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24527 OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=XMM_B():r:dq:u128 IMM0:r:b 24528 } 24529 24530 24531 24532 24533 24534 { 24535 ICLASS : VEXTRACTI128 24536 CPL : 3 24537 CATEGORY : AVX2 24538 EXTENSION : AVX2 24539 EXCEPTIONS: avx-type-6 24540 PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24541 OPERANDS : MEM0:w:dq:u128 REG0=YMM_R():r:qq:u128 IMM0:r:b 24542 24543 PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24544 OPERANDS : REG0=XMM_B():w:dq:u128 REG1=YMM_R():r:qq:u128 IMM0:r:b 24545 } 24546 24547 24548 ########################################################################### 24549 24550 ### # VPMASKMOVD masked load and store 24551 ### # VPMASKMOVQ masked load and store 24552 24553 24554 24555 24556 { 24557 ICLASS : VPMASKMOVD 24558 CPL : 3 24559 CATEGORY : AVX2 24560 EXTENSION : AVX2 24561 ATTRIBUTES: maskop 24562 EXCEPTIONS: avx-type-6 24563 PATTERN : VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24564 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 24565 24566 24567 PATTERN : VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24568 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 24569 } 24570 { 24571 ICLASS : VPMASKMOVQ 24572 CPL : 3 24573 CATEGORY : AVX2 24574 EXTENSION : AVX2 24575 ATTRIBUTES: maskop 24576 EXCEPTIONS: avx-type-6 24577 24578 PATTERN : VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24579 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 24580 24581 24582 PATTERN : VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24583 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 24584 } 24585 24586 { 24587 ICLASS : VPMASKMOVD 24588 CPL : 3 24589 CATEGORY : AVX2 24590 EXTENSION : AVX2 24591 ATTRIBUTES: maskop 24592 EXCEPTIONS: avx-type-6 24593 PATTERN : VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24594 OPERANDS : MEM0:w:dq:u32 REG0=XMM_N():r:dq:u32 REG1=XMM_R():r:dq:u32 24595 24596 24597 PATTERN : VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24598 OPERANDS : MEM0:w:qq:u32 REG0=YMM_N():r:qq:u32 REG1=YMM_R():r:qq:u32 24599 } 24600 { 24601 ICLASS : VPMASKMOVQ 24602 CPL : 3 24603 CATEGORY : AVX2 24604 EXTENSION : AVX2 24605 ATTRIBUTES: maskop 24606 EXCEPTIONS: avx-type-6 24607 PATTERN : VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24608 OPERANDS : MEM0:w:dq:u64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:u64 24609 24610 24611 PATTERN : VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24612 OPERANDS : MEM0:w:qq:u64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:u64 24613 } 24614 ########################################################################### 24615 24616 24617 ### # VPERM2I128 256b only 24618 24619 { 24620 ICLASS : VPERM2I128 24621 CPL : 3 24622 CATEGORY : AVX2 24623 EXTENSION : AVX2 24624 EXCEPTIONS: avx-type-6 # Note: vperm2f128 is type 4... 24625 24626 PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24627 OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 IMM0:r:b 24628 24629 PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24630 OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 IMM0:r:b 24631 } 24632 24633 24634 { 24635 ICLASS : VPERMQ 24636 CPL : 3 24637 CATEGORY : AVX2 24638 EXTENSION : AVX2 24639 EXCEPTIONS: avx-type-4 24640 24641 PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24642 OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:qq:u64 IMM0:r:b 24643 24644 PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24645 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b 24646 } 24647 24648 { 24649 ICLASS : VPERMPD 24650 CPL : 3 24651 CATEGORY : AVX2 24652 EXTENSION : AVX2 24653 EXCEPTIONS: avx-type-4 24654 24655 PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24656 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b 24657 24658 PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24659 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b 24660 } 24661 24662 24663 24664 24665 24666 24667 24668 24669 { 24670 ICLASS : VPERMD 24671 CPL : 3 24672 CATEGORY : AVX2 24673 EXTENSION : AVX2 24674 EXCEPTIONS: avx-type-4 24675 24676 24677 PATTERN : VV1 0x36 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24678 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 24679 24680 PATTERN : VV1 0x36 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24681 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 24682 } 24683 { 24684 ICLASS : VPERMPS 24685 CPL : 3 24686 CATEGORY : AVX2 24687 EXTENSION : AVX2 24688 EXCEPTIONS: avx-type-4 24689 24690 PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24691 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 24692 24693 PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24694 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 24695 } 24696 24697 24698 ########################################################################### 24699 24700 24701 ### # VPBLENDD imm 128/256 24702 24703 24704 24705 { 24706 ICLASS : VPBLENDD 24707 CPL : 3 24708 CATEGORY : AVX2 24709 EXTENSION : AVX2 24710 EXCEPTIONS: avx-type-4 24711 24712 PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24713 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b 24714 24715 PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24716 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b 24717 24718 24719 PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 24720 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 IMM0:r:b 24721 24722 PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 24723 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 IMM0:r:b 24724 } 24725 24726 24727 24728 ########################################################################### 24729 24730 { 24731 ICLASS : VPBROADCASTB 24732 COMMENT : gpr 128/256 24733 CPL : 3 24734 CATEGORY : BROADCAST 24735 EXTENSION : AVX2 24736 EXCEPTIONS: avx-type-6 24737 24738 PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24739 OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 24740 24741 PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24742 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO16_8 24743 24744 PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24745 OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 24746 24747 PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24748 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO32_8 24749 24750 } 24751 24752 24753 24754 24755 { 24756 ICLASS : VPBROADCASTW 24757 COMMENT : gpr 128/256 24758 CPL : 3 24759 CATEGORY : BROADCAST 24760 EXTENSION : AVX2 24761 EXCEPTIONS: avx-type-6 24762 24763 PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24764 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO8_16 24765 24766 PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24767 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO8_16 24768 24769 PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24770 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO16_16 24771 24772 PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24773 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO16_16 24774 } 24775 24776 24777 24778 24779 ### # VPBROADCASTD gpr/mem 24780 24781 24782 { 24783 ICLASS : VPBROADCASTD 24784 COMMENT : gpr 128/256 24785 CPL : 3 24786 CATEGORY : BROADCAST 24787 EXTENSION : AVX2 24788 EXCEPTIONS: avx-type-6 24789 24790 PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24791 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 24792 24793 PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24794 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO4_32 24795 24796 24797 PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24798 OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 24799 24800 PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24801 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO8_32 24802 } 24803 24804 24805 24806 ### # VPBROADCASTQ gpr/mem 24807 24808 { 24809 ICLASS : VPBROADCASTQ 24810 COMMENT : gpr 128/256 24811 CPL : 3 24812 CATEGORY : BROADCAST 24813 EXTENSION : AVX2 24814 EXCEPTIONS: avx-type-6 24815 24816 PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24817 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 24818 24819 PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24820 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO2_64 24821 24822 PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24823 OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 24824 24825 PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24826 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO4_64 24827 } 24828 24829 24830 24831 24832 24833 24834 { 24835 ICLASS : VBROADCASTSS 24836 CPL : 3 24837 CATEGORY : BROADCAST 24838 EXTENSION : AVX2 24839 EXCEPTIONS: avx-type-6 24840 COMMENT : xmm,xmm and ymm,xmm 24841 PATTERN : VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24842 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO4_32 24843 24844 PATTERN : VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24845 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO8_32 24846 } 24847 24848 24849 { 24850 ICLASS : VBROADCASTSD 24851 CPL : 3 24852 CATEGORY : BROADCAST 24853 EXTENSION : AVX2 24854 EXCEPTIONS: avx-type-6 24855 COMMENT : ymm,xmm only 24856 PATTERN : VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24857 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f64 EMX_BROADCAST_1TO4_64 24858 } 24859 24860 24861 24862 { 24863 ICLASS : VBROADCASTI128 24864 CPL : 3 24865 CATEGORY : BROADCAST 24866 EXTENSION : AVX2 24867 EXCEPTIONS: avx-type-6 24868 COMMENT : memonly 256 -- FIXME: make types u64 like in AVX1? 24869 PATTERN : VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24870 OPERANDS : REG0=YMM_R():w:qq:u128 MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64 24871 } 24872 24873 24874 ###FILE: ../xed/datafiles/avxhsw/hsw-isa.txt 24875 24876 #BEGIN_LEGAL 24877 # 24878 #Copyright (c) 2016 Intel Corporation 24879 # 24880 # Licensed under the Apache License, Version 2.0 (the "License"); 24881 # you may not use this file except in compliance with the License. 24882 # You may obtain a copy of the License at 24883 # 24884 # http://www.apache.org/licenses/LICENSE-2.0 24885 # 24886 # Unless required by applicable law or agreed to in writing, software 24887 # distributed under the License is distributed on an "AS IS" BASIS, 24888 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24889 # See the License for the specific language governing permissions and 24890 # limitations under the License. 24891 # 24892 #END_LEGAL 24893 INSTRUCTIONS():: 24894 24895 { 24896 ICLASS : TZCNT 24897 CPL : 3 24898 CATEGORY : BMI1 24899 EXTENSION : BMI1 24900 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] 24901 PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24902 OPERANDS : REG0=GPRv_R():w MEM0:r:v 24903 24904 PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24905 OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r 24906 } 24907 24908 { 24909 ICLASS : BSF 24910 VERSION : 1 24911 COMMENT : AMD reused 0FBC for TZCNT and made BSF not have a refining prefix. This version replaces the normal version of BSF 24912 CPL : 3 24913 CATEGORY : BITBYTE 24914 EXTENSION : BASE 24915 ISA_SET : I386 24916 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] 24917 24918 PATTERN : 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24919 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 24920 24921 PATTERN : 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24922 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 24923 24924 PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24925 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 24926 24927 PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24928 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 24929 } 24930 24931 { 24932 ICLASS : INVPCID 24933 CPL : 0 24934 CATEGORY : MISC 24935 EXTENSION : INVPCID 24936 ISA_SET : INVPCID 24937 ATTRIBUTES : RING0 NOTSX 24938 PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() 24939 OPERANDS : REG0=GPR64_R():r MEM0:r:dq 24940 PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode32 MODRM() CR_WIDTH() 24941 OPERANDS : REG0=GPR32_R():r MEM0:r:dq 24942 COMMENT : 24943 } 24944 24945 24946 ###FILE: ../xed/datafiles/avxhsw/hsw-lzcnt.txt 24947 24948 #BEGIN_LEGAL 24949 # 24950 #Copyright (c) 2016 Intel Corporation 24951 # 24952 # Licensed under the Apache License, Version 2.0 (the "License"); 24953 # you may not use this file except in compliance with the License. 24954 # You may obtain a copy of the License at 24955 # 24956 # http://www.apache.org/licenses/LICENSE-2.0 24957 # 24958 # Unless required by applicable law or agreed to in writing, software 24959 # distributed under the License is distributed on an "AS IS" BASIS, 24960 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24961 # See the License for the specific language governing permissions and 24962 # limitations under the License. 24963 # 24964 #END_LEGAL 24965 INSTRUCTIONS():: 24966 24967 # LZCNT reg16, reg/mem16 F30FBD /r 24968 # LZCNT reg32, reg/mem32 F30FBD /r 24969 # LZCNT reg64, reg/mem64 F30FBD /r 24970 24971 { 24972 ICLASS : LZCNT 24973 # This replace the AMD version in LZCNT builds 24974 VERSION : 2 24975 CPL : 3 24976 CATEGORY : LZCNT 24977 EXTENSION : LZCNT 24978 COMMENT: : These next one WAS introduced first by AMD circa SSE4a. 24979 FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] 24980 PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24981 OPERANDS : REG0=GPRv_R():w:v MEM0:r:v 24982 PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 24983 OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v 24984 } 24985 24986 24987 { 24988 ICLASS : BSR 24989 VERSION : 2 24990 COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR 24991 CPL : 3 24992 CATEGORY : BITBYTE 24993 EXTENSION : BASE 24994 ISA_SET : I386 24995 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] 24996 PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 24997 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 24998 24999 PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25000 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 25001 25002 PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25003 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 25004 25005 PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25006 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 25007 } 25008 25009 25010 ###FILE: ../xed/datafiles/avxhsw/hsw-vex-gpr-isa.txt 25011 25012 #BEGIN_LEGAL 25013 # 25014 #Copyright (c) 2016 Intel Corporation 25015 # 25016 # Licensed under the Apache License, Version 2.0 (the "License"); 25017 # you may not use this file except in compliance with the License. 25018 # You may obtain a copy of the License at 25019 # 25020 # http://www.apache.org/licenses/LICENSE-2.0 25021 # 25022 # Unless required by applicable law or agreed to in writing, software 25023 # distributed under the License is distributed on an "AS IS" BASIS, 25024 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25025 # See the License for the specific language governing permissions and 25026 # limitations under the License. 25027 # 25028 #END_LEGAL 25029 25030 AVX_INSTRUCTIONS():: 25031 25032 { 25033 ICLASS : PDEP 25034 CPL : 3 25035 CATEGORY : BMI2 25036 EXTENSION : BMI2 25037 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] 25038 25039 #32b 25040 PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25041 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 25042 25043 PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25044 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 25045 25046 PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25047 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 25048 25049 PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25050 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 25051 25052 # 64b 25053 PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25054 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q 25055 25056 PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25057 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q 25058 } 25059 25060 { 25061 ICLASS : PEXT 25062 CPL : 3 25063 CATEGORY : BMI2 25064 EXTENSION : BMI2 25065 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] 25066 25067 25068 #32b 25069 PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25070 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 25071 25072 PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25073 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 25074 25075 PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25076 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 25077 25078 PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25079 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 25080 25081 # 64b 25082 PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25083 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q 25084 25085 PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25086 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q 25087 } 25088 25089 25090 { 25091 ICLASS : ANDN 25092 CPL : 3 25093 CATEGORY : BMI1 25094 EXTENSION : BMI1 25095 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] 25096 25097 # 32b 25098 PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25099 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 25100 25101 PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25102 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 25103 25104 PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25105 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 25106 25107 PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25108 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 25109 25110 # 64b 25111 PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25112 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q 25113 25114 PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25115 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q 25116 } 25117 25118 { 25119 ICLASS : BLSR 25120 CPL : 3 25121 CATEGORY : BMI1 25122 EXTENSION : BMI1 25123 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] 25124 25125 # 32b 25126 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 25127 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 25128 25129 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 25130 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 25131 25132 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 25133 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 25134 25135 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 25136 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 25137 25138 # 64b 25139 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 25140 OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q 25141 25142 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 25143 OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q 25144 25145 } 25146 25147 { 25148 ICLASS : BLSMSK 25149 CPL : 3 25150 CATEGORY : BMI1 25151 EXTENSION : BMI1 25152 FLAGS : MUST [ of-0 sf-mod zf-0 af-u pf-u cf-mod ] 25153 25154 #32b 25155 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 25156 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 25157 25158 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 25159 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 25160 25161 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 25162 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 25163 25164 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 25165 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 25166 25167 #64b 25168 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 25169 OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q 25170 25171 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 25172 OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q 25173 } 25174 25175 { 25176 ICLASS : BLSI 25177 CPL : 3 25178 CATEGORY : BMI1 25179 EXTENSION : BMI1 25180 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] 25181 25182 # 32b 25183 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 25184 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 25185 25186 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 25187 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 25188 25189 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 25190 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 25191 25192 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 25193 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 25194 25195 # 64b 25196 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 25197 OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q 25198 25199 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 25200 OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q 25201 } 25202 25203 { 25204 ICLASS : BZHI 25205 CPL : 3 25206 CATEGORY : BMI2 25207 EXTENSION : BMI2 25208 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-mod ] 25209 25210 # 32b 25211 PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25212 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 25213 25214 PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25215 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 25216 25217 PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25218 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 25219 25220 PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25221 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 25222 25223 # 64b 25224 PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25225 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q 25226 25227 PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25228 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q 25229 } 25230 25231 { 25232 ICLASS : BEXTR 25233 CPL : 3 25234 CATEGORY : BMI1 25235 EXTENSION : BMI1 25236 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] 25237 25238 # 32b 25239 PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25240 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 25241 25242 PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25243 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 25244 25245 PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25246 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 25247 25248 PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25249 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 25250 25251 # 64b 25252 PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25253 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q 25254 25255 PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25256 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q 25257 } 25258 25259 25260 25261 { 25262 ICLASS : SHLX 25263 CPL : 3 25264 CATEGORY : BMI2 25265 EXTENSION : BMI2 25266 25267 # 32b 25268 PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25269 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 25270 25271 PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25272 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 25273 25274 PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25275 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 25276 25277 PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25278 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 25279 25280 # 64b 25281 PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25282 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q 25283 25284 PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25285 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q 25286 } 25287 { 25288 ICLASS : SARX 25289 CPL : 3 25290 CATEGORY : BMI2 25291 EXTENSION : BMI2 25292 25293 # 32b 25294 PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25295 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 25296 25297 PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25298 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 25299 25300 PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25301 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 25302 25303 PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25304 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 25305 25306 # 64b 25307 PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25308 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q 25309 25310 PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25311 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q 25312 } 25313 { 25314 ICLASS : SHRX 25315 CPL : 3 25316 CATEGORY : BMI2 25317 EXTENSION : BMI2 25318 25319 # 32b 25320 PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25321 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 25322 25323 PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25324 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 25325 25326 PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25327 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 25328 25329 PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25330 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 25331 25332 # 64b 25333 PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25334 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q 25335 25336 PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25337 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q 25338 } 25339 25340 25341 25342 { 25343 ICLASS : MULX 25344 CPL : 3 25345 CATEGORY : BMI2 25346 EXTENSION : BMI2 25347 25348 # reg:w vvvv:w rm:r rdx:r 25349 # 32b 25350 PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25351 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP 25352 25353 PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25354 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP 25355 PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25356 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP 25357 25358 PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25359 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP 25360 25361 # 64b 25362 PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25363 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q REG2=VGPR64_B():r:q REG3=XED_REG_RDX:r:SUPP 25364 PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25365 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q MEM0:r:q REG2=XED_REG_RDX:r:SUPP 25366 } 25367 25368 { 25369 ICLASS : RORX 25370 CPL : 3 25371 CATEGORY : BMI2 25372 EXTENSION : BMI2 25373 25374 # reg(w) rm(r) / vvvv must be 1111. / 2010-01-08 CART change 25375 25376 # 32b 25377 PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 25378 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b 25379 25380 PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 25381 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b 25382 PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 25383 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b 25384 25385 PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 25386 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b 25387 25388 # 64b 25389 PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 25390 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q IMM0:r:b 25391 PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 25392 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b 25393 } 25394 25395 25396 ###FILE: ../xed/datafiles/avxhsw/hsw-vshift-isa.txt 25397 25398 #BEGIN_LEGAL 25399 # 25400 #Copyright (c) 2016 Intel Corporation 25401 # 25402 # Licensed under the Apache License, Version 2.0 (the "License"); 25403 # you may not use this file except in compliance with the License. 25404 # You may obtain a copy of the License at 25405 # 25406 # http://www.apache.org/licenses/LICENSE-2.0 25407 # 25408 # Unless required by applicable law or agreed to in writing, software 25409 # distributed under the License is distributed on an "AS IS" BASIS, 25410 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25411 # See the License for the specific language governing permissions and 25412 # limitations under the License. 25413 # 25414 #END_LEGAL 25415 AVX_INSTRUCTIONS():: 25416 25417 25418 25419 25420 { 25421 ICLASS : VPSLLVD 25422 CPL : 3 25423 CATEGORY : AVX2 25424 EXTENSION : AVX2 25425 EXCEPTIONS: avx-type-4 25426 PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25427 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 25428 25429 PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25430 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 25431 25432 PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25433 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 25434 25435 PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25436 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 25437 25438 } 25439 { 25440 ICLASS : VPSLLVQ 25441 CPL : 3 25442 CATEGORY : AVX2 25443 EXTENSION : AVX2 25444 EXCEPTIONS: avx-type-4 25445 PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25446 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 25447 25448 PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25449 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 25450 25451 PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25452 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 25453 25454 PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25455 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 25456 25457 } 25458 25459 { 25460 ICLASS : VPSRLVD 25461 CPL : 3 25462 CATEGORY : AVX2 25463 EXTENSION : AVX2 25464 EXCEPTIONS: avx-type-4 25465 PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25466 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 25467 25468 PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25469 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 25470 25471 PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25472 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 25473 25474 PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25475 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 25476 25477 } 25478 { 25479 ICLASS : VPSRLVQ 25480 CPL : 3 25481 CATEGORY : AVX2 25482 EXTENSION : AVX2 25483 EXCEPTIONS: avx-type-4 25484 PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25485 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 25486 25487 PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25488 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 25489 25490 PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25491 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 25492 25493 PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25494 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 25495 25496 } 25497 25498 { 25499 ICLASS : VPSRAVD 25500 CPL : 3 25501 CATEGORY : AVX2 25502 EXTENSION : AVX2 25503 EXCEPTIONS: avx-type-4 25504 PATTERN : VV1 0x46 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25505 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 25506 25507 PATTERN : VV1 0x46 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25508 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 25509 25510 PATTERN : VV1 0x46 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25511 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 25512 25513 PATTERN : VV1 0x46 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25514 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 25515 25516 } 25517 25518 25519 25520 25521 ###FILE: ../xed/datafiles/avxhsw/movnt-load-isa.txt 25522 25523 #BEGIN_LEGAL 25524 # 25525 #Copyright (c) 2016 Intel Corporation 25526 # 25527 # Licensed under the Apache License, Version 2.0 (the "License"); 25528 # you may not use this file except in compliance with the License. 25529 # You may obtain a copy of the License at 25530 # 25531 # http://www.apache.org/licenses/LICENSE-2.0 25532 # 25533 # Unless required by applicable law or agreed to in writing, software 25534 # distributed under the License is distributed on an "AS IS" BASIS, 25535 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25536 # See the License for the specific language governing permissions and 25537 # limitations under the License. 25538 # 25539 #END_LEGAL 25540 AVX_INSTRUCTIONS():: 25541 25542 25543 { 25544 ICLASS : VMOVNTDQA 25545 CPL : 3 25546 CATEGORY : DATAXFER 25547 EXTENSION : AVX2 25548 EXCEPTIONS: avx-type-1 25549 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX 25550 25551 PATTERN : VV1 0x2A V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25552 OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq 25553 } 25554 25555 25556 25557 25558 25559 ###FILE: ../xed/datafiles/avxhsw/vmfunc-isa.txt 25560 25561 #BEGIN_LEGAL 25562 # 25563 #Copyright (c) 2016 Intel Corporation 25564 # 25565 # Licensed under the Apache License, Version 2.0 (the "License"); 25566 # you may not use this file except in compliance with the License. 25567 # You may obtain a copy of the License at 25568 # 25569 # http://www.apache.org/licenses/LICENSE-2.0 25570 # 25571 # Unless required by applicable law or agreed to in writing, software 25572 # distributed under the License is distributed on an "AS IS" BASIS, 25573 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25574 # See the License for the specific language governing permissions and 25575 # limitations under the License. 25576 # 25577 #END_LEGAL 25578 INSTRUCTIONS():: 25579 25580 { 25581 ICLASS : VMFUNC 25582 CPL : 3 25583 CATEGORY : VTX 25584 EXTENSION : VMFUNC 25585 ISA_SET : VMFUNC 25586 ATTRIBUTES : 25587 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix 25588 OPERANDS : 25589 } 25590 25591 25592 ###FILE: ../xed/datafiles/avxhsw/rtm.xed 25593 25594 #BEGIN_LEGAL 25595 # 25596 #Copyright (c) 2016 Intel Corporation 25597 # 25598 # Licensed under the Apache License, Version 2.0 (the "License"); 25599 # you may not use this file except in compliance with the License. 25600 # You may obtain a copy of the License at 25601 # 25602 # http://www.apache.org/licenses/LICENSE-2.0 25603 # 25604 # Unless required by applicable law or agreed to in writing, software 25605 # distributed under the License is distributed on an "AS IS" BASIS, 25606 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25607 # See the License for the specific language governing permissions and 25608 # limitations under the License. 25609 # 25610 #END_LEGAL 25611 INSTRUCTIONS():: 25612 25613 { 25614 ICLASS : XBEGIN 25615 CPL : 3 25616 CATEGORY : COND_BR 25617 EXTENSION : RTM 25618 COMMENT : Not always a branch. If aborts, then branches & eax is written 25619 25620 PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[0b000] BRDISPz() 25621 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP REG1=XED_REG_EAX:cw:SUPP 25622 } 25623 25624 { 25625 ICLASS : XEND 25626 CPL : 3 25627 CATEGORY : COND_BR 25628 EXTENSION : RTM 25629 COMMENT : Transaction end. may branch 25630 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix 25631 OPERANDS : 25632 } 25633 25634 { 25635 ICLASS : XABORT 25636 CPL : 3 25637 CATEGORY : UNCOND_BR 25638 EXTENSION : RTM 25639 COMMENT : Transaction abort. Branches. NOP outside of transaction; Thus eax is rcw. 25640 PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b111] RM[0b000] UIMM8() 25641 OPERANDS : REG0=XED_REG_EAX:rcw:SUPP IMM0:r:b 25642 } 25643 25644 25645 { 25646 ICLASS : XTEST 25647 CPL : 3 25648 CATEGORY : LOGICAL 25649 EXTENSION : RTM 25650 COMMENT : test if in RTM transaction mode 25651 FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-0 cf-0 ] 25652 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix 25653 OPERANDS : 25654 } 25655 25656 25657 ###FILE: ../xed/datafiles/avx/avx-fma-isa.txt 25658 25659 #BEGIN_LEGAL 25660 # 25661 #Copyright (c) 2016 Intel Corporation 25662 # 25663 # Licensed under the Apache License, Version 2.0 (the "License"); 25664 # you may not use this file except in compliance with the License. 25665 # You may obtain a copy of the License at 25666 # 25667 # http://www.apache.org/licenses/LICENSE-2.0 25668 # 25669 # Unless required by applicable law or agreed to in writing, software 25670 # distributed under the License is distributed on an "AS IS" BASIS, 25671 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25672 # See the License for the specific language governing permissions and 25673 # limitations under the License. 25674 # 25675 #END_LEGAL 25676 AVX_INSTRUCTIONS():: 25677 25678 # Issues: encoder is at a loss for vmaddps xmm0,xmm0,xmm0,xmm0. 25679 # Encoder must enforce equality between two parameters. Never had to do this before. 25680 # Extra check? 25681 # Decoder must rip off suffixes _DDMR, _DDRM, _DRMD in disassembly (eventually) 25682 ############################################################################################# 25683 # Operand orders: 25684 # A = B * C + D 25685 #Type 1) reg0 reg0 mem/reg1 reg2 DDMR 312 or 132 25686 #Type 2) reg0 reg0 reg1 mem/reg2 DDRM 123 or 213 25687 #Type 3) reg0 reg1 mem/reg2 reg0 DRMD 321 or 231 25688 25689 # dst is in MODRM.REG 25690 # regsrc is in VEX.vvvv 25691 # memop is in MODRM.RM 25692 ############################################################################################ 25693 25694 25695 25696 25697 25698 25699 25700 25701 25702 25703 25704 25705 ########################################################## 25706 25707 25708 25709 25710 25711 25712 25713 25714 25715 25716 25717 25718 ################################################################## 25719 25720 25721 25722 25723 25724 25725 25726 25727 25728 25729 25730 25731 25732 ################################################################## 25733 { 25734 ICLASS : VFMADD132PD 25735 EXCEPTIONS: avx-type-2 25736 CPL : 3 25737 CATEGORY : VFMA 25738 EXTENSION : FMA 25739 ATTRIBUTES: MXCSR 25740 # R/M 128 25741 PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25742 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 25743 # R/R 128 25744 PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25745 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 25746 25747 25748 # R/M 256 25749 PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25750 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 25751 # R/R 256 25752 PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25753 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 25754 } 25755 { 25756 ICLASS : VFMADD132PS 25757 EXCEPTIONS: avx-type-2 25758 CPL : 3 25759 CATEGORY : VFMA 25760 EXTENSION : FMA 25761 ATTRIBUTES: MXCSR 25762 # R/M 128 25763 PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25764 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 25765 # R/R 128 25766 PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25767 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 25768 25769 25770 # R/M 256 25771 PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25772 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 25773 # R/R 256 25774 PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25775 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 25776 } 25777 { 25778 ICLASS : VFMADD132SD 25779 EXCEPTIONS: avx-type-3 25780 CPL : 3 25781 CATEGORY : VFMA 25782 EXTENSION : FMA 25783 ATTRIBUTES: MXCSR simd_scalar 25784 # R/M 128 25785 PATTERN : VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25786 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 25787 # R/R 128 25788 PATTERN : VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25789 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 25790 } 25791 { 25792 ICLASS : VFMADD132SS 25793 EXCEPTIONS: avx-type-3 25794 CPL : 3 25795 CATEGORY : VFMA 25796 EXTENSION : FMA 25797 ATTRIBUTES: MXCSR simd_scalar 25798 # R/M 128 25799 PATTERN : VV1 0x99 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25800 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 25801 # R/R 128 25802 PATTERN : VV1 0x99 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25803 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 25804 25805 } 25806 25807 { 25808 ICLASS : VFMADD213PD 25809 EXCEPTIONS: avx-type-2 25810 CPL : 3 25811 CATEGORY : VFMA 25812 EXTENSION : FMA 25813 ATTRIBUTES: MXCSR 25814 # R/M 128 25815 PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25816 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 25817 # R/R 128 25818 PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25819 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 25820 25821 25822 # R/M 256 25823 PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25824 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 25825 # R/R 256 25826 PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25827 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 25828 } 25829 { 25830 ICLASS : VFMADD213PS 25831 EXCEPTIONS: avx-type-2 25832 CPL : 3 25833 CATEGORY : VFMA 25834 EXTENSION : FMA 25835 ATTRIBUTES: MXCSR 25836 # R/M 128 25837 PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25838 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 25839 # R/R 128 25840 PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25841 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 25842 25843 25844 # R/M 256 25845 PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25846 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 25847 # R/R 256 25848 PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25849 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 25850 } 25851 { 25852 ICLASS : VFMADD213SD 25853 EXCEPTIONS: avx-type-3 25854 CPL : 3 25855 CATEGORY : VFMA 25856 EXTENSION : FMA 25857 ATTRIBUTES: MXCSR simd_scalar 25858 # R/M 128 25859 PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25860 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 25861 # R/R 128 25862 PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25863 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 25864 25865 } 25866 { 25867 ICLASS : VFMADD213SS 25868 EXCEPTIONS: avx-type-3 25869 CPL : 3 25870 CATEGORY : VFMA 25871 EXTENSION : FMA 25872 ATTRIBUTES: MXCSR simd_scalar 25873 # R/M 128 25874 PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25875 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 25876 # R/R 128 25877 PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25878 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 25879 } 25880 25881 { 25882 ICLASS : VFMADD231PD 25883 EXCEPTIONS: avx-type-2 25884 CPL : 3 25885 CATEGORY : VFMA 25886 EXTENSION : FMA 25887 ATTRIBUTES: MXCSR 25888 # R/M 128 25889 PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25890 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 25891 # R/R 128 25892 PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25893 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 25894 25895 25896 # R/M 256 25897 PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25898 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 25899 # R/R 256 25900 PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25901 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 25902 25903 } 25904 { 25905 ICLASS : VFMADD231PS 25906 EXCEPTIONS: avx-type-2 25907 CPL : 3 25908 CATEGORY : VFMA 25909 EXTENSION : FMA 25910 ATTRIBUTES: MXCSR 25911 # R/M 128 25912 PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25913 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 25914 # R/R 128 25915 PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25916 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 25917 25918 # R/M 256 25919 PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25920 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 25921 # R/R 256 25922 PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25923 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 25924 25925 } 25926 { 25927 ICLASS : VFMADD231SD 25928 EXCEPTIONS: avx-type-3 25929 CPL : 3 25930 CATEGORY : VFMA 25931 EXTENSION : FMA 25932 ATTRIBUTES: MXCSR simd_scalar 25933 # R/M 128 25934 PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25935 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 25936 # R/R 128 25937 PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25938 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 25939 25940 } 25941 { 25942 ICLASS : VFMADD231SS 25943 EXCEPTIONS: avx-type-3 25944 CPL : 3 25945 CATEGORY : VFMA 25946 EXTENSION : FMA 25947 ATTRIBUTES: MXCSR simd_scalar 25948 # R/M 128 25949 PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25950 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 25951 # R/R 128 25952 PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25953 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 25954 25955 } 25956 25957 25958 ################################################### 25959 { 25960 ICLASS : VFMADDSUB132PD 25961 EXCEPTIONS: avx-type-2 25962 CPL : 3 25963 CATEGORY : VFMA 25964 EXTENSION : FMA 25965 ATTRIBUTES: MXCSR 25966 # R/M 128 25967 PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25968 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 25969 # R/R 128 25970 PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25971 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 25972 25973 25974 # R/M 256 25975 PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25976 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 25977 # R/R 256 25978 PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25979 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 25980 } 25981 { 25982 ICLASS : VFMADDSUB213PD 25983 EXCEPTIONS: avx-type-2 25984 CPL : 3 25985 CATEGORY : VFMA 25986 EXTENSION : FMA 25987 ATTRIBUTES: MXCSR 25988 # R/M 128 25989 PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25990 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 25991 # R/R 128 25992 PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 25993 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 25994 25995 25996 # R/M 256 25997 PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 25998 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 25999 # R/R 256 26000 PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26001 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26002 } 26003 { 26004 ICLASS : VFMADDSUB231PD 26005 EXCEPTIONS: avx-type-2 26006 CPL : 3 26007 CATEGORY : VFMA 26008 EXTENSION : FMA 26009 ATTRIBUTES: MXCSR 26010 # R/M 128 26011 PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26012 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26013 # R/R 128 26014 PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26015 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26016 26017 26018 # R/M 256 26019 PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26020 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26021 # R/R 256 26022 PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26023 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26024 26025 } 26026 26027 { 26028 ICLASS : VFMADDSUB132PS 26029 EXCEPTIONS: avx-type-2 26030 CPL : 3 26031 CATEGORY : VFMA 26032 EXTENSION : FMA 26033 ATTRIBUTES: MXCSR 26034 # R/M 128 26035 PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26036 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26037 # R/R 128 26038 PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26039 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26040 26041 26042 # R/M 256 26043 PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26044 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26045 # R/R 256 26046 PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26047 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26048 } 26049 { 26050 ICLASS : VFMADDSUB213PS 26051 EXCEPTIONS: avx-type-2 26052 CPL : 3 26053 CATEGORY : VFMA 26054 EXTENSION : FMA 26055 ATTRIBUTES: MXCSR 26056 # R/M 128 26057 PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26058 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26059 # R/R 128 26060 PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26061 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26062 26063 26064 # R/M 256 26065 PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26066 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26067 # R/R 256 26068 PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26069 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26070 } 26071 { 26072 ICLASS : VFMADDSUB231PS 26073 EXCEPTIONS: avx-type-2 26074 CPL : 3 26075 CATEGORY : VFMA 26076 EXTENSION : FMA 26077 ATTRIBUTES: MXCSR 26078 # R/M 128 26079 PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26080 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26081 # R/R 128 26082 PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26083 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26084 26085 # R/M 256 26086 PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26087 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26088 # R/R 256 26089 PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26090 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26091 26092 } 26093 ################################################### 26094 26095 { 26096 ICLASS : VFMSUBADD132PD 26097 EXCEPTIONS: avx-type-2 26098 CPL : 3 26099 CATEGORY : VFMA 26100 EXTENSION : FMA 26101 ATTRIBUTES: MXCSR 26102 # R/M 128 26103 PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26104 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26105 # R/R 128 26106 PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26107 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26108 26109 26110 # R/M 256 26111 PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26112 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26113 # R/R 256 26114 PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26115 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26116 } 26117 { 26118 ICLASS : VFMSUBADD213PD 26119 EXCEPTIONS: avx-type-2 26120 CPL : 3 26121 CATEGORY : VFMA 26122 EXTENSION : FMA 26123 ATTRIBUTES: MXCSR 26124 # R/M 128 26125 PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26126 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26127 # R/R 128 26128 PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26129 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26130 26131 26132 # R/M 256 26133 PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26134 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26135 # R/R 256 26136 PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26137 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26138 } 26139 { 26140 ICLASS : VFMSUBADD231PD 26141 EXCEPTIONS: avx-type-2 26142 CPL : 3 26143 CATEGORY : VFMA 26144 EXTENSION : FMA 26145 ATTRIBUTES: MXCSR 26146 # R/M 128 26147 PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26148 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26149 # R/R 128 26150 PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26151 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26152 26153 26154 # R/M 256 26155 PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26156 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26157 # R/R 256 26158 PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26159 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26160 26161 } 26162 26163 { 26164 ICLASS : VFMSUBADD132PS 26165 EXCEPTIONS: avx-type-2 26166 CPL : 3 26167 CATEGORY : VFMA 26168 EXTENSION : FMA 26169 ATTRIBUTES: MXCSR 26170 # R/M 128 26171 PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26172 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26173 # R/R 128 26174 PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26175 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26176 26177 26178 # R/M 256 26179 PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26180 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26181 # R/R 256 26182 PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26183 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26184 } 26185 { 26186 ICLASS : VFMSUBADD213PS 26187 EXCEPTIONS: avx-type-2 26188 CPL : 3 26189 CATEGORY : VFMA 26190 EXTENSION : FMA 26191 ATTRIBUTES: MXCSR 26192 # R/M 128 26193 PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26194 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26195 # R/R 128 26196 PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26197 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26198 26199 26200 # R/M 256 26201 PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26202 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26203 # R/R 256 26204 PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26205 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26206 } 26207 { 26208 ICLASS : VFMSUBADD231PS 26209 EXCEPTIONS: avx-type-2 26210 CPL : 3 26211 CATEGORY : VFMA 26212 EXTENSION : FMA 26213 ATTRIBUTES: MXCSR 26214 # R/M 128 26215 PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26216 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26217 # R/R 128 26218 PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26219 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26220 26221 # R/M 256 26222 PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26223 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26224 # R/R 256 26225 PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26226 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26227 26228 } 26229 26230 26231 ################################################### 26232 26233 { 26234 ICLASS : VFMSUB132PD 26235 EXCEPTIONS: avx-type-2 26236 CPL : 3 26237 CATEGORY : VFMA 26238 EXTENSION : FMA 26239 ATTRIBUTES: MXCSR 26240 # R/M 128 26241 PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26242 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26243 # R/R 128 26244 PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26245 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26246 26247 26248 # R/M 256 26249 PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26250 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26251 # R/R 256 26252 PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26253 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26254 } 26255 { 26256 ICLASS : VFMSUB132PS 26257 EXCEPTIONS: avx-type-2 26258 CPL : 3 26259 CATEGORY : VFMA 26260 EXTENSION : FMA 26261 ATTRIBUTES: MXCSR 26262 # R/M 128 26263 PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26264 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26265 # R/R 128 26266 PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26267 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26268 26269 26270 # R/M 256 26271 PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26272 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26273 # R/R 256 26274 PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26275 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26276 } 26277 { 26278 ICLASS : VFMSUB132SD 26279 EXCEPTIONS: avx-type-3 26280 CPL : 3 26281 CATEGORY : VFMA 26282 EXTENSION : FMA 26283 ATTRIBUTES: MXCSR simd_scalar 26284 # R/M 128 26285 PATTERN : VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26286 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 26287 # R/R 128 26288 PATTERN : VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26289 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 26290 } 26291 { 26292 ICLASS : VFMSUB132SS 26293 EXCEPTIONS: avx-type-3 26294 CPL : 3 26295 CATEGORY : VFMA 26296 EXTENSION : FMA 26297 ATTRIBUTES: MXCSR simd_scalar 26298 # R/M 128 26299 PATTERN : VV1 0x9B V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26300 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 26301 # R/R 128 26302 PATTERN : VV1 0x9B V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26303 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 26304 26305 } 26306 26307 { 26308 ICLASS : VFMSUB213PD 26309 EXCEPTIONS: avx-type-2 26310 CPL : 3 26311 CATEGORY : VFMA 26312 EXTENSION : FMA 26313 ATTRIBUTES: MXCSR 26314 # R/M 128 26315 PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26316 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26317 # R/R 128 26318 PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26319 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26320 26321 26322 # R/M 256 26323 PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26324 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26325 # R/R 256 26326 PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26327 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26328 } 26329 { 26330 ICLASS : VFMSUB213PS 26331 EXCEPTIONS: avx-type-2 26332 CPL : 3 26333 CATEGORY : VFMA 26334 EXTENSION : FMA 26335 ATTRIBUTES: MXCSR 26336 # R/M 128 26337 PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26338 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26339 # R/R 128 26340 PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26341 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26342 26343 26344 # R/M 256 26345 PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26346 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26347 # R/R 256 26348 PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26349 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26350 } 26351 { 26352 ICLASS : VFMSUB213SD 26353 EXCEPTIONS: avx-type-3 26354 CPL : 3 26355 CATEGORY : VFMA 26356 EXTENSION : FMA 26357 ATTRIBUTES: MXCSR simd_scalar 26358 # R/M 128 26359 PATTERN : VV1 0xAB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26360 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 26361 # R/R 128 26362 PATTERN : VV1 0xAB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26363 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 26364 26365 } 26366 { 26367 ICLASS : VFMSUB213SS 26368 EXCEPTIONS: avx-type-3 26369 CPL : 3 26370 CATEGORY : VFMA 26371 EXTENSION : FMA 26372 ATTRIBUTES: MXCSR simd_scalar 26373 # R/M 128 26374 PATTERN : VV1 0xAB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26375 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 26376 # R/R 128 26377 PATTERN : VV1 0xAB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26378 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 26379 } 26380 26381 { 26382 ICLASS : VFMSUB231PD 26383 EXCEPTIONS: avx-type-2 26384 CPL : 3 26385 CATEGORY : VFMA 26386 EXTENSION : FMA 26387 ATTRIBUTES: MXCSR 26388 # R/M 128 26389 PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26390 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26391 # R/R 128 26392 PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26393 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26394 26395 26396 # R/M 256 26397 PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26398 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26399 # R/R 256 26400 PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26401 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26402 26403 } 26404 { 26405 ICLASS : VFMSUB231PS 26406 EXCEPTIONS: avx-type-2 26407 CPL : 3 26408 CATEGORY : VFMA 26409 EXTENSION : FMA 26410 ATTRIBUTES: MXCSR 26411 # R/M 128 26412 PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26413 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26414 # R/R 128 26415 PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26416 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26417 26418 # R/M 256 26419 PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26420 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26421 # R/R 256 26422 PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26423 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26424 26425 } 26426 { 26427 ICLASS : VFMSUB231SD 26428 EXCEPTIONS: avx-type-3 26429 CPL : 3 26430 CATEGORY : VFMA 26431 EXTENSION : FMA 26432 ATTRIBUTES: MXCSR simd_scalar 26433 # R/M 128 26434 PATTERN : VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26435 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 26436 # R/R 128 26437 PATTERN : VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26438 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 26439 26440 } 26441 { 26442 ICLASS : VFMSUB231SS 26443 EXCEPTIONS: avx-type-3 26444 CPL : 3 26445 CATEGORY : VFMA 26446 EXTENSION : FMA 26447 ATTRIBUTES: MXCSR simd_scalar 26448 # R/M 128 26449 PATTERN : VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26450 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 26451 # R/R 128 26452 PATTERN : VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26453 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 26454 26455 } 26456 26457 ################################################### 26458 26459 26460 { 26461 ICLASS : VFNMADD132PD 26462 EXCEPTIONS: avx-type-2 26463 CPL : 3 26464 CATEGORY : VFMA 26465 EXTENSION : FMA 26466 ATTRIBUTES: MXCSR 26467 # R/M 128 26468 PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26469 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26470 # R/R 128 26471 PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26472 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26473 26474 26475 # R/M 256 26476 PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26477 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26478 # R/R 256 26479 PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26480 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26481 } 26482 { 26483 ICLASS : VFNMADD132PS 26484 EXCEPTIONS: avx-type-2 26485 CPL : 3 26486 CATEGORY : VFMA 26487 EXTENSION : FMA 26488 ATTRIBUTES: MXCSR 26489 # R/M 128 26490 PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26491 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26492 # R/R 128 26493 PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26494 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26495 26496 26497 # R/M 256 26498 PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26499 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26500 # R/R 256 26501 PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26502 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26503 } 26504 { 26505 ICLASS : VFNMADD132SD 26506 EXCEPTIONS: avx-type-3 26507 CPL : 3 26508 CATEGORY : VFMA 26509 EXTENSION : FMA 26510 ATTRIBUTES: MXCSR simd_scalar 26511 # R/M 128 26512 PATTERN : VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26513 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 26514 # R/R 128 26515 PATTERN : VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26516 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 26517 } 26518 { 26519 ICLASS : VFNMADD132SS 26520 EXCEPTIONS: avx-type-3 26521 CPL : 3 26522 CATEGORY : VFMA 26523 EXTENSION : FMA 26524 ATTRIBUTES: MXCSR simd_scalar 26525 # R/M 128 26526 PATTERN : VV1 0x9D V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26527 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 26528 # R/R 128 26529 PATTERN : VV1 0x9D V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26530 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 26531 26532 } 26533 26534 { 26535 ICLASS : VFNMADD213PD 26536 EXCEPTIONS: avx-type-2 26537 CPL : 3 26538 CATEGORY : VFMA 26539 EXTENSION : FMA 26540 ATTRIBUTES: MXCSR 26541 # R/M 128 26542 PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26543 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26544 # R/R 128 26545 PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26546 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26547 26548 26549 # R/M 256 26550 PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26551 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26552 # R/R 256 26553 PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26554 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26555 } 26556 { 26557 ICLASS : VFNMADD213PS 26558 EXCEPTIONS: avx-type-2 26559 CPL : 3 26560 CATEGORY : VFMA 26561 EXTENSION : FMA 26562 ATTRIBUTES: MXCSR 26563 # R/M 128 26564 PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26565 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26566 # R/R 128 26567 PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26568 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26569 26570 26571 # R/M 256 26572 PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26573 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26574 # R/R 256 26575 PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26576 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26577 } 26578 { 26579 ICLASS : VFNMADD213SD 26580 EXCEPTIONS: avx-type-3 26581 CPL : 3 26582 CATEGORY : VFMA 26583 EXTENSION : FMA 26584 ATTRIBUTES: MXCSR simd_scalar 26585 # R/M 128 26586 PATTERN : VV1 0xAD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26587 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 26588 # R/R 128 26589 PATTERN : VV1 0xAD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26590 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 26591 26592 } 26593 { 26594 ICLASS : VFNMADD213SS 26595 EXCEPTIONS: avx-type-3 26596 CPL : 3 26597 CATEGORY : VFMA 26598 EXTENSION : FMA 26599 ATTRIBUTES: MXCSR simd_scalar 26600 # R/M 128 26601 PATTERN : VV1 0xAD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26602 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 26603 # R/R 128 26604 PATTERN : VV1 0xAD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26605 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 26606 } 26607 26608 { 26609 ICLASS : VFNMADD231PD 26610 EXCEPTIONS: avx-type-2 26611 CPL : 3 26612 CATEGORY : VFMA 26613 EXTENSION : FMA 26614 ATTRIBUTES: MXCSR 26615 # R/M 128 26616 PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26617 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26618 # R/R 128 26619 PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26620 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26621 26622 26623 # R/M 256 26624 PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26625 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26626 # R/R 256 26627 PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26628 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26629 26630 } 26631 { 26632 ICLASS : VFNMADD231PS 26633 EXCEPTIONS: avx-type-2 26634 CPL : 3 26635 CATEGORY : VFMA 26636 EXTENSION : FMA 26637 ATTRIBUTES: MXCSR 26638 # R/M 128 26639 PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26640 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26641 # R/R 128 26642 PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26643 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26644 26645 # R/M 256 26646 PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26647 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26648 # R/R 256 26649 PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26650 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26651 26652 } 26653 { 26654 ICLASS : VFNMADD231SD 26655 EXCEPTIONS: avx-type-3 26656 CPL : 3 26657 CATEGORY : VFMA 26658 EXTENSION : FMA 26659 ATTRIBUTES: MXCSR simd_scalar 26660 # R/M 128 26661 PATTERN : VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26662 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 26663 # R/R 128 26664 PATTERN : VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26665 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 26666 26667 } 26668 { 26669 ICLASS : VFNMADD231SS 26670 EXCEPTIONS: avx-type-3 26671 CPL : 3 26672 CATEGORY : VFMA 26673 EXTENSION : FMA 26674 ATTRIBUTES: MXCSR simd_scalar 26675 # R/M 128 26676 PATTERN : VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26677 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 26678 # R/R 128 26679 PATTERN : VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26680 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 26681 26682 } 26683 26684 ################################################### 26685 26686 26687 { 26688 ICLASS : VFNMSUB132PD 26689 EXCEPTIONS: avx-type-2 26690 CPL : 3 26691 CATEGORY : VFMA 26692 EXTENSION : FMA 26693 ATTRIBUTES: MXCSR 26694 # R/M 128 26695 PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26696 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26697 # R/R 128 26698 PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26699 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26700 26701 26702 # R/M 256 26703 PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26704 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26705 # R/R 256 26706 PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26707 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26708 } 26709 { 26710 ICLASS : VFNMSUB132PS 26711 EXCEPTIONS: avx-type-2 26712 CPL : 3 26713 CATEGORY : VFMA 26714 EXTENSION : FMA 26715 ATTRIBUTES: MXCSR 26716 # R/M 128 26717 PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26718 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26719 # R/R 128 26720 PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26721 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26722 26723 26724 # R/M 256 26725 PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26726 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26727 # R/R 256 26728 PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26729 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26730 } 26731 { 26732 ICLASS : VFNMSUB132SD 26733 EXCEPTIONS: avx-type-3 26734 CPL : 3 26735 CATEGORY : VFMA 26736 EXTENSION : FMA 26737 ATTRIBUTES: MXCSR simd_scalar 26738 # R/M 128 26739 PATTERN : VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26740 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 26741 # R/R 128 26742 PATTERN : VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26743 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 26744 } 26745 { 26746 ICLASS : VFNMSUB132SS 26747 EXCEPTIONS: avx-type-3 26748 CPL : 3 26749 CATEGORY : VFMA 26750 EXTENSION : FMA 26751 ATTRIBUTES: MXCSR simd_scalar 26752 # R/M 128 26753 PATTERN : VV1 0x9F V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26754 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 26755 # R/R 128 26756 PATTERN : VV1 0x9F V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26757 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 26758 26759 } 26760 26761 { 26762 ICLASS : VFNMSUB213PD 26763 EXCEPTIONS: avx-type-2 26764 CPL : 3 26765 CATEGORY : VFMA 26766 EXTENSION : FMA 26767 ATTRIBUTES: MXCSR 26768 # R/M 128 26769 PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26770 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26771 # R/R 128 26772 PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26773 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26774 26775 26776 # R/M 256 26777 PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26778 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26779 # R/R 256 26780 PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26781 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26782 } 26783 { 26784 ICLASS : VFNMSUB213PS 26785 EXCEPTIONS: avx-type-2 26786 CPL : 3 26787 CATEGORY : VFMA 26788 EXTENSION : FMA 26789 ATTRIBUTES: MXCSR 26790 # R/M 128 26791 PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26792 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26793 # R/R 128 26794 PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26795 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26796 26797 26798 # R/M 256 26799 PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26800 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26801 # R/R 256 26802 PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26803 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26804 } 26805 { 26806 ICLASS : VFNMSUB213SD 26807 EXCEPTIONS: avx-type-3 26808 CPL : 3 26809 CATEGORY : VFMA 26810 EXTENSION : FMA 26811 ATTRIBUTES: MXCSR simd_scalar 26812 # R/M 128 26813 PATTERN : VV1 0xAF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26814 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 26815 # R/R 128 26816 PATTERN : VV1 0xAF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26817 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 26818 26819 } 26820 { 26821 ICLASS : VFNMSUB213SS 26822 EXCEPTIONS: avx-type-3 26823 CPL : 3 26824 CATEGORY : VFMA 26825 EXTENSION : FMA 26826 ATTRIBUTES: MXCSR simd_scalar 26827 # R/M 128 26828 PATTERN : VV1 0xAF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26829 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 26830 # R/R 128 26831 PATTERN : VV1 0xAF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26832 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 26833 } 26834 26835 { 26836 ICLASS : VFNMSUB231PD 26837 EXCEPTIONS: avx-type-2 26838 CPL : 3 26839 CATEGORY : VFMA 26840 EXTENSION : FMA 26841 ATTRIBUTES: MXCSR 26842 # R/M 128 26843 PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26844 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 26845 # R/R 128 26846 PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26847 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 26848 26849 26850 # R/M 256 26851 PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26852 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 26853 # R/R 256 26854 PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26855 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 26856 26857 } 26858 { 26859 ICLASS : VFNMSUB231PS 26860 EXCEPTIONS: avx-type-2 26861 CPL : 3 26862 CATEGORY : VFMA 26863 EXTENSION : FMA 26864 ATTRIBUTES: MXCSR 26865 # R/M 128 26866 PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26867 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 26868 # R/R 128 26869 PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26870 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 26871 26872 # R/M 256 26873 PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26874 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 26875 # R/R 256 26876 PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26877 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 26878 26879 } 26880 { 26881 ICLASS : VFNMSUB231SD 26882 EXCEPTIONS: avx-type-3 26883 CPL : 3 26884 CATEGORY : VFMA 26885 EXTENSION : FMA 26886 ATTRIBUTES: MXCSR simd_scalar 26887 # R/M 128 26888 PATTERN : VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26889 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 26890 # R/R 128 26891 PATTERN : VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26892 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 26893 26894 } 26895 { 26896 ICLASS : VFNMSUB231SS 26897 EXCEPTIONS: avx-type-3 26898 CPL : 3 26899 CATEGORY : VFMA 26900 EXTENSION : FMA 26901 ATTRIBUTES: MXCSR simd_scalar 26902 # R/M 128 26903 PATTERN : VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 26904 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 26905 # R/R 128 26906 PATTERN : VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 26907 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 26908 26909 } 26910 26911 ################################################### 26912 26913 26914 26915 26916 26917 26918 ###FILE: ../xed/datafiles/bdw/lin2.xed.txt 26919 26920 #BEGIN_LEGAL 26921 # 26922 #Copyright (c) 2016 Intel Corporation 26923 # 26924 # Licensed under the Apache License, Version 2.0 (the "License"); 26925 # you may not use this file except in compliance with the License. 26926 # You may obtain a copy of the License at 26927 # 26928 # http://www.apache.org/licenses/LICENSE-2.0 26929 # 26930 # Unless required by applicable law or agreed to in writing, software 26931 # distributed under the License is distributed on an "AS IS" BASIS, 26932 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26933 # See the License for the specific language governing permissions and 26934 # limitations under the License. 26935 # 26936 #END_LEGAL 26937 INSTRUCTIONS():: 26938 26939 { 26940 ICLASS : ADCX 26941 CPL : 3 26942 CATEGORY : BDW 26943 EXTENSION : BDW 26944 FLAGS : MUST [ cf-tst cf-mod ] 26945 # reg:rw rm:r 26946 # 32b 26947 PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66() 26948 OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d 26949 PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66() 26950 OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d 26951 26952 # 64b 26953 PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W1 IMMUNE66() 26954 OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q 26955 PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 IMMUNE66() 26956 OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q 26957 } 26958 26959 26960 26961 { 26962 ICLASS : ADOX 26963 CPL : 3 26964 CATEGORY : BDW 26965 EXTENSION : BDW 26966 FLAGS : MUST [ of-tst of-mod ] 26967 # reg:rw rm:r 26968 # 32b 26969 PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66() 26970 OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d 26971 PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66() 26972 OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d 26973 26974 # 64b 26975 PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() 26976 OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q 26977 PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() 26978 OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q 26979 } 26980 26981 26982 26983 ###FILE: ../xed/datafiles/bdw/rdseed.xed.txt 26984 26985 #BEGIN_LEGAL 26986 # 26987 #Copyright (c) 2016 Intel Corporation 26988 # 26989 # Licensed under the Apache License, Version 2.0 (the "License"); 26990 # you may not use this file except in compliance with the License. 26991 # You may obtain a copy of the License at 26992 # 26993 # http://www.apache.org/licenses/LICENSE-2.0 26994 # 26995 # Unless required by applicable law or agreed to in writing, software 26996 # distributed under the License is distributed on an "AS IS" BASIS, 26997 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26998 # See the License for the specific language governing permissions and 26999 # limitations under the License. 27000 # 27001 #END_LEGAL 27002 INSTRUCTIONS():: 27003 27004 { 27005 ICLASS : RDSEED 27006 CPL : 3 27007 CATEGORY : RDSEED 27008 EXTENSION : RDSEED 27009 ISA_SET : RDSEED 27010 FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] 27011 PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining 27012 OPERANDS : REG0=GPRv_B():w 27013 } 27014 27015 27016 27017 ###FILE: ../xed/datafiles/bdw/smap.xed.txt 27018 27019 #BEGIN_LEGAL 27020 # 27021 #Copyright (c) 2016 Intel Corporation 27022 # 27023 # Licensed under the Apache License, Version 2.0 (the "License"); 27024 # you may not use this file except in compliance with the License. 27025 # You may obtain a copy of the License at 27026 # 27027 # http://www.apache.org/licenses/LICENSE-2.0 27028 # 27029 # Unless required by applicable law or agreed to in writing, software 27030 # distributed under the License is distributed on an "AS IS" BASIS, 27031 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27032 # See the License for the specific language governing permissions and 27033 # limitations under the License. 27034 # 27035 #END_LEGAL 27036 27037 INSTRUCTIONS():: 27038 27039 { 27040 ICLASS : CLAC 27041 CPL : 0 27042 CATEGORY : SMAP 27043 EXTENSION : SMAP 27044 FLAGS : MUST [ ac-0 ] 27045 # 0F 01 CA = 1100_1010 = 11_001_010 27046 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix 27047 OPERANDS : 27048 } 27049 27050 { 27051 ICLASS : STAC 27052 CPL : 0 27053 CATEGORY : SMAP 27054 EXTENSION : SMAP 27055 FLAGS : MUST [ ac-1 ] 27056 # 0F 01 CB = 1100_1011 = 11_001_011 27057 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix 27058 OPERANDS : 27059 } 27060 27061 27062 27063 ###FILE: ../xed/datafiles/sgx/sgx-isa.xed.txt 27064 27065 #BEGIN_LEGAL 27066 # 27067 #Copyright (c) 2016 Intel Corporation 27068 # 27069 # Licensed under the Apache License, Version 2.0 (the "License"); 27070 # you may not use this file except in compliance with the License. 27071 # You may obtain a copy of the License at 27072 # 27073 # http://www.apache.org/licenses/LICENSE-2.0 27074 # 27075 # Unless required by applicable law or agreed to in writing, software 27076 # distributed under the License is distributed on an "AS IS" BASIS, 27077 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27078 # See the License for the specific language governing permissions and 27079 # limitations under the License. 27080 # 27081 #END_LEGAL 27082 27083 INSTRUCTIONS():: 27084 27085 # Both read EAX 27086 # Both may read or write or r/w RBX, RCX, RDX 27087 # ENCLU 0f 01 D7 27088 # D7 = 1101 0111 27089 27090 # ENCLS 0f 01 CF 27091 # CF = 1100_1111 27092 27093 27094 27095 { 27096 ICLASS: ENCLU 27097 CPL: 3 27098 CATEGORY: SGX 27099 EXTENSION: SGX 27100 ISA_SET: SGX 27101 COMMENT: May set flags 27102 PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix 27103 OPERANDS: REG0=XED_REG_EAX:r:SUPP \ 27104 REG1=XED_REG_RBX:crw:SUPP \ 27105 REG2=XED_REG_RCX:crw:SUPP \ 27106 REG3=XED_REG_RDX:crw:SUPP 27107 } 27108 27109 { 27110 27111 ICLASS: ENCLS 27112 CPL: 0 27113 CATEGORY: SGX 27114 EXTENSION: SGX 27115 ISA_SET: SGX 27116 COMMENT: May set flags 27117 PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix 27118 OPERANDS: REG0=XED_REG_EAX:r:SUPP \ 27119 REG1=XED_REG_RBX:crw:SUPP \ 27120 REG2=XED_REG_RCX:crw:SUPP \ 27121 REG3=XED_REG_RDX:crw:SUPP 27122 27123 } 27124 27125 27126 ###FILE: ../xed/datafiles/pku/pku-isa.xed.txt 27127 27128 #BEGIN_LEGAL 27129 # 27130 #Copyright (c) 2016 Intel Corporation 27131 # 27132 # Licensed under the Apache License, Version 2.0 (the "License"); 27133 # you may not use this file except in compliance with the License. 27134 # You may obtain a copy of the License at 27135 # 27136 # http://www.apache.org/licenses/LICENSE-2.0 27137 # 27138 # Unless required by applicable law or agreed to in writing, software 27139 # distributed under the License is distributed on an "AS IS" BASIS, 27140 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27141 # See the License for the specific language governing permissions and 27142 # limitations under the License. 27143 # 27144 #END_LEGAL 27145 27146 27147 INSTRUCTIONS():: 27148 27149 { 27150 ICLASS: RDPKRU 27151 CPL: 3 27152 CATEGORY: PKU 27153 EXTENSION: PKU 27154 ISA_SET: PKU 27155 ATTRIBUTES: 27156 PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] 27157 OPERANDS: REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:r:SUPP 27158 } 27159 27160 27161 { 27162 ICLASS: WRPKRU 27163 CPL: 3 27164 CATEGORY: PKU 27165 EXTENSION: PKU 27166 ISA_SET: PKU 27167 ATTRIBUTES: 27168 PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] 27169 OPERANDS: REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP 27170 } 27171 27172 27173 27174 ###FILE: ../xed/datafiles/memory/clwb.xed.txt 27175 27176 #BEGIN_LEGAL 27177 # 27178 #Copyright (c) 2016 Intel Corporation 27179 # 27180 # Licensed under the Apache License, Version 2.0 (the "License"); 27181 # you may not use this file except in compliance with the License. 27182 # You may obtain a copy of the License at 27183 # 27184 # http://www.apache.org/licenses/LICENSE-2.0 27185 # 27186 # Unless required by applicable law or agreed to in writing, software 27187 # distributed under the License is distributed on an "AS IS" BASIS, 27188 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27189 # See the License for the specific language governing permissions and 27190 # limitations under the License. 27191 # 27192 #END_LEGAL 27193 27194 INSTRUCTIONS():: 27195 27196 { 27197 ICLASS: CLWB 27198 CPL: 3 27199 CATEGORY: CLWB 27200 EXTENSION: CLWB 27201 ISA_SET: CLWB 27202 ATTRIBUTES: PREFETCH # check TSX-friendlyness 27203 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() 27204 OPERANDS : MEM0:r:mprefetch 27205 } 27206 27207 27208 27209 27210 ###FILE: ../xed/datafiles/memory/clflushopt.xed.txt 27211 27212 #BEGIN_LEGAL 27213 # 27214 #Copyright (c) 2016 Intel Corporation 27215 # 27216 # Licensed under the Apache License, Version 2.0 (the "License"); 27217 # you may not use this file except in compliance with the License. 27218 # You may obtain a copy of the License at 27219 # 27220 # http://www.apache.org/licenses/LICENSE-2.0 27221 # 27222 # Unless required by applicable law or agreed to in writing, software 27223 # distributed under the License is distributed on an "AS IS" BASIS, 27224 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27225 # See the License for the specific language governing permissions and 27226 # limitations under the License. 27227 # 27228 #END_LEGAL 27229 27230 INSTRUCTIONS():: 27231 27232 { 27233 ICLASS: CLFLUSHOPT 27234 CPL: 3 27235 CATEGORY: CLFLUSHOPT 27236 EXTENSION: CLFLUSHOPT 27237 ISA_SET: CLFLUSHOPT 27238 ATTRIBUTES: PREFETCH # check TSX-friendlyness 27239 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM() 27240 OPERANDS : MEM0:r:mprefetch 27241 } 27242 27243 27244 27245 27246 ###FILE: ../xed/datafiles/pt/intelpt-isa.xed.txt 27247 27248 #BEGIN_LEGAL 27249 # 27250 #Copyright (c) 2016 Intel Corporation 27251 # 27252 # Licensed under the Apache License, Version 2.0 (the "License"); 27253 # you may not use this file except in compliance with the License. 27254 # You may obtain a copy of the License at 27255 # 27256 # http://www.apache.org/licenses/LICENSE-2.0 27257 # 27258 # Unless required by applicable law or agreed to in writing, software 27259 # distributed under the License is distributed on an "AS IS" BASIS, 27260 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27261 # See the License for the specific language governing permissions and 27262 # limitations under the License. 27263 # 27264 #END_LEGAL 27265 27266 27267 INSTRUCTIONS():: 27268 { 27269 ICLASS : PTWRITE 27270 CPL : 3 27271 CATEGORY : PT 27272 EXTENSION : PT 27273 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix 27274 OPERANDS : REG0=GPRy_B():r 27275 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM() 27276 OPERANDS : MEM0:r:y 27277 27278 } 27279 27280 27281 ###FILE: ../xed/datafiles/knl/knl-fixup.txt 27282 27283 #BEGIN_LEGAL 27284 # 27285 #Copyright (c) 2016 Intel Corporation 27286 # 27287 # Licensed under the Apache License, Version 2.0 (the "License"); 27288 # you may not use this file except in compliance with the License. 27289 # You may obtain a copy of the License at 27290 # 27291 # http://www.apache.org/licenses/LICENSE-2.0 27292 # 27293 # Unless required by applicable law or agreed to in writing, software 27294 # distributed under the License is distributed on an "AS IS" BASIS, 27295 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27296 # See the License for the specific language governing permissions and 27297 # limitations under the License. 27298 # 27299 #END_LEGAL 27300 27301 INSTRUCTIONS():: 27302 UDELETE : PREFETCH_RESERVED_0F0Dr2 27303 27304 27305 ###FILE: ../xed/datafiles/knl/knl-isa.xed.txt 27306 27307 #BEGIN_LEGAL 27308 # 27309 #Copyright (c) 2016 Intel Corporation 27310 # 27311 # Licensed under the Apache License, Version 2.0 (the "License"); 27312 # you may not use this file except in compliance with the License. 27313 # You may obtain a copy of the License at 27314 # 27315 # http://www.apache.org/licenses/LICENSE-2.0 27316 # 27317 # Unless required by applicable law or agreed to in writing, software 27318 # distributed under the License is distributed on an "AS IS" BASIS, 27319 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27320 # See the License for the specific language governing permissions and 27321 # limitations under the License. 27322 # 27323 #END_LEGAL 27324 # 27325 # 27326 # 27327 # ***** GENERATED FILE -- DO NOT EDIT! ***** 27328 # ***** GENERATED FILE -- DO NOT EDIT! ***** 27329 # ***** GENERATED FILE -- DO NOT EDIT! ***** 27330 # 27331 # 27332 # 27333 EVEX_INSTRUCTIONS():: 27334 # EMITTING VEXP2PD (VEXP2PD-512-1) 27335 { 27336 ICLASS: VEXP2PD 27337 CPL: 3 27338 CATEGORY: AVX512 27339 EXTENSION: AVX512EVEX 27340 ISA_SET: AVX512ER_512 27341 EXCEPTIONS: AVX512-E2 27342 REAL_OPCODE: Y 27343 ATTRIBUTES: MXCSR MASKOP_EVEX 27344 PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 27345 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 27346 IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 27347 } 27348 27349 { 27350 ICLASS: VEXP2PD 27351 CPL: 3 27352 CATEGORY: AVX512 27353 EXTENSION: AVX512EVEX 27354 ISA_SET: AVX512ER_512 27355 EXCEPTIONS: AVX512-E2 27356 REAL_OPCODE: Y 27357 ATTRIBUTES: MXCSR MASKOP_EVEX 27358 PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 27359 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 27360 IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 27361 } 27362 27363 { 27364 ICLASS: VEXP2PD 27365 CPL: 3 27366 CATEGORY: AVX512 27367 EXTENSION: AVX512EVEX 27368 ISA_SET: AVX512ER_512 27369 EXCEPTIONS: AVX512-E2 27370 REAL_OPCODE: Y 27371 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 27372 PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27373 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27374 IFORM: VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 27375 } 27376 27377 27378 # EMITTING VEXP2PS (VEXP2PS-512-1) 27379 { 27380 ICLASS: VEXP2PS 27381 CPL: 3 27382 CATEGORY: AVX512 27383 EXTENSION: AVX512EVEX 27384 ISA_SET: AVX512ER_512 27385 EXCEPTIONS: AVX512-E2 27386 REAL_OPCODE: Y 27387 ATTRIBUTES: MXCSR MASKOP_EVEX 27388 PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 27389 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 27390 IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 27391 } 27392 27393 { 27394 ICLASS: VEXP2PS 27395 CPL: 3 27396 CATEGORY: AVX512 27397 EXTENSION: AVX512EVEX 27398 ISA_SET: AVX512ER_512 27399 EXCEPTIONS: AVX512-E2 27400 REAL_OPCODE: Y 27401 ATTRIBUTES: MXCSR MASKOP_EVEX 27402 PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 27403 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 27404 IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 27405 } 27406 27407 { 27408 ICLASS: VEXP2PS 27409 CPL: 3 27410 CATEGORY: AVX512 27411 EXTENSION: AVX512EVEX 27412 ISA_SET: AVX512ER_512 27413 EXCEPTIONS: AVX512-E2 27414 REAL_OPCODE: Y 27415 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 27416 PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 27417 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27418 IFORM: VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 27419 } 27420 27421 27422 # EMITTING VGATHERPF0DPD (VGATHERPF0DPD-512-1) 27423 { 27424 ICLASS: VGATHERPF0DPD 27425 CPL: 3 27426 CATEGORY: GATHER 27427 EXTENSION: AVX512EVEX 27428 ISA_SET: AVX512PF_512 27429 EXCEPTIONS: AVX512-E12NP 27430 REAL_OPCODE: Y 27431 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 27432 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 27433 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 27434 IFORM: VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 27435 } 27436 27437 27438 # EMITTING VGATHERPF0DPS (VGATHERPF0DPS-512-1) 27439 { 27440 ICLASS: VGATHERPF0DPS 27441 CPL: 3 27442 CATEGORY: GATHER 27443 EXTENSION: AVX512EVEX 27444 ISA_SET: AVX512PF_512 27445 EXCEPTIONS: AVX512-E12NP 27446 REAL_OPCODE: Y 27447 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 27448 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 27449 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 27450 IFORM: VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 27451 } 27452 27453 27454 # EMITTING VGATHERPF0QPD (VGATHERPF0QPD-512-1) 27455 { 27456 ICLASS: VGATHERPF0QPD 27457 CPL: 3 27458 CATEGORY: GATHER 27459 EXTENSION: AVX512EVEX 27460 ISA_SET: AVX512PF_512 27461 EXCEPTIONS: AVX512-E12NP 27462 REAL_OPCODE: Y 27463 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 27464 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 27465 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 27466 IFORM: VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 27467 } 27468 27469 27470 # EMITTING VGATHERPF0QPS (VGATHERPF0QPS-512-1) 27471 { 27472 ICLASS: VGATHERPF0QPS 27473 CPL: 3 27474 CATEGORY: GATHER 27475 EXTENSION: AVX512EVEX 27476 ISA_SET: AVX512PF_512 27477 EXCEPTIONS: AVX512-E12NP 27478 REAL_OPCODE: Y 27479 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 27480 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 27481 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 27482 IFORM: VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 27483 } 27484 27485 27486 # EMITTING VGATHERPF1DPD (VGATHERPF1DPD-512-1) 27487 { 27488 ICLASS: VGATHERPF1DPD 27489 CPL: 3 27490 CATEGORY: GATHER 27491 EXTENSION: AVX512EVEX 27492 ISA_SET: AVX512PF_512 27493 EXCEPTIONS: AVX512-E12NP 27494 REAL_OPCODE: Y 27495 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 27496 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 27497 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 27498 IFORM: VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 27499 } 27500 27501 27502 # EMITTING VGATHERPF1DPS (VGATHERPF1DPS-512-1) 27503 { 27504 ICLASS: VGATHERPF1DPS 27505 CPL: 3 27506 CATEGORY: GATHER 27507 EXTENSION: AVX512EVEX 27508 ISA_SET: AVX512PF_512 27509 EXCEPTIONS: AVX512-E12NP 27510 REAL_OPCODE: Y 27511 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 27512 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 27513 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 27514 IFORM: VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 27515 } 27516 27517 27518 # EMITTING VGATHERPF1QPD (VGATHERPF1QPD-512-1) 27519 { 27520 ICLASS: VGATHERPF1QPD 27521 CPL: 3 27522 CATEGORY: GATHER 27523 EXTENSION: AVX512EVEX 27524 ISA_SET: AVX512PF_512 27525 EXCEPTIONS: AVX512-E12NP 27526 REAL_OPCODE: Y 27527 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 27528 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 27529 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 27530 IFORM: VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 27531 } 27532 27533 27534 # EMITTING VGATHERPF1QPS (VGATHERPF1QPS-512-1) 27535 { 27536 ICLASS: VGATHERPF1QPS 27537 CPL: 3 27538 CATEGORY: GATHER 27539 EXTENSION: AVX512EVEX 27540 ISA_SET: AVX512PF_512 27541 EXCEPTIONS: AVX512-E12NP 27542 REAL_OPCODE: Y 27543 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 27544 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 27545 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 27546 IFORM: VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 27547 } 27548 27549 27550 # EMITTING VRCP28PD (VRCP28PD-512-1) 27551 { 27552 ICLASS: VRCP28PD 27553 CPL: 3 27554 CATEGORY: AVX512 27555 EXTENSION: AVX512EVEX 27556 ISA_SET: AVX512ER_512 27557 EXCEPTIONS: AVX512-E2 27558 REAL_OPCODE: Y 27559 ATTRIBUTES: MXCSR MASKOP_EVEX 27560 PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 27561 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 27562 IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 27563 } 27564 27565 { 27566 ICLASS: VRCP28PD 27567 CPL: 3 27568 CATEGORY: AVX512 27569 EXTENSION: AVX512EVEX 27570 ISA_SET: AVX512ER_512 27571 EXCEPTIONS: AVX512-E2 27572 REAL_OPCODE: Y 27573 ATTRIBUTES: MXCSR MASKOP_EVEX 27574 PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 27575 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 27576 IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 27577 } 27578 27579 { 27580 ICLASS: VRCP28PD 27581 CPL: 3 27582 CATEGORY: AVX512 27583 EXTENSION: AVX512EVEX 27584 ISA_SET: AVX512ER_512 27585 EXCEPTIONS: AVX512-E2 27586 REAL_OPCODE: Y 27587 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 27588 PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27589 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27590 IFORM: VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 27591 } 27592 27593 27594 # EMITTING VRCP28PS (VRCP28PS-512-1) 27595 { 27596 ICLASS: VRCP28PS 27597 CPL: 3 27598 CATEGORY: AVX512 27599 EXTENSION: AVX512EVEX 27600 ISA_SET: AVX512ER_512 27601 EXCEPTIONS: AVX512-E2 27602 REAL_OPCODE: Y 27603 ATTRIBUTES: MXCSR MASKOP_EVEX 27604 PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 27605 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 27606 IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 27607 } 27608 27609 { 27610 ICLASS: VRCP28PS 27611 CPL: 3 27612 CATEGORY: AVX512 27613 EXTENSION: AVX512EVEX 27614 ISA_SET: AVX512ER_512 27615 EXCEPTIONS: AVX512-E2 27616 REAL_OPCODE: Y 27617 ATTRIBUTES: MXCSR MASKOP_EVEX 27618 PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 27619 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 27620 IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 27621 } 27622 27623 { 27624 ICLASS: VRCP28PS 27625 CPL: 3 27626 CATEGORY: AVX512 27627 EXTENSION: AVX512EVEX 27628 ISA_SET: AVX512ER_512 27629 EXCEPTIONS: AVX512-E2 27630 REAL_OPCODE: Y 27631 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 27632 PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 27633 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27634 IFORM: VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 27635 } 27636 27637 27638 # EMITTING VRCP28SD (VRCP28SD-128-1) 27639 { 27640 ICLASS: VRCP28SD 27641 CPL: 3 27642 CATEGORY: AVX512 27643 EXTENSION: AVX512EVEX 27644 ISA_SET: AVX512ER_SCALAR 27645 EXCEPTIONS: AVX512-E3 27646 REAL_OPCODE: Y 27647 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 27648 PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 27649 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 27650 IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 27651 } 27652 27653 { 27654 ICLASS: VRCP28SD 27655 CPL: 3 27656 CATEGORY: AVX512 27657 EXTENSION: AVX512EVEX 27658 ISA_SET: AVX512ER_SCALAR 27659 EXCEPTIONS: AVX512-E3 27660 REAL_OPCODE: Y 27661 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 27662 PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 27663 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 27664 IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 27665 } 27666 27667 { 27668 ICLASS: VRCP28SD 27669 CPL: 3 27670 CATEGORY: AVX512 27671 EXTENSION: AVX512EVEX 27672 ISA_SET: AVX512ER_SCALAR 27673 EXCEPTIONS: AVX512-E3 27674 REAL_OPCODE: Y 27675 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 27676 PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 27677 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 27678 IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER 27679 } 27680 27681 27682 # EMITTING VRCP28SS (VRCP28SS-128-1) 27683 { 27684 ICLASS: VRCP28SS 27685 CPL: 3 27686 CATEGORY: AVX512 27687 EXTENSION: AVX512EVEX 27688 ISA_SET: AVX512ER_SCALAR 27689 EXCEPTIONS: AVX512-E3 27690 REAL_OPCODE: Y 27691 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 27692 PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 27693 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 27694 IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 27695 } 27696 27697 { 27698 ICLASS: VRCP28SS 27699 CPL: 3 27700 CATEGORY: AVX512 27701 EXTENSION: AVX512EVEX 27702 ISA_SET: AVX512ER_SCALAR 27703 EXCEPTIONS: AVX512-E3 27704 REAL_OPCODE: Y 27705 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 27706 PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 27707 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 27708 IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 27709 } 27710 27711 { 27712 ICLASS: VRCP28SS 27713 CPL: 3 27714 CATEGORY: AVX512 27715 EXTENSION: AVX512EVEX 27716 ISA_SET: AVX512ER_SCALAR 27717 EXCEPTIONS: AVX512-E3 27718 REAL_OPCODE: Y 27719 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 27720 PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 27721 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 27722 IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER 27723 } 27724 27725 27726 # EMITTING VRSQRT28PD (VRSQRT28PD-512-1) 27727 { 27728 ICLASS: VRSQRT28PD 27729 CPL: 3 27730 CATEGORY: AVX512 27731 EXTENSION: AVX512EVEX 27732 ISA_SET: AVX512ER_512 27733 EXCEPTIONS: AVX512-E2 27734 REAL_OPCODE: Y 27735 ATTRIBUTES: MXCSR MASKOP_EVEX 27736 PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 27737 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 27738 IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 27739 } 27740 27741 { 27742 ICLASS: VRSQRT28PD 27743 CPL: 3 27744 CATEGORY: AVX512 27745 EXTENSION: AVX512EVEX 27746 ISA_SET: AVX512ER_512 27747 EXCEPTIONS: AVX512-E2 27748 REAL_OPCODE: Y 27749 ATTRIBUTES: MXCSR MASKOP_EVEX 27750 PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 27751 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 27752 IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 27753 } 27754 27755 { 27756 ICLASS: VRSQRT28PD 27757 CPL: 3 27758 CATEGORY: AVX512 27759 EXTENSION: AVX512EVEX 27760 ISA_SET: AVX512ER_512 27761 EXCEPTIONS: AVX512-E2 27762 REAL_OPCODE: Y 27763 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 27764 PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27765 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27766 IFORM: VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 27767 } 27768 27769 27770 # EMITTING VRSQRT28PS (VRSQRT28PS-512-1) 27771 { 27772 ICLASS: VRSQRT28PS 27773 CPL: 3 27774 CATEGORY: AVX512 27775 EXTENSION: AVX512EVEX 27776 ISA_SET: AVX512ER_512 27777 EXCEPTIONS: AVX512-E2 27778 REAL_OPCODE: Y 27779 ATTRIBUTES: MXCSR MASKOP_EVEX 27780 PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 27781 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 27782 IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 27783 } 27784 27785 { 27786 ICLASS: VRSQRT28PS 27787 CPL: 3 27788 CATEGORY: AVX512 27789 EXTENSION: AVX512EVEX 27790 ISA_SET: AVX512ER_512 27791 EXCEPTIONS: AVX512-E2 27792 REAL_OPCODE: Y 27793 ATTRIBUTES: MXCSR MASKOP_EVEX 27794 PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 27795 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 27796 IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 27797 } 27798 27799 { 27800 ICLASS: VRSQRT28PS 27801 CPL: 3 27802 CATEGORY: AVX512 27803 EXTENSION: AVX512EVEX 27804 ISA_SET: AVX512ER_512 27805 EXCEPTIONS: AVX512-E2 27806 REAL_OPCODE: Y 27807 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 27808 PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 27809 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27810 IFORM: VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 27811 } 27812 27813 27814 # EMITTING VRSQRT28SD (VRSQRT28SD-128-1) 27815 { 27816 ICLASS: VRSQRT28SD 27817 CPL: 3 27818 CATEGORY: AVX512 27819 EXTENSION: AVX512EVEX 27820 ISA_SET: AVX512ER_SCALAR 27821 EXCEPTIONS: AVX512-E3 27822 REAL_OPCODE: Y 27823 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 27824 PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 27825 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 27826 IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 27827 } 27828 27829 { 27830 ICLASS: VRSQRT28SD 27831 CPL: 3 27832 CATEGORY: AVX512 27833 EXTENSION: AVX512EVEX 27834 ISA_SET: AVX512ER_SCALAR 27835 EXCEPTIONS: AVX512-E3 27836 REAL_OPCODE: Y 27837 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 27838 PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 27839 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 27840 IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 27841 } 27842 27843 { 27844 ICLASS: VRSQRT28SD 27845 CPL: 3 27846 CATEGORY: AVX512 27847 EXTENSION: AVX512EVEX 27848 ISA_SET: AVX512ER_SCALAR 27849 EXCEPTIONS: AVX512-E3 27850 REAL_OPCODE: Y 27851 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 27852 PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 27853 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 27854 IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER 27855 } 27856 27857 27858 # EMITTING VRSQRT28SS (VRSQRT28SS-128-1) 27859 { 27860 ICLASS: VRSQRT28SS 27861 CPL: 3 27862 CATEGORY: AVX512 27863 EXTENSION: AVX512EVEX 27864 ISA_SET: AVX512ER_SCALAR 27865 EXCEPTIONS: AVX512-E3 27866 REAL_OPCODE: Y 27867 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 27868 PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 27869 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 27870 IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 27871 } 27872 27873 { 27874 ICLASS: VRSQRT28SS 27875 CPL: 3 27876 CATEGORY: AVX512 27877 EXTENSION: AVX512EVEX 27878 ISA_SET: AVX512ER_SCALAR 27879 EXCEPTIONS: AVX512-E3 27880 REAL_OPCODE: Y 27881 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 27882 PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 27883 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 27884 IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 27885 } 27886 27887 { 27888 ICLASS: VRSQRT28SS 27889 CPL: 3 27890 CATEGORY: AVX512 27891 EXTENSION: AVX512EVEX 27892 ISA_SET: AVX512ER_SCALAR 27893 EXCEPTIONS: AVX512-E3 27894 REAL_OPCODE: Y 27895 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 27896 PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 27897 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 27898 IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER 27899 } 27900 27901 27902 # EMITTING VSCATTERPF0DPD (VSCATTERPF0DPD-512-1) 27903 { 27904 ICLASS: VSCATTERPF0DPD 27905 CPL: 3 27906 CATEGORY: SCATTER 27907 EXTENSION: AVX512EVEX 27908 ISA_SET: AVX512PF_512 27909 EXCEPTIONS: AVX512-E12NP 27910 REAL_OPCODE: Y 27911 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 27912 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 27913 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 27914 IFORM: VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 27915 } 27916 27917 27918 # EMITTING VSCATTERPF0DPS (VSCATTERPF0DPS-512-1) 27919 { 27920 ICLASS: VSCATTERPF0DPS 27921 CPL: 3 27922 CATEGORY: SCATTER 27923 EXTENSION: AVX512EVEX 27924 ISA_SET: AVX512PF_512 27925 EXCEPTIONS: AVX512-E12NP 27926 REAL_OPCODE: Y 27927 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 27928 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 27929 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 27930 IFORM: VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 27931 } 27932 27933 27934 # EMITTING VSCATTERPF0QPD (VSCATTERPF0QPD-512-1) 27935 { 27936 ICLASS: VSCATTERPF0QPD 27937 CPL: 3 27938 CATEGORY: SCATTER 27939 EXTENSION: AVX512EVEX 27940 ISA_SET: AVX512PF_512 27941 EXCEPTIONS: AVX512-E12NP 27942 REAL_OPCODE: Y 27943 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 27944 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 27945 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 27946 IFORM: VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 27947 } 27948 27949 27950 # EMITTING VSCATTERPF0QPS (VSCATTERPF0QPS-512-1) 27951 { 27952 ICLASS: VSCATTERPF0QPS 27953 CPL: 3 27954 CATEGORY: SCATTER 27955 EXTENSION: AVX512EVEX 27956 ISA_SET: AVX512PF_512 27957 EXCEPTIONS: AVX512-E12NP 27958 REAL_OPCODE: Y 27959 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 27960 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 27961 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 27962 IFORM: VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 27963 } 27964 27965 27966 # EMITTING VSCATTERPF1DPD (VSCATTERPF1DPD-512-1) 27967 { 27968 ICLASS: VSCATTERPF1DPD 27969 CPL: 3 27970 CATEGORY: SCATTER 27971 EXTENSION: AVX512EVEX 27972 ISA_SET: AVX512PF_512 27973 EXCEPTIONS: AVX512-E12NP 27974 REAL_OPCODE: Y 27975 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 27976 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 27977 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 27978 IFORM: VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 27979 } 27980 27981 27982 # EMITTING VSCATTERPF1DPS (VSCATTERPF1DPS-512-1) 27983 { 27984 ICLASS: VSCATTERPF1DPS 27985 CPL: 3 27986 CATEGORY: SCATTER 27987 EXTENSION: AVX512EVEX 27988 ISA_SET: AVX512PF_512 27989 EXCEPTIONS: AVX512-E12NP 27990 REAL_OPCODE: Y 27991 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 27992 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 27993 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 27994 IFORM: VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 27995 } 27996 27997 27998 # EMITTING VSCATTERPF1QPD (VSCATTERPF1QPD-512-1) 27999 { 28000 ICLASS: VSCATTERPF1QPD 28001 CPL: 3 28002 CATEGORY: SCATTER 28003 EXTENSION: AVX512EVEX 28004 ISA_SET: AVX512PF_512 28005 EXCEPTIONS: AVX512-E12NP 28006 REAL_OPCODE: Y 28007 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 28008 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 28009 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 28010 IFORM: VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 28011 } 28012 28013 28014 # EMITTING VSCATTERPF1QPS (VSCATTERPF1QPS-512-1) 28015 { 28016 ICLASS: VSCATTERPF1QPS 28017 CPL: 3 28018 CATEGORY: SCATTER 28019 EXTENSION: AVX512EVEX 28020 ISA_SET: AVX512PF_512 28021 EXCEPTIONS: AVX512-E12NP 28022 REAL_OPCODE: Y 28023 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 28024 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 28025 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 28026 IFORM: VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 28027 } 28028 28029 28030 INSTRUCTIONS():: 28031 # EMITTING PREFETCHWT1 (PREFETCHWT1-N/A-1) 28032 { 28033 ICLASS: PREFETCHWT1 28034 CPL: 3 28035 CATEGORY: AVX512 28036 EXTENSION: PREFETCHWT1 28037 ISA_SET: PREFETCHWT1 28038 REAL_OPCODE: Y 28039 ATTRIBUTES: PREFETCH 28040 PATTERN: 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 28041 OPERANDS: MEM0:r:b:u8 28042 IFORM: PREFETCHWT1_MEMu8 28043 } 28044 28045 28046 28047 28048 ###FILE: ../xed/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt 28049 28050 #BEGIN_LEGAL 28051 # 28052 #Copyright (c) 2016 Intel Corporation 28053 # 28054 # Licensed under the Apache License, Version 2.0 (the "License"); 28055 # you may not use this file except in compliance with the License. 28056 # You may obtain a copy of the License at 28057 # 28058 # http://www.apache.org/licenses/LICENSE-2.0 28059 # 28060 # Unless required by applicable law or agreed to in writing, software 28061 # distributed under the License is distributed on an "AS IS" BASIS, 28062 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28063 # See the License for the specific language governing permissions and 28064 # limitations under the License. 28065 # 28066 #END_LEGAL 28067 # 28068 # 28069 # 28070 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28071 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28072 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28073 # 28074 # 28075 # 28076 EVEX_INSTRUCTIONS():: 28077 # EMITTING V4FMADDPS (V4FMADDPS-512-1) 28078 { 28079 ICLASS: V4FMADDPS 28080 CPL: 3 28081 CATEGORY: AVX512_4FMAPS 28082 EXTENSION: AVX512EVEX 28083 ISA_SET: AVX512_4FMAPS_512 28084 EXCEPTIONS: AVX512-E2 28085 REAL_OPCODE: Y 28086 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX 28087 PATTERN: EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 28088 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 28089 IFORM: V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 28090 } 28091 28092 28093 # EMITTING V4FMADDSS (V4FMADDSS-128-1) 28094 { 28095 ICLASS: V4FMADDSS 28096 CPL: 3 28097 CATEGORY: AVX512_4FMAPS 28098 EXTENSION: AVX512EVEX 28099 ISA_SET: AVX512_4FMAPS_SCALAR 28100 EXCEPTIONS: AVX512-E2 28101 REAL_OPCODE: Y 28102 ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR 28103 PATTERN: EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 28104 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 28105 IFORM: V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 28106 } 28107 28108 28109 # EMITTING V4FNMADDPS (V4FNMADDPS-512-1) 28110 { 28111 ICLASS: V4FNMADDPS 28112 CPL: 3 28113 CATEGORY: AVX512_4FMAPS 28114 EXTENSION: AVX512EVEX 28115 ISA_SET: AVX512_4FMAPS_512 28116 EXCEPTIONS: AVX512-E2 28117 REAL_OPCODE: Y 28118 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX 28119 PATTERN: EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 28120 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 28121 IFORM: V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 28122 } 28123 28124 28125 # EMITTING V4FNMADDSS (V4FNMADDSS-128-1) 28126 { 28127 ICLASS: V4FNMADDSS 28128 CPL: 3 28129 CATEGORY: AVX512_4FMAPS 28130 EXTENSION: AVX512EVEX 28131 ISA_SET: AVX512_4FMAPS_SCALAR 28132 EXCEPTIONS: AVX512-E2 28133 REAL_OPCODE: Y 28134 ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR 28135 PATTERN: EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 28136 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 28137 IFORM: V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 28138 } 28139 28140 28141 28142 28143 ###FILE: ../xed/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt 28144 28145 #BEGIN_LEGAL 28146 # 28147 #Copyright (c) 2016 Intel Corporation 28148 # 28149 # Licensed under the Apache License, Version 2.0 (the "License"); 28150 # you may not use this file except in compliance with the License. 28151 # You may obtain a copy of the License at 28152 # 28153 # http://www.apache.org/licenses/LICENSE-2.0 28154 # 28155 # Unless required by applicable law or agreed to in writing, software 28156 # distributed under the License is distributed on an "AS IS" BASIS, 28157 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28158 # See the License for the specific language governing permissions and 28159 # limitations under the License. 28160 # 28161 #END_LEGAL 28162 # 28163 # 28164 # 28165 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28166 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28167 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28168 # 28169 # 28170 # 28171 EVEX_INSTRUCTIONS():: 28172 # EMITTING VP4DPWSSD (VP4DPWSSD-512-1) 28173 { 28174 ICLASS: VP4DPWSSD 28175 CPL: 3 28176 CATEGORY: AVX512_4VNNIW 28177 EXTENSION: AVX512EVEX 28178 ISA_SET: AVX512_4VNNIW_512 28179 EXCEPTIONS: AVX512-E4 28180 REAL_OPCODE: Y 28181 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX 28182 PATTERN: EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 28183 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 28184 IFORM: VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 28185 } 28186 28187 28188 # EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1) 28189 { 28190 ICLASS: VP4DPWSSDS 28191 CPL: 3 28192 CATEGORY: AVX512_4VNNIW 28193 EXTENSION: AVX512EVEX 28194 ISA_SET: AVX512_4VNNIW_512 28195 EXCEPTIONS: AVX512-E4 28196 REAL_OPCODE: Y 28197 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX 28198 PATTERN: EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 28199 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 28200 IFORM: VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 28201 } 28202 28203 28204 28205 28206 ###FILE: ../xed/datafiles/vpopcntdq-512/vpopcntdq-512-isa.xed.txt 28207 28208 #BEGIN_LEGAL 28209 # 28210 #Copyright (c) 2016 Intel Corporation 28211 # 28212 # Licensed under the Apache License, Version 2.0 (the "License"); 28213 # you may not use this file except in compliance with the License. 28214 # You may obtain a copy of the License at 28215 # 28216 # http://www.apache.org/licenses/LICENSE-2.0 28217 # 28218 # Unless required by applicable law or agreed to in writing, software 28219 # distributed under the License is distributed on an "AS IS" BASIS, 28220 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28221 # See the License for the specific language governing permissions and 28222 # limitations under the License. 28223 # 28224 #END_LEGAL 28225 # 28226 # 28227 # 28228 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28229 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28230 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28231 # 28232 # 28233 # 28234 EVEX_INSTRUCTIONS():: 28235 # EMITTING VPOPCNTD (VPOPCNTD-512-1) 28236 { 28237 ICLASS: VPOPCNTD 28238 CPL: 3 28239 CATEGORY: AVX512 28240 EXTENSION: AVX512EVEX 28241 ISA_SET: AVX512_VPOPCNTDQ_512 28242 EXCEPTIONS: AVX512-E4 28243 REAL_OPCODE: Y 28244 ATTRIBUTES: MASKOP_EVEX 28245 PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 28246 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 28247 IFORM: VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 28248 } 28249 28250 { 28251 ICLASS: VPOPCNTD 28252 CPL: 3 28253 CATEGORY: AVX512 28254 EXTENSION: AVX512EVEX 28255 ISA_SET: AVX512_VPOPCNTDQ_512 28256 EXCEPTIONS: AVX512-E4 28257 REAL_OPCODE: Y 28258 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 28259 PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 28260 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 28261 IFORM: VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 28262 } 28263 28264 28265 # EMITTING VPOPCNTQ (VPOPCNTQ-512-1) 28266 { 28267 ICLASS: VPOPCNTQ 28268 CPL: 3 28269 CATEGORY: AVX512 28270 EXTENSION: AVX512EVEX 28271 ISA_SET: AVX512_VPOPCNTDQ_512 28272 EXCEPTIONS: AVX512-E4 28273 REAL_OPCODE: Y 28274 ATTRIBUTES: MASKOP_EVEX 28275 PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 28276 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 28277 IFORM: VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 28278 } 28279 28280 { 28281 ICLASS: VPOPCNTQ 28282 CPL: 3 28283 CATEGORY: AVX512 28284 EXTENSION: AVX512EVEX 28285 ISA_SET: AVX512_VPOPCNTDQ_512 28286 EXCEPTIONS: AVX512-E4 28287 REAL_OPCODE: Y 28288 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 28289 PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28290 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 28291 IFORM: VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 28292 } 28293 28294 28295 28296 28297 ###FILE: ../xed/datafiles/avx512f/avx512-foundation-isa.xed.txt 28298 28299 #BEGIN_LEGAL 28300 # 28301 #Copyright (c) 2016 Intel Corporation 28302 # 28303 # Licensed under the Apache License, Version 2.0 (the "License"); 28304 # you may not use this file except in compliance with the License. 28305 # You may obtain a copy of the License at 28306 # 28307 # http://www.apache.org/licenses/LICENSE-2.0 28308 # 28309 # Unless required by applicable law or agreed to in writing, software 28310 # distributed under the License is distributed on an "AS IS" BASIS, 28311 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28312 # See the License for the specific language governing permissions and 28313 # limitations under the License. 28314 # 28315 #END_LEGAL 28316 # 28317 # 28318 # 28319 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28320 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28321 # ***** GENERATED FILE -- DO NOT EDIT! ***** 28322 # 28323 # 28324 # 28325 EVEX_INSTRUCTIONS():: 28326 # EMITTING VADDPD (VADDPD-512-1) 28327 { 28328 ICLASS: VADDPD 28329 CPL: 3 28330 CATEGORY: AVX512 28331 EXTENSION: AVX512EVEX 28332 ISA_SET: AVX512F_512 28333 EXCEPTIONS: AVX512-E2 28334 REAL_OPCODE: Y 28335 ATTRIBUTES: MXCSR MASKOP_EVEX 28336 PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 28337 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 28338 IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 28339 } 28340 28341 { 28342 ICLASS: VADDPD 28343 CPL: 3 28344 CATEGORY: AVX512 28345 EXTENSION: AVX512EVEX 28346 ISA_SET: AVX512F_512 28347 EXCEPTIONS: AVX512-E2 28348 REAL_OPCODE: Y 28349 ATTRIBUTES: MXCSR MASKOP_EVEX 28350 PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 28351 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 28352 IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 28353 } 28354 28355 { 28356 ICLASS: VADDPD 28357 CPL: 3 28358 CATEGORY: AVX512 28359 EXTENSION: AVX512EVEX 28360 ISA_SET: AVX512F_512 28361 EXCEPTIONS: AVX512-E2 28362 REAL_OPCODE: Y 28363 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 28364 PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 28365 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 28366 IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 28367 } 28368 28369 28370 # EMITTING VADDPS (VADDPS-512-1) 28371 { 28372 ICLASS: VADDPS 28373 CPL: 3 28374 CATEGORY: AVX512 28375 EXTENSION: AVX512EVEX 28376 ISA_SET: AVX512F_512 28377 EXCEPTIONS: AVX512-E2 28378 REAL_OPCODE: Y 28379 ATTRIBUTES: MXCSR MASKOP_EVEX 28380 PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 28381 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 28382 IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 28383 } 28384 28385 { 28386 ICLASS: VADDPS 28387 CPL: 3 28388 CATEGORY: AVX512 28389 EXTENSION: AVX512EVEX 28390 ISA_SET: AVX512F_512 28391 EXCEPTIONS: AVX512-E2 28392 REAL_OPCODE: Y 28393 ATTRIBUTES: MXCSR MASKOP_EVEX 28394 PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 28395 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 28396 IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 28397 } 28398 28399 { 28400 ICLASS: VADDPS 28401 CPL: 3 28402 CATEGORY: AVX512 28403 EXTENSION: AVX512EVEX 28404 ISA_SET: AVX512F_512 28405 EXCEPTIONS: AVX512-E2 28406 REAL_OPCODE: Y 28407 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 28408 PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 28409 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 28410 IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 28411 } 28412 28413 28414 # EMITTING VADDSD (VADDSD-128-1) 28415 { 28416 ICLASS: VADDSD 28417 CPL: 3 28418 CATEGORY: AVX512 28419 EXTENSION: AVX512EVEX 28420 ISA_SET: AVX512F_SCALAR 28421 EXCEPTIONS: AVX512-E3 28422 REAL_OPCODE: Y 28423 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 28424 PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 28425 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 28426 IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 28427 } 28428 28429 { 28430 ICLASS: VADDSD 28431 CPL: 3 28432 CATEGORY: AVX512 28433 EXTENSION: AVX512EVEX 28434 ISA_SET: AVX512F_SCALAR 28435 EXCEPTIONS: AVX512-E3 28436 REAL_OPCODE: Y 28437 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 28438 PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 28439 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 28440 IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 28441 } 28442 28443 { 28444 ICLASS: VADDSD 28445 CPL: 3 28446 CATEGORY: AVX512 28447 EXTENSION: AVX512EVEX 28448 ISA_SET: AVX512F_SCALAR 28449 EXCEPTIONS: AVX512-E3 28450 REAL_OPCODE: Y 28451 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 28452 PATTERN: EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 28453 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 28454 IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 28455 } 28456 28457 28458 # EMITTING VADDSS (VADDSS-128-1) 28459 { 28460 ICLASS: VADDSS 28461 CPL: 3 28462 CATEGORY: AVX512 28463 EXTENSION: AVX512EVEX 28464 ISA_SET: AVX512F_SCALAR 28465 EXCEPTIONS: AVX512-E3 28466 REAL_OPCODE: Y 28467 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 28468 PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 28469 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 28470 IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 28471 } 28472 28473 { 28474 ICLASS: VADDSS 28475 CPL: 3 28476 CATEGORY: AVX512 28477 EXTENSION: AVX512EVEX 28478 ISA_SET: AVX512F_SCALAR 28479 EXCEPTIONS: AVX512-E3 28480 REAL_OPCODE: Y 28481 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 28482 PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 28483 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 28484 IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 28485 } 28486 28487 { 28488 ICLASS: VADDSS 28489 CPL: 3 28490 CATEGORY: AVX512 28491 EXTENSION: AVX512EVEX 28492 ISA_SET: AVX512F_SCALAR 28493 EXCEPTIONS: AVX512-E3 28494 REAL_OPCODE: Y 28495 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 28496 PATTERN: EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 28497 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 28498 IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 28499 } 28500 28501 28502 # EMITTING VALIGND (VALIGND-512-1) 28503 { 28504 ICLASS: VALIGND 28505 CPL: 3 28506 CATEGORY: AVX512 28507 EXTENSION: AVX512EVEX 28508 ISA_SET: AVX512F_512 28509 EXCEPTIONS: AVX512-E4NF 28510 REAL_OPCODE: Y 28511 ATTRIBUTES: MASKOP_EVEX 28512 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 28513 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b 28514 IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 28515 } 28516 28517 { 28518 ICLASS: VALIGND 28519 CPL: 3 28520 CATEGORY: AVX512 28521 EXTENSION: AVX512EVEX 28522 ISA_SET: AVX512F_512 28523 EXCEPTIONS: AVX512-E4NF 28524 REAL_OPCODE: Y 28525 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 28526 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 28527 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 28528 IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 28529 } 28530 28531 28532 # EMITTING VALIGNQ (VALIGNQ-512-1) 28533 { 28534 ICLASS: VALIGNQ 28535 CPL: 3 28536 CATEGORY: AVX512 28537 EXTENSION: AVX512EVEX 28538 ISA_SET: AVX512F_512 28539 EXCEPTIONS: AVX512-E4NF 28540 REAL_OPCODE: Y 28541 ATTRIBUTES: MASKOP_EVEX 28542 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 28543 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b 28544 IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 28545 } 28546 28547 { 28548 ICLASS: VALIGNQ 28549 CPL: 3 28550 CATEGORY: AVX512 28551 EXTENSION: AVX512EVEX 28552 ISA_SET: AVX512F_512 28553 EXCEPTIONS: AVX512-E4NF 28554 REAL_OPCODE: Y 28555 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 28556 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 28557 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 28558 IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 28559 } 28560 28561 28562 # EMITTING VBLENDMPD (VBLENDMPD-512-1) 28563 { 28564 ICLASS: VBLENDMPD 28565 CPL: 3 28566 CATEGORY: BLEND 28567 EXTENSION: AVX512EVEX 28568 ISA_SET: AVX512F_512 28569 EXCEPTIONS: AVX512-E4 28570 REAL_OPCODE: Y 28571 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 28572 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 28573 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 28574 IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 28575 } 28576 28577 { 28578 ICLASS: VBLENDMPD 28579 CPL: 3 28580 CATEGORY: BLEND 28581 EXTENSION: AVX512EVEX 28582 ISA_SET: AVX512F_512 28583 EXCEPTIONS: AVX512-E4 28584 REAL_OPCODE: Y 28585 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 28586 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 28587 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 28588 IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 28589 } 28590 28591 28592 # EMITTING VBLENDMPS (VBLENDMPS-512-1) 28593 { 28594 ICLASS: VBLENDMPS 28595 CPL: 3 28596 CATEGORY: BLEND 28597 EXTENSION: AVX512EVEX 28598 ISA_SET: AVX512F_512 28599 EXCEPTIONS: AVX512-E4 28600 REAL_OPCODE: Y 28601 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 28602 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 28603 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 28604 IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 28605 } 28606 28607 { 28608 ICLASS: VBLENDMPS 28609 CPL: 3 28610 CATEGORY: BLEND 28611 EXTENSION: AVX512EVEX 28612 ISA_SET: AVX512F_512 28613 EXCEPTIONS: AVX512-E4 28614 REAL_OPCODE: Y 28615 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 28616 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 28617 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 28618 IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 28619 } 28620 28621 28622 # EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-512-1) 28623 { 28624 ICLASS: VBROADCASTF32X4 28625 CPL: 3 28626 CATEGORY: BROADCAST 28627 EXTENSION: AVX512EVEX 28628 ISA_SET: AVX512F_512 28629 EXCEPTIONS: AVX512-E6 28630 REAL_OPCODE: Y 28631 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 28632 PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() 28633 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO16_32 28634 IFORM: VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 28635 } 28636 28637 28638 # EMITTING VBROADCASTF64X4 (VBROADCASTF64X4-512-1) 28639 { 28640 ICLASS: VBROADCASTF64X4 28641 CPL: 3 28642 CATEGORY: BROADCAST 28643 EXTENSION: AVX512EVEX 28644 ISA_SET: AVX512F_512 28645 EXCEPTIONS: AVX512-E6 28646 REAL_OPCODE: Y 28647 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 28648 PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() 28649 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 EMX_BROADCAST_4TO8_64 28650 IFORM: VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 28651 } 28652 28653 28654 # EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-512-1) 28655 { 28656 ICLASS: VBROADCASTI32X4 28657 CPL: 3 28658 CATEGORY: BROADCAST 28659 EXTENSION: AVX512EVEX 28660 ISA_SET: AVX512F_512 28661 EXCEPTIONS: AVX512-E6 28662 REAL_OPCODE: Y 28663 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 28664 PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() 28665 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO16_32 28666 IFORM: VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 28667 } 28668 28669 28670 # EMITTING VBROADCASTI64X4 (VBROADCASTI64X4-512-1) 28671 { 28672 ICLASS: VBROADCASTI64X4 28673 CPL: 3 28674 CATEGORY: BROADCAST 28675 EXTENSION: AVX512EVEX 28676 ISA_SET: AVX512F_512 28677 EXCEPTIONS: AVX512-E6 28678 REAL_OPCODE: Y 28679 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 28680 PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() 28681 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 EMX_BROADCAST_4TO8_64 28682 IFORM: VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 28683 } 28684 28685 28686 # EMITTING VBROADCASTSD (VBROADCASTSD-512-1) 28687 { 28688 ICLASS: VBROADCASTSD 28689 CPL: 3 28690 CATEGORY: BROADCAST 28691 EXTENSION: AVX512EVEX 28692 ISA_SET: AVX512F_512 28693 EXCEPTIONS: AVX512-E6 28694 REAL_OPCODE: Y 28695 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 28696 PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() 28697 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO8_64 28698 IFORM: VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 28699 } 28700 28701 28702 # EMITTING VBROADCASTSD (VBROADCASTSD-512-2) 28703 { 28704 ICLASS: VBROADCASTSD 28705 CPL: 3 28706 CATEGORY: BROADCAST 28707 EXTENSION: AVX512EVEX 28708 ISA_SET: AVX512F_512 28709 EXCEPTIONS: AVX512-E6 28710 REAL_OPCODE: Y 28711 ATTRIBUTES: MASKOP_EVEX 28712 PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 28713 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO8_64 28714 IFORM: VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 28715 } 28716 28717 28718 # EMITTING VBROADCASTSS (VBROADCASTSS-512-1) 28719 { 28720 ICLASS: VBROADCASTSS 28721 CPL: 3 28722 CATEGORY: BROADCAST 28723 EXTENSION: AVX512EVEX 28724 ISA_SET: AVX512F_512 28725 EXCEPTIONS: AVX512-E6 28726 REAL_OPCODE: Y 28727 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 28728 PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 28729 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO16_32 28730 IFORM: VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 28731 } 28732 28733 28734 # EMITTING VBROADCASTSS (VBROADCASTSS-512-2) 28735 { 28736 ICLASS: VBROADCASTSS 28737 CPL: 3 28738 CATEGORY: BROADCAST 28739 EXTENSION: AVX512EVEX 28740 ISA_SET: AVX512F_512 28741 EXCEPTIONS: AVX512-E6 28742 REAL_OPCODE: Y 28743 ATTRIBUTES: MASKOP_EVEX 28744 PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 28745 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO16_32 28746 IFORM: VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 28747 } 28748 28749 28750 # EMITTING VCMPPD (VCMPPD-512-1) 28751 { 28752 ICLASS: VCMPPD 28753 CPL: 3 28754 CATEGORY: AVX512 28755 EXTENSION: AVX512EVEX 28756 ISA_SET: AVX512F_512 28757 EXCEPTIONS: AVX512-E2 28758 REAL_OPCODE: Y 28759 ATTRIBUTES: MXCSR MASKOP_EVEX 28760 PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() 28761 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 28762 IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 28763 } 28764 28765 { 28766 ICLASS: VCMPPD 28767 CPL: 3 28768 CATEGORY: AVX512 28769 EXTENSION: AVX512EVEX 28770 ISA_SET: AVX512F_512 28771 EXCEPTIONS: AVX512-E2 28772 REAL_OPCODE: Y 28773 ATTRIBUTES: MXCSR MASKOP_EVEX 28774 PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8() 28775 OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 28776 IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 28777 } 28778 28779 { 28780 ICLASS: VCMPPD 28781 CPL: 3 28782 CATEGORY: AVX512 28783 EXTENSION: AVX512EVEX 28784 ISA_SET: AVX512F_512 28785 EXCEPTIONS: AVX512-E2 28786 REAL_OPCODE: Y 28787 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 28788 PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 28789 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 28790 IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 28791 } 28792 28793 28794 # EMITTING VCMPPS (VCMPPS-512-1) 28795 { 28796 ICLASS: VCMPPS 28797 CPL: 3 28798 CATEGORY: AVX512 28799 EXTENSION: AVX512EVEX 28800 ISA_SET: AVX512F_512 28801 EXCEPTIONS: AVX512-E2 28802 REAL_OPCODE: Y 28803 ATTRIBUTES: MXCSR MASKOP_EVEX 28804 PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() 28805 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 28806 IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 28807 } 28808 28809 { 28810 ICLASS: VCMPPS 28811 CPL: 3 28812 CATEGORY: AVX512 28813 EXTENSION: AVX512EVEX 28814 ISA_SET: AVX512F_512 28815 EXCEPTIONS: AVX512-E2 28816 REAL_OPCODE: Y 28817 ATTRIBUTES: MXCSR MASKOP_EVEX 28818 PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() 28819 OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 28820 IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 28821 } 28822 28823 { 28824 ICLASS: VCMPPS 28825 CPL: 3 28826 CATEGORY: AVX512 28827 EXTENSION: AVX512EVEX 28828 ISA_SET: AVX512F_512 28829 EXCEPTIONS: AVX512-E2 28830 REAL_OPCODE: Y 28831 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 28832 PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 28833 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 28834 IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 28835 } 28836 28837 28838 # EMITTING VCMPSD (VCMPSD-128-1) 28839 { 28840 ICLASS: VCMPSD 28841 CPL: 3 28842 CATEGORY: AVX512 28843 EXTENSION: AVX512EVEX 28844 ISA_SET: AVX512F_SCALAR 28845 EXCEPTIONS: AVX512-E3 28846 REAL_OPCODE: Y 28847 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 28848 PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8() 28849 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 28850 IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 28851 } 28852 28853 { 28854 ICLASS: VCMPSD 28855 CPL: 3 28856 CATEGORY: AVX512 28857 EXTENSION: AVX512EVEX 28858 ISA_SET: AVX512F_SCALAR 28859 EXCEPTIONS: AVX512-E3 28860 REAL_OPCODE: Y 28861 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 28862 PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8() 28863 OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 28864 IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 28865 } 28866 28867 { 28868 ICLASS: VCMPSD 28869 CPL: 3 28870 CATEGORY: AVX512 28871 EXTENSION: AVX512EVEX 28872 ISA_SET: AVX512F_SCALAR 28873 EXCEPTIONS: AVX512-E3 28874 REAL_OPCODE: Y 28875 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 28876 PATTERN: EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 28877 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 28878 IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 28879 } 28880 28881 28882 # EMITTING VCMPSS (VCMPSS-128-1) 28883 { 28884 ICLASS: VCMPSS 28885 CPL: 3 28886 CATEGORY: AVX512 28887 EXTENSION: AVX512EVEX 28888 ISA_SET: AVX512F_SCALAR 28889 EXCEPTIONS: AVX512-E3 28890 REAL_OPCODE: Y 28891 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 28892 PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8() 28893 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 28894 IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 28895 } 28896 28897 { 28898 ICLASS: VCMPSS 28899 CPL: 3 28900 CATEGORY: AVX512 28901 EXTENSION: AVX512EVEX 28902 ISA_SET: AVX512F_SCALAR 28903 EXCEPTIONS: AVX512-E3 28904 REAL_OPCODE: Y 28905 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 28906 PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() 28907 OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 28908 IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 28909 } 28910 28911 { 28912 ICLASS: VCMPSS 28913 CPL: 3 28914 CATEGORY: AVX512 28915 EXTENSION: AVX512EVEX 28916 ISA_SET: AVX512F_SCALAR 28917 EXCEPTIONS: AVX512-E3 28918 REAL_OPCODE: Y 28919 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 28920 PATTERN: EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 28921 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 28922 IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 28923 } 28924 28925 28926 # EMITTING VCOMISD (VCOMISD-128-1) 28927 { 28928 ICLASS: VCOMISD 28929 CPL: 3 28930 CATEGORY: AVX512 28931 EXTENSION: AVX512EVEX 28932 ISA_SET: AVX512F_SCALAR 28933 EXCEPTIONS: AVX512-E3NF 28934 REAL_OPCODE: Y 28935 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 28936 ATTRIBUTES: MXCSR SIMD_SCALAR 28937 PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 28938 OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 28939 IFORM: VCOMISD_XMMf64_XMMf64_AVX512 28940 } 28941 28942 { 28943 ICLASS: VCOMISD 28944 CPL: 3 28945 CATEGORY: AVX512 28946 EXTENSION: AVX512EVEX 28947 ISA_SET: AVX512F_SCALAR 28948 EXCEPTIONS: AVX512-E3NF 28949 REAL_OPCODE: Y 28950 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 28951 ATTRIBUTES: MXCSR SIMD_SCALAR 28952 PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 28953 OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 28954 IFORM: VCOMISD_XMMf64_XMMf64_AVX512 28955 } 28956 28957 { 28958 ICLASS: VCOMISD 28959 CPL: 3 28960 CATEGORY: AVX512 28961 EXTENSION: AVX512EVEX 28962 ISA_SET: AVX512F_SCALAR 28963 EXCEPTIONS: AVX512-E3NF 28964 REAL_OPCODE: Y 28965 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 28966 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR 28967 PATTERN: EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 28968 OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 28969 IFORM: VCOMISD_XMMf64_MEMf64_AVX512 28970 } 28971 28972 28973 # EMITTING VCOMISS (VCOMISS-128-1) 28974 { 28975 ICLASS: VCOMISS 28976 CPL: 3 28977 CATEGORY: AVX512 28978 EXTENSION: AVX512EVEX 28979 ISA_SET: AVX512F_SCALAR 28980 EXCEPTIONS: AVX512-E3NF 28981 REAL_OPCODE: Y 28982 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 28983 ATTRIBUTES: MXCSR SIMD_SCALAR 28984 PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 28985 OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 28986 IFORM: VCOMISS_XMMf32_XMMf32_AVX512 28987 } 28988 28989 { 28990 ICLASS: VCOMISS 28991 CPL: 3 28992 CATEGORY: AVX512 28993 EXTENSION: AVX512EVEX 28994 ISA_SET: AVX512F_SCALAR 28995 EXCEPTIONS: AVX512-E3NF 28996 REAL_OPCODE: Y 28997 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 28998 ATTRIBUTES: MXCSR SIMD_SCALAR 28999 PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 29000 OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 29001 IFORM: VCOMISS_XMMf32_XMMf32_AVX512 29002 } 29003 29004 { 29005 ICLASS: VCOMISS 29006 CPL: 3 29007 CATEGORY: AVX512 29008 EXTENSION: AVX512EVEX 29009 ISA_SET: AVX512F_SCALAR 29010 EXCEPTIONS: AVX512-E3NF 29011 REAL_OPCODE: Y 29012 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 29013 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR 29014 PATTERN: EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() 29015 OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 29016 IFORM: VCOMISS_XMMf32_MEMf32_AVX512 29017 } 29018 29019 29020 # EMITTING VCOMPRESSPD (VCOMPRESSPD-512-1) 29021 { 29022 ICLASS: VCOMPRESSPD 29023 CPL: 3 29024 CATEGORY: COMPRESS 29025 EXTENSION: AVX512EVEX 29026 ISA_SET: AVX512F_512 29027 EXCEPTIONS: AVX512-E4 29028 REAL_OPCODE: Y 29029 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 29030 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 29031 OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 29032 IFORM: VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 29033 } 29034 29035 29036 # EMITTING VCOMPRESSPD (VCOMPRESSPD-512-2) 29037 { 29038 ICLASS: VCOMPRESSPD 29039 CPL: 3 29040 CATEGORY: COMPRESS 29041 EXTENSION: AVX512EVEX 29042 ISA_SET: AVX512F_512 29043 EXCEPTIONS: AVX512-E4 29044 REAL_OPCODE: Y 29045 ATTRIBUTES: MASKOP_EVEX 29046 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 29047 OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 29048 IFORM: VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 29049 } 29050 29051 29052 # EMITTING VCOMPRESSPS (VCOMPRESSPS-512-1) 29053 { 29054 ICLASS: VCOMPRESSPS 29055 CPL: 3 29056 CATEGORY: COMPRESS 29057 EXTENSION: AVX512EVEX 29058 ISA_SET: AVX512F_512 29059 EXCEPTIONS: AVX512-E4 29060 REAL_OPCODE: Y 29061 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 29062 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 29063 OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 29064 IFORM: VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 29065 } 29066 29067 29068 # EMITTING VCOMPRESSPS (VCOMPRESSPS-512-2) 29069 { 29070 ICLASS: VCOMPRESSPS 29071 CPL: 3 29072 CATEGORY: COMPRESS 29073 EXTENSION: AVX512EVEX 29074 ISA_SET: AVX512F_512 29075 EXCEPTIONS: AVX512-E4 29076 REAL_OPCODE: Y 29077 ATTRIBUTES: MASKOP_EVEX 29078 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 29079 OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 29080 IFORM: VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 29081 } 29082 29083 29084 # EMITTING VCVTDQ2PD (VCVTDQ2PD-512-1) 29085 { 29086 ICLASS: VCVTDQ2PD 29087 CPL: 3 29088 CATEGORY: CONVERT 29089 EXTENSION: AVX512EVEX 29090 ISA_SET: AVX512F_512 29091 EXCEPTIONS: AVX512-E5 29092 REAL_OPCODE: Y 29093 ATTRIBUTES: MASKOP_EVEX 29094 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 29095 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 29096 IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 29097 } 29098 29099 { 29100 ICLASS: VCVTDQ2PD 29101 CPL: 3 29102 CATEGORY: CONVERT 29103 EXTENSION: AVX512EVEX 29104 ISA_SET: AVX512F_512 29105 EXCEPTIONS: AVX512-E5 29106 REAL_OPCODE: Y 29107 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 29108 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 29109 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 29110 IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 29111 } 29112 29113 29114 # EMITTING VCVTDQ2PS (VCVTDQ2PS-512-1) 29115 { 29116 ICLASS: VCVTDQ2PS 29117 CPL: 3 29118 CATEGORY: CONVERT 29119 EXTENSION: AVX512EVEX 29120 ISA_SET: AVX512F_512 29121 EXCEPTIONS: AVX512-E2 29122 REAL_OPCODE: Y 29123 ATTRIBUTES: MXCSR MASKOP_EVEX 29124 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 29125 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 29126 IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 29127 } 29128 29129 { 29130 ICLASS: VCVTDQ2PS 29131 CPL: 3 29132 CATEGORY: CONVERT 29133 EXTENSION: AVX512EVEX 29134 ISA_SET: AVX512F_512 29135 EXCEPTIONS: AVX512-E2 29136 REAL_OPCODE: Y 29137 ATTRIBUTES: MXCSR MASKOP_EVEX 29138 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 29139 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 29140 IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 29141 } 29142 29143 { 29144 ICLASS: VCVTDQ2PS 29145 CPL: 3 29146 CATEGORY: CONVERT 29147 EXTENSION: AVX512EVEX 29148 ISA_SET: AVX512F_512 29149 EXCEPTIONS: AVX512-E2 29150 REAL_OPCODE: Y 29151 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 29152 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 29153 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 29154 IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 29155 } 29156 29157 29158 # EMITTING VCVTPD2DQ (VCVTPD2DQ-512-1) 29159 { 29160 ICLASS: VCVTPD2DQ 29161 CPL: 3 29162 CATEGORY: CONVERT 29163 EXTENSION: AVX512EVEX 29164 ISA_SET: AVX512F_512 29165 EXCEPTIONS: AVX512-E2 29166 REAL_OPCODE: Y 29167 ATTRIBUTES: MXCSR MASKOP_EVEX 29168 PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 29169 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 29170 IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 29171 } 29172 29173 { 29174 ICLASS: VCVTPD2DQ 29175 CPL: 3 29176 CATEGORY: CONVERT 29177 EXTENSION: AVX512EVEX 29178 ISA_SET: AVX512F_512 29179 EXCEPTIONS: AVX512-E2 29180 REAL_OPCODE: Y 29181 ATTRIBUTES: MXCSR MASKOP_EVEX 29182 PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 29183 OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 29184 IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 29185 } 29186 29187 { 29188 ICLASS: VCVTPD2DQ 29189 CPL: 3 29190 CATEGORY: CONVERT 29191 EXTENSION: AVX512EVEX 29192 ISA_SET: AVX512F_512 29193 EXCEPTIONS: AVX512-E2 29194 REAL_OPCODE: Y 29195 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 29196 PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 29197 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 29198 IFORM: VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 29199 } 29200 29201 29202 # EMITTING VCVTPD2PS (VCVTPD2PS-512-1) 29203 { 29204 ICLASS: VCVTPD2PS 29205 CPL: 3 29206 CATEGORY: CONVERT 29207 EXTENSION: AVX512EVEX 29208 ISA_SET: AVX512F_512 29209 EXCEPTIONS: AVX512-E2 29210 REAL_OPCODE: Y 29211 ATTRIBUTES: MXCSR MASKOP_EVEX 29212 PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 29213 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 29214 IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 29215 } 29216 29217 { 29218 ICLASS: VCVTPD2PS 29219 CPL: 3 29220 CATEGORY: CONVERT 29221 EXTENSION: AVX512EVEX 29222 ISA_SET: AVX512F_512 29223 EXCEPTIONS: AVX512-E2 29224 REAL_OPCODE: Y 29225 ATTRIBUTES: MXCSR MASKOP_EVEX 29226 PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 29227 OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 29228 IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 29229 } 29230 29231 { 29232 ICLASS: VCVTPD2PS 29233 CPL: 3 29234 CATEGORY: CONVERT 29235 EXTENSION: AVX512EVEX 29236 ISA_SET: AVX512F_512 29237 EXCEPTIONS: AVX512-E2 29238 REAL_OPCODE: Y 29239 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 29240 PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 29241 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 29242 IFORM: VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 29243 } 29244 29245 29246 # EMITTING VCVTPD2UDQ (VCVTPD2UDQ-512-1) 29247 { 29248 ICLASS: VCVTPD2UDQ 29249 CPL: 3 29250 CATEGORY: CONVERT 29251 EXTENSION: AVX512EVEX 29252 ISA_SET: AVX512F_512 29253 EXCEPTIONS: AVX512-E2 29254 REAL_OPCODE: Y 29255 ATTRIBUTES: MXCSR MASKOP_EVEX 29256 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 29257 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 29258 IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 29259 } 29260 29261 { 29262 ICLASS: VCVTPD2UDQ 29263 CPL: 3 29264 CATEGORY: CONVERT 29265 EXTENSION: AVX512EVEX 29266 ISA_SET: AVX512F_512 29267 EXCEPTIONS: AVX512-E2 29268 REAL_OPCODE: Y 29269 ATTRIBUTES: MXCSR MASKOP_EVEX 29270 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 29271 OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 29272 IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 29273 } 29274 29275 { 29276 ICLASS: VCVTPD2UDQ 29277 CPL: 3 29278 CATEGORY: CONVERT 29279 EXTENSION: AVX512EVEX 29280 ISA_SET: AVX512F_512 29281 EXCEPTIONS: AVX512-E2 29282 REAL_OPCODE: Y 29283 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 29284 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 29285 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 29286 IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 29287 } 29288 29289 29290 # EMITTING VCVTPH2PS (VCVTPH2PS-512-1) 29291 { 29292 ICLASS: VCVTPH2PS 29293 CPL: 3 29294 CATEGORY: CONVERT 29295 EXTENSION: AVX512EVEX 29296 ISA_SET: AVX512F_512 29297 EXCEPTIONS: AVX512-E11 29298 REAL_OPCODE: Y 29299 ATTRIBUTES: MXCSR MASKOP_EVEX 29300 PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 29301 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 29302 IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 29303 } 29304 29305 { 29306 ICLASS: VCVTPH2PS 29307 CPL: 3 29308 CATEGORY: CONVERT 29309 EXTENSION: AVX512EVEX 29310 ISA_SET: AVX512F_512 29311 EXCEPTIONS: AVX512-E11 29312 REAL_OPCODE: Y 29313 ATTRIBUTES: MXCSR MASKOP_EVEX 29314 PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 29315 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 29316 IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 29317 } 29318 29319 { 29320 ICLASS: VCVTPH2PS 29321 CPL: 3 29322 CATEGORY: CONVERT 29323 EXTENSION: AVX512EVEX 29324 ISA_SET: AVX512F_512 29325 EXCEPTIONS: AVX512-E11 29326 REAL_OPCODE: Y 29327 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 29328 PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 29329 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16 29330 IFORM: VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 29331 } 29332 29333 29334 # EMITTING VCVTPS2DQ (VCVTPS2DQ-512-1) 29335 { 29336 ICLASS: VCVTPS2DQ 29337 CPL: 3 29338 CATEGORY: CONVERT 29339 EXTENSION: AVX512EVEX 29340 ISA_SET: AVX512F_512 29341 EXCEPTIONS: AVX512-E2 29342 REAL_OPCODE: Y 29343 ATTRIBUTES: MXCSR MASKOP_EVEX 29344 PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 29345 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 29346 IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 29347 } 29348 29349 { 29350 ICLASS: VCVTPS2DQ 29351 CPL: 3 29352 CATEGORY: CONVERT 29353 EXTENSION: AVX512EVEX 29354 ISA_SET: AVX512F_512 29355 EXCEPTIONS: AVX512-E2 29356 REAL_OPCODE: Y 29357 ATTRIBUTES: MXCSR MASKOP_EVEX 29358 PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 29359 OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 29360 IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 29361 } 29362 29363 { 29364 ICLASS: VCVTPS2DQ 29365 CPL: 3 29366 CATEGORY: CONVERT 29367 EXTENSION: AVX512EVEX 29368 ISA_SET: AVX512F_512 29369 EXCEPTIONS: AVX512-E2 29370 REAL_OPCODE: Y 29371 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 29372 PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 29373 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 29374 IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 29375 } 29376 29377 29378 # EMITTING VCVTPS2PD (VCVTPS2PD-512-1) 29379 { 29380 ICLASS: VCVTPS2PD 29381 CPL: 3 29382 CATEGORY: CONVERT 29383 EXTENSION: AVX512EVEX 29384 ISA_SET: AVX512F_512 29385 EXCEPTIONS: AVX512-E3 29386 REAL_OPCODE: Y 29387 ATTRIBUTES: MXCSR MASKOP_EVEX 29388 PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 29389 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 29390 IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 29391 } 29392 29393 { 29394 ICLASS: VCVTPS2PD 29395 CPL: 3 29396 CATEGORY: CONVERT 29397 EXTENSION: AVX512EVEX 29398 ISA_SET: AVX512F_512 29399 EXCEPTIONS: AVX512-E3 29400 REAL_OPCODE: Y 29401 ATTRIBUTES: MXCSR MASKOP_EVEX 29402 PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 29403 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 29404 IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 29405 } 29406 29407 { 29408 ICLASS: VCVTPS2PD 29409 CPL: 3 29410 CATEGORY: CONVERT 29411 EXTENSION: AVX512EVEX 29412 ISA_SET: AVX512F_512 29413 EXCEPTIONS: AVX512-E3 29414 REAL_OPCODE: Y 29415 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 29416 PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 29417 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 29418 IFORM: VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 29419 } 29420 29421 29422 # EMITTING VCVTPS2PH (VCVTPS2PH-512-1) 29423 { 29424 ICLASS: VCVTPS2PH 29425 CPL: 3 29426 CATEGORY: CONVERT 29427 EXTENSION: AVX512EVEX 29428 ISA_SET: AVX512F_512 29429 EXCEPTIONS: AVX512-E11NF 29430 REAL_OPCODE: Y 29431 ATTRIBUTES: MXCSR MASKOP_EVEX 29432 PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 29433 OPERANDS: REG0=YMM_B3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b 29434 IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 29435 } 29436 29437 { 29438 ICLASS: VCVTPS2PH 29439 CPL: 3 29440 CATEGORY: CONVERT 29441 EXTENSION: AVX512EVEX 29442 ISA_SET: AVX512F_512 29443 EXCEPTIONS: AVX512-E11NF 29444 REAL_OPCODE: Y 29445 ATTRIBUTES: MXCSR MASKOP_EVEX 29446 PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() 29447 OPERANDS: REG0=YMM_B3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b 29448 IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 29449 } 29450 29451 29452 # EMITTING VCVTPS2PH (VCVTPS2PH-512-2) 29453 { 29454 ICLASS: VCVTPS2PH 29455 CPL: 3 29456 CATEGORY: CONVERT 29457 EXTENSION: AVX512EVEX 29458 ISA_SET: AVX512F_512 29459 EXCEPTIONS: AVX512-E11NF 29460 REAL_OPCODE: Y 29461 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 29462 PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() 29463 OPERANDS: MEM0:w:qq:f16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b 29464 IFORM: VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 29465 } 29466 29467 29468 # EMITTING VCVTPS2UDQ (VCVTPS2UDQ-512-1) 29469 { 29470 ICLASS: VCVTPS2UDQ 29471 CPL: 3 29472 CATEGORY: CONVERT 29473 EXTENSION: AVX512EVEX 29474 ISA_SET: AVX512F_512 29475 EXCEPTIONS: AVX512-E2 29476 REAL_OPCODE: Y 29477 ATTRIBUTES: MXCSR MASKOP_EVEX 29478 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 29479 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 29480 IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 29481 } 29482 29483 { 29484 ICLASS: VCVTPS2UDQ 29485 CPL: 3 29486 CATEGORY: CONVERT 29487 EXTENSION: AVX512EVEX 29488 ISA_SET: AVX512F_512 29489 EXCEPTIONS: AVX512-E2 29490 REAL_OPCODE: Y 29491 ATTRIBUTES: MXCSR MASKOP_EVEX 29492 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 29493 OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 29494 IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 29495 } 29496 29497 { 29498 ICLASS: VCVTPS2UDQ 29499 CPL: 3 29500 CATEGORY: CONVERT 29501 EXTENSION: AVX512EVEX 29502 ISA_SET: AVX512F_512 29503 EXCEPTIONS: AVX512-E2 29504 REAL_OPCODE: Y 29505 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 29506 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 29507 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 29508 IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 29509 } 29510 29511 29512 # EMITTING VCVTSD2SI (VCVTSD2SI-128-1) 29513 { 29514 ICLASS: VCVTSD2SI 29515 CPL: 3 29516 CATEGORY: CONVERT 29517 EXTENSION: AVX512EVEX 29518 ISA_SET: AVX512F_SCALAR 29519 EXCEPTIONS: AVX512-E3NF 29520 REAL_OPCODE: Y 29521 ATTRIBUTES: MXCSR SIMD_SCALAR 29522 PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 29523 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 29524 IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 29525 } 29526 29527 { 29528 ICLASS: VCVTSD2SI 29529 CPL: 3 29530 CATEGORY: CONVERT 29531 EXTENSION: AVX512EVEX 29532 ISA_SET: AVX512F_SCALAR 29533 EXCEPTIONS: AVX512-E3NF 29534 REAL_OPCODE: Y 29535 ATTRIBUTES: MXCSR SIMD_SCALAR 29536 PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 29537 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 29538 IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 29539 } 29540 29541 { 29542 ICLASS: VCVTSD2SI 29543 CPL: 3 29544 CATEGORY: CONVERT 29545 EXTENSION: AVX512EVEX 29546 ISA_SET: AVX512F_SCALAR 29547 EXCEPTIONS: AVX512-E3NF 29548 REAL_OPCODE: Y 29549 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 29550 PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 29551 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 29552 IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 29553 } 29554 29555 29556 # EMITTING VCVTSD2SI (VCVTSD2SI-128-2) 29557 { 29558 ICLASS: VCVTSD2SI 29559 CPL: 3 29560 CATEGORY: CONVERT 29561 EXTENSION: AVX512EVEX 29562 ISA_SET: AVX512F_SCALAR 29563 EXCEPTIONS: AVX512-E3NF 29564 REAL_OPCODE: Y 29565 ATTRIBUTES: MXCSR SIMD_SCALAR 29566 PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 29567 OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 29568 IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 29569 } 29570 29571 { 29572 ICLASS: VCVTSD2SI 29573 CPL: 3 29574 CATEGORY: CONVERT 29575 EXTENSION: AVX512EVEX 29576 ISA_SET: AVX512F_SCALAR 29577 EXCEPTIONS: AVX512-E3NF 29578 REAL_OPCODE: Y 29579 ATTRIBUTES: MXCSR SIMD_SCALAR 29580 PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 29581 OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 29582 IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 29583 } 29584 29585 { 29586 ICLASS: VCVTSD2SI 29587 CPL: 3 29588 CATEGORY: CONVERT 29589 EXTENSION: AVX512EVEX 29590 ISA_SET: AVX512F_SCALAR 29591 EXCEPTIONS: AVX512-E3NF 29592 REAL_OPCODE: Y 29593 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 29594 PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 29595 OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 29596 IFORM: VCVTSD2SI_GPR64i64_MEMf64_AVX512 29597 } 29598 29599 29600 # EMITTING VCVTSD2SS (VCVTSD2SS-128-1) 29601 { 29602 ICLASS: VCVTSD2SS 29603 CPL: 3 29604 CATEGORY: CONVERT 29605 EXTENSION: AVX512EVEX 29606 ISA_SET: AVX512F_SCALAR 29607 EXCEPTIONS: AVX512-E3 29608 REAL_OPCODE: Y 29609 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 29610 PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 29611 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 29612 IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 29613 } 29614 29615 { 29616 ICLASS: VCVTSD2SS 29617 CPL: 3 29618 CATEGORY: CONVERT 29619 EXTENSION: AVX512EVEX 29620 ISA_SET: AVX512F_SCALAR 29621 EXCEPTIONS: AVX512-E3 29622 REAL_OPCODE: Y 29623 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 29624 PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 29625 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 29626 IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 29627 } 29628 29629 { 29630 ICLASS: VCVTSD2SS 29631 CPL: 3 29632 CATEGORY: CONVERT 29633 EXTENSION: AVX512EVEX 29634 ISA_SET: AVX512F_SCALAR 29635 EXCEPTIONS: AVX512-E3 29636 REAL_OPCODE: Y 29637 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 29638 PATTERN: EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 29639 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 29640 IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 29641 } 29642 29643 29644 # EMITTING VCVTSD2USI (VCVTSD2USI-128-1) 29645 { 29646 ICLASS: VCVTSD2USI 29647 CPL: 3 29648 CATEGORY: CONVERT 29649 EXTENSION: AVX512EVEX 29650 ISA_SET: AVX512F_SCALAR 29651 EXCEPTIONS: AVX512-E3NF 29652 REAL_OPCODE: Y 29653 ATTRIBUTES: MXCSR SIMD_SCALAR 29654 PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 29655 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 29656 IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 29657 } 29658 29659 { 29660 ICLASS: VCVTSD2USI 29661 CPL: 3 29662 CATEGORY: CONVERT 29663 EXTENSION: AVX512EVEX 29664 ISA_SET: AVX512F_SCALAR 29665 EXCEPTIONS: AVX512-E3NF 29666 REAL_OPCODE: Y 29667 ATTRIBUTES: MXCSR SIMD_SCALAR 29668 PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 29669 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 29670 IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 29671 } 29672 29673 { 29674 ICLASS: VCVTSD2USI 29675 CPL: 3 29676 CATEGORY: CONVERT 29677 EXTENSION: AVX512EVEX 29678 ISA_SET: AVX512F_SCALAR 29679 EXCEPTIONS: AVX512-E3NF 29680 REAL_OPCODE: Y 29681 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 29682 PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 29683 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 29684 IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 29685 } 29686 29687 29688 # EMITTING VCVTSD2USI (VCVTSD2USI-128-2) 29689 { 29690 ICLASS: VCVTSD2USI 29691 CPL: 3 29692 CATEGORY: CONVERT 29693 EXTENSION: AVX512EVEX 29694 ISA_SET: AVX512F_SCALAR 29695 EXCEPTIONS: AVX512-E3NF 29696 REAL_OPCODE: Y 29697 ATTRIBUTES: MXCSR SIMD_SCALAR 29698 PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 29699 OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 29700 IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 29701 } 29702 29703 { 29704 ICLASS: VCVTSD2USI 29705 CPL: 3 29706 CATEGORY: CONVERT 29707 EXTENSION: AVX512EVEX 29708 ISA_SET: AVX512F_SCALAR 29709 EXCEPTIONS: AVX512-E3NF 29710 REAL_OPCODE: Y 29711 ATTRIBUTES: MXCSR SIMD_SCALAR 29712 PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 29713 OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 29714 IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 29715 } 29716 29717 { 29718 ICLASS: VCVTSD2USI 29719 CPL: 3 29720 CATEGORY: CONVERT 29721 EXTENSION: AVX512EVEX 29722 ISA_SET: AVX512F_SCALAR 29723 EXCEPTIONS: AVX512-E3NF 29724 REAL_OPCODE: Y 29725 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 29726 PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 29727 OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 29728 IFORM: VCVTSD2USI_GPR64u64_MEMf64_AVX512 29729 } 29730 29731 29732 # EMITTING VCVTSI2SD (VCVTSI2SD-128-1) 29733 { 29734 ICLASS: VCVTSI2SD 29735 CPL: 3 29736 CATEGORY: CONVERT 29737 EXTENSION: AVX512EVEX 29738 ISA_SET: AVX512F_SCALAR 29739 EXCEPTIONS: AVX512-E10NF 29740 REAL_OPCODE: Y 29741 ATTRIBUTES: SIMD_SCALAR 29742 PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 29743 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 29744 IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 29745 } 29746 29747 { 29748 ICLASS: VCVTSI2SD 29749 CPL: 3 29750 CATEGORY: CONVERT 29751 EXTENSION: AVX512EVEX 29752 ISA_SET: AVX512F_SCALAR 29753 EXCEPTIONS: AVX512-E10NF 29754 REAL_OPCODE: Y 29755 ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER 29756 PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 29757 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 29758 IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 29759 } 29760 29761 29762 # EMITTING VCVTSI2SD (VCVTSI2SD-128-2) 29763 { 29764 ICLASS: VCVTSI2SD 29765 CPL: 3 29766 CATEGORY: CONVERT 29767 EXTENSION: AVX512EVEX 29768 ISA_SET: AVX512F_SCALAR 29769 EXCEPTIONS: AVX512-E3NF 29770 REAL_OPCODE: Y 29771 ATTRIBUTES: MXCSR SIMD_SCALAR 29772 PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 29773 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 29774 IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 29775 } 29776 29777 { 29778 ICLASS: VCVTSI2SD 29779 CPL: 3 29780 CATEGORY: CONVERT 29781 EXTENSION: AVX512EVEX 29782 ISA_SET: AVX512F_SCALAR 29783 EXCEPTIONS: AVX512-E3NF 29784 REAL_OPCODE: Y 29785 ATTRIBUTES: MXCSR SIMD_SCALAR 29786 PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 29787 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 29788 IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 29789 } 29790 29791 { 29792 ICLASS: VCVTSI2SD 29793 CPL: 3 29794 CATEGORY: CONVERT 29795 EXTENSION: AVX512EVEX 29796 ISA_SET: AVX512F_SCALAR 29797 EXCEPTIONS: AVX512-E3NF 29798 REAL_OPCODE: Y 29799 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 29800 PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() 29801 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64 29802 IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 29803 } 29804 29805 29806 # EMITTING VCVTSI2SS (VCVTSI2SS-128-1) 29807 { 29808 ICLASS: VCVTSI2SS 29809 CPL: 3 29810 CATEGORY: CONVERT 29811 EXTENSION: AVX512EVEX 29812 ISA_SET: AVX512F_SCALAR 29813 EXCEPTIONS: AVX512-E3NF 29814 REAL_OPCODE: Y 29815 ATTRIBUTES: MXCSR SIMD_SCALAR 29816 PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 29817 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 29818 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 29819 } 29820 29821 { 29822 ICLASS: VCVTSI2SS 29823 CPL: 3 29824 CATEGORY: CONVERT 29825 EXTENSION: AVX512EVEX 29826 ISA_SET: AVX512F_SCALAR 29827 EXCEPTIONS: AVX512-E3NF 29828 REAL_OPCODE: Y 29829 ATTRIBUTES: MXCSR SIMD_SCALAR 29830 PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 ZEROING=0 MASK=0 29831 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 29832 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 29833 } 29834 29835 { 29836 ICLASS: VCVTSI2SS 29837 CPL: 3 29838 CATEGORY: CONVERT 29839 EXTENSION: AVX512EVEX 29840 ISA_SET: AVX512F_SCALAR 29841 EXCEPTIONS: AVX512-E3NF 29842 REAL_OPCODE: Y 29843 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 29844 PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 29845 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 29846 IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 29847 } 29848 29849 29850 # EMITTING VCVTSI2SS (VCVTSI2SS-128-2) 29851 { 29852 ICLASS: VCVTSI2SS 29853 CPL: 3 29854 CATEGORY: CONVERT 29855 EXTENSION: AVX512EVEX 29856 ISA_SET: AVX512F_SCALAR 29857 EXCEPTIONS: AVX512-E3NF 29858 REAL_OPCODE: Y 29859 ATTRIBUTES: MXCSR SIMD_SCALAR 29860 PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 29861 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 29862 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 29863 } 29864 29865 { 29866 ICLASS: VCVTSI2SS 29867 CPL: 3 29868 CATEGORY: CONVERT 29869 EXTENSION: AVX512EVEX 29870 ISA_SET: AVX512F_SCALAR 29871 EXCEPTIONS: AVX512-E3NF 29872 REAL_OPCODE: Y 29873 ATTRIBUTES: MXCSR SIMD_SCALAR 29874 PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 29875 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 29876 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 29877 } 29878 29879 { 29880 ICLASS: VCVTSI2SS 29881 CPL: 3 29882 CATEGORY: CONVERT 29883 EXTENSION: AVX512EVEX 29884 ISA_SET: AVX512F_SCALAR 29885 EXCEPTIONS: AVX512-E3NF 29886 REAL_OPCODE: Y 29887 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 29888 PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() 29889 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64 29890 IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 29891 } 29892 29893 29894 # EMITTING VCVTSS2SD (VCVTSS2SD-128-1) 29895 { 29896 ICLASS: VCVTSS2SD 29897 CPL: 3 29898 CATEGORY: CONVERT 29899 EXTENSION: AVX512EVEX 29900 ISA_SET: AVX512F_SCALAR 29901 EXCEPTIONS: AVX512-E3 29902 REAL_OPCODE: Y 29903 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 29904 PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 29905 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 29906 IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 29907 } 29908 29909 { 29910 ICLASS: VCVTSS2SD 29911 CPL: 3 29912 CATEGORY: CONVERT 29913 EXTENSION: AVX512EVEX 29914 ISA_SET: AVX512F_SCALAR 29915 EXCEPTIONS: AVX512-E3 29916 REAL_OPCODE: Y 29917 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 29918 PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 29919 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 29920 IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 29921 } 29922 29923 { 29924 ICLASS: VCVTSS2SD 29925 CPL: 3 29926 CATEGORY: CONVERT 29927 EXTENSION: AVX512EVEX 29928 ISA_SET: AVX512F_SCALAR 29929 EXCEPTIONS: AVX512-E3 29930 REAL_OPCODE: Y 29931 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 29932 PATTERN: EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 29933 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 29934 IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 29935 } 29936 29937 29938 # EMITTING VCVTSS2SI (VCVTSS2SI-128-1) 29939 { 29940 ICLASS: VCVTSS2SI 29941 CPL: 3 29942 CATEGORY: CONVERT 29943 EXTENSION: AVX512EVEX 29944 ISA_SET: AVX512F_SCALAR 29945 EXCEPTIONS: AVX512-E3NF 29946 REAL_OPCODE: Y 29947 ATTRIBUTES: MXCSR SIMD_SCALAR 29948 PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 29949 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 29950 IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 29951 } 29952 29953 { 29954 ICLASS: VCVTSS2SI 29955 CPL: 3 29956 CATEGORY: CONVERT 29957 EXTENSION: AVX512EVEX 29958 ISA_SET: AVX512F_SCALAR 29959 EXCEPTIONS: AVX512-E3NF 29960 REAL_OPCODE: Y 29961 ATTRIBUTES: MXCSR SIMD_SCALAR 29962 PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 29963 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 29964 IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 29965 } 29966 29967 { 29968 ICLASS: VCVTSS2SI 29969 CPL: 3 29970 CATEGORY: CONVERT 29971 EXTENSION: AVX512EVEX 29972 ISA_SET: AVX512F_SCALAR 29973 EXCEPTIONS: AVX512-E3NF 29974 REAL_OPCODE: Y 29975 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 29976 PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 29977 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 29978 IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 29979 } 29980 29981 29982 # EMITTING VCVTSS2SI (VCVTSS2SI-128-2) 29983 { 29984 ICLASS: VCVTSS2SI 29985 CPL: 3 29986 CATEGORY: CONVERT 29987 EXTENSION: AVX512EVEX 29988 ISA_SET: AVX512F_SCALAR 29989 EXCEPTIONS: AVX512-E3NF 29990 REAL_OPCODE: Y 29991 ATTRIBUTES: MXCSR SIMD_SCALAR 29992 PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 29993 OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 29994 IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 29995 } 29996 29997 { 29998 ICLASS: VCVTSS2SI 29999 CPL: 3 30000 CATEGORY: CONVERT 30001 EXTENSION: AVX512EVEX 30002 ISA_SET: AVX512F_SCALAR 30003 EXCEPTIONS: AVX512-E3NF 30004 REAL_OPCODE: Y 30005 ATTRIBUTES: MXCSR SIMD_SCALAR 30006 PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 30007 OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 30008 IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 30009 } 30010 30011 { 30012 ICLASS: VCVTSS2SI 30013 CPL: 3 30014 CATEGORY: CONVERT 30015 EXTENSION: AVX512EVEX 30016 ISA_SET: AVX512F_SCALAR 30017 EXCEPTIONS: AVX512-E3NF 30018 REAL_OPCODE: Y 30019 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 30020 PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 30021 OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 30022 IFORM: VCVTSS2SI_GPR64i64_MEMf32_AVX512 30023 } 30024 30025 30026 # EMITTING VCVTSS2USI (VCVTSS2USI-128-1) 30027 { 30028 ICLASS: VCVTSS2USI 30029 CPL: 3 30030 CATEGORY: CONVERT 30031 EXTENSION: AVX512EVEX 30032 ISA_SET: AVX512F_SCALAR 30033 EXCEPTIONS: AVX512-E3NF 30034 REAL_OPCODE: Y 30035 ATTRIBUTES: MXCSR SIMD_SCALAR 30036 PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 30037 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 30038 IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 30039 } 30040 30041 { 30042 ICLASS: VCVTSS2USI 30043 CPL: 3 30044 CATEGORY: CONVERT 30045 EXTENSION: AVX512EVEX 30046 ISA_SET: AVX512F_SCALAR 30047 EXCEPTIONS: AVX512-E3NF 30048 REAL_OPCODE: Y 30049 ATTRIBUTES: MXCSR SIMD_SCALAR 30050 PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 30051 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 30052 IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 30053 } 30054 30055 { 30056 ICLASS: VCVTSS2USI 30057 CPL: 3 30058 CATEGORY: CONVERT 30059 EXTENSION: AVX512EVEX 30060 ISA_SET: AVX512F_SCALAR 30061 EXCEPTIONS: AVX512-E3NF 30062 REAL_OPCODE: Y 30063 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 30064 PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 30065 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 30066 IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 30067 } 30068 30069 30070 # EMITTING VCVTSS2USI (VCVTSS2USI-128-2) 30071 { 30072 ICLASS: VCVTSS2USI 30073 CPL: 3 30074 CATEGORY: CONVERT 30075 EXTENSION: AVX512EVEX 30076 ISA_SET: AVX512F_SCALAR 30077 EXCEPTIONS: AVX512-E3NF 30078 REAL_OPCODE: Y 30079 ATTRIBUTES: MXCSR SIMD_SCALAR 30080 PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 30081 OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 30082 IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 30083 } 30084 30085 { 30086 ICLASS: VCVTSS2USI 30087 CPL: 3 30088 CATEGORY: CONVERT 30089 EXTENSION: AVX512EVEX 30090 ISA_SET: AVX512F_SCALAR 30091 EXCEPTIONS: AVX512-E3NF 30092 REAL_OPCODE: Y 30093 ATTRIBUTES: MXCSR SIMD_SCALAR 30094 PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 30095 OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 30096 IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 30097 } 30098 30099 { 30100 ICLASS: VCVTSS2USI 30101 CPL: 3 30102 CATEGORY: CONVERT 30103 EXTENSION: AVX512EVEX 30104 ISA_SET: AVX512F_SCALAR 30105 EXCEPTIONS: AVX512-E3NF 30106 REAL_OPCODE: Y 30107 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 30108 PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 30109 OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 30110 IFORM: VCVTSS2USI_GPR64u64_MEMf32_AVX512 30111 } 30112 30113 30114 # EMITTING VCVTTPD2DQ (VCVTTPD2DQ-512-1) 30115 { 30116 ICLASS: VCVTTPD2DQ 30117 CPL: 3 30118 CATEGORY: CONVERT 30119 EXTENSION: AVX512EVEX 30120 ISA_SET: AVX512F_512 30121 EXCEPTIONS: AVX512-E2 30122 REAL_OPCODE: Y 30123 ATTRIBUTES: MXCSR MASKOP_EVEX 30124 PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 30125 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 30126 IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 30127 } 30128 30129 { 30130 ICLASS: VCVTTPD2DQ 30131 CPL: 3 30132 CATEGORY: CONVERT 30133 EXTENSION: AVX512EVEX 30134 ISA_SET: AVX512F_512 30135 EXCEPTIONS: AVX512-E2 30136 REAL_OPCODE: Y 30137 ATTRIBUTES: MXCSR MASKOP_EVEX 30138 PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 30139 OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 30140 IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 30141 } 30142 30143 { 30144 ICLASS: VCVTTPD2DQ 30145 CPL: 3 30146 CATEGORY: CONVERT 30147 EXTENSION: AVX512EVEX 30148 ISA_SET: AVX512F_512 30149 EXCEPTIONS: AVX512-E2 30150 REAL_OPCODE: Y 30151 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 30152 PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 30153 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 30154 IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 30155 } 30156 30157 30158 # EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-512-1) 30159 { 30160 ICLASS: VCVTTPD2UDQ 30161 CPL: 3 30162 CATEGORY: CONVERT 30163 EXTENSION: AVX512EVEX 30164 ISA_SET: AVX512F_512 30165 EXCEPTIONS: AVX512-E2 30166 REAL_OPCODE: Y 30167 ATTRIBUTES: MXCSR MASKOP_EVEX 30168 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 30169 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 30170 IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 30171 } 30172 30173 { 30174 ICLASS: VCVTTPD2UDQ 30175 CPL: 3 30176 CATEGORY: CONVERT 30177 EXTENSION: AVX512EVEX 30178 ISA_SET: AVX512F_512 30179 EXCEPTIONS: AVX512-E2 30180 REAL_OPCODE: Y 30181 ATTRIBUTES: MXCSR MASKOP_EVEX 30182 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 30183 OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 30184 IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 30185 } 30186 30187 { 30188 ICLASS: VCVTTPD2UDQ 30189 CPL: 3 30190 CATEGORY: CONVERT 30191 EXTENSION: AVX512EVEX 30192 ISA_SET: AVX512F_512 30193 EXCEPTIONS: AVX512-E2 30194 REAL_OPCODE: Y 30195 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 30196 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 30197 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 30198 IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 30199 } 30200 30201 30202 # EMITTING VCVTTPS2DQ (VCVTTPS2DQ-512-1) 30203 { 30204 ICLASS: VCVTTPS2DQ 30205 CPL: 3 30206 CATEGORY: CONVERT 30207 EXTENSION: AVX512EVEX 30208 ISA_SET: AVX512F_512 30209 EXCEPTIONS: AVX512-E2 30210 REAL_OPCODE: Y 30211 ATTRIBUTES: MXCSR MASKOP_EVEX 30212 PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 30213 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 30214 IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 30215 } 30216 30217 { 30218 ICLASS: VCVTTPS2DQ 30219 CPL: 3 30220 CATEGORY: CONVERT 30221 EXTENSION: AVX512EVEX 30222 ISA_SET: AVX512F_512 30223 EXCEPTIONS: AVX512-E2 30224 REAL_OPCODE: Y 30225 ATTRIBUTES: MXCSR MASKOP_EVEX 30226 PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 30227 OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 30228 IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 30229 } 30230 30231 { 30232 ICLASS: VCVTTPS2DQ 30233 CPL: 3 30234 CATEGORY: CONVERT 30235 EXTENSION: AVX512EVEX 30236 ISA_SET: AVX512F_512 30237 EXCEPTIONS: AVX512-E2 30238 REAL_OPCODE: Y 30239 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 30240 PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 30241 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 30242 IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 30243 } 30244 30245 30246 # EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-512-1) 30247 { 30248 ICLASS: VCVTTPS2UDQ 30249 CPL: 3 30250 CATEGORY: CONVERT 30251 EXTENSION: AVX512EVEX 30252 ISA_SET: AVX512F_512 30253 EXCEPTIONS: AVX512-E2 30254 REAL_OPCODE: Y 30255 ATTRIBUTES: MXCSR MASKOP_EVEX 30256 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 30257 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 30258 IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 30259 } 30260 30261 { 30262 ICLASS: VCVTTPS2UDQ 30263 CPL: 3 30264 CATEGORY: CONVERT 30265 EXTENSION: AVX512EVEX 30266 ISA_SET: AVX512F_512 30267 EXCEPTIONS: AVX512-E2 30268 REAL_OPCODE: Y 30269 ATTRIBUTES: MXCSR MASKOP_EVEX 30270 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 30271 OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 30272 IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 30273 } 30274 30275 { 30276 ICLASS: VCVTTPS2UDQ 30277 CPL: 3 30278 CATEGORY: CONVERT 30279 EXTENSION: AVX512EVEX 30280 ISA_SET: AVX512F_512 30281 EXCEPTIONS: AVX512-E2 30282 REAL_OPCODE: Y 30283 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 30284 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 30285 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 30286 IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 30287 } 30288 30289 30290 # EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1) 30291 { 30292 ICLASS: VCVTTSD2SI 30293 CPL: 3 30294 CATEGORY: CONVERT 30295 EXTENSION: AVX512EVEX 30296 ISA_SET: AVX512F_SCALAR 30297 EXCEPTIONS: AVX512-E3NF 30298 REAL_OPCODE: Y 30299 ATTRIBUTES: MXCSR SIMD_SCALAR 30300 PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 30301 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 30302 IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 30303 } 30304 30305 { 30306 ICLASS: VCVTTSD2SI 30307 CPL: 3 30308 CATEGORY: CONVERT 30309 EXTENSION: AVX512EVEX 30310 ISA_SET: AVX512F_SCALAR 30311 EXCEPTIONS: AVX512-E3NF 30312 REAL_OPCODE: Y 30313 ATTRIBUTES: MXCSR SIMD_SCALAR 30314 PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 30315 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 30316 IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 30317 } 30318 30319 { 30320 ICLASS: VCVTTSD2SI 30321 CPL: 3 30322 CATEGORY: CONVERT 30323 EXTENSION: AVX512EVEX 30324 ISA_SET: AVX512F_SCALAR 30325 EXCEPTIONS: AVX512-E3NF 30326 REAL_OPCODE: Y 30327 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 30328 PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 30329 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 30330 IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 30331 } 30332 30333 30334 # EMITTING VCVTTSD2SI (VCVTTSD2SI-128-2) 30335 { 30336 ICLASS: VCVTTSD2SI 30337 CPL: 3 30338 CATEGORY: CONVERT 30339 EXTENSION: AVX512EVEX 30340 ISA_SET: AVX512F_SCALAR 30341 EXCEPTIONS: AVX512-E3NF 30342 REAL_OPCODE: Y 30343 ATTRIBUTES: MXCSR SIMD_SCALAR 30344 PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 30345 OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 30346 IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 30347 } 30348 30349 { 30350 ICLASS: VCVTTSD2SI 30351 CPL: 3 30352 CATEGORY: CONVERT 30353 EXTENSION: AVX512EVEX 30354 ISA_SET: AVX512F_SCALAR 30355 EXCEPTIONS: AVX512-E3NF 30356 REAL_OPCODE: Y 30357 ATTRIBUTES: MXCSR SIMD_SCALAR 30358 PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 30359 OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 30360 IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 30361 } 30362 30363 { 30364 ICLASS: VCVTTSD2SI 30365 CPL: 3 30366 CATEGORY: CONVERT 30367 EXTENSION: AVX512EVEX 30368 ISA_SET: AVX512F_SCALAR 30369 EXCEPTIONS: AVX512-E3NF 30370 REAL_OPCODE: Y 30371 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 30372 PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 30373 OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 30374 IFORM: VCVTTSD2SI_GPR64i64_MEMf64_AVX512 30375 } 30376 30377 30378 # EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1) 30379 { 30380 ICLASS: VCVTTSD2USI 30381 CPL: 3 30382 CATEGORY: CONVERT 30383 EXTENSION: AVX512EVEX 30384 ISA_SET: AVX512F_SCALAR 30385 EXCEPTIONS: AVX512-E3NF 30386 REAL_OPCODE: Y 30387 ATTRIBUTES: MXCSR SIMD_SCALAR 30388 PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 30389 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 30390 IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 30391 } 30392 30393 { 30394 ICLASS: VCVTTSD2USI 30395 CPL: 3 30396 CATEGORY: CONVERT 30397 EXTENSION: AVX512EVEX 30398 ISA_SET: AVX512F_SCALAR 30399 EXCEPTIONS: AVX512-E3NF 30400 REAL_OPCODE: Y 30401 ATTRIBUTES: MXCSR SIMD_SCALAR 30402 PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 30403 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 30404 IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 30405 } 30406 30407 { 30408 ICLASS: VCVTTSD2USI 30409 CPL: 3 30410 CATEGORY: CONVERT 30411 EXTENSION: AVX512EVEX 30412 ISA_SET: AVX512F_SCALAR 30413 EXCEPTIONS: AVX512-E3NF 30414 REAL_OPCODE: Y 30415 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 30416 PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 30417 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 30418 IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 30419 } 30420 30421 30422 # EMITTING VCVTTSD2USI (VCVTTSD2USI-128-2) 30423 { 30424 ICLASS: VCVTTSD2USI 30425 CPL: 3 30426 CATEGORY: CONVERT 30427 EXTENSION: AVX512EVEX 30428 ISA_SET: AVX512F_SCALAR 30429 EXCEPTIONS: AVX512-E3NF 30430 REAL_OPCODE: Y 30431 ATTRIBUTES: MXCSR SIMD_SCALAR 30432 PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 30433 OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 30434 IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 30435 } 30436 30437 { 30438 ICLASS: VCVTTSD2USI 30439 CPL: 3 30440 CATEGORY: CONVERT 30441 EXTENSION: AVX512EVEX 30442 ISA_SET: AVX512F_SCALAR 30443 EXCEPTIONS: AVX512-E3NF 30444 REAL_OPCODE: Y 30445 ATTRIBUTES: MXCSR SIMD_SCALAR 30446 PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 30447 OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 30448 IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 30449 } 30450 30451 { 30452 ICLASS: VCVTTSD2USI 30453 CPL: 3 30454 CATEGORY: CONVERT 30455 EXTENSION: AVX512EVEX 30456 ISA_SET: AVX512F_SCALAR 30457 EXCEPTIONS: AVX512-E3NF 30458 REAL_OPCODE: Y 30459 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 30460 PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 30461 OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 30462 IFORM: VCVTTSD2USI_GPR64u64_MEMf64_AVX512 30463 } 30464 30465 30466 # EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1) 30467 { 30468 ICLASS: VCVTTSS2SI 30469 CPL: 3 30470 CATEGORY: CONVERT 30471 EXTENSION: AVX512EVEX 30472 ISA_SET: AVX512F_SCALAR 30473 EXCEPTIONS: AVX512-E3NF 30474 REAL_OPCODE: Y 30475 ATTRIBUTES: MXCSR SIMD_SCALAR 30476 PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 30477 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 30478 IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 30479 } 30480 30481 { 30482 ICLASS: VCVTTSS2SI 30483 CPL: 3 30484 CATEGORY: CONVERT 30485 EXTENSION: AVX512EVEX 30486 ISA_SET: AVX512F_SCALAR 30487 EXCEPTIONS: AVX512-E3NF 30488 REAL_OPCODE: Y 30489 ATTRIBUTES: MXCSR SIMD_SCALAR 30490 PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 30491 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 30492 IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 30493 } 30494 30495 { 30496 ICLASS: VCVTTSS2SI 30497 CPL: 3 30498 CATEGORY: CONVERT 30499 EXTENSION: AVX512EVEX 30500 ISA_SET: AVX512F_SCALAR 30501 EXCEPTIONS: AVX512-E3NF 30502 REAL_OPCODE: Y 30503 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 30504 PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 30505 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 30506 IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 30507 } 30508 30509 30510 # EMITTING VCVTTSS2SI (VCVTTSS2SI-128-2) 30511 { 30512 ICLASS: VCVTTSS2SI 30513 CPL: 3 30514 CATEGORY: CONVERT 30515 EXTENSION: AVX512EVEX 30516 ISA_SET: AVX512F_SCALAR 30517 EXCEPTIONS: AVX512-E3NF 30518 REAL_OPCODE: Y 30519 ATTRIBUTES: MXCSR SIMD_SCALAR 30520 PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 30521 OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 30522 IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 30523 } 30524 30525 { 30526 ICLASS: VCVTTSS2SI 30527 CPL: 3 30528 CATEGORY: CONVERT 30529 EXTENSION: AVX512EVEX 30530 ISA_SET: AVX512F_SCALAR 30531 EXCEPTIONS: AVX512-E3NF 30532 REAL_OPCODE: Y 30533 ATTRIBUTES: MXCSR SIMD_SCALAR 30534 PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 30535 OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 30536 IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 30537 } 30538 30539 { 30540 ICLASS: VCVTTSS2SI 30541 CPL: 3 30542 CATEGORY: CONVERT 30543 EXTENSION: AVX512EVEX 30544 ISA_SET: AVX512F_SCALAR 30545 EXCEPTIONS: AVX512-E3NF 30546 REAL_OPCODE: Y 30547 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 30548 PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 30549 OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 30550 IFORM: VCVTTSS2SI_GPR64i64_MEMf32_AVX512 30551 } 30552 30553 30554 # EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1) 30555 { 30556 ICLASS: VCVTTSS2USI 30557 CPL: 3 30558 CATEGORY: CONVERT 30559 EXTENSION: AVX512EVEX 30560 ISA_SET: AVX512F_SCALAR 30561 EXCEPTIONS: AVX512-E3NF 30562 REAL_OPCODE: Y 30563 ATTRIBUTES: MXCSR SIMD_SCALAR 30564 PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 30565 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 30566 IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 30567 } 30568 30569 { 30570 ICLASS: VCVTTSS2USI 30571 CPL: 3 30572 CATEGORY: CONVERT 30573 EXTENSION: AVX512EVEX 30574 ISA_SET: AVX512F_SCALAR 30575 EXCEPTIONS: AVX512-E3NF 30576 REAL_OPCODE: Y 30577 ATTRIBUTES: MXCSR SIMD_SCALAR 30578 PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 30579 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 30580 IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 30581 } 30582 30583 { 30584 ICLASS: VCVTTSS2USI 30585 CPL: 3 30586 CATEGORY: CONVERT 30587 EXTENSION: AVX512EVEX 30588 ISA_SET: AVX512F_SCALAR 30589 EXCEPTIONS: AVX512-E3NF 30590 REAL_OPCODE: Y 30591 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 30592 PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 30593 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 30594 IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 30595 } 30596 30597 30598 # EMITTING VCVTTSS2USI (VCVTTSS2USI-128-2) 30599 { 30600 ICLASS: VCVTTSS2USI 30601 CPL: 3 30602 CATEGORY: CONVERT 30603 EXTENSION: AVX512EVEX 30604 ISA_SET: AVX512F_SCALAR 30605 EXCEPTIONS: AVX512-E3NF 30606 REAL_OPCODE: Y 30607 ATTRIBUTES: MXCSR SIMD_SCALAR 30608 PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 30609 OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 30610 IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 30611 } 30612 30613 { 30614 ICLASS: VCVTTSS2USI 30615 CPL: 3 30616 CATEGORY: CONVERT 30617 EXTENSION: AVX512EVEX 30618 ISA_SET: AVX512F_SCALAR 30619 EXCEPTIONS: AVX512-E3NF 30620 REAL_OPCODE: Y 30621 ATTRIBUTES: MXCSR SIMD_SCALAR 30622 PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 30623 OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 30624 IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 30625 } 30626 30627 { 30628 ICLASS: VCVTTSS2USI 30629 CPL: 3 30630 CATEGORY: CONVERT 30631 EXTENSION: AVX512EVEX 30632 ISA_SET: AVX512F_SCALAR 30633 EXCEPTIONS: AVX512-E3NF 30634 REAL_OPCODE: Y 30635 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_D 30636 PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 30637 OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 30638 IFORM: VCVTTSS2USI_GPR64u64_MEMf32_AVX512 30639 } 30640 30641 30642 # EMITTING VCVTUDQ2PD (VCVTUDQ2PD-512-1) 30643 { 30644 ICLASS: VCVTUDQ2PD 30645 CPL: 3 30646 CATEGORY: CONVERT 30647 EXTENSION: AVX512EVEX 30648 ISA_SET: AVX512F_512 30649 EXCEPTIONS: AVX512-E5 30650 REAL_OPCODE: Y 30651 ATTRIBUTES: MASKOP_EVEX 30652 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 30653 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 30654 IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 30655 } 30656 30657 { 30658 ICLASS: VCVTUDQ2PD 30659 CPL: 3 30660 CATEGORY: CONVERT 30661 EXTENSION: AVX512EVEX 30662 ISA_SET: AVX512F_512 30663 EXCEPTIONS: AVX512-E5 30664 REAL_OPCODE: Y 30665 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 30666 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 30667 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 30668 IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 30669 } 30670 30671 30672 # EMITTING VCVTUDQ2PS (VCVTUDQ2PS-512-1) 30673 { 30674 ICLASS: VCVTUDQ2PS 30675 CPL: 3 30676 CATEGORY: CONVERT 30677 EXTENSION: AVX512EVEX 30678 ISA_SET: AVX512F_512 30679 EXCEPTIONS: AVX512-E2 30680 REAL_OPCODE: Y 30681 ATTRIBUTES: MXCSR MASKOP_EVEX 30682 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 30683 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 30684 IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 30685 } 30686 30687 { 30688 ICLASS: VCVTUDQ2PS 30689 CPL: 3 30690 CATEGORY: CONVERT 30691 EXTENSION: AVX512EVEX 30692 ISA_SET: AVX512F_512 30693 EXCEPTIONS: AVX512-E2 30694 REAL_OPCODE: Y 30695 ATTRIBUTES: MXCSR MASKOP_EVEX 30696 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 30697 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 30698 IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 30699 } 30700 30701 { 30702 ICLASS: VCVTUDQ2PS 30703 CPL: 3 30704 CATEGORY: CONVERT 30705 EXTENSION: AVX512EVEX 30706 ISA_SET: AVX512F_512 30707 EXCEPTIONS: AVX512-E2 30708 REAL_OPCODE: Y 30709 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 30710 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 30711 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 30712 IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 30713 } 30714 30715 30716 # EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1) 30717 { 30718 ICLASS: VCVTUSI2SD 30719 CPL: 3 30720 CATEGORY: CONVERT 30721 EXTENSION: AVX512EVEX 30722 ISA_SET: AVX512F_SCALAR 30723 EXCEPTIONS: AVX512-E10NF 30724 REAL_OPCODE: Y 30725 ATTRIBUTES: SIMD_SCALAR 30726 PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 30727 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 30728 IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 30729 } 30730 30731 { 30732 ICLASS: VCVTUSI2SD 30733 CPL: 3 30734 CATEGORY: CONVERT 30735 EXTENSION: AVX512EVEX 30736 ISA_SET: AVX512F_SCALAR 30737 EXCEPTIONS: AVX512-E10NF 30738 REAL_OPCODE: Y 30739 ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER 30740 PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 30741 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 30742 IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 30743 } 30744 30745 30746 # EMITTING VCVTUSI2SD (VCVTUSI2SD-128-2) 30747 { 30748 ICLASS: VCVTUSI2SD 30749 CPL: 3 30750 CATEGORY: CONVERT 30751 EXTENSION: AVX512EVEX 30752 ISA_SET: AVX512F_SCALAR 30753 EXCEPTIONS: AVX512-E3NF 30754 REAL_OPCODE: Y 30755 ATTRIBUTES: MXCSR SIMD_SCALAR 30756 PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 30757 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 30758 IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 30759 } 30760 30761 { 30762 ICLASS: VCVTUSI2SD 30763 CPL: 3 30764 CATEGORY: CONVERT 30765 EXTENSION: AVX512EVEX 30766 ISA_SET: AVX512F_SCALAR 30767 EXCEPTIONS: AVX512-E3NF 30768 REAL_OPCODE: Y 30769 ATTRIBUTES: MXCSR SIMD_SCALAR 30770 PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 30771 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 30772 IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 30773 } 30774 30775 { 30776 ICLASS: VCVTUSI2SD 30777 CPL: 3 30778 CATEGORY: CONVERT 30779 EXTENSION: AVX512EVEX 30780 ISA_SET: AVX512F_SCALAR 30781 EXCEPTIONS: AVX512-E3NF 30782 REAL_OPCODE: Y 30783 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 30784 PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() 30785 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64 30786 IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 30787 } 30788 30789 30790 # EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1) 30791 { 30792 ICLASS: VCVTUSI2SS 30793 CPL: 3 30794 CATEGORY: CONVERT 30795 EXTENSION: AVX512EVEX 30796 ISA_SET: AVX512F_SCALAR 30797 EXCEPTIONS: AVX512-E3NF 30798 REAL_OPCODE: Y 30799 ATTRIBUTES: MXCSR SIMD_SCALAR 30800 PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 30801 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 30802 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 30803 } 30804 30805 { 30806 ICLASS: VCVTUSI2SS 30807 CPL: 3 30808 CATEGORY: CONVERT 30809 EXTENSION: AVX512EVEX 30810 ISA_SET: AVX512F_SCALAR 30811 EXCEPTIONS: AVX512-E3NF 30812 REAL_OPCODE: Y 30813 ATTRIBUTES: MXCSR SIMD_SCALAR 30814 PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 ZEROING=0 MASK=0 30815 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 30816 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 30817 } 30818 30819 { 30820 ICLASS: VCVTUSI2SS 30821 CPL: 3 30822 CATEGORY: CONVERT 30823 EXTENSION: AVX512EVEX 30824 ISA_SET: AVX512F_SCALAR 30825 EXCEPTIONS: AVX512-E3NF 30826 REAL_OPCODE: Y 30827 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 30828 PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 30829 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 30830 IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 30831 } 30832 30833 30834 # EMITTING VCVTUSI2SS (VCVTUSI2SS-128-2) 30835 { 30836 ICLASS: VCVTUSI2SS 30837 CPL: 3 30838 CATEGORY: CONVERT 30839 EXTENSION: AVX512EVEX 30840 ISA_SET: AVX512F_SCALAR 30841 EXCEPTIONS: AVX512-E3NF 30842 REAL_OPCODE: Y 30843 ATTRIBUTES: MXCSR SIMD_SCALAR 30844 PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 30845 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 30846 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 30847 } 30848 30849 { 30850 ICLASS: VCVTUSI2SS 30851 CPL: 3 30852 CATEGORY: CONVERT 30853 EXTENSION: AVX512EVEX 30854 ISA_SET: AVX512F_SCALAR 30855 EXCEPTIONS: AVX512-E3NF 30856 REAL_OPCODE: Y 30857 ATTRIBUTES: MXCSR SIMD_SCALAR 30858 PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 30859 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 30860 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 30861 } 30862 30863 { 30864 ICLASS: VCVTUSI2SS 30865 CPL: 3 30866 CATEGORY: CONVERT 30867 EXTENSION: AVX512EVEX 30868 ISA_SET: AVX512F_SCALAR 30869 EXCEPTIONS: AVX512-E3NF 30870 REAL_OPCODE: Y 30871 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 30872 PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() 30873 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64 30874 IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 30875 } 30876 30877 30878 # EMITTING VDIVPD (VDIVPD-512-1) 30879 { 30880 ICLASS: VDIVPD 30881 CPL: 3 30882 CATEGORY: AVX512 30883 EXTENSION: AVX512EVEX 30884 ISA_SET: AVX512F_512 30885 EXCEPTIONS: AVX512-E2 30886 REAL_OPCODE: Y 30887 ATTRIBUTES: MXCSR MASKOP_EVEX 30888 PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 30889 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 30890 IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 30891 } 30892 30893 { 30894 ICLASS: VDIVPD 30895 CPL: 3 30896 CATEGORY: AVX512 30897 EXTENSION: AVX512EVEX 30898 ISA_SET: AVX512F_512 30899 EXCEPTIONS: AVX512-E2 30900 REAL_OPCODE: Y 30901 ATTRIBUTES: MXCSR MASKOP_EVEX 30902 PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 30903 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 30904 IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 30905 } 30906 30907 { 30908 ICLASS: VDIVPD 30909 CPL: 3 30910 CATEGORY: AVX512 30911 EXTENSION: AVX512EVEX 30912 ISA_SET: AVX512F_512 30913 EXCEPTIONS: AVX512-E2 30914 REAL_OPCODE: Y 30915 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 30916 PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 30917 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 30918 IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 30919 } 30920 30921 30922 # EMITTING VDIVPS (VDIVPS-512-1) 30923 { 30924 ICLASS: VDIVPS 30925 CPL: 3 30926 CATEGORY: AVX512 30927 EXTENSION: AVX512EVEX 30928 ISA_SET: AVX512F_512 30929 EXCEPTIONS: AVX512-E2 30930 REAL_OPCODE: Y 30931 ATTRIBUTES: MXCSR MASKOP_EVEX 30932 PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 30933 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 30934 IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 30935 } 30936 30937 { 30938 ICLASS: VDIVPS 30939 CPL: 3 30940 CATEGORY: AVX512 30941 EXTENSION: AVX512EVEX 30942 ISA_SET: AVX512F_512 30943 EXCEPTIONS: AVX512-E2 30944 REAL_OPCODE: Y 30945 ATTRIBUTES: MXCSR MASKOP_EVEX 30946 PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 30947 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 30948 IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 30949 } 30950 30951 { 30952 ICLASS: VDIVPS 30953 CPL: 3 30954 CATEGORY: AVX512 30955 EXTENSION: AVX512EVEX 30956 ISA_SET: AVX512F_512 30957 EXCEPTIONS: AVX512-E2 30958 REAL_OPCODE: Y 30959 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 30960 PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 30961 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 30962 IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 30963 } 30964 30965 30966 # EMITTING VDIVSD (VDIVSD-128-1) 30967 { 30968 ICLASS: VDIVSD 30969 CPL: 3 30970 CATEGORY: AVX512 30971 EXTENSION: AVX512EVEX 30972 ISA_SET: AVX512F_SCALAR 30973 EXCEPTIONS: AVX512-E3 30974 REAL_OPCODE: Y 30975 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 30976 PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 30977 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 30978 IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 30979 } 30980 30981 { 30982 ICLASS: VDIVSD 30983 CPL: 3 30984 CATEGORY: AVX512 30985 EXTENSION: AVX512EVEX 30986 ISA_SET: AVX512F_SCALAR 30987 EXCEPTIONS: AVX512-E3 30988 REAL_OPCODE: Y 30989 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 30990 PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 30991 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 30992 IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 30993 } 30994 30995 { 30996 ICLASS: VDIVSD 30997 CPL: 3 30998 CATEGORY: AVX512 30999 EXTENSION: AVX512EVEX 31000 ISA_SET: AVX512F_SCALAR 31001 EXCEPTIONS: AVX512-E3 31002 REAL_OPCODE: Y 31003 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 31004 PATTERN: EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 31005 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 31006 IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31007 } 31008 31009 31010 # EMITTING VDIVSS (VDIVSS-128-1) 31011 { 31012 ICLASS: VDIVSS 31013 CPL: 3 31014 CATEGORY: AVX512 31015 EXTENSION: AVX512EVEX 31016 ISA_SET: AVX512F_SCALAR 31017 EXCEPTIONS: AVX512-E3 31018 REAL_OPCODE: Y 31019 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31020 PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 31021 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31022 IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31023 } 31024 31025 { 31026 ICLASS: VDIVSS 31027 CPL: 3 31028 CATEGORY: AVX512 31029 EXTENSION: AVX512EVEX 31030 ISA_SET: AVX512F_SCALAR 31031 EXCEPTIONS: AVX512-E3 31032 REAL_OPCODE: Y 31033 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31034 PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 31035 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31036 IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31037 } 31038 31039 { 31040 ICLASS: VDIVSS 31041 CPL: 3 31042 CATEGORY: AVX512 31043 EXTENSION: AVX512EVEX 31044 ISA_SET: AVX512F_SCALAR 31045 EXCEPTIONS: AVX512-E3 31046 REAL_OPCODE: Y 31047 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 31048 PATTERN: EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 31049 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 31050 IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31051 } 31052 31053 31054 # EMITTING VEXPANDPD (VEXPANDPD-512-1) 31055 { 31056 ICLASS: VEXPANDPD 31057 CPL: 3 31058 CATEGORY: EXPAND 31059 EXTENSION: AVX512EVEX 31060 ISA_SET: AVX512F_512 31061 EXCEPTIONS: AVX512-E4 31062 REAL_OPCODE: Y 31063 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 31064 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 31065 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 31066 IFORM: VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 31067 } 31068 31069 31070 # EMITTING VEXPANDPD (VEXPANDPD-512-2) 31071 { 31072 ICLASS: VEXPANDPD 31073 CPL: 3 31074 CATEGORY: EXPAND 31075 EXTENSION: AVX512EVEX 31076 ISA_SET: AVX512F_512 31077 EXCEPTIONS: AVX512-E4 31078 REAL_OPCODE: Y 31079 ATTRIBUTES: MASKOP_EVEX 31080 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 31081 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 31082 IFORM: VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 31083 } 31084 31085 31086 # EMITTING VEXPANDPS (VEXPANDPS-512-1) 31087 { 31088 ICLASS: VEXPANDPS 31089 CPL: 3 31090 CATEGORY: EXPAND 31091 EXTENSION: AVX512EVEX 31092 ISA_SET: AVX512F_512 31093 EXCEPTIONS: AVX512-E4 31094 REAL_OPCODE: Y 31095 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 31096 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 31097 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 31098 IFORM: VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 31099 } 31100 31101 31102 # EMITTING VEXPANDPS (VEXPANDPS-512-2) 31103 { 31104 ICLASS: VEXPANDPS 31105 CPL: 3 31106 CATEGORY: EXPAND 31107 EXTENSION: AVX512EVEX 31108 ISA_SET: AVX512F_512 31109 EXCEPTIONS: AVX512-E4 31110 REAL_OPCODE: Y 31111 ATTRIBUTES: MASKOP_EVEX 31112 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 31113 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 31114 IFORM: VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 31115 } 31116 31117 31118 # EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-1) 31119 { 31120 ICLASS: VEXTRACTF32X4 31121 CPL: 3 31122 CATEGORY: AVX512 31123 EXTENSION: AVX512EVEX 31124 ISA_SET: AVX512F_512 31125 EXCEPTIONS: AVX512-E6NF 31126 REAL_OPCODE: Y 31127 ATTRIBUTES: MASKOP_EVEX 31128 PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 31129 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b 31130 IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 31131 } 31132 31133 31134 # EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-2) 31135 { 31136 ICLASS: VEXTRACTF32X4 31137 CPL: 3 31138 CATEGORY: AVX512 31139 EXTENSION: AVX512EVEX 31140 ISA_SET: AVX512F_512 31141 EXCEPTIONS: AVX512-E6NF 31142 REAL_OPCODE: Y 31143 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 31144 PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 31145 OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b 31146 IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 31147 } 31148 31149 31150 # EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-1) 31151 { 31152 ICLASS: VEXTRACTF64X4 31153 CPL: 3 31154 CATEGORY: AVX512 31155 EXTENSION: AVX512EVEX 31156 ISA_SET: AVX512F_512 31157 EXCEPTIONS: AVX512-E6NF 31158 REAL_OPCODE: Y 31159 ATTRIBUTES: MASKOP_EVEX 31160 PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 31161 OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b 31162 IFORM: VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 31163 } 31164 31165 31166 # EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-2) 31167 { 31168 ICLASS: VEXTRACTF64X4 31169 CPL: 3 31170 CATEGORY: AVX512 31171 EXTENSION: AVX512EVEX 31172 ISA_SET: AVX512F_512 31173 EXCEPTIONS: AVX512-E6NF 31174 REAL_OPCODE: Y 31175 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 31176 PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() 31177 OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b 31178 IFORM: VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 31179 } 31180 31181 31182 # EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-1) 31183 { 31184 ICLASS: VEXTRACTI32X4 31185 CPL: 3 31186 CATEGORY: AVX512 31187 EXTENSION: AVX512EVEX 31188 ISA_SET: AVX512F_512 31189 EXCEPTIONS: AVX512-E6NF 31190 REAL_OPCODE: Y 31191 ATTRIBUTES: MASKOP_EVEX 31192 PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 31193 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b 31194 IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 31195 } 31196 31197 31198 # EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-2) 31199 { 31200 ICLASS: VEXTRACTI32X4 31201 CPL: 3 31202 CATEGORY: AVX512 31203 EXTENSION: AVX512EVEX 31204 ISA_SET: AVX512F_512 31205 EXCEPTIONS: AVX512-E6NF 31206 REAL_OPCODE: Y 31207 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 31208 PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 31209 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b 31210 IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 31211 } 31212 31213 31214 # EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-1) 31215 { 31216 ICLASS: VEXTRACTI64X4 31217 CPL: 3 31218 CATEGORY: AVX512 31219 EXTENSION: AVX512EVEX 31220 ISA_SET: AVX512F_512 31221 EXCEPTIONS: AVX512-E6NF 31222 REAL_OPCODE: Y 31223 ATTRIBUTES: MASKOP_EVEX 31224 PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 31225 OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b 31226 IFORM: VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 31227 } 31228 31229 31230 # EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-2) 31231 { 31232 ICLASS: VEXTRACTI64X4 31233 CPL: 3 31234 CATEGORY: AVX512 31235 EXTENSION: AVX512EVEX 31236 ISA_SET: AVX512F_512 31237 EXCEPTIONS: AVX512-E6NF 31238 REAL_OPCODE: Y 31239 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 31240 PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() 31241 OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b 31242 IFORM: VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 31243 } 31244 31245 31246 # EMITTING VEXTRACTPS (VEXTRACTPS-128-1) 31247 { 31248 ICLASS: VEXTRACTPS 31249 CPL: 3 31250 CATEGORY: AVX512 31251 EXTENSION: AVX512EVEX 31252 ISA_SET: AVX512F_128N 31253 EXCEPTIONS: AVX512-E9NF 31254 REAL_OPCODE: Y 31255 PATTERN: EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() 31256 OPERANDS: REG0=GPR32_B():w:d:f32 REG1=XMM_R3():r:dq:f32 IMM0:r:b 31257 IFORM: VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 31258 } 31259 31260 { 31261 ICLASS: VEXTRACTPS 31262 CPL: 3 31263 CATEGORY: AVX512 31264 EXTENSION: AVX512EVEX 31265 ISA_SET: AVX512F_128N 31266 EXCEPTIONS: AVX512-E9NF 31267 REAL_OPCODE: Y 31268 ATTRIBUTES: DISP8_GPR_WRITER_STORE 31269 PATTERN: EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() 31270 OPERANDS: MEM0:w:d:f32 REG0=XMM_R3():r:dq:f32 IMM0:r:b 31271 IFORM: VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 31272 } 31273 31274 31275 # EMITTING VFIXUPIMMPD (VFIXUPIMMPD-512-1) 31276 { 31277 ICLASS: VFIXUPIMMPD 31278 CPL: 3 31279 CATEGORY: AVX512 31280 EXTENSION: AVX512EVEX 31281 ISA_SET: AVX512F_512 31282 EXCEPTIONS: AVX512-E2 31283 REAL_OPCODE: Y 31284 ATTRIBUTES: MXCSR MASKOP_EVEX 31285 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 31286 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 31287 IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 31288 } 31289 31290 { 31291 ICLASS: VFIXUPIMMPD 31292 CPL: 3 31293 CATEGORY: AVX512 31294 EXTENSION: AVX512EVEX 31295 ISA_SET: AVX512F_512 31296 EXCEPTIONS: AVX512-E2 31297 REAL_OPCODE: Y 31298 ATTRIBUTES: MXCSR MASKOP_EVEX 31299 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() 31300 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 31301 IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 31302 } 31303 31304 { 31305 ICLASS: VFIXUPIMMPD 31306 CPL: 3 31307 CATEGORY: AVX512 31308 EXTENSION: AVX512EVEX 31309 ISA_SET: AVX512F_512 31310 EXCEPTIONS: AVX512-E2 31311 REAL_OPCODE: Y 31312 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 31313 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 31314 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 31315 IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 31316 } 31317 31318 31319 # EMITTING VFIXUPIMMPS (VFIXUPIMMPS-512-1) 31320 { 31321 ICLASS: VFIXUPIMMPS 31322 CPL: 3 31323 CATEGORY: AVX512 31324 EXTENSION: AVX512EVEX 31325 ISA_SET: AVX512F_512 31326 EXCEPTIONS: AVX512-E2 31327 REAL_OPCODE: Y 31328 ATTRIBUTES: MXCSR MASKOP_EVEX 31329 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 31330 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 31331 IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 31332 } 31333 31334 { 31335 ICLASS: VFIXUPIMMPS 31336 CPL: 3 31337 CATEGORY: AVX512 31338 EXTENSION: AVX512EVEX 31339 ISA_SET: AVX512F_512 31340 EXCEPTIONS: AVX512-E2 31341 REAL_OPCODE: Y 31342 ATTRIBUTES: MXCSR MASKOP_EVEX 31343 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() 31344 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 31345 IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 31346 } 31347 31348 { 31349 ICLASS: VFIXUPIMMPS 31350 CPL: 3 31351 CATEGORY: AVX512 31352 EXTENSION: AVX512EVEX 31353 ISA_SET: AVX512F_512 31354 EXCEPTIONS: AVX512-E2 31355 REAL_OPCODE: Y 31356 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 31357 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 31358 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 31359 IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 31360 } 31361 31362 31363 # EMITTING VFIXUPIMMSD (VFIXUPIMMSD-128-1) 31364 { 31365 ICLASS: VFIXUPIMMSD 31366 CPL: 3 31367 CATEGORY: AVX512 31368 EXTENSION: AVX512EVEX 31369 ISA_SET: AVX512F_SCALAR 31370 EXCEPTIONS: AVX512-E3 31371 REAL_OPCODE: Y 31372 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31373 PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() 31374 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 31375 IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 31376 } 31377 31378 { 31379 ICLASS: VFIXUPIMMSD 31380 CPL: 3 31381 CATEGORY: AVX512 31382 EXTENSION: AVX512EVEX 31383 ISA_SET: AVX512F_SCALAR 31384 EXCEPTIONS: AVX512-E3 31385 REAL_OPCODE: Y 31386 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31387 PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() 31388 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 31389 IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 31390 } 31391 31392 { 31393 ICLASS: VFIXUPIMMSD 31394 CPL: 3 31395 CATEGORY: AVX512 31396 EXTENSION: AVX512EVEX 31397 ISA_SET: AVX512F_SCALAR 31398 EXCEPTIONS: AVX512-E3 31399 REAL_OPCODE: Y 31400 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 31401 PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 31402 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 31403 IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 31404 } 31405 31406 31407 # EMITTING VFIXUPIMMSS (VFIXUPIMMSS-128-1) 31408 { 31409 ICLASS: VFIXUPIMMSS 31410 CPL: 3 31411 CATEGORY: AVX512 31412 EXTENSION: AVX512EVEX 31413 ISA_SET: AVX512F_SCALAR 31414 EXCEPTIONS: AVX512-E3 31415 REAL_OPCODE: Y 31416 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31417 PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() 31418 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 31419 IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 31420 } 31421 31422 { 31423 ICLASS: VFIXUPIMMSS 31424 CPL: 3 31425 CATEGORY: AVX512 31426 EXTENSION: AVX512EVEX 31427 ISA_SET: AVX512F_SCALAR 31428 EXCEPTIONS: AVX512-E3 31429 REAL_OPCODE: Y 31430 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31431 PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() 31432 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 31433 IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 31434 } 31435 31436 { 31437 ICLASS: VFIXUPIMMSS 31438 CPL: 3 31439 CATEGORY: AVX512 31440 EXTENSION: AVX512EVEX 31441 ISA_SET: AVX512F_SCALAR 31442 EXCEPTIONS: AVX512-E3 31443 REAL_OPCODE: Y 31444 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 31445 PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 31446 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 31447 IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 31448 } 31449 31450 31451 # EMITTING VFMADD132PD (VFMADD132PD-512-1) 31452 { 31453 ICLASS: VFMADD132PD 31454 CPL: 3 31455 CATEGORY: VFMA 31456 EXTENSION: AVX512EVEX 31457 ISA_SET: AVX512F_512 31458 EXCEPTIONS: AVX512-E2 31459 REAL_OPCODE: Y 31460 ATTRIBUTES: MXCSR MASKOP_EVEX 31461 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 31462 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 31463 IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 31464 } 31465 31466 { 31467 ICLASS: VFMADD132PD 31468 CPL: 3 31469 CATEGORY: VFMA 31470 EXTENSION: AVX512EVEX 31471 ISA_SET: AVX512F_512 31472 EXCEPTIONS: AVX512-E2 31473 REAL_OPCODE: Y 31474 ATTRIBUTES: MXCSR MASKOP_EVEX 31475 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 31476 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 31477 IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 31478 } 31479 31480 { 31481 ICLASS: VFMADD132PD 31482 CPL: 3 31483 CATEGORY: VFMA 31484 EXTENSION: AVX512EVEX 31485 ISA_SET: AVX512F_512 31486 EXCEPTIONS: AVX512-E2 31487 REAL_OPCODE: Y 31488 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 31489 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 31490 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 31491 IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 31492 } 31493 31494 31495 # EMITTING VFMADD132PS (VFMADD132PS-512-1) 31496 { 31497 ICLASS: VFMADD132PS 31498 CPL: 3 31499 CATEGORY: VFMA 31500 EXTENSION: AVX512EVEX 31501 ISA_SET: AVX512F_512 31502 EXCEPTIONS: AVX512-E2 31503 REAL_OPCODE: Y 31504 ATTRIBUTES: MXCSR MASKOP_EVEX 31505 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 31506 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 31507 IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 31508 } 31509 31510 { 31511 ICLASS: VFMADD132PS 31512 CPL: 3 31513 CATEGORY: VFMA 31514 EXTENSION: AVX512EVEX 31515 ISA_SET: AVX512F_512 31516 EXCEPTIONS: AVX512-E2 31517 REAL_OPCODE: Y 31518 ATTRIBUTES: MXCSR MASKOP_EVEX 31519 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 31520 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 31521 IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 31522 } 31523 31524 { 31525 ICLASS: VFMADD132PS 31526 CPL: 3 31527 CATEGORY: VFMA 31528 EXTENSION: AVX512EVEX 31529 ISA_SET: AVX512F_512 31530 EXCEPTIONS: AVX512-E2 31531 REAL_OPCODE: Y 31532 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 31533 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 31534 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 31535 IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 31536 } 31537 31538 31539 # EMITTING VFMADD132SD (VFMADD132SD-128-1) 31540 { 31541 ICLASS: VFMADD132SD 31542 CPL: 3 31543 CATEGORY: VFMA 31544 EXTENSION: AVX512EVEX 31545 ISA_SET: AVX512F_SCALAR 31546 EXCEPTIONS: AVX512-E3 31547 REAL_OPCODE: Y 31548 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31549 PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 31550 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31551 IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31552 } 31553 31554 { 31555 ICLASS: VFMADD132SD 31556 CPL: 3 31557 CATEGORY: VFMA 31558 EXTENSION: AVX512EVEX 31559 ISA_SET: AVX512F_SCALAR 31560 EXCEPTIONS: AVX512-E3 31561 REAL_OPCODE: Y 31562 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31563 PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 31564 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31565 IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31566 } 31567 31568 { 31569 ICLASS: VFMADD132SD 31570 CPL: 3 31571 CATEGORY: VFMA 31572 EXTENSION: AVX512EVEX 31573 ISA_SET: AVX512F_SCALAR 31574 EXCEPTIONS: AVX512-E3 31575 REAL_OPCODE: Y 31576 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 31577 PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 31578 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 31579 IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31580 } 31581 31582 31583 # EMITTING VFMADD132SS (VFMADD132SS-128-1) 31584 { 31585 ICLASS: VFMADD132SS 31586 CPL: 3 31587 CATEGORY: VFMA 31588 EXTENSION: AVX512EVEX 31589 ISA_SET: AVX512F_SCALAR 31590 EXCEPTIONS: AVX512-E3 31591 REAL_OPCODE: Y 31592 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31593 PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 31594 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31595 IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31596 } 31597 31598 { 31599 ICLASS: VFMADD132SS 31600 CPL: 3 31601 CATEGORY: VFMA 31602 EXTENSION: AVX512EVEX 31603 ISA_SET: AVX512F_SCALAR 31604 EXCEPTIONS: AVX512-E3 31605 REAL_OPCODE: Y 31606 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31607 PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 31608 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31609 IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31610 } 31611 31612 { 31613 ICLASS: VFMADD132SS 31614 CPL: 3 31615 CATEGORY: VFMA 31616 EXTENSION: AVX512EVEX 31617 ISA_SET: AVX512F_SCALAR 31618 EXCEPTIONS: AVX512-E3 31619 REAL_OPCODE: Y 31620 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 31621 PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 31622 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 31623 IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31624 } 31625 31626 31627 # EMITTING VFMADD213PD (VFMADD213PD-512-1) 31628 { 31629 ICLASS: VFMADD213PD 31630 CPL: 3 31631 CATEGORY: VFMA 31632 EXTENSION: AVX512EVEX 31633 ISA_SET: AVX512F_512 31634 EXCEPTIONS: AVX512-E2 31635 REAL_OPCODE: Y 31636 ATTRIBUTES: MXCSR MASKOP_EVEX 31637 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 31638 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 31639 IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 31640 } 31641 31642 { 31643 ICLASS: VFMADD213PD 31644 CPL: 3 31645 CATEGORY: VFMA 31646 EXTENSION: AVX512EVEX 31647 ISA_SET: AVX512F_512 31648 EXCEPTIONS: AVX512-E2 31649 REAL_OPCODE: Y 31650 ATTRIBUTES: MXCSR MASKOP_EVEX 31651 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 31652 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 31653 IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 31654 } 31655 31656 { 31657 ICLASS: VFMADD213PD 31658 CPL: 3 31659 CATEGORY: VFMA 31660 EXTENSION: AVX512EVEX 31661 ISA_SET: AVX512F_512 31662 EXCEPTIONS: AVX512-E2 31663 REAL_OPCODE: Y 31664 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 31665 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 31666 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 31667 IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 31668 } 31669 31670 31671 # EMITTING VFMADD213PS (VFMADD213PS-512-1) 31672 { 31673 ICLASS: VFMADD213PS 31674 CPL: 3 31675 CATEGORY: VFMA 31676 EXTENSION: AVX512EVEX 31677 ISA_SET: AVX512F_512 31678 EXCEPTIONS: AVX512-E2 31679 REAL_OPCODE: Y 31680 ATTRIBUTES: MXCSR MASKOP_EVEX 31681 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 31682 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 31683 IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 31684 } 31685 31686 { 31687 ICLASS: VFMADD213PS 31688 CPL: 3 31689 CATEGORY: VFMA 31690 EXTENSION: AVX512EVEX 31691 ISA_SET: AVX512F_512 31692 EXCEPTIONS: AVX512-E2 31693 REAL_OPCODE: Y 31694 ATTRIBUTES: MXCSR MASKOP_EVEX 31695 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 31696 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 31697 IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 31698 } 31699 31700 { 31701 ICLASS: VFMADD213PS 31702 CPL: 3 31703 CATEGORY: VFMA 31704 EXTENSION: AVX512EVEX 31705 ISA_SET: AVX512F_512 31706 EXCEPTIONS: AVX512-E2 31707 REAL_OPCODE: Y 31708 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 31709 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 31710 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 31711 IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 31712 } 31713 31714 31715 # EMITTING VFMADD213SD (VFMADD213SD-128-1) 31716 { 31717 ICLASS: VFMADD213SD 31718 CPL: 3 31719 CATEGORY: VFMA 31720 EXTENSION: AVX512EVEX 31721 ISA_SET: AVX512F_SCALAR 31722 EXCEPTIONS: AVX512-E3 31723 REAL_OPCODE: Y 31724 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31725 PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 31726 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31727 IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31728 } 31729 31730 { 31731 ICLASS: VFMADD213SD 31732 CPL: 3 31733 CATEGORY: VFMA 31734 EXTENSION: AVX512EVEX 31735 ISA_SET: AVX512F_SCALAR 31736 EXCEPTIONS: AVX512-E3 31737 REAL_OPCODE: Y 31738 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31739 PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 31740 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31741 IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31742 } 31743 31744 { 31745 ICLASS: VFMADD213SD 31746 CPL: 3 31747 CATEGORY: VFMA 31748 EXTENSION: AVX512EVEX 31749 ISA_SET: AVX512F_SCALAR 31750 EXCEPTIONS: AVX512-E3 31751 REAL_OPCODE: Y 31752 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 31753 PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 31754 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 31755 IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31756 } 31757 31758 31759 # EMITTING VFMADD213SS (VFMADD213SS-128-1) 31760 { 31761 ICLASS: VFMADD213SS 31762 CPL: 3 31763 CATEGORY: VFMA 31764 EXTENSION: AVX512EVEX 31765 ISA_SET: AVX512F_SCALAR 31766 EXCEPTIONS: AVX512-E3 31767 REAL_OPCODE: Y 31768 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31769 PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 31770 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31771 IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31772 } 31773 31774 { 31775 ICLASS: VFMADD213SS 31776 CPL: 3 31777 CATEGORY: VFMA 31778 EXTENSION: AVX512EVEX 31779 ISA_SET: AVX512F_SCALAR 31780 EXCEPTIONS: AVX512-E3 31781 REAL_OPCODE: Y 31782 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31783 PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 31784 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31785 IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31786 } 31787 31788 { 31789 ICLASS: VFMADD213SS 31790 CPL: 3 31791 CATEGORY: VFMA 31792 EXTENSION: AVX512EVEX 31793 ISA_SET: AVX512F_SCALAR 31794 EXCEPTIONS: AVX512-E3 31795 REAL_OPCODE: Y 31796 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 31797 PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 31798 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 31799 IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31800 } 31801 31802 31803 # EMITTING VFMADD231PD (VFMADD231PD-512-1) 31804 { 31805 ICLASS: VFMADD231PD 31806 CPL: 3 31807 CATEGORY: VFMA 31808 EXTENSION: AVX512EVEX 31809 ISA_SET: AVX512F_512 31810 EXCEPTIONS: AVX512-E2 31811 REAL_OPCODE: Y 31812 ATTRIBUTES: MXCSR MASKOP_EVEX 31813 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 31814 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 31815 IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 31816 } 31817 31818 { 31819 ICLASS: VFMADD231PD 31820 CPL: 3 31821 CATEGORY: VFMA 31822 EXTENSION: AVX512EVEX 31823 ISA_SET: AVX512F_512 31824 EXCEPTIONS: AVX512-E2 31825 REAL_OPCODE: Y 31826 ATTRIBUTES: MXCSR MASKOP_EVEX 31827 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 31828 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 31829 IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 31830 } 31831 31832 { 31833 ICLASS: VFMADD231PD 31834 CPL: 3 31835 CATEGORY: VFMA 31836 EXTENSION: AVX512EVEX 31837 ISA_SET: AVX512F_512 31838 EXCEPTIONS: AVX512-E2 31839 REAL_OPCODE: Y 31840 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 31841 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 31842 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 31843 IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 31844 } 31845 31846 31847 # EMITTING VFMADD231PS (VFMADD231PS-512-1) 31848 { 31849 ICLASS: VFMADD231PS 31850 CPL: 3 31851 CATEGORY: VFMA 31852 EXTENSION: AVX512EVEX 31853 ISA_SET: AVX512F_512 31854 EXCEPTIONS: AVX512-E2 31855 REAL_OPCODE: Y 31856 ATTRIBUTES: MXCSR MASKOP_EVEX 31857 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 31858 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 31859 IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 31860 } 31861 31862 { 31863 ICLASS: VFMADD231PS 31864 CPL: 3 31865 CATEGORY: VFMA 31866 EXTENSION: AVX512EVEX 31867 ISA_SET: AVX512F_512 31868 EXCEPTIONS: AVX512-E2 31869 REAL_OPCODE: Y 31870 ATTRIBUTES: MXCSR MASKOP_EVEX 31871 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 31872 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 31873 IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 31874 } 31875 31876 { 31877 ICLASS: VFMADD231PS 31878 CPL: 3 31879 CATEGORY: VFMA 31880 EXTENSION: AVX512EVEX 31881 ISA_SET: AVX512F_512 31882 EXCEPTIONS: AVX512-E2 31883 REAL_OPCODE: Y 31884 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 31885 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 31886 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 31887 IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 31888 } 31889 31890 31891 # EMITTING VFMADD231SD (VFMADD231SD-128-1) 31892 { 31893 ICLASS: VFMADD231SD 31894 CPL: 3 31895 CATEGORY: VFMA 31896 EXTENSION: AVX512EVEX 31897 ISA_SET: AVX512F_SCALAR 31898 EXCEPTIONS: AVX512-E3 31899 REAL_OPCODE: Y 31900 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31901 PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 31902 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31903 IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31904 } 31905 31906 { 31907 ICLASS: VFMADD231SD 31908 CPL: 3 31909 CATEGORY: VFMA 31910 EXTENSION: AVX512EVEX 31911 ISA_SET: AVX512F_SCALAR 31912 EXCEPTIONS: AVX512-E3 31913 REAL_OPCODE: Y 31914 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31915 PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 31916 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31917 IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31918 } 31919 31920 { 31921 ICLASS: VFMADD231SD 31922 CPL: 3 31923 CATEGORY: VFMA 31924 EXTENSION: AVX512EVEX 31925 ISA_SET: AVX512F_SCALAR 31926 EXCEPTIONS: AVX512-E3 31927 REAL_OPCODE: Y 31928 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 31929 PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 31930 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 31931 IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31932 } 31933 31934 31935 # EMITTING VFMADD231SS (VFMADD231SS-128-1) 31936 { 31937 ICLASS: VFMADD231SS 31938 CPL: 3 31939 CATEGORY: VFMA 31940 EXTENSION: AVX512EVEX 31941 ISA_SET: AVX512F_SCALAR 31942 EXCEPTIONS: AVX512-E3 31943 REAL_OPCODE: Y 31944 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31945 PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 31946 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31947 IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31948 } 31949 31950 { 31951 ICLASS: VFMADD231SS 31952 CPL: 3 31953 CATEGORY: VFMA 31954 EXTENSION: AVX512EVEX 31955 ISA_SET: AVX512F_SCALAR 31956 EXCEPTIONS: AVX512-E3 31957 REAL_OPCODE: Y 31958 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 31959 PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 31960 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31961 IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31962 } 31963 31964 { 31965 ICLASS: VFMADD231SS 31966 CPL: 3 31967 CATEGORY: VFMA 31968 EXTENSION: AVX512EVEX 31969 ISA_SET: AVX512F_SCALAR 31970 EXCEPTIONS: AVX512-E3 31971 REAL_OPCODE: Y 31972 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 31973 PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 31974 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 31975 IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31976 } 31977 31978 31979 # EMITTING VFMADDSUB132PD (VFMADDSUB132PD-512-1) 31980 { 31981 ICLASS: VFMADDSUB132PD 31982 CPL: 3 31983 CATEGORY: VFMA 31984 EXTENSION: AVX512EVEX 31985 ISA_SET: AVX512F_512 31986 EXCEPTIONS: AVX512-E2 31987 REAL_OPCODE: Y 31988 ATTRIBUTES: MXCSR MASKOP_EVEX 31989 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 31990 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 31991 IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 31992 } 31993 31994 { 31995 ICLASS: VFMADDSUB132PD 31996 CPL: 3 31997 CATEGORY: VFMA 31998 EXTENSION: AVX512EVEX 31999 ISA_SET: AVX512F_512 32000 EXCEPTIONS: AVX512-E2 32001 REAL_OPCODE: Y 32002 ATTRIBUTES: MXCSR MASKOP_EVEX 32003 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 32004 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32005 IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32006 } 32007 32008 { 32009 ICLASS: VFMADDSUB132PD 32010 CPL: 3 32011 CATEGORY: VFMA 32012 EXTENSION: AVX512EVEX 32013 ISA_SET: AVX512F_512 32014 EXCEPTIONS: AVX512-E2 32015 REAL_OPCODE: Y 32016 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32017 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 32018 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 32019 IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 32020 } 32021 32022 32023 # EMITTING VFMADDSUB132PS (VFMADDSUB132PS-512-1) 32024 { 32025 ICLASS: VFMADDSUB132PS 32026 CPL: 3 32027 CATEGORY: VFMA 32028 EXTENSION: AVX512EVEX 32029 ISA_SET: AVX512F_512 32030 EXCEPTIONS: AVX512-E2 32031 REAL_OPCODE: Y 32032 ATTRIBUTES: MXCSR MASKOP_EVEX 32033 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 32034 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32035 IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32036 } 32037 32038 { 32039 ICLASS: VFMADDSUB132PS 32040 CPL: 3 32041 CATEGORY: VFMA 32042 EXTENSION: AVX512EVEX 32043 ISA_SET: AVX512F_512 32044 EXCEPTIONS: AVX512-E2 32045 REAL_OPCODE: Y 32046 ATTRIBUTES: MXCSR MASKOP_EVEX 32047 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 32048 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32049 IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32050 } 32051 32052 { 32053 ICLASS: VFMADDSUB132PS 32054 CPL: 3 32055 CATEGORY: VFMA 32056 EXTENSION: AVX512EVEX 32057 ISA_SET: AVX512F_512 32058 EXCEPTIONS: AVX512-E2 32059 REAL_OPCODE: Y 32060 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32061 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 32062 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 32063 IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 32064 } 32065 32066 32067 # EMITTING VFMADDSUB213PD (VFMADDSUB213PD-512-1) 32068 { 32069 ICLASS: VFMADDSUB213PD 32070 CPL: 3 32071 CATEGORY: VFMA 32072 EXTENSION: AVX512EVEX 32073 ISA_SET: AVX512F_512 32074 EXCEPTIONS: AVX512-E2 32075 REAL_OPCODE: Y 32076 ATTRIBUTES: MXCSR MASKOP_EVEX 32077 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 32078 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32079 IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32080 } 32081 32082 { 32083 ICLASS: VFMADDSUB213PD 32084 CPL: 3 32085 CATEGORY: VFMA 32086 EXTENSION: AVX512EVEX 32087 ISA_SET: AVX512F_512 32088 EXCEPTIONS: AVX512-E2 32089 REAL_OPCODE: Y 32090 ATTRIBUTES: MXCSR MASKOP_EVEX 32091 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 32092 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32093 IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32094 } 32095 32096 { 32097 ICLASS: VFMADDSUB213PD 32098 CPL: 3 32099 CATEGORY: VFMA 32100 EXTENSION: AVX512EVEX 32101 ISA_SET: AVX512F_512 32102 EXCEPTIONS: AVX512-E2 32103 REAL_OPCODE: Y 32104 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32105 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 32106 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 32107 IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 32108 } 32109 32110 32111 # EMITTING VFMADDSUB213PS (VFMADDSUB213PS-512-1) 32112 { 32113 ICLASS: VFMADDSUB213PS 32114 CPL: 3 32115 CATEGORY: VFMA 32116 EXTENSION: AVX512EVEX 32117 ISA_SET: AVX512F_512 32118 EXCEPTIONS: AVX512-E2 32119 REAL_OPCODE: Y 32120 ATTRIBUTES: MXCSR MASKOP_EVEX 32121 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 32122 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32123 IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32124 } 32125 32126 { 32127 ICLASS: VFMADDSUB213PS 32128 CPL: 3 32129 CATEGORY: VFMA 32130 EXTENSION: AVX512EVEX 32131 ISA_SET: AVX512F_512 32132 EXCEPTIONS: AVX512-E2 32133 REAL_OPCODE: Y 32134 ATTRIBUTES: MXCSR MASKOP_EVEX 32135 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 32136 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32137 IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32138 } 32139 32140 { 32141 ICLASS: VFMADDSUB213PS 32142 CPL: 3 32143 CATEGORY: VFMA 32144 EXTENSION: AVX512EVEX 32145 ISA_SET: AVX512F_512 32146 EXCEPTIONS: AVX512-E2 32147 REAL_OPCODE: Y 32148 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32149 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 32150 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 32151 IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 32152 } 32153 32154 32155 # EMITTING VFMADDSUB231PD (VFMADDSUB231PD-512-1) 32156 { 32157 ICLASS: VFMADDSUB231PD 32158 CPL: 3 32159 CATEGORY: VFMA 32160 EXTENSION: AVX512EVEX 32161 ISA_SET: AVX512F_512 32162 EXCEPTIONS: AVX512-E2 32163 REAL_OPCODE: Y 32164 ATTRIBUTES: MXCSR MASKOP_EVEX 32165 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 32166 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32167 IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32168 } 32169 32170 { 32171 ICLASS: VFMADDSUB231PD 32172 CPL: 3 32173 CATEGORY: VFMA 32174 EXTENSION: AVX512EVEX 32175 ISA_SET: AVX512F_512 32176 EXCEPTIONS: AVX512-E2 32177 REAL_OPCODE: Y 32178 ATTRIBUTES: MXCSR MASKOP_EVEX 32179 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 32180 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32181 IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32182 } 32183 32184 { 32185 ICLASS: VFMADDSUB231PD 32186 CPL: 3 32187 CATEGORY: VFMA 32188 EXTENSION: AVX512EVEX 32189 ISA_SET: AVX512F_512 32190 EXCEPTIONS: AVX512-E2 32191 REAL_OPCODE: Y 32192 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32193 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 32194 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 32195 IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 32196 } 32197 32198 32199 # EMITTING VFMADDSUB231PS (VFMADDSUB231PS-512-1) 32200 { 32201 ICLASS: VFMADDSUB231PS 32202 CPL: 3 32203 CATEGORY: VFMA 32204 EXTENSION: AVX512EVEX 32205 ISA_SET: AVX512F_512 32206 EXCEPTIONS: AVX512-E2 32207 REAL_OPCODE: Y 32208 ATTRIBUTES: MXCSR MASKOP_EVEX 32209 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 32210 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32211 IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32212 } 32213 32214 { 32215 ICLASS: VFMADDSUB231PS 32216 CPL: 3 32217 CATEGORY: VFMA 32218 EXTENSION: AVX512EVEX 32219 ISA_SET: AVX512F_512 32220 EXCEPTIONS: AVX512-E2 32221 REAL_OPCODE: Y 32222 ATTRIBUTES: MXCSR MASKOP_EVEX 32223 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 32224 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32225 IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32226 } 32227 32228 { 32229 ICLASS: VFMADDSUB231PS 32230 CPL: 3 32231 CATEGORY: VFMA 32232 EXTENSION: AVX512EVEX 32233 ISA_SET: AVX512F_512 32234 EXCEPTIONS: AVX512-E2 32235 REAL_OPCODE: Y 32236 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32237 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 32238 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 32239 IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 32240 } 32241 32242 32243 # EMITTING VFMSUB132PD (VFMSUB132PD-512-1) 32244 { 32245 ICLASS: VFMSUB132PD 32246 CPL: 3 32247 CATEGORY: VFMA 32248 EXTENSION: AVX512EVEX 32249 ISA_SET: AVX512F_512 32250 EXCEPTIONS: AVX512-E2 32251 REAL_OPCODE: Y 32252 ATTRIBUTES: MXCSR MASKOP_EVEX 32253 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 32254 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32255 IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32256 } 32257 32258 { 32259 ICLASS: VFMSUB132PD 32260 CPL: 3 32261 CATEGORY: VFMA 32262 EXTENSION: AVX512EVEX 32263 ISA_SET: AVX512F_512 32264 EXCEPTIONS: AVX512-E2 32265 REAL_OPCODE: Y 32266 ATTRIBUTES: MXCSR MASKOP_EVEX 32267 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 32268 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32269 IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32270 } 32271 32272 { 32273 ICLASS: VFMSUB132PD 32274 CPL: 3 32275 CATEGORY: VFMA 32276 EXTENSION: AVX512EVEX 32277 ISA_SET: AVX512F_512 32278 EXCEPTIONS: AVX512-E2 32279 REAL_OPCODE: Y 32280 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32281 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 32282 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 32283 IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 32284 } 32285 32286 32287 # EMITTING VFMSUB132PS (VFMSUB132PS-512-1) 32288 { 32289 ICLASS: VFMSUB132PS 32290 CPL: 3 32291 CATEGORY: VFMA 32292 EXTENSION: AVX512EVEX 32293 ISA_SET: AVX512F_512 32294 EXCEPTIONS: AVX512-E2 32295 REAL_OPCODE: Y 32296 ATTRIBUTES: MXCSR MASKOP_EVEX 32297 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 32298 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32299 IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32300 } 32301 32302 { 32303 ICLASS: VFMSUB132PS 32304 CPL: 3 32305 CATEGORY: VFMA 32306 EXTENSION: AVX512EVEX 32307 ISA_SET: AVX512F_512 32308 EXCEPTIONS: AVX512-E2 32309 REAL_OPCODE: Y 32310 ATTRIBUTES: MXCSR MASKOP_EVEX 32311 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 32312 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32313 IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32314 } 32315 32316 { 32317 ICLASS: VFMSUB132PS 32318 CPL: 3 32319 CATEGORY: VFMA 32320 EXTENSION: AVX512EVEX 32321 ISA_SET: AVX512F_512 32322 EXCEPTIONS: AVX512-E2 32323 REAL_OPCODE: Y 32324 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32325 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 32326 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 32327 IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 32328 } 32329 32330 32331 # EMITTING VFMSUB132SD (VFMSUB132SD-128-1) 32332 { 32333 ICLASS: VFMSUB132SD 32334 CPL: 3 32335 CATEGORY: VFMA 32336 EXTENSION: AVX512EVEX 32337 ISA_SET: AVX512F_SCALAR 32338 EXCEPTIONS: AVX512-E3 32339 REAL_OPCODE: Y 32340 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32341 PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 32342 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 32343 IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 32344 } 32345 32346 { 32347 ICLASS: VFMSUB132SD 32348 CPL: 3 32349 CATEGORY: VFMA 32350 EXTENSION: AVX512EVEX 32351 ISA_SET: AVX512F_SCALAR 32352 EXCEPTIONS: AVX512-E3 32353 REAL_OPCODE: Y 32354 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32355 PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 32356 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 32357 IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 32358 } 32359 32360 { 32361 ICLASS: VFMSUB132SD 32362 CPL: 3 32363 CATEGORY: VFMA 32364 EXTENSION: AVX512EVEX 32365 ISA_SET: AVX512F_SCALAR 32366 EXCEPTIONS: AVX512-E3 32367 REAL_OPCODE: Y 32368 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 32369 PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 32370 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 32371 IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 32372 } 32373 32374 32375 # EMITTING VFMSUB132SS (VFMSUB132SS-128-1) 32376 { 32377 ICLASS: VFMSUB132SS 32378 CPL: 3 32379 CATEGORY: VFMA 32380 EXTENSION: AVX512EVEX 32381 ISA_SET: AVX512F_SCALAR 32382 EXCEPTIONS: AVX512-E3 32383 REAL_OPCODE: Y 32384 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32385 PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 32386 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 32387 IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 32388 } 32389 32390 { 32391 ICLASS: VFMSUB132SS 32392 CPL: 3 32393 CATEGORY: VFMA 32394 EXTENSION: AVX512EVEX 32395 ISA_SET: AVX512F_SCALAR 32396 EXCEPTIONS: AVX512-E3 32397 REAL_OPCODE: Y 32398 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32399 PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 32400 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 32401 IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 32402 } 32403 32404 { 32405 ICLASS: VFMSUB132SS 32406 CPL: 3 32407 CATEGORY: VFMA 32408 EXTENSION: AVX512EVEX 32409 ISA_SET: AVX512F_SCALAR 32410 EXCEPTIONS: AVX512-E3 32411 REAL_OPCODE: Y 32412 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 32413 PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 32414 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 32415 IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 32416 } 32417 32418 32419 # EMITTING VFMSUB213PD (VFMSUB213PD-512-1) 32420 { 32421 ICLASS: VFMSUB213PD 32422 CPL: 3 32423 CATEGORY: VFMA 32424 EXTENSION: AVX512EVEX 32425 ISA_SET: AVX512F_512 32426 EXCEPTIONS: AVX512-E2 32427 REAL_OPCODE: Y 32428 ATTRIBUTES: MXCSR MASKOP_EVEX 32429 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 32430 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32431 IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32432 } 32433 32434 { 32435 ICLASS: VFMSUB213PD 32436 CPL: 3 32437 CATEGORY: VFMA 32438 EXTENSION: AVX512EVEX 32439 ISA_SET: AVX512F_512 32440 EXCEPTIONS: AVX512-E2 32441 REAL_OPCODE: Y 32442 ATTRIBUTES: MXCSR MASKOP_EVEX 32443 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 32444 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32445 IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32446 } 32447 32448 { 32449 ICLASS: VFMSUB213PD 32450 CPL: 3 32451 CATEGORY: VFMA 32452 EXTENSION: AVX512EVEX 32453 ISA_SET: AVX512F_512 32454 EXCEPTIONS: AVX512-E2 32455 REAL_OPCODE: Y 32456 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32457 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 32458 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 32459 IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 32460 } 32461 32462 32463 # EMITTING VFMSUB213PS (VFMSUB213PS-512-1) 32464 { 32465 ICLASS: VFMSUB213PS 32466 CPL: 3 32467 CATEGORY: VFMA 32468 EXTENSION: AVX512EVEX 32469 ISA_SET: AVX512F_512 32470 EXCEPTIONS: AVX512-E2 32471 REAL_OPCODE: Y 32472 ATTRIBUTES: MXCSR MASKOP_EVEX 32473 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 32474 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32475 IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32476 } 32477 32478 { 32479 ICLASS: VFMSUB213PS 32480 CPL: 3 32481 CATEGORY: VFMA 32482 EXTENSION: AVX512EVEX 32483 ISA_SET: AVX512F_512 32484 EXCEPTIONS: AVX512-E2 32485 REAL_OPCODE: Y 32486 ATTRIBUTES: MXCSR MASKOP_EVEX 32487 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 32488 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32489 IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32490 } 32491 32492 { 32493 ICLASS: VFMSUB213PS 32494 CPL: 3 32495 CATEGORY: VFMA 32496 EXTENSION: AVX512EVEX 32497 ISA_SET: AVX512F_512 32498 EXCEPTIONS: AVX512-E2 32499 REAL_OPCODE: Y 32500 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32501 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 32502 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 32503 IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 32504 } 32505 32506 32507 # EMITTING VFMSUB213SD (VFMSUB213SD-128-1) 32508 { 32509 ICLASS: VFMSUB213SD 32510 CPL: 3 32511 CATEGORY: VFMA 32512 EXTENSION: AVX512EVEX 32513 ISA_SET: AVX512F_SCALAR 32514 EXCEPTIONS: AVX512-E3 32515 REAL_OPCODE: Y 32516 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32517 PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 32518 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 32519 IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 32520 } 32521 32522 { 32523 ICLASS: VFMSUB213SD 32524 CPL: 3 32525 CATEGORY: VFMA 32526 EXTENSION: AVX512EVEX 32527 ISA_SET: AVX512F_SCALAR 32528 EXCEPTIONS: AVX512-E3 32529 REAL_OPCODE: Y 32530 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32531 PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 32532 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 32533 IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 32534 } 32535 32536 { 32537 ICLASS: VFMSUB213SD 32538 CPL: 3 32539 CATEGORY: VFMA 32540 EXTENSION: AVX512EVEX 32541 ISA_SET: AVX512F_SCALAR 32542 EXCEPTIONS: AVX512-E3 32543 REAL_OPCODE: Y 32544 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 32545 PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 32546 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 32547 IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 32548 } 32549 32550 32551 # EMITTING VFMSUB213SS (VFMSUB213SS-128-1) 32552 { 32553 ICLASS: VFMSUB213SS 32554 CPL: 3 32555 CATEGORY: VFMA 32556 EXTENSION: AVX512EVEX 32557 ISA_SET: AVX512F_SCALAR 32558 EXCEPTIONS: AVX512-E3 32559 REAL_OPCODE: Y 32560 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32561 PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 32562 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 32563 IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 32564 } 32565 32566 { 32567 ICLASS: VFMSUB213SS 32568 CPL: 3 32569 CATEGORY: VFMA 32570 EXTENSION: AVX512EVEX 32571 ISA_SET: AVX512F_SCALAR 32572 EXCEPTIONS: AVX512-E3 32573 REAL_OPCODE: Y 32574 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32575 PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 32576 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 32577 IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 32578 } 32579 32580 { 32581 ICLASS: VFMSUB213SS 32582 CPL: 3 32583 CATEGORY: VFMA 32584 EXTENSION: AVX512EVEX 32585 ISA_SET: AVX512F_SCALAR 32586 EXCEPTIONS: AVX512-E3 32587 REAL_OPCODE: Y 32588 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 32589 PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 32590 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 32591 IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 32592 } 32593 32594 32595 # EMITTING VFMSUB231PD (VFMSUB231PD-512-1) 32596 { 32597 ICLASS: VFMSUB231PD 32598 CPL: 3 32599 CATEGORY: VFMA 32600 EXTENSION: AVX512EVEX 32601 ISA_SET: AVX512F_512 32602 EXCEPTIONS: AVX512-E2 32603 REAL_OPCODE: Y 32604 ATTRIBUTES: MXCSR MASKOP_EVEX 32605 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 32606 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32607 IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32608 } 32609 32610 { 32611 ICLASS: VFMSUB231PD 32612 CPL: 3 32613 CATEGORY: VFMA 32614 EXTENSION: AVX512EVEX 32615 ISA_SET: AVX512F_512 32616 EXCEPTIONS: AVX512-E2 32617 REAL_OPCODE: Y 32618 ATTRIBUTES: MXCSR MASKOP_EVEX 32619 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 32620 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32621 IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32622 } 32623 32624 { 32625 ICLASS: VFMSUB231PD 32626 CPL: 3 32627 CATEGORY: VFMA 32628 EXTENSION: AVX512EVEX 32629 ISA_SET: AVX512F_512 32630 EXCEPTIONS: AVX512-E2 32631 REAL_OPCODE: Y 32632 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32633 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 32634 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 32635 IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 32636 } 32637 32638 32639 # EMITTING VFMSUB231PS (VFMSUB231PS-512-1) 32640 { 32641 ICLASS: VFMSUB231PS 32642 CPL: 3 32643 CATEGORY: VFMA 32644 EXTENSION: AVX512EVEX 32645 ISA_SET: AVX512F_512 32646 EXCEPTIONS: AVX512-E2 32647 REAL_OPCODE: Y 32648 ATTRIBUTES: MXCSR MASKOP_EVEX 32649 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 32650 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32651 IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32652 } 32653 32654 { 32655 ICLASS: VFMSUB231PS 32656 CPL: 3 32657 CATEGORY: VFMA 32658 EXTENSION: AVX512EVEX 32659 ISA_SET: AVX512F_512 32660 EXCEPTIONS: AVX512-E2 32661 REAL_OPCODE: Y 32662 ATTRIBUTES: MXCSR MASKOP_EVEX 32663 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 32664 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32665 IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32666 } 32667 32668 { 32669 ICLASS: VFMSUB231PS 32670 CPL: 3 32671 CATEGORY: VFMA 32672 EXTENSION: AVX512EVEX 32673 ISA_SET: AVX512F_512 32674 EXCEPTIONS: AVX512-E2 32675 REAL_OPCODE: Y 32676 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32677 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 32678 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 32679 IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 32680 } 32681 32682 32683 # EMITTING VFMSUB231SD (VFMSUB231SD-128-1) 32684 { 32685 ICLASS: VFMSUB231SD 32686 CPL: 3 32687 CATEGORY: VFMA 32688 EXTENSION: AVX512EVEX 32689 ISA_SET: AVX512F_SCALAR 32690 EXCEPTIONS: AVX512-E3 32691 REAL_OPCODE: Y 32692 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32693 PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 32694 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 32695 IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 32696 } 32697 32698 { 32699 ICLASS: VFMSUB231SD 32700 CPL: 3 32701 CATEGORY: VFMA 32702 EXTENSION: AVX512EVEX 32703 ISA_SET: AVX512F_SCALAR 32704 EXCEPTIONS: AVX512-E3 32705 REAL_OPCODE: Y 32706 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32707 PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 32708 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 32709 IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 32710 } 32711 32712 { 32713 ICLASS: VFMSUB231SD 32714 CPL: 3 32715 CATEGORY: VFMA 32716 EXTENSION: AVX512EVEX 32717 ISA_SET: AVX512F_SCALAR 32718 EXCEPTIONS: AVX512-E3 32719 REAL_OPCODE: Y 32720 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 32721 PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 32722 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 32723 IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 32724 } 32725 32726 32727 # EMITTING VFMSUB231SS (VFMSUB231SS-128-1) 32728 { 32729 ICLASS: VFMSUB231SS 32730 CPL: 3 32731 CATEGORY: VFMA 32732 EXTENSION: AVX512EVEX 32733 ISA_SET: AVX512F_SCALAR 32734 EXCEPTIONS: AVX512-E3 32735 REAL_OPCODE: Y 32736 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32737 PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 32738 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 32739 IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 32740 } 32741 32742 { 32743 ICLASS: VFMSUB231SS 32744 CPL: 3 32745 CATEGORY: VFMA 32746 EXTENSION: AVX512EVEX 32747 ISA_SET: AVX512F_SCALAR 32748 EXCEPTIONS: AVX512-E3 32749 REAL_OPCODE: Y 32750 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 32751 PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 32752 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 32753 IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 32754 } 32755 32756 { 32757 ICLASS: VFMSUB231SS 32758 CPL: 3 32759 CATEGORY: VFMA 32760 EXTENSION: AVX512EVEX 32761 ISA_SET: AVX512F_SCALAR 32762 EXCEPTIONS: AVX512-E3 32763 REAL_OPCODE: Y 32764 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 32765 PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 32766 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 32767 IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 32768 } 32769 32770 32771 # EMITTING VFMSUBADD132PD (VFMSUBADD132PD-512-1) 32772 { 32773 ICLASS: VFMSUBADD132PD 32774 CPL: 3 32775 CATEGORY: VFMA 32776 EXTENSION: AVX512EVEX 32777 ISA_SET: AVX512F_512 32778 EXCEPTIONS: AVX512-E2 32779 REAL_OPCODE: Y 32780 ATTRIBUTES: MXCSR MASKOP_EVEX 32781 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 32782 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32783 IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32784 } 32785 32786 { 32787 ICLASS: VFMSUBADD132PD 32788 CPL: 3 32789 CATEGORY: VFMA 32790 EXTENSION: AVX512EVEX 32791 ISA_SET: AVX512F_512 32792 EXCEPTIONS: AVX512-E2 32793 REAL_OPCODE: Y 32794 ATTRIBUTES: MXCSR MASKOP_EVEX 32795 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 32796 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32797 IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32798 } 32799 32800 { 32801 ICLASS: VFMSUBADD132PD 32802 CPL: 3 32803 CATEGORY: VFMA 32804 EXTENSION: AVX512EVEX 32805 ISA_SET: AVX512F_512 32806 EXCEPTIONS: AVX512-E2 32807 REAL_OPCODE: Y 32808 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32809 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 32810 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 32811 IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 32812 } 32813 32814 32815 # EMITTING VFMSUBADD132PS (VFMSUBADD132PS-512-1) 32816 { 32817 ICLASS: VFMSUBADD132PS 32818 CPL: 3 32819 CATEGORY: VFMA 32820 EXTENSION: AVX512EVEX 32821 ISA_SET: AVX512F_512 32822 EXCEPTIONS: AVX512-E2 32823 REAL_OPCODE: Y 32824 ATTRIBUTES: MXCSR MASKOP_EVEX 32825 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 32826 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32827 IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32828 } 32829 32830 { 32831 ICLASS: VFMSUBADD132PS 32832 CPL: 3 32833 CATEGORY: VFMA 32834 EXTENSION: AVX512EVEX 32835 ISA_SET: AVX512F_512 32836 EXCEPTIONS: AVX512-E2 32837 REAL_OPCODE: Y 32838 ATTRIBUTES: MXCSR MASKOP_EVEX 32839 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 32840 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32841 IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32842 } 32843 32844 { 32845 ICLASS: VFMSUBADD132PS 32846 CPL: 3 32847 CATEGORY: VFMA 32848 EXTENSION: AVX512EVEX 32849 ISA_SET: AVX512F_512 32850 EXCEPTIONS: AVX512-E2 32851 REAL_OPCODE: Y 32852 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32853 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 32854 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 32855 IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 32856 } 32857 32858 32859 # EMITTING VFMSUBADD213PD (VFMSUBADD213PD-512-1) 32860 { 32861 ICLASS: VFMSUBADD213PD 32862 CPL: 3 32863 CATEGORY: VFMA 32864 EXTENSION: AVX512EVEX 32865 ISA_SET: AVX512F_512 32866 EXCEPTIONS: AVX512-E2 32867 REAL_OPCODE: Y 32868 ATTRIBUTES: MXCSR MASKOP_EVEX 32869 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 32870 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32871 IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32872 } 32873 32874 { 32875 ICLASS: VFMSUBADD213PD 32876 CPL: 3 32877 CATEGORY: VFMA 32878 EXTENSION: AVX512EVEX 32879 ISA_SET: AVX512F_512 32880 EXCEPTIONS: AVX512-E2 32881 REAL_OPCODE: Y 32882 ATTRIBUTES: MXCSR MASKOP_EVEX 32883 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 32884 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32885 IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32886 } 32887 32888 { 32889 ICLASS: VFMSUBADD213PD 32890 CPL: 3 32891 CATEGORY: VFMA 32892 EXTENSION: AVX512EVEX 32893 ISA_SET: AVX512F_512 32894 EXCEPTIONS: AVX512-E2 32895 REAL_OPCODE: Y 32896 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32897 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 32898 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 32899 IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 32900 } 32901 32902 32903 # EMITTING VFMSUBADD213PS (VFMSUBADD213PS-512-1) 32904 { 32905 ICLASS: VFMSUBADD213PS 32906 CPL: 3 32907 CATEGORY: VFMA 32908 EXTENSION: AVX512EVEX 32909 ISA_SET: AVX512F_512 32910 EXCEPTIONS: AVX512-E2 32911 REAL_OPCODE: Y 32912 ATTRIBUTES: MXCSR MASKOP_EVEX 32913 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 32914 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32915 IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32916 } 32917 32918 { 32919 ICLASS: VFMSUBADD213PS 32920 CPL: 3 32921 CATEGORY: VFMA 32922 EXTENSION: AVX512EVEX 32923 ISA_SET: AVX512F_512 32924 EXCEPTIONS: AVX512-E2 32925 REAL_OPCODE: Y 32926 ATTRIBUTES: MXCSR MASKOP_EVEX 32927 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 32928 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 32929 IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 32930 } 32931 32932 { 32933 ICLASS: VFMSUBADD213PS 32934 CPL: 3 32935 CATEGORY: VFMA 32936 EXTENSION: AVX512EVEX 32937 ISA_SET: AVX512F_512 32938 EXCEPTIONS: AVX512-E2 32939 REAL_OPCODE: Y 32940 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32941 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 32942 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 32943 IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 32944 } 32945 32946 32947 # EMITTING VFMSUBADD231PD (VFMSUBADD231PD-512-1) 32948 { 32949 ICLASS: VFMSUBADD231PD 32950 CPL: 3 32951 CATEGORY: VFMA 32952 EXTENSION: AVX512EVEX 32953 ISA_SET: AVX512F_512 32954 EXCEPTIONS: AVX512-E2 32955 REAL_OPCODE: Y 32956 ATTRIBUTES: MXCSR MASKOP_EVEX 32957 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 32958 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32959 IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32960 } 32961 32962 { 32963 ICLASS: VFMSUBADD231PD 32964 CPL: 3 32965 CATEGORY: VFMA 32966 EXTENSION: AVX512EVEX 32967 ISA_SET: AVX512F_512 32968 EXCEPTIONS: AVX512-E2 32969 REAL_OPCODE: Y 32970 ATTRIBUTES: MXCSR MASKOP_EVEX 32971 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 32972 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 32973 IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 32974 } 32975 32976 { 32977 ICLASS: VFMSUBADD231PD 32978 CPL: 3 32979 CATEGORY: VFMA 32980 EXTENSION: AVX512EVEX 32981 ISA_SET: AVX512F_512 32982 EXCEPTIONS: AVX512-E2 32983 REAL_OPCODE: Y 32984 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 32985 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 32986 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 32987 IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 32988 } 32989 32990 32991 # EMITTING VFMSUBADD231PS (VFMSUBADD231PS-512-1) 32992 { 32993 ICLASS: VFMSUBADD231PS 32994 CPL: 3 32995 CATEGORY: VFMA 32996 EXTENSION: AVX512EVEX 32997 ISA_SET: AVX512F_512 32998 EXCEPTIONS: AVX512-E2 32999 REAL_OPCODE: Y 33000 ATTRIBUTES: MXCSR MASKOP_EVEX 33001 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 33002 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33003 IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33004 } 33005 33006 { 33007 ICLASS: VFMSUBADD231PS 33008 CPL: 3 33009 CATEGORY: VFMA 33010 EXTENSION: AVX512EVEX 33011 ISA_SET: AVX512F_512 33012 EXCEPTIONS: AVX512-E2 33013 REAL_OPCODE: Y 33014 ATTRIBUTES: MXCSR MASKOP_EVEX 33015 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 33016 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33017 IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33018 } 33019 33020 { 33021 ICLASS: VFMSUBADD231PS 33022 CPL: 3 33023 CATEGORY: VFMA 33024 EXTENSION: AVX512EVEX 33025 ISA_SET: AVX512F_512 33026 EXCEPTIONS: AVX512-E2 33027 REAL_OPCODE: Y 33028 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33029 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 33030 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 33031 IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 33032 } 33033 33034 33035 # EMITTING VFNMADD132PD (VFNMADD132PD-512-1) 33036 { 33037 ICLASS: VFNMADD132PD 33038 CPL: 3 33039 CATEGORY: VFMA 33040 EXTENSION: AVX512EVEX 33041 ISA_SET: AVX512F_512 33042 EXCEPTIONS: AVX512-E2 33043 REAL_OPCODE: Y 33044 ATTRIBUTES: MXCSR MASKOP_EVEX 33045 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 33046 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33047 IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33048 } 33049 33050 { 33051 ICLASS: VFNMADD132PD 33052 CPL: 3 33053 CATEGORY: VFMA 33054 EXTENSION: AVX512EVEX 33055 ISA_SET: AVX512F_512 33056 EXCEPTIONS: AVX512-E2 33057 REAL_OPCODE: Y 33058 ATTRIBUTES: MXCSR MASKOP_EVEX 33059 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 33060 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33061 IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33062 } 33063 33064 { 33065 ICLASS: VFNMADD132PD 33066 CPL: 3 33067 CATEGORY: VFMA 33068 EXTENSION: AVX512EVEX 33069 ISA_SET: AVX512F_512 33070 EXCEPTIONS: AVX512-E2 33071 REAL_OPCODE: Y 33072 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33073 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 33074 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 33075 IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 33076 } 33077 33078 33079 # EMITTING VFNMADD132PS (VFNMADD132PS-512-1) 33080 { 33081 ICLASS: VFNMADD132PS 33082 CPL: 3 33083 CATEGORY: VFMA 33084 EXTENSION: AVX512EVEX 33085 ISA_SET: AVX512F_512 33086 EXCEPTIONS: AVX512-E2 33087 REAL_OPCODE: Y 33088 ATTRIBUTES: MXCSR MASKOP_EVEX 33089 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 33090 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33091 IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33092 } 33093 33094 { 33095 ICLASS: VFNMADD132PS 33096 CPL: 3 33097 CATEGORY: VFMA 33098 EXTENSION: AVX512EVEX 33099 ISA_SET: AVX512F_512 33100 EXCEPTIONS: AVX512-E2 33101 REAL_OPCODE: Y 33102 ATTRIBUTES: MXCSR MASKOP_EVEX 33103 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 33104 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33105 IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33106 } 33107 33108 { 33109 ICLASS: VFNMADD132PS 33110 CPL: 3 33111 CATEGORY: VFMA 33112 EXTENSION: AVX512EVEX 33113 ISA_SET: AVX512F_512 33114 EXCEPTIONS: AVX512-E2 33115 REAL_OPCODE: Y 33116 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33117 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 33118 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 33119 IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 33120 } 33121 33122 33123 # EMITTING VFNMADD132SD (VFNMADD132SD-128-1) 33124 { 33125 ICLASS: VFNMADD132SD 33126 CPL: 3 33127 CATEGORY: VFMA 33128 EXTENSION: AVX512EVEX 33129 ISA_SET: AVX512F_SCALAR 33130 EXCEPTIONS: AVX512-E3 33131 REAL_OPCODE: Y 33132 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33133 PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 33134 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33135 IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33136 } 33137 33138 { 33139 ICLASS: VFNMADD132SD 33140 CPL: 3 33141 CATEGORY: VFMA 33142 EXTENSION: AVX512EVEX 33143 ISA_SET: AVX512F_SCALAR 33144 EXCEPTIONS: AVX512-E3 33145 REAL_OPCODE: Y 33146 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33147 PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 33148 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33149 IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33150 } 33151 33152 { 33153 ICLASS: VFNMADD132SD 33154 CPL: 3 33155 CATEGORY: VFMA 33156 EXTENSION: AVX512EVEX 33157 ISA_SET: AVX512F_SCALAR 33158 EXCEPTIONS: AVX512-E3 33159 REAL_OPCODE: Y 33160 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 33161 PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 33162 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 33163 IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 33164 } 33165 33166 33167 # EMITTING VFNMADD132SS (VFNMADD132SS-128-1) 33168 { 33169 ICLASS: VFNMADD132SS 33170 CPL: 3 33171 CATEGORY: VFMA 33172 EXTENSION: AVX512EVEX 33173 ISA_SET: AVX512F_SCALAR 33174 EXCEPTIONS: AVX512-E3 33175 REAL_OPCODE: Y 33176 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33177 PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 33178 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33179 IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33180 } 33181 33182 { 33183 ICLASS: VFNMADD132SS 33184 CPL: 3 33185 CATEGORY: VFMA 33186 EXTENSION: AVX512EVEX 33187 ISA_SET: AVX512F_SCALAR 33188 EXCEPTIONS: AVX512-E3 33189 REAL_OPCODE: Y 33190 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33191 PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 33192 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33193 IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33194 } 33195 33196 { 33197 ICLASS: VFNMADD132SS 33198 CPL: 3 33199 CATEGORY: VFMA 33200 EXTENSION: AVX512EVEX 33201 ISA_SET: AVX512F_SCALAR 33202 EXCEPTIONS: AVX512-E3 33203 REAL_OPCODE: Y 33204 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 33205 PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 33206 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 33207 IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 33208 } 33209 33210 33211 # EMITTING VFNMADD213PD (VFNMADD213PD-512-1) 33212 { 33213 ICLASS: VFNMADD213PD 33214 CPL: 3 33215 CATEGORY: VFMA 33216 EXTENSION: AVX512EVEX 33217 ISA_SET: AVX512F_512 33218 EXCEPTIONS: AVX512-E2 33219 REAL_OPCODE: Y 33220 ATTRIBUTES: MXCSR MASKOP_EVEX 33221 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 33222 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33223 IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33224 } 33225 33226 { 33227 ICLASS: VFNMADD213PD 33228 CPL: 3 33229 CATEGORY: VFMA 33230 EXTENSION: AVX512EVEX 33231 ISA_SET: AVX512F_512 33232 EXCEPTIONS: AVX512-E2 33233 REAL_OPCODE: Y 33234 ATTRIBUTES: MXCSR MASKOP_EVEX 33235 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 33236 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33237 IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33238 } 33239 33240 { 33241 ICLASS: VFNMADD213PD 33242 CPL: 3 33243 CATEGORY: VFMA 33244 EXTENSION: AVX512EVEX 33245 ISA_SET: AVX512F_512 33246 EXCEPTIONS: AVX512-E2 33247 REAL_OPCODE: Y 33248 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33249 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 33250 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 33251 IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 33252 } 33253 33254 33255 # EMITTING VFNMADD213PS (VFNMADD213PS-512-1) 33256 { 33257 ICLASS: VFNMADD213PS 33258 CPL: 3 33259 CATEGORY: VFMA 33260 EXTENSION: AVX512EVEX 33261 ISA_SET: AVX512F_512 33262 EXCEPTIONS: AVX512-E2 33263 REAL_OPCODE: Y 33264 ATTRIBUTES: MXCSR MASKOP_EVEX 33265 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 33266 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33267 IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33268 } 33269 33270 { 33271 ICLASS: VFNMADD213PS 33272 CPL: 3 33273 CATEGORY: VFMA 33274 EXTENSION: AVX512EVEX 33275 ISA_SET: AVX512F_512 33276 EXCEPTIONS: AVX512-E2 33277 REAL_OPCODE: Y 33278 ATTRIBUTES: MXCSR MASKOP_EVEX 33279 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 33280 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33281 IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33282 } 33283 33284 { 33285 ICLASS: VFNMADD213PS 33286 CPL: 3 33287 CATEGORY: VFMA 33288 EXTENSION: AVX512EVEX 33289 ISA_SET: AVX512F_512 33290 EXCEPTIONS: AVX512-E2 33291 REAL_OPCODE: Y 33292 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33293 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 33294 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 33295 IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 33296 } 33297 33298 33299 # EMITTING VFNMADD213SD (VFNMADD213SD-128-1) 33300 { 33301 ICLASS: VFNMADD213SD 33302 CPL: 3 33303 CATEGORY: VFMA 33304 EXTENSION: AVX512EVEX 33305 ISA_SET: AVX512F_SCALAR 33306 EXCEPTIONS: AVX512-E3 33307 REAL_OPCODE: Y 33308 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33309 PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 33310 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33311 IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33312 } 33313 33314 { 33315 ICLASS: VFNMADD213SD 33316 CPL: 3 33317 CATEGORY: VFMA 33318 EXTENSION: AVX512EVEX 33319 ISA_SET: AVX512F_SCALAR 33320 EXCEPTIONS: AVX512-E3 33321 REAL_OPCODE: Y 33322 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33323 PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 33324 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33325 IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33326 } 33327 33328 { 33329 ICLASS: VFNMADD213SD 33330 CPL: 3 33331 CATEGORY: VFMA 33332 EXTENSION: AVX512EVEX 33333 ISA_SET: AVX512F_SCALAR 33334 EXCEPTIONS: AVX512-E3 33335 REAL_OPCODE: Y 33336 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 33337 PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 33338 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 33339 IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 33340 } 33341 33342 33343 # EMITTING VFNMADD213SS (VFNMADD213SS-128-1) 33344 { 33345 ICLASS: VFNMADD213SS 33346 CPL: 3 33347 CATEGORY: VFMA 33348 EXTENSION: AVX512EVEX 33349 ISA_SET: AVX512F_SCALAR 33350 EXCEPTIONS: AVX512-E3 33351 REAL_OPCODE: Y 33352 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33353 PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 33354 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33355 IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33356 } 33357 33358 { 33359 ICLASS: VFNMADD213SS 33360 CPL: 3 33361 CATEGORY: VFMA 33362 EXTENSION: AVX512EVEX 33363 ISA_SET: AVX512F_SCALAR 33364 EXCEPTIONS: AVX512-E3 33365 REAL_OPCODE: Y 33366 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33367 PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 33368 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33369 IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33370 } 33371 33372 { 33373 ICLASS: VFNMADD213SS 33374 CPL: 3 33375 CATEGORY: VFMA 33376 EXTENSION: AVX512EVEX 33377 ISA_SET: AVX512F_SCALAR 33378 EXCEPTIONS: AVX512-E3 33379 REAL_OPCODE: Y 33380 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 33381 PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 33382 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 33383 IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 33384 } 33385 33386 33387 # EMITTING VFNMADD231PD (VFNMADD231PD-512-1) 33388 { 33389 ICLASS: VFNMADD231PD 33390 CPL: 3 33391 CATEGORY: VFMA 33392 EXTENSION: AVX512EVEX 33393 ISA_SET: AVX512F_512 33394 EXCEPTIONS: AVX512-E2 33395 REAL_OPCODE: Y 33396 ATTRIBUTES: MXCSR MASKOP_EVEX 33397 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 33398 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33399 IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33400 } 33401 33402 { 33403 ICLASS: VFNMADD231PD 33404 CPL: 3 33405 CATEGORY: VFMA 33406 EXTENSION: AVX512EVEX 33407 ISA_SET: AVX512F_512 33408 EXCEPTIONS: AVX512-E2 33409 REAL_OPCODE: Y 33410 ATTRIBUTES: MXCSR MASKOP_EVEX 33411 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 33412 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33413 IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33414 } 33415 33416 { 33417 ICLASS: VFNMADD231PD 33418 CPL: 3 33419 CATEGORY: VFMA 33420 EXTENSION: AVX512EVEX 33421 ISA_SET: AVX512F_512 33422 EXCEPTIONS: AVX512-E2 33423 REAL_OPCODE: Y 33424 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33425 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 33426 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 33427 IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 33428 } 33429 33430 33431 # EMITTING VFNMADD231PS (VFNMADD231PS-512-1) 33432 { 33433 ICLASS: VFNMADD231PS 33434 CPL: 3 33435 CATEGORY: VFMA 33436 EXTENSION: AVX512EVEX 33437 ISA_SET: AVX512F_512 33438 EXCEPTIONS: AVX512-E2 33439 REAL_OPCODE: Y 33440 ATTRIBUTES: MXCSR MASKOP_EVEX 33441 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 33442 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33443 IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33444 } 33445 33446 { 33447 ICLASS: VFNMADD231PS 33448 CPL: 3 33449 CATEGORY: VFMA 33450 EXTENSION: AVX512EVEX 33451 ISA_SET: AVX512F_512 33452 EXCEPTIONS: AVX512-E2 33453 REAL_OPCODE: Y 33454 ATTRIBUTES: MXCSR MASKOP_EVEX 33455 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 33456 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33457 IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33458 } 33459 33460 { 33461 ICLASS: VFNMADD231PS 33462 CPL: 3 33463 CATEGORY: VFMA 33464 EXTENSION: AVX512EVEX 33465 ISA_SET: AVX512F_512 33466 EXCEPTIONS: AVX512-E2 33467 REAL_OPCODE: Y 33468 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33469 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 33470 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 33471 IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 33472 } 33473 33474 33475 # EMITTING VFNMADD231SD (VFNMADD231SD-128-1) 33476 { 33477 ICLASS: VFNMADD231SD 33478 CPL: 3 33479 CATEGORY: VFMA 33480 EXTENSION: AVX512EVEX 33481 ISA_SET: AVX512F_SCALAR 33482 EXCEPTIONS: AVX512-E3 33483 REAL_OPCODE: Y 33484 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33485 PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 33486 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33487 IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33488 } 33489 33490 { 33491 ICLASS: VFNMADD231SD 33492 CPL: 3 33493 CATEGORY: VFMA 33494 EXTENSION: AVX512EVEX 33495 ISA_SET: AVX512F_SCALAR 33496 EXCEPTIONS: AVX512-E3 33497 REAL_OPCODE: Y 33498 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33499 PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 33500 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33501 IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33502 } 33503 33504 { 33505 ICLASS: VFNMADD231SD 33506 CPL: 3 33507 CATEGORY: VFMA 33508 EXTENSION: AVX512EVEX 33509 ISA_SET: AVX512F_SCALAR 33510 EXCEPTIONS: AVX512-E3 33511 REAL_OPCODE: Y 33512 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 33513 PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 33514 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 33515 IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 33516 } 33517 33518 33519 # EMITTING VFNMADD231SS (VFNMADD231SS-128-1) 33520 { 33521 ICLASS: VFNMADD231SS 33522 CPL: 3 33523 CATEGORY: VFMA 33524 EXTENSION: AVX512EVEX 33525 ISA_SET: AVX512F_SCALAR 33526 EXCEPTIONS: AVX512-E3 33527 REAL_OPCODE: Y 33528 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33529 PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 33530 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33531 IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33532 } 33533 33534 { 33535 ICLASS: VFNMADD231SS 33536 CPL: 3 33537 CATEGORY: VFMA 33538 EXTENSION: AVX512EVEX 33539 ISA_SET: AVX512F_SCALAR 33540 EXCEPTIONS: AVX512-E3 33541 REAL_OPCODE: Y 33542 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33543 PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 33544 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33545 IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33546 } 33547 33548 { 33549 ICLASS: VFNMADD231SS 33550 CPL: 3 33551 CATEGORY: VFMA 33552 EXTENSION: AVX512EVEX 33553 ISA_SET: AVX512F_SCALAR 33554 EXCEPTIONS: AVX512-E3 33555 REAL_OPCODE: Y 33556 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 33557 PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 33558 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 33559 IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 33560 } 33561 33562 33563 # EMITTING VFNMSUB132PD (VFNMSUB132PD-512-1) 33564 { 33565 ICLASS: VFNMSUB132PD 33566 CPL: 3 33567 CATEGORY: VFMA 33568 EXTENSION: AVX512EVEX 33569 ISA_SET: AVX512F_512 33570 EXCEPTIONS: AVX512-E2 33571 REAL_OPCODE: Y 33572 ATTRIBUTES: MXCSR MASKOP_EVEX 33573 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 33574 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33575 IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33576 } 33577 33578 { 33579 ICLASS: VFNMSUB132PD 33580 CPL: 3 33581 CATEGORY: VFMA 33582 EXTENSION: AVX512EVEX 33583 ISA_SET: AVX512F_512 33584 EXCEPTIONS: AVX512-E2 33585 REAL_OPCODE: Y 33586 ATTRIBUTES: MXCSR MASKOP_EVEX 33587 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 33588 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33589 IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33590 } 33591 33592 { 33593 ICLASS: VFNMSUB132PD 33594 CPL: 3 33595 CATEGORY: VFMA 33596 EXTENSION: AVX512EVEX 33597 ISA_SET: AVX512F_512 33598 EXCEPTIONS: AVX512-E2 33599 REAL_OPCODE: Y 33600 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33601 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 33602 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 33603 IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 33604 } 33605 33606 33607 # EMITTING VFNMSUB132PS (VFNMSUB132PS-512-1) 33608 { 33609 ICLASS: VFNMSUB132PS 33610 CPL: 3 33611 CATEGORY: VFMA 33612 EXTENSION: AVX512EVEX 33613 ISA_SET: AVX512F_512 33614 EXCEPTIONS: AVX512-E2 33615 REAL_OPCODE: Y 33616 ATTRIBUTES: MXCSR MASKOP_EVEX 33617 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 33618 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33619 IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33620 } 33621 33622 { 33623 ICLASS: VFNMSUB132PS 33624 CPL: 3 33625 CATEGORY: VFMA 33626 EXTENSION: AVX512EVEX 33627 ISA_SET: AVX512F_512 33628 EXCEPTIONS: AVX512-E2 33629 REAL_OPCODE: Y 33630 ATTRIBUTES: MXCSR MASKOP_EVEX 33631 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 33632 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33633 IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33634 } 33635 33636 { 33637 ICLASS: VFNMSUB132PS 33638 CPL: 3 33639 CATEGORY: VFMA 33640 EXTENSION: AVX512EVEX 33641 ISA_SET: AVX512F_512 33642 EXCEPTIONS: AVX512-E2 33643 REAL_OPCODE: Y 33644 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33645 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 33646 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 33647 IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 33648 } 33649 33650 33651 # EMITTING VFNMSUB132SD (VFNMSUB132SD-128-1) 33652 { 33653 ICLASS: VFNMSUB132SD 33654 CPL: 3 33655 CATEGORY: VFMA 33656 EXTENSION: AVX512EVEX 33657 ISA_SET: AVX512F_SCALAR 33658 EXCEPTIONS: AVX512-E3 33659 REAL_OPCODE: Y 33660 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33661 PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 33662 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33663 IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33664 } 33665 33666 { 33667 ICLASS: VFNMSUB132SD 33668 CPL: 3 33669 CATEGORY: VFMA 33670 EXTENSION: AVX512EVEX 33671 ISA_SET: AVX512F_SCALAR 33672 EXCEPTIONS: AVX512-E3 33673 REAL_OPCODE: Y 33674 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33675 PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 33676 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33677 IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33678 } 33679 33680 { 33681 ICLASS: VFNMSUB132SD 33682 CPL: 3 33683 CATEGORY: VFMA 33684 EXTENSION: AVX512EVEX 33685 ISA_SET: AVX512F_SCALAR 33686 EXCEPTIONS: AVX512-E3 33687 REAL_OPCODE: Y 33688 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 33689 PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 33690 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 33691 IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 33692 } 33693 33694 33695 # EMITTING VFNMSUB132SS (VFNMSUB132SS-128-1) 33696 { 33697 ICLASS: VFNMSUB132SS 33698 CPL: 3 33699 CATEGORY: VFMA 33700 EXTENSION: AVX512EVEX 33701 ISA_SET: AVX512F_SCALAR 33702 EXCEPTIONS: AVX512-E3 33703 REAL_OPCODE: Y 33704 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33705 PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 33706 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33707 IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33708 } 33709 33710 { 33711 ICLASS: VFNMSUB132SS 33712 CPL: 3 33713 CATEGORY: VFMA 33714 EXTENSION: AVX512EVEX 33715 ISA_SET: AVX512F_SCALAR 33716 EXCEPTIONS: AVX512-E3 33717 REAL_OPCODE: Y 33718 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33719 PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 33720 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33721 IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33722 } 33723 33724 { 33725 ICLASS: VFNMSUB132SS 33726 CPL: 3 33727 CATEGORY: VFMA 33728 EXTENSION: AVX512EVEX 33729 ISA_SET: AVX512F_SCALAR 33730 EXCEPTIONS: AVX512-E3 33731 REAL_OPCODE: Y 33732 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 33733 PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 33734 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 33735 IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 33736 } 33737 33738 33739 # EMITTING VFNMSUB213PD (VFNMSUB213PD-512-1) 33740 { 33741 ICLASS: VFNMSUB213PD 33742 CPL: 3 33743 CATEGORY: VFMA 33744 EXTENSION: AVX512EVEX 33745 ISA_SET: AVX512F_512 33746 EXCEPTIONS: AVX512-E2 33747 REAL_OPCODE: Y 33748 ATTRIBUTES: MXCSR MASKOP_EVEX 33749 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 33750 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33751 IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33752 } 33753 33754 { 33755 ICLASS: VFNMSUB213PD 33756 CPL: 3 33757 CATEGORY: VFMA 33758 EXTENSION: AVX512EVEX 33759 ISA_SET: AVX512F_512 33760 EXCEPTIONS: AVX512-E2 33761 REAL_OPCODE: Y 33762 ATTRIBUTES: MXCSR MASKOP_EVEX 33763 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 33764 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33765 IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33766 } 33767 33768 { 33769 ICLASS: VFNMSUB213PD 33770 CPL: 3 33771 CATEGORY: VFMA 33772 EXTENSION: AVX512EVEX 33773 ISA_SET: AVX512F_512 33774 EXCEPTIONS: AVX512-E2 33775 REAL_OPCODE: Y 33776 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33777 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 33778 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 33779 IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 33780 } 33781 33782 33783 # EMITTING VFNMSUB213PS (VFNMSUB213PS-512-1) 33784 { 33785 ICLASS: VFNMSUB213PS 33786 CPL: 3 33787 CATEGORY: VFMA 33788 EXTENSION: AVX512EVEX 33789 ISA_SET: AVX512F_512 33790 EXCEPTIONS: AVX512-E2 33791 REAL_OPCODE: Y 33792 ATTRIBUTES: MXCSR MASKOP_EVEX 33793 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 33794 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33795 IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33796 } 33797 33798 { 33799 ICLASS: VFNMSUB213PS 33800 CPL: 3 33801 CATEGORY: VFMA 33802 EXTENSION: AVX512EVEX 33803 ISA_SET: AVX512F_512 33804 EXCEPTIONS: AVX512-E2 33805 REAL_OPCODE: Y 33806 ATTRIBUTES: MXCSR MASKOP_EVEX 33807 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 33808 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33809 IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33810 } 33811 33812 { 33813 ICLASS: VFNMSUB213PS 33814 CPL: 3 33815 CATEGORY: VFMA 33816 EXTENSION: AVX512EVEX 33817 ISA_SET: AVX512F_512 33818 EXCEPTIONS: AVX512-E2 33819 REAL_OPCODE: Y 33820 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33821 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 33822 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 33823 IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 33824 } 33825 33826 33827 # EMITTING VFNMSUB213SD (VFNMSUB213SD-128-1) 33828 { 33829 ICLASS: VFNMSUB213SD 33830 CPL: 3 33831 CATEGORY: VFMA 33832 EXTENSION: AVX512EVEX 33833 ISA_SET: AVX512F_SCALAR 33834 EXCEPTIONS: AVX512-E3 33835 REAL_OPCODE: Y 33836 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33837 PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 33838 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33839 IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33840 } 33841 33842 { 33843 ICLASS: VFNMSUB213SD 33844 CPL: 3 33845 CATEGORY: VFMA 33846 EXTENSION: AVX512EVEX 33847 ISA_SET: AVX512F_SCALAR 33848 EXCEPTIONS: AVX512-E3 33849 REAL_OPCODE: Y 33850 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33851 PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 33852 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33853 IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33854 } 33855 33856 { 33857 ICLASS: VFNMSUB213SD 33858 CPL: 3 33859 CATEGORY: VFMA 33860 EXTENSION: AVX512EVEX 33861 ISA_SET: AVX512F_SCALAR 33862 EXCEPTIONS: AVX512-E3 33863 REAL_OPCODE: Y 33864 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 33865 PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 33866 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 33867 IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 33868 } 33869 33870 33871 # EMITTING VFNMSUB213SS (VFNMSUB213SS-128-1) 33872 { 33873 ICLASS: VFNMSUB213SS 33874 CPL: 3 33875 CATEGORY: VFMA 33876 EXTENSION: AVX512EVEX 33877 ISA_SET: AVX512F_SCALAR 33878 EXCEPTIONS: AVX512-E3 33879 REAL_OPCODE: Y 33880 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33881 PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 33882 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33883 IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33884 } 33885 33886 { 33887 ICLASS: VFNMSUB213SS 33888 CPL: 3 33889 CATEGORY: VFMA 33890 EXTENSION: AVX512EVEX 33891 ISA_SET: AVX512F_SCALAR 33892 EXCEPTIONS: AVX512-E3 33893 REAL_OPCODE: Y 33894 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 33895 PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 33896 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33897 IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33898 } 33899 33900 { 33901 ICLASS: VFNMSUB213SS 33902 CPL: 3 33903 CATEGORY: VFMA 33904 EXTENSION: AVX512EVEX 33905 ISA_SET: AVX512F_SCALAR 33906 EXCEPTIONS: AVX512-E3 33907 REAL_OPCODE: Y 33908 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 33909 PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 33910 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 33911 IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 33912 } 33913 33914 33915 # EMITTING VFNMSUB231PD (VFNMSUB231PD-512-1) 33916 { 33917 ICLASS: VFNMSUB231PD 33918 CPL: 3 33919 CATEGORY: VFMA 33920 EXTENSION: AVX512EVEX 33921 ISA_SET: AVX512F_512 33922 EXCEPTIONS: AVX512-E2 33923 REAL_OPCODE: Y 33924 ATTRIBUTES: MXCSR MASKOP_EVEX 33925 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 33926 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33927 IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33928 } 33929 33930 { 33931 ICLASS: VFNMSUB231PD 33932 CPL: 3 33933 CATEGORY: VFMA 33934 EXTENSION: AVX512EVEX 33935 ISA_SET: AVX512F_512 33936 EXCEPTIONS: AVX512-E2 33937 REAL_OPCODE: Y 33938 ATTRIBUTES: MXCSR MASKOP_EVEX 33939 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 33940 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 33941 IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 33942 } 33943 33944 { 33945 ICLASS: VFNMSUB231PD 33946 CPL: 3 33947 CATEGORY: VFMA 33948 EXTENSION: AVX512EVEX 33949 ISA_SET: AVX512F_512 33950 EXCEPTIONS: AVX512-E2 33951 REAL_OPCODE: Y 33952 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33953 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 33954 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 33955 IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 33956 } 33957 33958 33959 # EMITTING VFNMSUB231PS (VFNMSUB231PS-512-1) 33960 { 33961 ICLASS: VFNMSUB231PS 33962 CPL: 3 33963 CATEGORY: VFMA 33964 EXTENSION: AVX512EVEX 33965 ISA_SET: AVX512F_512 33966 EXCEPTIONS: AVX512-E2 33967 REAL_OPCODE: Y 33968 ATTRIBUTES: MXCSR MASKOP_EVEX 33969 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 33970 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33971 IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33972 } 33973 33974 { 33975 ICLASS: VFNMSUB231PS 33976 CPL: 3 33977 CATEGORY: VFMA 33978 EXTENSION: AVX512EVEX 33979 ISA_SET: AVX512F_512 33980 EXCEPTIONS: AVX512-E2 33981 REAL_OPCODE: Y 33982 ATTRIBUTES: MXCSR MASKOP_EVEX 33983 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 33984 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 33985 IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 33986 } 33987 33988 { 33989 ICLASS: VFNMSUB231PS 33990 CPL: 3 33991 CATEGORY: VFMA 33992 EXTENSION: AVX512EVEX 33993 ISA_SET: AVX512F_512 33994 EXCEPTIONS: AVX512-E2 33995 REAL_OPCODE: Y 33996 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 33997 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 33998 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 33999 IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 34000 } 34001 34002 34003 # EMITTING VFNMSUB231SD (VFNMSUB231SD-128-1) 34004 { 34005 ICLASS: VFNMSUB231SD 34006 CPL: 3 34007 CATEGORY: VFMA 34008 EXTENSION: AVX512EVEX 34009 ISA_SET: AVX512F_SCALAR 34010 EXCEPTIONS: AVX512-E3 34011 REAL_OPCODE: Y 34012 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34013 PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 34014 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 34015 IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 34016 } 34017 34018 { 34019 ICLASS: VFNMSUB231SD 34020 CPL: 3 34021 CATEGORY: VFMA 34022 EXTENSION: AVX512EVEX 34023 ISA_SET: AVX512F_SCALAR 34024 EXCEPTIONS: AVX512-E3 34025 REAL_OPCODE: Y 34026 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34027 PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 34028 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 34029 IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 34030 } 34031 34032 { 34033 ICLASS: VFNMSUB231SD 34034 CPL: 3 34035 CATEGORY: VFMA 34036 EXTENSION: AVX512EVEX 34037 ISA_SET: AVX512F_SCALAR 34038 EXCEPTIONS: AVX512-E3 34039 REAL_OPCODE: Y 34040 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 34041 PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 34042 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 34043 IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 34044 } 34045 34046 34047 # EMITTING VFNMSUB231SS (VFNMSUB231SS-128-1) 34048 { 34049 ICLASS: VFNMSUB231SS 34050 CPL: 3 34051 CATEGORY: VFMA 34052 EXTENSION: AVX512EVEX 34053 ISA_SET: AVX512F_SCALAR 34054 EXCEPTIONS: AVX512-E3 34055 REAL_OPCODE: Y 34056 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34057 PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 34058 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 34059 IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 34060 } 34061 34062 { 34063 ICLASS: VFNMSUB231SS 34064 CPL: 3 34065 CATEGORY: VFMA 34066 EXTENSION: AVX512EVEX 34067 ISA_SET: AVX512F_SCALAR 34068 EXCEPTIONS: AVX512-E3 34069 REAL_OPCODE: Y 34070 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34071 PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 34072 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 34073 IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 34074 } 34075 34076 { 34077 ICLASS: VFNMSUB231SS 34078 CPL: 3 34079 CATEGORY: VFMA 34080 EXTENSION: AVX512EVEX 34081 ISA_SET: AVX512F_SCALAR 34082 EXCEPTIONS: AVX512-E3 34083 REAL_OPCODE: Y 34084 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 34085 PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 34086 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 34087 IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 34088 } 34089 34090 34091 # EMITTING VGATHERDPD (VGATHERDPD-512-1) 34092 { 34093 ICLASS: VGATHERDPD 34094 CPL: 3 34095 CATEGORY: GATHER 34096 EXTENSION: AVX512EVEX 34097 ISA_SET: AVX512F_512 34098 EXCEPTIONS: AVX512-E12 34099 REAL_OPCODE: Y 34100 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 34101 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 34102 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f64 34103 IFORM: VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 34104 } 34105 34106 34107 # EMITTING VGATHERDPS (VGATHERDPS-512-1) 34108 { 34109 ICLASS: VGATHERDPS 34110 CPL: 3 34111 CATEGORY: GATHER 34112 EXTENSION: AVX512EVEX 34113 ISA_SET: AVX512F_512 34114 EXCEPTIONS: AVX512-E12 34115 REAL_OPCODE: Y 34116 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 34117 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 34118 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f32 34119 IFORM: VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 34120 } 34121 34122 34123 # EMITTING VGATHERQPD (VGATHERQPD-512-1) 34124 { 34125 ICLASS: VGATHERQPD 34126 CPL: 3 34127 CATEGORY: GATHER 34128 EXTENSION: AVX512EVEX 34129 ISA_SET: AVX512F_512 34130 EXCEPTIONS: AVX512-E12 34131 REAL_OPCODE: Y 34132 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 34133 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 34134 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:f64 34135 IFORM: VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 34136 } 34137 34138 34139 # EMITTING VGATHERQPS (VGATHERQPS-512-1) 34140 { 34141 ICLASS: VGATHERQPS 34142 CPL: 3 34143 CATEGORY: GATHER 34144 EXTENSION: AVX512EVEX 34145 ISA_SET: AVX512F_512 34146 EXCEPTIONS: AVX512-E12 34147 REAL_OPCODE: Y 34148 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 34149 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 34150 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f32 34151 IFORM: VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 34152 } 34153 34154 34155 # EMITTING VGETEXPPD (VGETEXPPD-512-1) 34156 { 34157 ICLASS: VGETEXPPD 34158 CPL: 3 34159 CATEGORY: AVX512 34160 EXTENSION: AVX512EVEX 34161 ISA_SET: AVX512F_512 34162 EXCEPTIONS: AVX512-E2 34163 REAL_OPCODE: Y 34164 ATTRIBUTES: MXCSR MASKOP_EVEX 34165 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 34166 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 34167 IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 34168 } 34169 34170 { 34171 ICLASS: VGETEXPPD 34172 CPL: 3 34173 CATEGORY: AVX512 34174 EXTENSION: AVX512EVEX 34175 ISA_SET: AVX512F_512 34176 EXCEPTIONS: AVX512-E2 34177 REAL_OPCODE: Y 34178 ATTRIBUTES: MXCSR MASKOP_EVEX 34179 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 34180 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 34181 IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 34182 } 34183 34184 { 34185 ICLASS: VGETEXPPD 34186 CPL: 3 34187 CATEGORY: AVX512 34188 EXTENSION: AVX512EVEX 34189 ISA_SET: AVX512F_512 34190 EXCEPTIONS: AVX512-E2 34191 REAL_OPCODE: Y 34192 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 34193 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 34194 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 34195 IFORM: VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 34196 } 34197 34198 34199 # EMITTING VGETEXPPS (VGETEXPPS-512-1) 34200 { 34201 ICLASS: VGETEXPPS 34202 CPL: 3 34203 CATEGORY: AVX512 34204 EXTENSION: AVX512EVEX 34205 ISA_SET: AVX512F_512 34206 EXCEPTIONS: AVX512-E2 34207 REAL_OPCODE: Y 34208 ATTRIBUTES: MXCSR MASKOP_EVEX 34209 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 34210 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 34211 IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 34212 } 34213 34214 { 34215 ICLASS: VGETEXPPS 34216 CPL: 3 34217 CATEGORY: AVX512 34218 EXTENSION: AVX512EVEX 34219 ISA_SET: AVX512F_512 34220 EXCEPTIONS: AVX512-E2 34221 REAL_OPCODE: Y 34222 ATTRIBUTES: MXCSR MASKOP_EVEX 34223 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 34224 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 34225 IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 34226 } 34227 34228 { 34229 ICLASS: VGETEXPPS 34230 CPL: 3 34231 CATEGORY: AVX512 34232 EXTENSION: AVX512EVEX 34233 ISA_SET: AVX512F_512 34234 EXCEPTIONS: AVX512-E2 34235 REAL_OPCODE: Y 34236 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 34237 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 34238 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 34239 IFORM: VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 34240 } 34241 34242 34243 # EMITTING VGETEXPSD (VGETEXPSD-128-1) 34244 { 34245 ICLASS: VGETEXPSD 34246 CPL: 3 34247 CATEGORY: AVX512 34248 EXTENSION: AVX512EVEX 34249 ISA_SET: AVX512F_SCALAR 34250 EXCEPTIONS: AVX512-E3 34251 REAL_OPCODE: Y 34252 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34253 PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 34254 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 34255 IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 34256 } 34257 34258 { 34259 ICLASS: VGETEXPSD 34260 CPL: 3 34261 CATEGORY: AVX512 34262 EXTENSION: AVX512EVEX 34263 ISA_SET: AVX512F_SCALAR 34264 EXCEPTIONS: AVX512-E3 34265 REAL_OPCODE: Y 34266 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34267 PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 34268 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 34269 IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 34270 } 34271 34272 { 34273 ICLASS: VGETEXPSD 34274 CPL: 3 34275 CATEGORY: AVX512 34276 EXTENSION: AVX512EVEX 34277 ISA_SET: AVX512F_SCALAR 34278 EXCEPTIONS: AVX512-E3 34279 REAL_OPCODE: Y 34280 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 34281 PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 34282 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 34283 IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 34284 } 34285 34286 34287 # EMITTING VGETEXPSS (VGETEXPSS-128-1) 34288 { 34289 ICLASS: VGETEXPSS 34290 CPL: 3 34291 CATEGORY: AVX512 34292 EXTENSION: AVX512EVEX 34293 ISA_SET: AVX512F_SCALAR 34294 EXCEPTIONS: AVX512-E3 34295 REAL_OPCODE: Y 34296 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34297 PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 34298 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 34299 IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 34300 } 34301 34302 { 34303 ICLASS: VGETEXPSS 34304 CPL: 3 34305 CATEGORY: AVX512 34306 EXTENSION: AVX512EVEX 34307 ISA_SET: AVX512F_SCALAR 34308 EXCEPTIONS: AVX512-E3 34309 REAL_OPCODE: Y 34310 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34311 PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 34312 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 34313 IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 34314 } 34315 34316 { 34317 ICLASS: VGETEXPSS 34318 CPL: 3 34319 CATEGORY: AVX512 34320 EXTENSION: AVX512EVEX 34321 ISA_SET: AVX512F_SCALAR 34322 EXCEPTIONS: AVX512-E3 34323 REAL_OPCODE: Y 34324 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 34325 PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 34326 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 34327 IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 34328 } 34329 34330 34331 # EMITTING VGETMANTPD (VGETMANTPD-512-1) 34332 { 34333 ICLASS: VGETMANTPD 34334 CPL: 3 34335 CATEGORY: AVX512 34336 EXTENSION: AVX512EVEX 34337 ISA_SET: AVX512F_512 34338 EXCEPTIONS: AVX512-E2 34339 REAL_OPCODE: Y 34340 ATTRIBUTES: MXCSR MASKOP_EVEX 34341 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 34342 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 34343 IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 34344 } 34345 34346 { 34347 ICLASS: VGETMANTPD 34348 CPL: 3 34349 CATEGORY: AVX512 34350 EXTENSION: AVX512EVEX 34351 ISA_SET: AVX512F_512 34352 EXCEPTIONS: AVX512-E2 34353 REAL_OPCODE: Y 34354 ATTRIBUTES: MXCSR MASKOP_EVEX 34355 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() 34356 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 34357 IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 34358 } 34359 34360 { 34361 ICLASS: VGETMANTPD 34362 CPL: 3 34363 CATEGORY: AVX512 34364 EXTENSION: AVX512EVEX 34365 ISA_SET: AVX512F_512 34366 EXCEPTIONS: AVX512-E2 34367 REAL_OPCODE: Y 34368 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 34369 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 34370 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 34371 IFORM: VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 34372 } 34373 34374 34375 # EMITTING VGETMANTPS (VGETMANTPS-512-1) 34376 { 34377 ICLASS: VGETMANTPS 34378 CPL: 3 34379 CATEGORY: AVX512 34380 EXTENSION: AVX512EVEX 34381 ISA_SET: AVX512F_512 34382 EXCEPTIONS: AVX512-E2 34383 REAL_OPCODE: Y 34384 ATTRIBUTES: MXCSR MASKOP_EVEX 34385 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 34386 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 34387 IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 34388 } 34389 34390 { 34391 ICLASS: VGETMANTPS 34392 CPL: 3 34393 CATEGORY: AVX512 34394 EXTENSION: AVX512EVEX 34395 ISA_SET: AVX512F_512 34396 EXCEPTIONS: AVX512-E2 34397 REAL_OPCODE: Y 34398 ATTRIBUTES: MXCSR MASKOP_EVEX 34399 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() 34400 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 34401 IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 34402 } 34403 34404 { 34405 ICLASS: VGETMANTPS 34406 CPL: 3 34407 CATEGORY: AVX512 34408 EXTENSION: AVX512EVEX 34409 ISA_SET: AVX512F_512 34410 EXCEPTIONS: AVX512-E2 34411 REAL_OPCODE: Y 34412 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 34413 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 34414 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 34415 IFORM: VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 34416 } 34417 34418 34419 # EMITTING VGETMANTSD (VGETMANTSD-128-1) 34420 { 34421 ICLASS: VGETMANTSD 34422 CPL: 3 34423 CATEGORY: AVX512 34424 EXTENSION: AVX512EVEX 34425 ISA_SET: AVX512F_SCALAR 34426 EXCEPTIONS: AVX512-E3 34427 REAL_OPCODE: Y 34428 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34429 PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() 34430 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 34431 IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 34432 } 34433 34434 { 34435 ICLASS: VGETMANTSD 34436 CPL: 3 34437 CATEGORY: AVX512 34438 EXTENSION: AVX512EVEX 34439 ISA_SET: AVX512F_SCALAR 34440 EXCEPTIONS: AVX512-E3 34441 REAL_OPCODE: Y 34442 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34443 PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() 34444 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 34445 IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 34446 } 34447 34448 { 34449 ICLASS: VGETMANTSD 34450 CPL: 3 34451 CATEGORY: AVX512 34452 EXTENSION: AVX512EVEX 34453 ISA_SET: AVX512F_SCALAR 34454 EXCEPTIONS: AVX512-E3 34455 REAL_OPCODE: Y 34456 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 34457 PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 34458 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 34459 IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 34460 } 34461 34462 34463 # EMITTING VGETMANTSS (VGETMANTSS-128-1) 34464 { 34465 ICLASS: VGETMANTSS 34466 CPL: 3 34467 CATEGORY: AVX512 34468 EXTENSION: AVX512EVEX 34469 ISA_SET: AVX512F_SCALAR 34470 EXCEPTIONS: AVX512-E3 34471 REAL_OPCODE: Y 34472 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34473 PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() 34474 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 34475 IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 34476 } 34477 34478 { 34479 ICLASS: VGETMANTSS 34480 CPL: 3 34481 CATEGORY: AVX512 34482 EXTENSION: AVX512EVEX 34483 ISA_SET: AVX512F_SCALAR 34484 EXCEPTIONS: AVX512-E3 34485 REAL_OPCODE: Y 34486 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34487 PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() 34488 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 34489 IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 34490 } 34491 34492 { 34493 ICLASS: VGETMANTSS 34494 CPL: 3 34495 CATEGORY: AVX512 34496 EXTENSION: AVX512EVEX 34497 ISA_SET: AVX512F_SCALAR 34498 EXCEPTIONS: AVX512-E3 34499 REAL_OPCODE: Y 34500 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 34501 PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 34502 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 34503 IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 34504 } 34505 34506 34507 # EMITTING VINSERTF32X4 (VINSERTF32X4-512-1) 34508 { 34509 ICLASS: VINSERTF32X4 34510 CPL: 3 34511 CATEGORY: AVX512 34512 EXTENSION: AVX512EVEX 34513 ISA_SET: AVX512F_512 34514 EXCEPTIONS: AVX512-E6NF 34515 REAL_OPCODE: Y 34516 ATTRIBUTES: MASKOP_EVEX 34517 PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 34518 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 34519 IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 34520 } 34521 34522 { 34523 ICLASS: VINSERTF32X4 34524 CPL: 3 34525 CATEGORY: AVX512 34526 EXTENSION: AVX512EVEX 34527 ISA_SET: AVX512F_512 34528 EXCEPTIONS: AVX512-E6NF 34529 REAL_OPCODE: Y 34530 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 34531 PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 34532 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:dq:f32 IMM0:r:b 34533 IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 34534 } 34535 34536 34537 # EMITTING VINSERTF64X4 (VINSERTF64X4-512-1) 34538 { 34539 ICLASS: VINSERTF64X4 34540 CPL: 3 34541 CATEGORY: AVX512 34542 EXTENSION: AVX512EVEX 34543 ISA_SET: AVX512F_512 34544 EXCEPTIONS: AVX512-E6NF 34545 REAL_OPCODE: Y 34546 ATTRIBUTES: MASKOP_EVEX 34547 PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 34548 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 34549 IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 34550 } 34551 34552 { 34553 ICLASS: VINSERTF64X4 34554 CPL: 3 34555 CATEGORY: AVX512 34556 EXTENSION: AVX512EVEX 34557 ISA_SET: AVX512F_512 34558 EXCEPTIONS: AVX512-E6NF 34559 REAL_OPCODE: Y 34560 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 34561 PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() 34562 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:qq:f64 IMM0:r:b 34563 IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 34564 } 34565 34566 34567 # EMITTING VINSERTI32X4 (VINSERTI32X4-512-1) 34568 { 34569 ICLASS: VINSERTI32X4 34570 CPL: 3 34571 CATEGORY: AVX512 34572 EXTENSION: AVX512EVEX 34573 ISA_SET: AVX512F_512 34574 EXCEPTIONS: AVX512-E6NF 34575 REAL_OPCODE: Y 34576 ATTRIBUTES: MASKOP_EVEX 34577 PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 34578 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 34579 IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 34580 } 34581 34582 { 34583 ICLASS: VINSERTI32X4 34584 CPL: 3 34585 CATEGORY: AVX512 34586 EXTENSION: AVX512EVEX 34587 ISA_SET: AVX512F_512 34588 EXCEPTIONS: AVX512-E6NF 34589 REAL_OPCODE: Y 34590 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 34591 PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 34592 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 IMM0:r:b 34593 IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 34594 } 34595 34596 34597 # EMITTING VINSERTI64X4 (VINSERTI64X4-512-1) 34598 { 34599 ICLASS: VINSERTI64X4 34600 CPL: 3 34601 CATEGORY: AVX512 34602 EXTENSION: AVX512EVEX 34603 ISA_SET: AVX512F_512 34604 EXCEPTIONS: AVX512-E6NF 34605 REAL_OPCODE: Y 34606 ATTRIBUTES: MASKOP_EVEX 34607 PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 34608 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 34609 IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 34610 } 34611 34612 { 34613 ICLASS: VINSERTI64X4 34614 CPL: 3 34615 CATEGORY: AVX512 34616 EXTENSION: AVX512EVEX 34617 ISA_SET: AVX512F_512 34618 EXCEPTIONS: AVX512-E6NF 34619 REAL_OPCODE: Y 34620 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 34621 PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() 34622 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:qq:u64 IMM0:r:b 34623 IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 34624 } 34625 34626 34627 # EMITTING VINSERTPS (VINSERTPS-128-1) 34628 { 34629 ICLASS: VINSERTPS 34630 CPL: 3 34631 CATEGORY: AVX512 34632 EXTENSION: AVX512EVEX 34633 ISA_SET: AVX512F_128N 34634 EXCEPTIONS: AVX512-E9NF 34635 REAL_OPCODE: Y 34636 PATTERN: EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() 34637 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 IMM0:r:b 34638 IFORM: VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 34639 } 34640 34641 { 34642 ICLASS: VINSERTPS 34643 CPL: 3 34644 CATEGORY: AVX512 34645 EXTENSION: AVX512EVEX 34646 ISA_SET: AVX512F_128N 34647 EXCEPTIONS: AVX512-E9NF 34648 REAL_OPCODE: Y 34649 ATTRIBUTES: DISP8_TUPLE1 34650 PATTERN: EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE1() 34651 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 34652 IFORM: VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 34653 } 34654 34655 34656 # EMITTING VMAXPD (VMAXPD-512-1) 34657 { 34658 ICLASS: VMAXPD 34659 CPL: 3 34660 CATEGORY: AVX512 34661 EXTENSION: AVX512EVEX 34662 ISA_SET: AVX512F_512 34663 EXCEPTIONS: AVX512-E2 34664 REAL_OPCODE: Y 34665 ATTRIBUTES: MXCSR MASKOP_EVEX 34666 PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 34667 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 34668 IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 34669 } 34670 34671 { 34672 ICLASS: VMAXPD 34673 CPL: 3 34674 CATEGORY: AVX512 34675 EXTENSION: AVX512EVEX 34676 ISA_SET: AVX512F_512 34677 EXCEPTIONS: AVX512-E2 34678 REAL_OPCODE: Y 34679 ATTRIBUTES: MXCSR MASKOP_EVEX 34680 PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 34681 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 34682 IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 34683 } 34684 34685 { 34686 ICLASS: VMAXPD 34687 CPL: 3 34688 CATEGORY: AVX512 34689 EXTENSION: AVX512EVEX 34690 ISA_SET: AVX512F_512 34691 EXCEPTIONS: AVX512-E2 34692 REAL_OPCODE: Y 34693 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 34694 PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 34695 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 34696 IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 34697 } 34698 34699 34700 # EMITTING VMAXPS (VMAXPS-512-1) 34701 { 34702 ICLASS: VMAXPS 34703 CPL: 3 34704 CATEGORY: AVX512 34705 EXTENSION: AVX512EVEX 34706 ISA_SET: AVX512F_512 34707 EXCEPTIONS: AVX512-E2 34708 REAL_OPCODE: Y 34709 ATTRIBUTES: MXCSR MASKOP_EVEX 34710 PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 34711 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 34712 IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 34713 } 34714 34715 { 34716 ICLASS: VMAXPS 34717 CPL: 3 34718 CATEGORY: AVX512 34719 EXTENSION: AVX512EVEX 34720 ISA_SET: AVX512F_512 34721 EXCEPTIONS: AVX512-E2 34722 REAL_OPCODE: Y 34723 ATTRIBUTES: MXCSR MASKOP_EVEX 34724 PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 34725 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 34726 IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 34727 } 34728 34729 { 34730 ICLASS: VMAXPS 34731 CPL: 3 34732 CATEGORY: AVX512 34733 EXTENSION: AVX512EVEX 34734 ISA_SET: AVX512F_512 34735 EXCEPTIONS: AVX512-E2 34736 REAL_OPCODE: Y 34737 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 34738 PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 34739 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 34740 IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 34741 } 34742 34743 34744 # EMITTING VMAXSD (VMAXSD-128-1) 34745 { 34746 ICLASS: VMAXSD 34747 CPL: 3 34748 CATEGORY: AVX512 34749 EXTENSION: AVX512EVEX 34750 ISA_SET: AVX512F_SCALAR 34751 EXCEPTIONS: AVX512-E3 34752 REAL_OPCODE: Y 34753 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34754 PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 34755 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 34756 IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 34757 } 34758 34759 { 34760 ICLASS: VMAXSD 34761 CPL: 3 34762 CATEGORY: AVX512 34763 EXTENSION: AVX512EVEX 34764 ISA_SET: AVX512F_SCALAR 34765 EXCEPTIONS: AVX512-E3 34766 REAL_OPCODE: Y 34767 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34768 PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 34769 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 34770 IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 34771 } 34772 34773 { 34774 ICLASS: VMAXSD 34775 CPL: 3 34776 CATEGORY: AVX512 34777 EXTENSION: AVX512EVEX 34778 ISA_SET: AVX512F_SCALAR 34779 EXCEPTIONS: AVX512-E3 34780 REAL_OPCODE: Y 34781 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 34782 PATTERN: EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 34783 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 34784 IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 34785 } 34786 34787 34788 # EMITTING VMAXSS (VMAXSS-128-1) 34789 { 34790 ICLASS: VMAXSS 34791 CPL: 3 34792 CATEGORY: AVX512 34793 EXTENSION: AVX512EVEX 34794 ISA_SET: AVX512F_SCALAR 34795 EXCEPTIONS: AVX512-E3 34796 REAL_OPCODE: Y 34797 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34798 PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 34799 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 34800 IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 34801 } 34802 34803 { 34804 ICLASS: VMAXSS 34805 CPL: 3 34806 CATEGORY: AVX512 34807 EXTENSION: AVX512EVEX 34808 ISA_SET: AVX512F_SCALAR 34809 EXCEPTIONS: AVX512-E3 34810 REAL_OPCODE: Y 34811 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34812 PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 34813 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 34814 IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 34815 } 34816 34817 { 34818 ICLASS: VMAXSS 34819 CPL: 3 34820 CATEGORY: AVX512 34821 EXTENSION: AVX512EVEX 34822 ISA_SET: AVX512F_SCALAR 34823 EXCEPTIONS: AVX512-E3 34824 REAL_OPCODE: Y 34825 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 34826 PATTERN: EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 34827 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 34828 IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 34829 } 34830 34831 34832 # EMITTING VMINPD (VMINPD-512-1) 34833 { 34834 ICLASS: VMINPD 34835 CPL: 3 34836 CATEGORY: AVX512 34837 EXTENSION: AVX512EVEX 34838 ISA_SET: AVX512F_512 34839 EXCEPTIONS: AVX512-E2 34840 REAL_OPCODE: Y 34841 ATTRIBUTES: MXCSR MASKOP_EVEX 34842 PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 34843 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 34844 IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 34845 } 34846 34847 { 34848 ICLASS: VMINPD 34849 CPL: 3 34850 CATEGORY: AVX512 34851 EXTENSION: AVX512EVEX 34852 ISA_SET: AVX512F_512 34853 EXCEPTIONS: AVX512-E2 34854 REAL_OPCODE: Y 34855 ATTRIBUTES: MXCSR MASKOP_EVEX 34856 PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 34857 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 34858 IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 34859 } 34860 34861 { 34862 ICLASS: VMINPD 34863 CPL: 3 34864 CATEGORY: AVX512 34865 EXTENSION: AVX512EVEX 34866 ISA_SET: AVX512F_512 34867 EXCEPTIONS: AVX512-E2 34868 REAL_OPCODE: Y 34869 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 34870 PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 34871 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 34872 IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 34873 } 34874 34875 34876 # EMITTING VMINPS (VMINPS-512-1) 34877 { 34878 ICLASS: VMINPS 34879 CPL: 3 34880 CATEGORY: AVX512 34881 EXTENSION: AVX512EVEX 34882 ISA_SET: AVX512F_512 34883 EXCEPTIONS: AVX512-E2 34884 REAL_OPCODE: Y 34885 ATTRIBUTES: MXCSR MASKOP_EVEX 34886 PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 34887 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 34888 IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 34889 } 34890 34891 { 34892 ICLASS: VMINPS 34893 CPL: 3 34894 CATEGORY: AVX512 34895 EXTENSION: AVX512EVEX 34896 ISA_SET: AVX512F_512 34897 EXCEPTIONS: AVX512-E2 34898 REAL_OPCODE: Y 34899 ATTRIBUTES: MXCSR MASKOP_EVEX 34900 PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 34901 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 34902 IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 34903 } 34904 34905 { 34906 ICLASS: VMINPS 34907 CPL: 3 34908 CATEGORY: AVX512 34909 EXTENSION: AVX512EVEX 34910 ISA_SET: AVX512F_512 34911 EXCEPTIONS: AVX512-E2 34912 REAL_OPCODE: Y 34913 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 34914 PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 34915 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 34916 IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 34917 } 34918 34919 34920 # EMITTING VMINSD (VMINSD-128-1) 34921 { 34922 ICLASS: VMINSD 34923 CPL: 3 34924 CATEGORY: AVX512 34925 EXTENSION: AVX512EVEX 34926 ISA_SET: AVX512F_SCALAR 34927 EXCEPTIONS: AVX512-E3 34928 REAL_OPCODE: Y 34929 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34930 PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 34931 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 34932 IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 34933 } 34934 34935 { 34936 ICLASS: VMINSD 34937 CPL: 3 34938 CATEGORY: AVX512 34939 EXTENSION: AVX512EVEX 34940 ISA_SET: AVX512F_SCALAR 34941 EXCEPTIONS: AVX512-E3 34942 REAL_OPCODE: Y 34943 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34944 PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 34945 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 34946 IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 34947 } 34948 34949 { 34950 ICLASS: VMINSD 34951 CPL: 3 34952 CATEGORY: AVX512 34953 EXTENSION: AVX512EVEX 34954 ISA_SET: AVX512F_SCALAR 34955 EXCEPTIONS: AVX512-E3 34956 REAL_OPCODE: Y 34957 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 34958 PATTERN: EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 34959 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 34960 IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 34961 } 34962 34963 34964 # EMITTING VMINSS (VMINSS-128-1) 34965 { 34966 ICLASS: VMINSS 34967 CPL: 3 34968 CATEGORY: AVX512 34969 EXTENSION: AVX512EVEX 34970 ISA_SET: AVX512F_SCALAR 34971 EXCEPTIONS: AVX512-E3 34972 REAL_OPCODE: Y 34973 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34974 PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 34975 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 34976 IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 34977 } 34978 34979 { 34980 ICLASS: VMINSS 34981 CPL: 3 34982 CATEGORY: AVX512 34983 EXTENSION: AVX512EVEX 34984 ISA_SET: AVX512F_SCALAR 34985 EXCEPTIONS: AVX512-E3 34986 REAL_OPCODE: Y 34987 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 34988 PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 34989 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 34990 IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 34991 } 34992 34993 { 34994 ICLASS: VMINSS 34995 CPL: 3 34996 CATEGORY: AVX512 34997 EXTENSION: AVX512EVEX 34998 ISA_SET: AVX512F_SCALAR 34999 EXCEPTIONS: AVX512-E3 35000 REAL_OPCODE: Y 35001 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 35002 PATTERN: EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 35003 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 35004 IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 35005 } 35006 35007 35008 # EMITTING VMOVAPD (VMOVAPD-512-1) 35009 { 35010 ICLASS: VMOVAPD 35011 CPL: 3 35012 CATEGORY: DATAXFER 35013 EXTENSION: AVX512EVEX 35014 ISA_SET: AVX512F_512 35015 EXCEPTIONS: AVX512-E1 35016 REAL_OPCODE: Y 35017 ATTRIBUTES: MASKOP_EVEX 35018 PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 35019 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 35020 IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 35021 } 35022 35023 { 35024 ICLASS: VMOVAPD 35025 CPL: 3 35026 CATEGORY: DATAXFER 35027 EXTENSION: AVX512EVEX 35028 ISA_SET: AVX512F_512 35029 EXCEPTIONS: AVX512-E1 35030 REAL_OPCODE: Y 35031 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35032 PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 35033 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 35034 IFORM: VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 35035 } 35036 35037 35038 # EMITTING VMOVAPD (VMOVAPD-512-2) 35039 { 35040 ICLASS: VMOVAPD 35041 CPL: 3 35042 CATEGORY: DATAXFER 35043 EXTENSION: AVX512EVEX 35044 ISA_SET: AVX512F_512 35045 EXCEPTIONS: AVX512-E1 35046 REAL_OPCODE: Y 35047 ATTRIBUTES: MASKOP_EVEX 35048 PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 35049 OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 35050 IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 35051 } 35052 35053 35054 # EMITTING VMOVAPD (VMOVAPD-512-3) 35055 { 35056 ICLASS: VMOVAPD 35057 CPL: 3 35058 CATEGORY: DATAXFER 35059 EXTENSION: AVX512EVEX 35060 ISA_SET: AVX512F_512 35061 EXCEPTIONS: AVX512-E1 35062 REAL_OPCODE: Y 35063 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35064 PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 35065 OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 35066 IFORM: VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 35067 } 35068 35069 35070 # EMITTING VMOVAPS (VMOVAPS-512-1) 35071 { 35072 ICLASS: VMOVAPS 35073 CPL: 3 35074 CATEGORY: DATAXFER 35075 EXTENSION: AVX512EVEX 35076 ISA_SET: AVX512F_512 35077 EXCEPTIONS: AVX512-E1 35078 REAL_OPCODE: Y 35079 ATTRIBUTES: MASKOP_EVEX 35080 PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 35081 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 35082 IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 35083 } 35084 35085 { 35086 ICLASS: VMOVAPS 35087 CPL: 3 35088 CATEGORY: DATAXFER 35089 EXTENSION: AVX512EVEX 35090 ISA_SET: AVX512F_512 35091 EXCEPTIONS: AVX512-E1 35092 REAL_OPCODE: Y 35093 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35094 PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 35095 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 35096 IFORM: VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 35097 } 35098 35099 35100 # EMITTING VMOVAPS (VMOVAPS-512-2) 35101 { 35102 ICLASS: VMOVAPS 35103 CPL: 3 35104 CATEGORY: DATAXFER 35105 EXTENSION: AVX512EVEX 35106 ISA_SET: AVX512F_512 35107 EXCEPTIONS: AVX512-E1 35108 REAL_OPCODE: Y 35109 ATTRIBUTES: MASKOP_EVEX 35110 PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 35111 OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 35112 IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 35113 } 35114 35115 35116 # EMITTING VMOVAPS (VMOVAPS-512-3) 35117 { 35118 ICLASS: VMOVAPS 35119 CPL: 3 35120 CATEGORY: DATAXFER 35121 EXTENSION: AVX512EVEX 35122 ISA_SET: AVX512F_512 35123 EXCEPTIONS: AVX512-E1 35124 REAL_OPCODE: Y 35125 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35126 PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 35127 OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 35128 IFORM: VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 35129 } 35130 35131 35132 # EMITTING VMOVD (VMOVD-128-1) 35133 { 35134 ICLASS: VMOVD 35135 CPL: 3 35136 CATEGORY: DATAXFER 35137 EXTENSION: AVX512EVEX 35138 ISA_SET: AVX512F_128N 35139 EXCEPTIONS: AVX512-E9NF 35140 REAL_OPCODE: Y 35141 PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 35142 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 35143 IFORM: VMOVD_XMMu32_GPR32u32_AVX512 35144 } 35145 35146 { 35147 ICLASS: VMOVD 35148 CPL: 3 35149 CATEGORY: DATAXFER 35150 EXTENSION: AVX512EVEX 35151 ISA_SET: AVX512F_128N 35152 EXCEPTIONS: AVX512-E9NF 35153 REAL_OPCODE: Y 35154 ATTRIBUTES: DISP8_GPR_READER 35155 PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 35156 OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 35157 IFORM: VMOVD_XMMu32_MEMu32_AVX512 35158 } 35159 35160 35161 # EMITTING VMOVD (VMOVD-128-2) 35162 { 35163 ICLASS: VMOVD 35164 CPL: 3 35165 CATEGORY: DATAXFER 35166 EXTENSION: AVX512EVEX 35167 ISA_SET: AVX512F_128N 35168 EXCEPTIONS: AVX512-E9NF 35169 REAL_OPCODE: Y 35170 PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 35171 OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 35172 IFORM: VMOVD_GPR32u32_XMMu32_AVX512 35173 } 35174 35175 { 35176 ICLASS: VMOVD 35177 CPL: 3 35178 CATEGORY: DATAXFER 35179 EXTENSION: AVX512EVEX 35180 ISA_SET: AVX512F_128N 35181 EXCEPTIONS: AVX512-E9NF 35182 REAL_OPCODE: Y 35183 ATTRIBUTES: DISP8_GPR_WRITER_STORE 35184 PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() 35185 OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 35186 IFORM: VMOVD_MEMu32_XMMu32_AVX512 35187 } 35188 35189 35190 # EMITTING VMOVDDUP (VMOVDDUP-512-1) 35191 { 35192 ICLASS: VMOVDDUP 35193 CPL: 3 35194 CATEGORY: DATAXFER 35195 EXTENSION: AVX512EVEX 35196 ISA_SET: AVX512F_512 35197 EXCEPTIONS: AVX512-E5NF 35198 REAL_OPCODE: Y 35199 ATTRIBUTES: MASKOP_EVEX 35200 PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 35201 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 35202 IFORM: VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 35203 } 35204 35205 { 35206 ICLASS: VMOVDDUP 35207 CPL: 3 35208 CATEGORY: DATAXFER 35209 EXTENSION: AVX512EVEX 35210 ISA_SET: AVX512F_512 35211 EXCEPTIONS: AVX512-E5NF 35212 REAL_OPCODE: Y 35213 ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP 35214 PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() 35215 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 35216 IFORM: VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 35217 } 35218 35219 35220 # EMITTING VMOVDQA32 (VMOVDQA32-512-1) 35221 { 35222 ICLASS: VMOVDQA32 35223 CPL: 3 35224 CATEGORY: DATAXFER 35225 EXTENSION: AVX512EVEX 35226 ISA_SET: AVX512F_512 35227 EXCEPTIONS: AVX512-E1 35228 REAL_OPCODE: Y 35229 ATTRIBUTES: MASKOP_EVEX 35230 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 35231 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 35232 IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 35233 } 35234 35235 { 35236 ICLASS: VMOVDQA32 35237 CPL: 3 35238 CATEGORY: DATAXFER 35239 EXTENSION: AVX512EVEX 35240 ISA_SET: AVX512F_512 35241 EXCEPTIONS: AVX512-E1 35242 REAL_OPCODE: Y 35243 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35244 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 35245 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 35246 IFORM: VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 35247 } 35248 35249 35250 # EMITTING VMOVDQA32 (VMOVDQA32-512-2) 35251 { 35252 ICLASS: VMOVDQA32 35253 CPL: 3 35254 CATEGORY: DATAXFER 35255 EXTENSION: AVX512EVEX 35256 ISA_SET: AVX512F_512 35257 EXCEPTIONS: AVX512-E1 35258 REAL_OPCODE: Y 35259 ATTRIBUTES: MASKOP_EVEX 35260 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 35261 OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 35262 IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 35263 } 35264 35265 35266 # EMITTING VMOVDQA32 (VMOVDQA32-512-3) 35267 { 35268 ICLASS: VMOVDQA32 35269 CPL: 3 35270 CATEGORY: DATAXFER 35271 EXTENSION: AVX512EVEX 35272 ISA_SET: AVX512F_512 35273 EXCEPTIONS: AVX512-E1 35274 REAL_OPCODE: Y 35275 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35276 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 35277 OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 35278 IFORM: VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 35279 } 35280 35281 35282 # EMITTING VMOVDQA64 (VMOVDQA64-512-1) 35283 { 35284 ICLASS: VMOVDQA64 35285 CPL: 3 35286 CATEGORY: DATAXFER 35287 EXTENSION: AVX512EVEX 35288 ISA_SET: AVX512F_512 35289 EXCEPTIONS: AVX512-E1 35290 REAL_OPCODE: Y 35291 ATTRIBUTES: MASKOP_EVEX 35292 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 35293 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 35294 IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 35295 } 35296 35297 { 35298 ICLASS: VMOVDQA64 35299 CPL: 3 35300 CATEGORY: DATAXFER 35301 EXTENSION: AVX512EVEX 35302 ISA_SET: AVX512F_512 35303 EXCEPTIONS: AVX512-E1 35304 REAL_OPCODE: Y 35305 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35306 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 35307 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 35308 IFORM: VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 35309 } 35310 35311 35312 # EMITTING VMOVDQA64 (VMOVDQA64-512-2) 35313 { 35314 ICLASS: VMOVDQA64 35315 CPL: 3 35316 CATEGORY: DATAXFER 35317 EXTENSION: AVX512EVEX 35318 ISA_SET: AVX512F_512 35319 EXCEPTIONS: AVX512-E1 35320 REAL_OPCODE: Y 35321 ATTRIBUTES: MASKOP_EVEX 35322 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 35323 OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 35324 IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 35325 } 35326 35327 35328 # EMITTING VMOVDQA64 (VMOVDQA64-512-3) 35329 { 35330 ICLASS: VMOVDQA64 35331 CPL: 3 35332 CATEGORY: DATAXFER 35333 EXTENSION: AVX512EVEX 35334 ISA_SET: AVX512F_512 35335 EXCEPTIONS: AVX512-E1 35336 REAL_OPCODE: Y 35337 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35338 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 35339 OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 35340 IFORM: VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 35341 } 35342 35343 35344 # EMITTING VMOVDQU32 (VMOVDQU32-512-1) 35345 { 35346 ICLASS: VMOVDQU32 35347 CPL: 3 35348 CATEGORY: DATAXFER 35349 EXTENSION: AVX512EVEX 35350 ISA_SET: AVX512F_512 35351 EXCEPTIONS: AVX512-E4 35352 REAL_OPCODE: Y 35353 ATTRIBUTES: MASKOP_EVEX 35354 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 35355 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 35356 IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 35357 } 35358 35359 { 35360 ICLASS: VMOVDQU32 35361 CPL: 3 35362 CATEGORY: DATAXFER 35363 EXTENSION: AVX512EVEX 35364 ISA_SET: AVX512F_512 35365 EXCEPTIONS: AVX512-E4 35366 REAL_OPCODE: Y 35367 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35368 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 35369 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 35370 IFORM: VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 35371 } 35372 35373 35374 # EMITTING VMOVDQU32 (VMOVDQU32-512-2) 35375 { 35376 ICLASS: VMOVDQU32 35377 CPL: 3 35378 CATEGORY: DATAXFER 35379 EXTENSION: AVX512EVEX 35380 ISA_SET: AVX512F_512 35381 EXCEPTIONS: AVX512-E4 35382 REAL_OPCODE: Y 35383 ATTRIBUTES: MASKOP_EVEX 35384 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 35385 OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 35386 IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 35387 } 35388 35389 35390 # EMITTING VMOVDQU32 (VMOVDQU32-512-3) 35391 { 35392 ICLASS: VMOVDQU32 35393 CPL: 3 35394 CATEGORY: DATAXFER 35395 EXTENSION: AVX512EVEX 35396 ISA_SET: AVX512F_512 35397 EXCEPTIONS: AVX512-E4 35398 REAL_OPCODE: Y 35399 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35400 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 35401 OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 35402 IFORM: VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 35403 } 35404 35405 35406 # EMITTING VMOVDQU64 (VMOVDQU64-512-1) 35407 { 35408 ICLASS: VMOVDQU64 35409 CPL: 3 35410 CATEGORY: DATAXFER 35411 EXTENSION: AVX512EVEX 35412 ISA_SET: AVX512F_512 35413 EXCEPTIONS: AVX512-E4 35414 REAL_OPCODE: Y 35415 ATTRIBUTES: MASKOP_EVEX 35416 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 35417 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 35418 IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 35419 } 35420 35421 { 35422 ICLASS: VMOVDQU64 35423 CPL: 3 35424 CATEGORY: DATAXFER 35425 EXTENSION: AVX512EVEX 35426 ISA_SET: AVX512F_512 35427 EXCEPTIONS: AVX512-E4 35428 REAL_OPCODE: Y 35429 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35430 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 35431 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 35432 IFORM: VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 35433 } 35434 35435 35436 # EMITTING VMOVDQU64 (VMOVDQU64-512-2) 35437 { 35438 ICLASS: VMOVDQU64 35439 CPL: 3 35440 CATEGORY: DATAXFER 35441 EXTENSION: AVX512EVEX 35442 ISA_SET: AVX512F_512 35443 EXCEPTIONS: AVX512-E4 35444 REAL_OPCODE: Y 35445 ATTRIBUTES: MASKOP_EVEX 35446 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 35447 OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 35448 IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 35449 } 35450 35451 35452 # EMITTING VMOVDQU64 (VMOVDQU64-512-3) 35453 { 35454 ICLASS: VMOVDQU64 35455 CPL: 3 35456 CATEGORY: DATAXFER 35457 EXTENSION: AVX512EVEX 35458 ISA_SET: AVX512F_512 35459 EXCEPTIONS: AVX512-E4 35460 REAL_OPCODE: Y 35461 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35462 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 35463 OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 35464 IFORM: VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 35465 } 35466 35467 35468 # EMITTING VMOVHLPS (VMOVHLPS-128-1) 35469 { 35470 ICLASS: VMOVHLPS 35471 CPL: 3 35472 CATEGORY: DATAXFER 35473 EXTENSION: AVX512EVEX 35474 ISA_SET: AVX512F_128N 35475 EXCEPTIONS: AVX512-E7NM128 35476 REAL_OPCODE: Y 35477 PATTERN: EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 35478 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 35479 IFORM: VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 35480 } 35481 35482 35483 # EMITTING VMOVHPD (VMOVHPD-128-1) 35484 { 35485 ICLASS: VMOVHPD 35486 CPL: 3 35487 CATEGORY: DATAXFER 35488 EXTENSION: AVX512EVEX 35489 ISA_SET: AVX512F_128N 35490 EXCEPTIONS: AVX512-E9NF 35491 REAL_OPCODE: Y 35492 ATTRIBUTES: DISP8_SCALAR 35493 PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 35494 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64 35495 IFORM: VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 35496 } 35497 35498 35499 # EMITTING VMOVHPD (VMOVHPD-128-2) 35500 { 35501 ICLASS: VMOVHPD 35502 CPL: 3 35503 CATEGORY: DATAXFER 35504 EXTENSION: AVX512EVEX 35505 ISA_SET: AVX512F_128N 35506 EXCEPTIONS: AVX512-E9NF 35507 REAL_OPCODE: Y 35508 ATTRIBUTES: DISP8_SCALAR 35509 PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 35510 OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64 35511 IFORM: VMOVHPD_MEMf64_XMMf64_AVX512 35512 } 35513 35514 35515 # EMITTING VMOVHPS (VMOVHPS-128-1) 35516 { 35517 ICLASS: VMOVHPS 35518 CPL: 3 35519 CATEGORY: DATAXFER 35520 EXTENSION: AVX512EVEX 35521 ISA_SET: AVX512F_128N 35522 EXCEPTIONS: AVX512-E9NF 35523 REAL_OPCODE: Y 35524 ATTRIBUTES: DISP8_TUPLE2 35525 PATTERN: EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() 35526 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 MEM0:r:q:f32 35527 IFORM: VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 35528 } 35529 35530 35531 # EMITTING VMOVHPS (VMOVHPS-128-2) 35532 { 35533 ICLASS: VMOVHPS 35534 CPL: 3 35535 CATEGORY: DATAXFER 35536 EXTENSION: AVX512EVEX 35537 ISA_SET: AVX512F_128N 35538 EXCEPTIONS: AVX512-E9NF 35539 REAL_OPCODE: Y 35540 ATTRIBUTES: DISP8_TUPLE2 35541 PATTERN: EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() 35542 OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:dq:f32 35543 IFORM: VMOVHPS_MEMf32_XMMf32_AVX512 35544 } 35545 35546 35547 # EMITTING VMOVLHPS (VMOVLHPS-128-1) 35548 { 35549 ICLASS: VMOVLHPS 35550 CPL: 3 35551 CATEGORY: DATAXFER 35552 EXTENSION: AVX512EVEX 35553 ISA_SET: AVX512F_128N 35554 EXCEPTIONS: AVX512-E7NM128 35555 REAL_OPCODE: Y 35556 PATTERN: EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 35557 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 REG2=XMM_B3():r:q:f32 35558 IFORM: VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 35559 } 35560 35561 35562 # EMITTING VMOVLPD (VMOVLPD-128-1) 35563 { 35564 ICLASS: VMOVLPD 35565 CPL: 3 35566 CATEGORY: DATAXFER 35567 EXTENSION: AVX512EVEX 35568 ISA_SET: AVX512F_128N 35569 EXCEPTIONS: AVX512-E9NF 35570 REAL_OPCODE: Y 35571 ATTRIBUTES: DISP8_SCALAR 35572 PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 35573 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64 35574 IFORM: VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 35575 } 35576 35577 35578 # EMITTING VMOVLPD (VMOVLPD-128-2) 35579 { 35580 ICLASS: VMOVLPD 35581 CPL: 3 35582 CATEGORY: DATAXFER 35583 EXTENSION: AVX512EVEX 35584 ISA_SET: AVX512F_128N 35585 EXCEPTIONS: AVX512-E9NF 35586 REAL_OPCODE: Y 35587 ATTRIBUTES: DISP8_SCALAR 35588 PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 35589 OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:q:f64 35590 IFORM: VMOVLPD_MEMf64_XMMf64_AVX512 35591 } 35592 35593 35594 # EMITTING VMOVLPS (VMOVLPS-128-1) 35595 { 35596 ICLASS: VMOVLPS 35597 CPL: 3 35598 CATEGORY: DATAXFER 35599 EXTENSION: AVX512EVEX 35600 ISA_SET: AVX512F_128N 35601 EXCEPTIONS: AVX512-E9NF 35602 REAL_OPCODE: Y 35603 ATTRIBUTES: DISP8_TUPLE2 35604 PATTERN: EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() 35605 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:f32 35606 IFORM: VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 35607 } 35608 35609 35610 # EMITTING VMOVLPS (VMOVLPS-128-2) 35611 { 35612 ICLASS: VMOVLPS 35613 CPL: 3 35614 CATEGORY: DATAXFER 35615 EXTENSION: AVX512EVEX 35616 ISA_SET: AVX512F_128N 35617 EXCEPTIONS: AVX512-E9NF 35618 REAL_OPCODE: Y 35619 ATTRIBUTES: DISP8_TUPLE2 35620 PATTERN: EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() 35621 OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:q:f32 35622 IFORM: VMOVLPS_MEMf32_XMMf32_AVX512 35623 } 35624 35625 35626 # EMITTING VMOVNTDQ (VMOVNTDQ-512-1) 35627 { 35628 ICLASS: VMOVNTDQ 35629 CPL: 3 35630 CATEGORY: DATAXFER 35631 EXTENSION: AVX512EVEX 35632 ISA_SET: AVX512F_512 35633 EXCEPTIONS: AVX512-E1NF 35634 REAL_OPCODE: Y 35635 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 35636 PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 35637 OPERANDS: MEM0:w:zd:u32 REG0=ZMM_R3():r:zu32 35638 IFORM: VMOVNTDQ_MEMu32_ZMMu32_AVX512 35639 } 35640 35641 35642 # EMITTING VMOVNTDQA (VMOVNTDQA-512-1) 35643 { 35644 ICLASS: VMOVNTDQA 35645 CPL: 3 35646 CATEGORY: DATAXFER 35647 EXTENSION: AVX512EVEX 35648 ISA_SET: AVX512F_512 35649 EXCEPTIONS: AVX512-E1NF 35650 REAL_OPCODE: Y 35651 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 35652 PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 35653 OPERANDS: REG0=ZMM_R3():w:zu32 MEM0:r:zd:u32 35654 IFORM: VMOVNTDQA_ZMMu32_MEMu32_AVX512 35655 } 35656 35657 35658 # EMITTING VMOVNTPD (VMOVNTPD-512-1) 35659 { 35660 ICLASS: VMOVNTPD 35661 CPL: 3 35662 CATEGORY: DATAXFER 35663 EXTENSION: AVX512EVEX 35664 ISA_SET: AVX512F_512 35665 EXCEPTIONS: AVX512-E1NF 35666 REAL_OPCODE: Y 35667 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 35668 PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() 35669 OPERANDS: MEM0:w:zd:f64 REG0=ZMM_R3():r:zf64 35670 IFORM: VMOVNTPD_MEMf64_ZMMf64_AVX512 35671 } 35672 35673 35674 # EMITTING VMOVNTPS (VMOVNTPS-512-1) 35675 { 35676 ICLASS: VMOVNTPS 35677 CPL: 3 35678 CATEGORY: DATAXFER 35679 EXTENSION: AVX512EVEX 35680 ISA_SET: AVX512F_512 35681 EXCEPTIONS: AVX512-E1NF 35682 REAL_OPCODE: Y 35683 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 35684 PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 35685 OPERANDS: MEM0:w:zd:f32 REG0=ZMM_R3():r:zf32 35686 IFORM: VMOVNTPS_MEMf32_ZMMf32_AVX512 35687 } 35688 35689 35690 # EMITTING VMOVQ (VMOVQ-128-1) 35691 { 35692 ICLASS: VMOVQ 35693 CPL: 3 35694 CATEGORY: DATAXFER 35695 EXTENSION: AVX512EVEX 35696 ISA_SET: AVX512F_128N 35697 EXCEPTIONS: AVX512-E9NF 35698 REAL_OPCODE: Y 35699 PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 35700 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=GPR64_B():r:q:u64 35701 IFORM: VMOVQ_XMMu64_GPR64u64_AVX512 35702 } 35703 35704 { 35705 ICLASS: VMOVQ 35706 CPL: 3 35707 CATEGORY: DATAXFER 35708 EXTENSION: AVX512EVEX 35709 ISA_SET: AVX512F_128N 35710 EXCEPTIONS: AVX512-E9NF 35711 REAL_OPCODE: Y 35712 ATTRIBUTES: DISP8_GPR_READER 35713 PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() 35714 OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 35715 IFORM: VMOVQ_XMMu64_MEMu64_AVX512 35716 } 35717 35718 35719 # EMITTING VMOVQ (VMOVQ-128-2) 35720 { 35721 ICLASS: VMOVQ 35722 CPL: 3 35723 CATEGORY: DATAXFER 35724 EXTENSION: AVX512EVEX 35725 ISA_SET: AVX512F_128N 35726 EXCEPTIONS: AVX512-E9NF 35727 REAL_OPCODE: Y 35728 PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 35729 OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 35730 IFORM: VMOVQ_GPR64u64_XMMu64_AVX512 35731 } 35732 35733 { 35734 ICLASS: VMOVQ 35735 CPL: 3 35736 CATEGORY: DATAXFER 35737 EXTENSION: AVX512EVEX 35738 ISA_SET: AVX512F_128N 35739 EXCEPTIONS: AVX512-E9NF 35740 REAL_OPCODE: Y 35741 ATTRIBUTES: DISP8_GPR_WRITER_STORE 35742 PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() 35743 OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 35744 IFORM: VMOVQ_MEMu64_XMMu64_AVX512 35745 } 35746 35747 35748 # EMITTING VMOVQ (VMOVQ-128-3) 35749 { 35750 ICLASS: VMOVQ 35751 CPL: 3 35752 CATEGORY: DATAXFER 35753 EXTENSION: AVX512EVEX 35754 ISA_SET: AVX512F_128N 35755 EXCEPTIONS: AVX512-E9NF 35756 REAL_OPCODE: Y 35757 PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 35758 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64 35759 IFORM: VMOVQ_XMMu64_XMMu64_AVX512 35760 } 35761 35762 { 35763 ICLASS: VMOVQ 35764 CPL: 3 35765 CATEGORY: DATAXFER 35766 EXTENSION: AVX512EVEX 35767 ISA_SET: AVX512F_128N 35768 EXCEPTIONS: AVX512-E9NF 35769 REAL_OPCODE: Y 35770 ATTRIBUTES: DISP8_SCALAR 35771 PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 35772 OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 35773 IFORM: VMOVQ_XMMu64_MEMu64_AVX512 35774 } 35775 35776 35777 # EMITTING VMOVQ (VMOVQ-128-4) 35778 { 35779 ICLASS: VMOVQ 35780 CPL: 3 35781 CATEGORY: DATAXFER 35782 EXTENSION: AVX512EVEX 35783 ISA_SET: AVX512F_128N 35784 EXCEPTIONS: AVX512-E9NF 35785 REAL_OPCODE: Y 35786 PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 35787 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64 35788 IFORM: VMOVQ_XMMu64_XMMu64_AVX512 35789 } 35790 35791 { 35792 ICLASS: VMOVQ 35793 CPL: 3 35794 CATEGORY: DATAXFER 35795 EXTENSION: AVX512EVEX 35796 ISA_SET: AVX512F_128N 35797 EXCEPTIONS: AVX512-E9NF 35798 REAL_OPCODE: Y 35799 ATTRIBUTES: DISP8_SCALAR 35800 PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 35801 OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 35802 IFORM: VMOVQ_MEMu64_XMMu64_AVX512 35803 } 35804 35805 35806 # EMITTING VMOVSD (VMOVSD-128-1) 35807 { 35808 ICLASS: VMOVSD 35809 CPL: 3 35810 CATEGORY: DATAXFER 35811 EXTENSION: AVX512EVEX 35812 ISA_SET: AVX512F_SCALAR 35813 EXCEPTIONS: AVX512-E5 35814 REAL_OPCODE: Y 35815 ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 35816 PATTERN: EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR() 35817 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 35818 IFORM: VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 35819 } 35820 35821 35822 # EMITTING VMOVSD (VMOVSD-128-2) 35823 { 35824 ICLASS: VMOVSD 35825 CPL: 3 35826 CATEGORY: DATAXFER 35827 EXTENSION: AVX512EVEX 35828 ISA_SET: AVX512F_SCALAR 35829 EXCEPTIONS: AVX512-E5 35830 REAL_OPCODE: Y 35831 ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 35832 PATTERN: EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR() 35833 OPERANDS: MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 35834 IFORM: VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 35835 } 35836 35837 35838 # EMITTING VMOVSD (VMOVSD-128-3) 35839 { 35840 ICLASS: VMOVSD 35841 CPL: 3 35842 CATEGORY: DATAXFER 35843 EXTENSION: AVX512EVEX 35844 ISA_SET: AVX512F_SCALAR 35845 EXCEPTIONS: AVX512-E5 35846 REAL_OPCODE: Y 35847 ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX 35848 PATTERN: EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 35849 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 35850 IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 35851 } 35852 35853 35854 # EMITTING VMOVSD (VMOVSD-128-4) 35855 { 35856 ICLASS: VMOVSD 35857 CPL: 3 35858 CATEGORY: DATAXFER 35859 EXTENSION: AVX512EVEX 35860 ISA_SET: AVX512F_SCALAR 35861 EXCEPTIONS: AVX512-E5 35862 REAL_OPCODE: Y 35863 ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX 35864 PATTERN: EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 35865 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_R3():r:dq:f64 35866 IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 35867 } 35868 35869 35870 # EMITTING VMOVSHDUP (VMOVSHDUP-512-1) 35871 { 35872 ICLASS: VMOVSHDUP 35873 CPL: 3 35874 CATEGORY: DATAXFER 35875 EXTENSION: AVX512EVEX 35876 ISA_SET: AVX512F_512 35877 EXCEPTIONS: AVX512-E4NF 35878 REAL_OPCODE: Y 35879 ATTRIBUTES: MASKOP_EVEX 35880 PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 35881 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 35882 IFORM: VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 35883 } 35884 35885 { 35886 ICLASS: VMOVSHDUP 35887 CPL: 3 35888 CATEGORY: DATAXFER 35889 EXTENSION: AVX512EVEX 35890 ISA_SET: AVX512F_512 35891 EXCEPTIONS: AVX512-E4NF 35892 REAL_OPCODE: Y 35893 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 35894 PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 35895 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 35896 IFORM: VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 35897 } 35898 35899 35900 # EMITTING VMOVSLDUP (VMOVSLDUP-512-1) 35901 { 35902 ICLASS: VMOVSLDUP 35903 CPL: 3 35904 CATEGORY: DATAXFER 35905 EXTENSION: AVX512EVEX 35906 ISA_SET: AVX512F_512 35907 EXCEPTIONS: AVX512-E4NF 35908 REAL_OPCODE: Y 35909 ATTRIBUTES: MASKOP_EVEX 35910 PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 35911 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 35912 IFORM: VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 35913 } 35914 35915 { 35916 ICLASS: VMOVSLDUP 35917 CPL: 3 35918 CATEGORY: DATAXFER 35919 EXTENSION: AVX512EVEX 35920 ISA_SET: AVX512F_512 35921 EXCEPTIONS: AVX512-E4NF 35922 REAL_OPCODE: Y 35923 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 35924 PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 35925 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 35926 IFORM: VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 35927 } 35928 35929 35930 # EMITTING VMOVSS (VMOVSS-128-1) 35931 { 35932 ICLASS: VMOVSS 35933 CPL: 3 35934 CATEGORY: DATAXFER 35935 EXTENSION: AVX512EVEX 35936 ISA_SET: AVX512F_SCALAR 35937 EXCEPTIONS: AVX512-E5 35938 REAL_OPCODE: Y 35939 ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 35940 PATTERN: EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR() 35941 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 35942 IFORM: VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 35943 } 35944 35945 35946 # EMITTING VMOVSS (VMOVSS-128-2) 35947 { 35948 ICLASS: VMOVSS 35949 CPL: 3 35950 CATEGORY: DATAXFER 35951 EXTENSION: AVX512EVEX 35952 ISA_SET: AVX512F_SCALAR 35953 EXCEPTIONS: AVX512-E5 35954 REAL_OPCODE: Y 35955 ATTRIBUTES: SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 35956 PATTERN: EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR() 35957 OPERANDS: MEM0:w:d:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 35958 IFORM: VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 35959 } 35960 35961 35962 # EMITTING VMOVSS (VMOVSS-128-3) 35963 { 35964 ICLASS: VMOVSS 35965 CPL: 3 35966 CATEGORY: DATAXFER 35967 EXTENSION: AVX512EVEX 35968 ISA_SET: AVX512F_SCALAR 35969 EXCEPTIONS: AVX512-E5 35970 REAL_OPCODE: Y 35971 ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX 35972 PATTERN: EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 35973 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 35974 IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 35975 } 35976 35977 35978 # EMITTING VMOVSS (VMOVSS-128-4) 35979 { 35980 ICLASS: VMOVSS 35981 CPL: 3 35982 CATEGORY: DATAXFER 35983 EXTENSION: AVX512EVEX 35984 ISA_SET: AVX512F_SCALAR 35985 EXCEPTIONS: AVX512-E5 35986 REAL_OPCODE: Y 35987 ATTRIBUTES: SIMD_SCALAR MASKOP_EVEX 35988 PATTERN: EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 35989 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_R3():r:dq:f32 35990 IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 35991 } 35992 35993 35994 # EMITTING VMOVUPD (VMOVUPD-512-1) 35995 { 35996 ICLASS: VMOVUPD 35997 CPL: 3 35998 CATEGORY: DATAXFER 35999 EXTENSION: AVX512EVEX 36000 ISA_SET: AVX512F_512 36001 EXCEPTIONS: AVX512-E4 36002 REAL_OPCODE: Y 36003 ATTRIBUTES: MASKOP_EVEX 36004 PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 36005 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 36006 IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 36007 } 36008 36009 { 36010 ICLASS: VMOVUPD 36011 CPL: 3 36012 CATEGORY: DATAXFER 36013 EXTENSION: AVX512EVEX 36014 ISA_SET: AVX512F_512 36015 EXCEPTIONS: AVX512-E4 36016 REAL_OPCODE: Y 36017 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36018 PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 36019 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 36020 IFORM: VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 36021 } 36022 36023 36024 # EMITTING VMOVUPD (VMOVUPD-512-2) 36025 { 36026 ICLASS: VMOVUPD 36027 CPL: 3 36028 CATEGORY: DATAXFER 36029 EXTENSION: AVX512EVEX 36030 ISA_SET: AVX512F_512 36031 EXCEPTIONS: AVX512-E4 36032 REAL_OPCODE: Y 36033 ATTRIBUTES: MASKOP_EVEX 36034 PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 36035 OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 36036 IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 36037 } 36038 36039 36040 # EMITTING VMOVUPD (VMOVUPD-512-3) 36041 { 36042 ICLASS: VMOVUPD 36043 CPL: 3 36044 CATEGORY: DATAXFER 36045 EXTENSION: AVX512EVEX 36046 ISA_SET: AVX512F_512 36047 EXCEPTIONS: AVX512-E4 36048 REAL_OPCODE: Y 36049 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36050 PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 36051 OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 36052 IFORM: VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 36053 } 36054 36055 36056 # EMITTING VMOVUPS (VMOVUPS-512-1) 36057 { 36058 ICLASS: VMOVUPS 36059 CPL: 3 36060 CATEGORY: DATAXFER 36061 EXTENSION: AVX512EVEX 36062 ISA_SET: AVX512F_512 36063 EXCEPTIONS: AVX512-E4 36064 REAL_OPCODE: Y 36065 ATTRIBUTES: MASKOP_EVEX 36066 PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 36067 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 36068 IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 36069 } 36070 36071 { 36072 ICLASS: VMOVUPS 36073 CPL: 3 36074 CATEGORY: DATAXFER 36075 EXTENSION: AVX512EVEX 36076 ISA_SET: AVX512F_512 36077 EXCEPTIONS: AVX512-E4 36078 REAL_OPCODE: Y 36079 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36080 PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 36081 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 36082 IFORM: VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 36083 } 36084 36085 36086 # EMITTING VMOVUPS (VMOVUPS-512-2) 36087 { 36088 ICLASS: VMOVUPS 36089 CPL: 3 36090 CATEGORY: DATAXFER 36091 EXTENSION: AVX512EVEX 36092 ISA_SET: AVX512F_512 36093 EXCEPTIONS: AVX512-E4 36094 REAL_OPCODE: Y 36095 ATTRIBUTES: MASKOP_EVEX 36096 PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 36097 OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 36098 IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 36099 } 36100 36101 36102 # EMITTING VMOVUPS (VMOVUPS-512-3) 36103 { 36104 ICLASS: VMOVUPS 36105 CPL: 3 36106 CATEGORY: DATAXFER 36107 EXTENSION: AVX512EVEX 36108 ISA_SET: AVX512F_512 36109 EXCEPTIONS: AVX512-E4 36110 REAL_OPCODE: Y 36111 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36112 PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 36113 OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 36114 IFORM: VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 36115 } 36116 36117 36118 # EMITTING VMULPD (VMULPD-512-1) 36119 { 36120 ICLASS: VMULPD 36121 CPL: 3 36122 CATEGORY: AVX512 36123 EXTENSION: AVX512EVEX 36124 ISA_SET: AVX512F_512 36125 EXCEPTIONS: AVX512-E2 36126 REAL_OPCODE: Y 36127 ATTRIBUTES: MXCSR MASKOP_EVEX 36128 PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 36129 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 36130 IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 36131 } 36132 36133 { 36134 ICLASS: VMULPD 36135 CPL: 3 36136 CATEGORY: AVX512 36137 EXTENSION: AVX512EVEX 36138 ISA_SET: AVX512F_512 36139 EXCEPTIONS: AVX512-E2 36140 REAL_OPCODE: Y 36141 ATTRIBUTES: MXCSR MASKOP_EVEX 36142 PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 36143 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 36144 IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 36145 } 36146 36147 { 36148 ICLASS: VMULPD 36149 CPL: 3 36150 CATEGORY: AVX512 36151 EXTENSION: AVX512EVEX 36152 ISA_SET: AVX512F_512 36153 EXCEPTIONS: AVX512-E2 36154 REAL_OPCODE: Y 36155 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36156 PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 36157 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 36158 IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 36159 } 36160 36161 36162 # EMITTING VMULPS (VMULPS-512-1) 36163 { 36164 ICLASS: VMULPS 36165 CPL: 3 36166 CATEGORY: AVX512 36167 EXTENSION: AVX512EVEX 36168 ISA_SET: AVX512F_512 36169 EXCEPTIONS: AVX512-E2 36170 REAL_OPCODE: Y 36171 ATTRIBUTES: MXCSR MASKOP_EVEX 36172 PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 36173 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 36174 IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 36175 } 36176 36177 { 36178 ICLASS: VMULPS 36179 CPL: 3 36180 CATEGORY: AVX512 36181 EXTENSION: AVX512EVEX 36182 ISA_SET: AVX512F_512 36183 EXCEPTIONS: AVX512-E2 36184 REAL_OPCODE: Y 36185 ATTRIBUTES: MXCSR MASKOP_EVEX 36186 PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 36187 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 36188 IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 36189 } 36190 36191 { 36192 ICLASS: VMULPS 36193 CPL: 3 36194 CATEGORY: AVX512 36195 EXTENSION: AVX512EVEX 36196 ISA_SET: AVX512F_512 36197 EXCEPTIONS: AVX512-E2 36198 REAL_OPCODE: Y 36199 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36200 PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 36201 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 36202 IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 36203 } 36204 36205 36206 # EMITTING VMULSD (VMULSD-128-1) 36207 { 36208 ICLASS: VMULSD 36209 CPL: 3 36210 CATEGORY: AVX512 36211 EXTENSION: AVX512EVEX 36212 ISA_SET: AVX512F_SCALAR 36213 EXCEPTIONS: AVX512-E3 36214 REAL_OPCODE: Y 36215 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 36216 PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 36217 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 36218 IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 36219 } 36220 36221 { 36222 ICLASS: VMULSD 36223 CPL: 3 36224 CATEGORY: AVX512 36225 EXTENSION: AVX512EVEX 36226 ISA_SET: AVX512F_SCALAR 36227 EXCEPTIONS: AVX512-E3 36228 REAL_OPCODE: Y 36229 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 36230 PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 36231 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 36232 IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 36233 } 36234 36235 { 36236 ICLASS: VMULSD 36237 CPL: 3 36238 CATEGORY: AVX512 36239 EXTENSION: AVX512EVEX 36240 ISA_SET: AVX512F_SCALAR 36241 EXCEPTIONS: AVX512-E3 36242 REAL_OPCODE: Y 36243 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 36244 PATTERN: EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 36245 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 36246 IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 36247 } 36248 36249 36250 # EMITTING VMULSS (VMULSS-128-1) 36251 { 36252 ICLASS: VMULSS 36253 CPL: 3 36254 CATEGORY: AVX512 36255 EXTENSION: AVX512EVEX 36256 ISA_SET: AVX512F_SCALAR 36257 EXCEPTIONS: AVX512-E3 36258 REAL_OPCODE: Y 36259 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 36260 PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 36261 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 36262 IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 36263 } 36264 36265 { 36266 ICLASS: VMULSS 36267 CPL: 3 36268 CATEGORY: AVX512 36269 EXTENSION: AVX512EVEX 36270 ISA_SET: AVX512F_SCALAR 36271 EXCEPTIONS: AVX512-E3 36272 REAL_OPCODE: Y 36273 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 36274 PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 36275 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 36276 IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 36277 } 36278 36279 { 36280 ICLASS: VMULSS 36281 CPL: 3 36282 CATEGORY: AVX512 36283 EXTENSION: AVX512EVEX 36284 ISA_SET: AVX512F_SCALAR 36285 EXCEPTIONS: AVX512-E3 36286 REAL_OPCODE: Y 36287 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 36288 PATTERN: EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 36289 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 36290 IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 36291 } 36292 36293 36294 # EMITTING VPABSD (VPABSD-512-1) 36295 { 36296 ICLASS: VPABSD 36297 CPL: 3 36298 CATEGORY: AVX512 36299 EXTENSION: AVX512EVEX 36300 ISA_SET: AVX512F_512 36301 EXCEPTIONS: AVX512-E4 36302 REAL_OPCODE: Y 36303 ATTRIBUTES: MASKOP_EVEX 36304 PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 36305 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 36306 IFORM: VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 36307 } 36308 36309 { 36310 ICLASS: VPABSD 36311 CPL: 3 36312 CATEGORY: AVX512 36313 EXTENSION: AVX512EVEX 36314 ISA_SET: AVX512F_512 36315 EXCEPTIONS: AVX512-E4 36316 REAL_OPCODE: Y 36317 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36318 PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 36319 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 36320 IFORM: VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 36321 } 36322 36323 36324 # EMITTING VPABSQ (VPABSQ-512-1) 36325 { 36326 ICLASS: VPABSQ 36327 CPL: 3 36328 CATEGORY: AVX512 36329 EXTENSION: AVX512EVEX 36330 ISA_SET: AVX512F_512 36331 EXCEPTIONS: AVX512-E4 36332 REAL_OPCODE: Y 36333 ATTRIBUTES: MASKOP_EVEX 36334 PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 36335 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64 36336 IFORM: VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 36337 } 36338 36339 { 36340 ICLASS: VPABSQ 36341 CPL: 3 36342 CATEGORY: AVX512 36343 EXTENSION: AVX512EVEX 36344 ISA_SET: AVX512F_512 36345 EXCEPTIONS: AVX512-E4 36346 REAL_OPCODE: Y 36347 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36348 PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 36349 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR 36350 IFORM: VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 36351 } 36352 36353 36354 # EMITTING VPADDD (VPADDD-512-1) 36355 { 36356 ICLASS: VPADDD 36357 CPL: 3 36358 CATEGORY: AVX512 36359 EXTENSION: AVX512EVEX 36360 ISA_SET: AVX512F_512 36361 EXCEPTIONS: AVX512-E4 36362 REAL_OPCODE: Y 36363 ATTRIBUTES: MASKOP_EVEX 36364 PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 36365 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 36366 IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 36367 } 36368 36369 { 36370 ICLASS: VPADDD 36371 CPL: 3 36372 CATEGORY: AVX512 36373 EXTENSION: AVX512EVEX 36374 ISA_SET: AVX512F_512 36375 EXCEPTIONS: AVX512-E4 36376 REAL_OPCODE: Y 36377 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36378 PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 36379 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 36380 IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 36381 } 36382 36383 36384 # EMITTING VPADDQ (VPADDQ-512-1) 36385 { 36386 ICLASS: VPADDQ 36387 CPL: 3 36388 CATEGORY: AVX512 36389 EXTENSION: AVX512EVEX 36390 ISA_SET: AVX512F_512 36391 EXCEPTIONS: AVX512-E4 36392 REAL_OPCODE: Y 36393 ATTRIBUTES: MASKOP_EVEX 36394 PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 36395 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 36396 IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 36397 } 36398 36399 { 36400 ICLASS: VPADDQ 36401 CPL: 3 36402 CATEGORY: AVX512 36403 EXTENSION: AVX512EVEX 36404 ISA_SET: AVX512F_512 36405 EXCEPTIONS: AVX512-E4 36406 REAL_OPCODE: Y 36407 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36408 PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 36409 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 36410 IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 36411 } 36412 36413 36414 # EMITTING VPANDD (VPANDD-512-1) 36415 { 36416 ICLASS: VPANDD 36417 CPL: 3 36418 CATEGORY: LOGICAL 36419 EXTENSION: AVX512EVEX 36420 ISA_SET: AVX512F_512 36421 EXCEPTIONS: AVX512-E4 36422 REAL_OPCODE: Y 36423 ATTRIBUTES: MASKOP_EVEX 36424 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 36425 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 36426 IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 36427 } 36428 36429 { 36430 ICLASS: VPANDD 36431 CPL: 3 36432 CATEGORY: LOGICAL 36433 EXTENSION: AVX512EVEX 36434 ISA_SET: AVX512F_512 36435 EXCEPTIONS: AVX512-E4 36436 REAL_OPCODE: Y 36437 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36438 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 36439 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 36440 IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 36441 } 36442 36443 36444 # EMITTING VPANDND (VPANDND-512-1) 36445 { 36446 ICLASS: VPANDND 36447 CPL: 3 36448 CATEGORY: LOGICAL 36449 EXTENSION: AVX512EVEX 36450 ISA_SET: AVX512F_512 36451 EXCEPTIONS: AVX512-E4 36452 REAL_OPCODE: Y 36453 ATTRIBUTES: MASKOP_EVEX 36454 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 36455 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 36456 IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 36457 } 36458 36459 { 36460 ICLASS: VPANDND 36461 CPL: 3 36462 CATEGORY: LOGICAL 36463 EXTENSION: AVX512EVEX 36464 ISA_SET: AVX512F_512 36465 EXCEPTIONS: AVX512-E4 36466 REAL_OPCODE: Y 36467 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36468 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 36469 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 36470 IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 36471 } 36472 36473 36474 # EMITTING VPANDNQ (VPANDNQ-512-1) 36475 { 36476 ICLASS: VPANDNQ 36477 CPL: 3 36478 CATEGORY: LOGICAL 36479 EXTENSION: AVX512EVEX 36480 ISA_SET: AVX512F_512 36481 EXCEPTIONS: AVX512-E4 36482 REAL_OPCODE: Y 36483 ATTRIBUTES: MASKOP_EVEX 36484 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 36485 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 36486 IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 36487 } 36488 36489 { 36490 ICLASS: VPANDNQ 36491 CPL: 3 36492 CATEGORY: LOGICAL 36493 EXTENSION: AVX512EVEX 36494 ISA_SET: AVX512F_512 36495 EXCEPTIONS: AVX512-E4 36496 REAL_OPCODE: Y 36497 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36498 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 36499 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 36500 IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 36501 } 36502 36503 36504 # EMITTING VPANDQ (VPANDQ-512-1) 36505 { 36506 ICLASS: VPANDQ 36507 CPL: 3 36508 CATEGORY: LOGICAL 36509 EXTENSION: AVX512EVEX 36510 ISA_SET: AVX512F_512 36511 EXCEPTIONS: AVX512-E4 36512 REAL_OPCODE: Y 36513 ATTRIBUTES: MASKOP_EVEX 36514 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 36515 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 36516 IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 36517 } 36518 36519 { 36520 ICLASS: VPANDQ 36521 CPL: 3 36522 CATEGORY: LOGICAL 36523 EXTENSION: AVX512EVEX 36524 ISA_SET: AVX512F_512 36525 EXCEPTIONS: AVX512-E4 36526 REAL_OPCODE: Y 36527 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36528 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 36529 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 36530 IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 36531 } 36532 36533 36534 # EMITTING VPBLENDMD (VPBLENDMD-512-1) 36535 { 36536 ICLASS: VPBLENDMD 36537 CPL: 3 36538 CATEGORY: BLEND 36539 EXTENSION: AVX512EVEX 36540 ISA_SET: AVX512F_512 36541 EXCEPTIONS: AVX512-E4 36542 REAL_OPCODE: Y 36543 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 36544 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 36545 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 36546 IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 36547 } 36548 36549 { 36550 ICLASS: VPBLENDMD 36551 CPL: 3 36552 CATEGORY: BLEND 36553 EXTENSION: AVX512EVEX 36554 ISA_SET: AVX512F_512 36555 EXCEPTIONS: AVX512-E4 36556 REAL_OPCODE: Y 36557 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 36558 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 36559 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 36560 IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 36561 } 36562 36563 36564 # EMITTING VPBLENDMQ (VPBLENDMQ-512-1) 36565 { 36566 ICLASS: VPBLENDMQ 36567 CPL: 3 36568 CATEGORY: BLEND 36569 EXTENSION: AVX512EVEX 36570 ISA_SET: AVX512F_512 36571 EXCEPTIONS: AVX512-E4 36572 REAL_OPCODE: Y 36573 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 36574 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 36575 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 36576 IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 36577 } 36578 36579 { 36580 ICLASS: VPBLENDMQ 36581 CPL: 3 36582 CATEGORY: BLEND 36583 EXTENSION: AVX512EVEX 36584 ISA_SET: AVX512F_512 36585 EXCEPTIONS: AVX512-E4 36586 REAL_OPCODE: Y 36587 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 36588 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 36589 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 36590 IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 36591 } 36592 36593 36594 # EMITTING VPBROADCASTD (VPBROADCASTD-512-1) 36595 { 36596 ICLASS: VPBROADCASTD 36597 CPL: 3 36598 CATEGORY: BROADCAST 36599 EXTENSION: AVX512EVEX 36600 ISA_SET: AVX512F_512 36601 EXCEPTIONS: AVX512-E6 36602 REAL_OPCODE: Y 36603 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 36604 PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 36605 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO16_32 36606 IFORM: VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 36607 } 36608 36609 36610 # EMITTING VPBROADCASTD (VPBROADCASTD-512-2) 36611 { 36612 ICLASS: VPBROADCASTD 36613 CPL: 3 36614 CATEGORY: BROADCAST 36615 EXTENSION: AVX512EVEX 36616 ISA_SET: AVX512F_512 36617 EXCEPTIONS: AVX512-E6 36618 REAL_OPCODE: Y 36619 ATTRIBUTES: MASKOP_EVEX 36620 PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 36621 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO16_32 36622 IFORM: VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 36623 } 36624 36625 36626 # EMITTING VPBROADCASTD (VPBROADCASTD-512-3) 36627 { 36628 ICLASS: VPBROADCASTD 36629 CPL: 3 36630 CATEGORY: BROADCAST 36631 EXTENSION: AVX512EVEX 36632 ISA_SET: AVX512F_512 36633 EXCEPTIONS: AVX512-E7NM 36634 REAL_OPCODE: Y 36635 ATTRIBUTES: MASKOP_EVEX 36636 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 36637 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 36638 IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 36639 } 36640 36641 36642 # EMITTING VPBROADCASTQ (VPBROADCASTQ-512-1) 36643 { 36644 ICLASS: VPBROADCASTQ 36645 CPL: 3 36646 CATEGORY: BROADCAST 36647 EXTENSION: AVX512EVEX 36648 ISA_SET: AVX512F_512 36649 EXCEPTIONS: AVX512-E6 36650 REAL_OPCODE: Y 36651 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 36652 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() 36653 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO8_64 36654 IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 36655 } 36656 36657 36658 # EMITTING VPBROADCASTQ (VPBROADCASTQ-512-2) 36659 { 36660 ICLASS: VPBROADCASTQ 36661 CPL: 3 36662 CATEGORY: BROADCAST 36663 EXTENSION: AVX512EVEX 36664 ISA_SET: AVX512F_512 36665 EXCEPTIONS: AVX512-E6 36666 REAL_OPCODE: Y 36667 ATTRIBUTES: MASKOP_EVEX 36668 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 36669 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO8_64 36670 IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 36671 } 36672 36673 36674 # EMITTING VPBROADCASTQ (VPBROADCASTQ-512-3) 36675 { 36676 ICLASS: VPBROADCASTQ 36677 CPL: 3 36678 CATEGORY: BROADCAST 36679 EXTENSION: AVX512EVEX 36680 ISA_SET: AVX512F_512 36681 EXCEPTIONS: AVX512-E7NM 36682 REAL_OPCODE: Y 36683 ATTRIBUTES: MASKOP_EVEX 36684 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 mode64 NOEVSR 36685 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64 36686 IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 36687 } 36688 36689 36690 # EMITTING VPCMPD (VPCMPD-512-1) 36691 { 36692 ICLASS: VPCMPD 36693 CPL: 3 36694 CATEGORY: AVX512 36695 EXTENSION: AVX512EVEX 36696 ISA_SET: AVX512F_512 36697 EXCEPTIONS: AVX512-E4 36698 REAL_OPCODE: Y 36699 ATTRIBUTES: MASKOP_EVEX 36700 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() 36701 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 IMM0:r:b 36702 IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 36703 } 36704 36705 { 36706 ICLASS: VPCMPD 36707 CPL: 3 36708 CATEGORY: AVX512 36709 EXTENSION: AVX512EVEX 36710 ISA_SET: AVX512F_512 36711 EXCEPTIONS: AVX512-E4 36712 REAL_OPCODE: Y 36713 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36714 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 36715 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b 36716 IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 36717 } 36718 36719 36720 # EMITTING VPCMPEQD (VPCMPEQD-512-1) 36721 { 36722 ICLASS: VPCMPEQD 36723 CPL: 3 36724 CATEGORY: AVX512 36725 EXTENSION: AVX512EVEX 36726 ISA_SET: AVX512F_512 36727 EXCEPTIONS: AVX512-E4 36728 REAL_OPCODE: Y 36729 ATTRIBUTES: MASKOP_EVEX 36730 PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 36731 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 36732 IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 36733 } 36734 36735 { 36736 ICLASS: VPCMPEQD 36737 CPL: 3 36738 CATEGORY: AVX512 36739 EXTENSION: AVX512EVEX 36740 ISA_SET: AVX512F_512 36741 EXCEPTIONS: AVX512-E4 36742 REAL_OPCODE: Y 36743 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36744 PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 36745 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 36746 IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 36747 } 36748 36749 36750 # EMITTING VPCMPEQQ (VPCMPEQQ-512-1) 36751 { 36752 ICLASS: VPCMPEQQ 36753 CPL: 3 36754 CATEGORY: AVX512 36755 EXTENSION: AVX512EVEX 36756 ISA_SET: AVX512F_512 36757 EXCEPTIONS: AVX512-E4 36758 REAL_OPCODE: Y 36759 ATTRIBUTES: MASKOP_EVEX 36760 PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 36761 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 36762 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 36763 } 36764 36765 { 36766 ICLASS: VPCMPEQQ 36767 CPL: 3 36768 CATEGORY: AVX512 36769 EXTENSION: AVX512EVEX 36770 ISA_SET: AVX512F_512 36771 EXCEPTIONS: AVX512-E4 36772 REAL_OPCODE: Y 36773 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36774 PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 36775 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 36776 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 36777 } 36778 36779 36780 # EMITTING VPCMPGTD (VPCMPGTD-512-1) 36781 { 36782 ICLASS: VPCMPGTD 36783 CPL: 3 36784 CATEGORY: AVX512 36785 EXTENSION: AVX512EVEX 36786 ISA_SET: AVX512F_512 36787 EXCEPTIONS: AVX512-E4 36788 REAL_OPCODE: Y 36789 ATTRIBUTES: MASKOP_EVEX 36790 PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 36791 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 36792 IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 36793 } 36794 36795 { 36796 ICLASS: VPCMPGTD 36797 CPL: 3 36798 CATEGORY: AVX512 36799 EXTENSION: AVX512EVEX 36800 ISA_SET: AVX512F_512 36801 EXCEPTIONS: AVX512-E4 36802 REAL_OPCODE: Y 36803 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36804 PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 36805 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR 36806 IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 36807 } 36808 36809 36810 # EMITTING VPCMPGTQ (VPCMPGTQ-512-1) 36811 { 36812 ICLASS: VPCMPGTQ 36813 CPL: 3 36814 CATEGORY: AVX512 36815 EXTENSION: AVX512EVEX 36816 ISA_SET: AVX512F_512 36817 EXCEPTIONS: AVX512-E4 36818 REAL_OPCODE: Y 36819 ATTRIBUTES: MASKOP_EVEX 36820 PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 36821 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 36822 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 36823 } 36824 36825 { 36826 ICLASS: VPCMPGTQ 36827 CPL: 3 36828 CATEGORY: AVX512 36829 EXTENSION: AVX512EVEX 36830 ISA_SET: AVX512F_512 36831 EXCEPTIONS: AVX512-E4 36832 REAL_OPCODE: Y 36833 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36834 PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 36835 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR 36836 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 36837 } 36838 36839 36840 # EMITTING VPCMPQ (VPCMPQ-512-1) 36841 { 36842 ICLASS: VPCMPQ 36843 CPL: 3 36844 CATEGORY: AVX512 36845 EXTENSION: AVX512EVEX 36846 ISA_SET: AVX512F_512 36847 EXCEPTIONS: AVX512-E4 36848 REAL_OPCODE: Y 36849 ATTRIBUTES: MASKOP_EVEX 36850 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() 36851 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 IMM0:r:b 36852 IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 36853 } 36854 36855 { 36856 ICLASS: VPCMPQ 36857 CPL: 3 36858 CATEGORY: AVX512 36859 EXTENSION: AVX512EVEX 36860 ISA_SET: AVX512F_512 36861 EXCEPTIONS: AVX512-E4 36862 REAL_OPCODE: Y 36863 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36864 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 36865 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b 36866 IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 36867 } 36868 36869 36870 # EMITTING VPCMPUD (VPCMPUD-512-1) 36871 { 36872 ICLASS: VPCMPUD 36873 CPL: 3 36874 CATEGORY: AVX512 36875 EXTENSION: AVX512EVEX 36876 ISA_SET: AVX512F_512 36877 EXCEPTIONS: AVX512-E4 36878 REAL_OPCODE: Y 36879 ATTRIBUTES: MASKOP_EVEX 36880 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() 36881 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b 36882 IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 36883 } 36884 36885 { 36886 ICLASS: VPCMPUD 36887 CPL: 3 36888 CATEGORY: AVX512 36889 EXTENSION: AVX512EVEX 36890 ISA_SET: AVX512F_512 36891 EXCEPTIONS: AVX512-E4 36892 REAL_OPCODE: Y 36893 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36894 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 36895 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 36896 IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 36897 } 36898 36899 36900 # EMITTING VPCMPUQ (VPCMPUQ-512-1) 36901 { 36902 ICLASS: VPCMPUQ 36903 CPL: 3 36904 CATEGORY: AVX512 36905 EXTENSION: AVX512EVEX 36906 ISA_SET: AVX512F_512 36907 EXCEPTIONS: AVX512-E4 36908 REAL_OPCODE: Y 36909 ATTRIBUTES: MASKOP_EVEX 36910 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() 36911 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b 36912 IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 36913 } 36914 36915 { 36916 ICLASS: VPCMPUQ 36917 CPL: 3 36918 CATEGORY: AVX512 36919 EXTENSION: AVX512EVEX 36920 ISA_SET: AVX512F_512 36921 EXCEPTIONS: AVX512-E4 36922 REAL_OPCODE: Y 36923 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36924 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 36925 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 36926 IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 36927 } 36928 36929 36930 # EMITTING VPCOMPRESSD (VPCOMPRESSD-512-1) 36931 { 36932 ICLASS: VPCOMPRESSD 36933 CPL: 3 36934 CATEGORY: COMPRESS 36935 EXTENSION: AVX512EVEX 36936 ISA_SET: AVX512F_512 36937 EXCEPTIONS: AVX512-E4 36938 REAL_OPCODE: Y 36939 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 36940 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 36941 OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 36942 IFORM: VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 36943 } 36944 36945 36946 # EMITTING VPCOMPRESSD (VPCOMPRESSD-512-2) 36947 { 36948 ICLASS: VPCOMPRESSD 36949 CPL: 3 36950 CATEGORY: COMPRESS 36951 EXTENSION: AVX512EVEX 36952 ISA_SET: AVX512F_512 36953 EXCEPTIONS: AVX512-E4 36954 REAL_OPCODE: Y 36955 ATTRIBUTES: MASKOP_EVEX 36956 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 36957 OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 36958 IFORM: VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 36959 } 36960 36961 36962 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-1) 36963 { 36964 ICLASS: VPCOMPRESSQ 36965 CPL: 3 36966 CATEGORY: COMPRESS 36967 EXTENSION: AVX512EVEX 36968 ISA_SET: AVX512F_512 36969 EXCEPTIONS: AVX512-E4 36970 REAL_OPCODE: Y 36971 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 36972 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 36973 OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 36974 IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 36975 } 36976 36977 36978 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-2) 36979 { 36980 ICLASS: VPCOMPRESSQ 36981 CPL: 3 36982 CATEGORY: COMPRESS 36983 EXTENSION: AVX512EVEX 36984 ISA_SET: AVX512F_512 36985 EXCEPTIONS: AVX512-E4 36986 REAL_OPCODE: Y 36987 ATTRIBUTES: MASKOP_EVEX 36988 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 36989 OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 36990 IFORM: VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 36991 } 36992 36993 36994 # EMITTING VPERMD (VPERMD-512-1) 36995 { 36996 ICLASS: VPERMD 36997 CPL: 3 36998 CATEGORY: AVX512 36999 EXTENSION: AVX512EVEX 37000 ISA_SET: AVX512F_512 37001 EXCEPTIONS: AVX512-E4NF 37002 REAL_OPCODE: Y 37003 ATTRIBUTES: MASKOP_EVEX 37004 PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37005 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 37006 IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 37007 } 37008 37009 { 37010 ICLASS: VPERMD 37011 CPL: 3 37012 CATEGORY: AVX512 37013 EXTENSION: AVX512EVEX 37014 ISA_SET: AVX512F_512 37015 EXCEPTIONS: AVX512-E4NF 37016 REAL_OPCODE: Y 37017 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37018 PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37019 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 37020 IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 37021 } 37022 37023 37024 # EMITTING VPERMI2D (VPERMI2D-512-1) 37025 { 37026 ICLASS: VPERMI2D 37027 CPL: 3 37028 CATEGORY: AVX512 37029 EXTENSION: AVX512EVEX 37030 ISA_SET: AVX512F_512 37031 EXCEPTIONS: AVX512-E4NF 37032 REAL_OPCODE: Y 37033 ATTRIBUTES: MASKOP_EVEX 37034 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37035 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 37036 IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 37037 } 37038 37039 { 37040 ICLASS: VPERMI2D 37041 CPL: 3 37042 CATEGORY: AVX512 37043 EXTENSION: AVX512EVEX 37044 ISA_SET: AVX512F_512 37045 EXCEPTIONS: AVX512-E4NF 37046 REAL_OPCODE: Y 37047 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37048 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37049 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 37050 IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 37051 } 37052 37053 37054 # EMITTING VPERMI2PD (VPERMI2PD-512-1) 37055 { 37056 ICLASS: VPERMI2PD 37057 CPL: 3 37058 CATEGORY: AVX512 37059 EXTENSION: AVX512EVEX 37060 ISA_SET: AVX512F_512 37061 EXCEPTIONS: AVX512-E4NF 37062 REAL_OPCODE: Y 37063 ATTRIBUTES: MASKOP_EVEX 37064 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37065 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 37066 IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 37067 } 37068 37069 { 37070 ICLASS: VPERMI2PD 37071 CPL: 3 37072 CATEGORY: AVX512 37073 EXTENSION: AVX512EVEX 37074 ISA_SET: AVX512F_512 37075 EXCEPTIONS: AVX512-E4NF 37076 REAL_OPCODE: Y 37077 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37078 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37079 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 37080 IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 37081 } 37082 37083 37084 # EMITTING VPERMI2PS (VPERMI2PS-512-1) 37085 { 37086 ICLASS: VPERMI2PS 37087 CPL: 3 37088 CATEGORY: AVX512 37089 EXTENSION: AVX512EVEX 37090 ISA_SET: AVX512F_512 37091 EXCEPTIONS: AVX512-E4NF 37092 REAL_OPCODE: Y 37093 ATTRIBUTES: MASKOP_EVEX 37094 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37095 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 37096 IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 37097 } 37098 37099 { 37100 ICLASS: VPERMI2PS 37101 CPL: 3 37102 CATEGORY: AVX512 37103 EXTENSION: AVX512EVEX 37104 ISA_SET: AVX512F_512 37105 EXCEPTIONS: AVX512-E4NF 37106 REAL_OPCODE: Y 37107 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37108 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37109 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 37110 IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 37111 } 37112 37113 37114 # EMITTING VPERMI2Q (VPERMI2Q-512-1) 37115 { 37116 ICLASS: VPERMI2Q 37117 CPL: 3 37118 CATEGORY: AVX512 37119 EXTENSION: AVX512EVEX 37120 ISA_SET: AVX512F_512 37121 EXCEPTIONS: AVX512-E4NF 37122 REAL_OPCODE: Y 37123 ATTRIBUTES: MASKOP_EVEX 37124 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37125 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 37126 IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 37127 } 37128 37129 { 37130 ICLASS: VPERMI2Q 37131 CPL: 3 37132 CATEGORY: AVX512 37133 EXTENSION: AVX512EVEX 37134 ISA_SET: AVX512F_512 37135 EXCEPTIONS: AVX512-E4NF 37136 REAL_OPCODE: Y 37137 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37138 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37139 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 37140 IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 37141 } 37142 37143 37144 # EMITTING VPERMILPD (VPERMILPD-512-1) 37145 { 37146 ICLASS: VPERMILPD 37147 CPL: 3 37148 CATEGORY: AVX512 37149 EXTENSION: AVX512EVEX 37150 ISA_SET: AVX512F_512 37151 EXCEPTIONS: AVX512-E4NF 37152 REAL_OPCODE: Y 37153 ATTRIBUTES: MASKOP_EVEX 37154 PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 37155 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 37156 IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 37157 } 37158 37159 { 37160 ICLASS: VPERMILPD 37161 CPL: 3 37162 CATEGORY: AVX512 37163 EXTENSION: AVX512EVEX 37164 ISA_SET: AVX512F_512 37165 EXCEPTIONS: AVX512-E4NF 37166 REAL_OPCODE: Y 37167 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37168 PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 37169 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 37170 IFORM: VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 37171 } 37172 37173 37174 # EMITTING VPERMILPD (VPERMILPD-512-2) 37175 { 37176 ICLASS: VPERMILPD 37177 CPL: 3 37178 CATEGORY: AVX512 37179 EXTENSION: AVX512EVEX 37180 ISA_SET: AVX512F_512 37181 EXCEPTIONS: AVX512-E4NF 37182 REAL_OPCODE: Y 37183 ATTRIBUTES: MASKOP_EVEX 37184 PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37185 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 37186 IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 37187 } 37188 37189 { 37190 ICLASS: VPERMILPD 37191 CPL: 3 37192 CATEGORY: AVX512 37193 EXTENSION: AVX512EVEX 37194 ISA_SET: AVX512F_512 37195 EXCEPTIONS: AVX512-E4NF 37196 REAL_OPCODE: Y 37197 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37198 PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37199 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 37200 IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 37201 } 37202 37203 37204 # EMITTING VPERMILPS (VPERMILPS-512-1) 37205 { 37206 ICLASS: VPERMILPS 37207 CPL: 3 37208 CATEGORY: AVX512 37209 EXTENSION: AVX512EVEX 37210 ISA_SET: AVX512F_512 37211 EXCEPTIONS: AVX512-E4NF 37212 REAL_OPCODE: Y 37213 ATTRIBUTES: MASKOP_EVEX 37214 PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 37215 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 37216 IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 37217 } 37218 37219 { 37220 ICLASS: VPERMILPS 37221 CPL: 3 37222 CATEGORY: AVX512 37223 EXTENSION: AVX512EVEX 37224 ISA_SET: AVX512F_512 37225 EXCEPTIONS: AVX512-E4NF 37226 REAL_OPCODE: Y 37227 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37228 PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 37229 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 37230 IFORM: VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 37231 } 37232 37233 37234 # EMITTING VPERMILPS (VPERMILPS-512-2) 37235 { 37236 ICLASS: VPERMILPS 37237 CPL: 3 37238 CATEGORY: AVX512 37239 EXTENSION: AVX512EVEX 37240 ISA_SET: AVX512F_512 37241 EXCEPTIONS: AVX512-E4NF 37242 REAL_OPCODE: Y 37243 ATTRIBUTES: MASKOP_EVEX 37244 PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37245 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 37246 IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 37247 } 37248 37249 { 37250 ICLASS: VPERMILPS 37251 CPL: 3 37252 CATEGORY: AVX512 37253 EXTENSION: AVX512EVEX 37254 ISA_SET: AVX512F_512 37255 EXCEPTIONS: AVX512-E4NF 37256 REAL_OPCODE: Y 37257 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37258 PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37259 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 37260 IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 37261 } 37262 37263 37264 # EMITTING VPERMPD (VPERMPD-512-1) 37265 { 37266 ICLASS: VPERMPD 37267 CPL: 3 37268 CATEGORY: AVX512 37269 EXTENSION: AVX512EVEX 37270 ISA_SET: AVX512F_512 37271 EXCEPTIONS: AVX512-E4NF 37272 REAL_OPCODE: Y 37273 ATTRIBUTES: MASKOP_EVEX 37274 PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 37275 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 37276 IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 37277 } 37278 37279 { 37280 ICLASS: VPERMPD 37281 CPL: 3 37282 CATEGORY: AVX512 37283 EXTENSION: AVX512EVEX 37284 ISA_SET: AVX512F_512 37285 EXCEPTIONS: AVX512-E4NF 37286 REAL_OPCODE: Y 37287 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37288 PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 37289 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 37290 IFORM: VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 37291 } 37292 37293 37294 # EMITTING VPERMPD (VPERMPD-512-2) 37295 { 37296 ICLASS: VPERMPD 37297 CPL: 3 37298 CATEGORY: AVX512 37299 EXTENSION: AVX512EVEX 37300 ISA_SET: AVX512F_512 37301 EXCEPTIONS: AVX512-E4NF 37302 REAL_OPCODE: Y 37303 ATTRIBUTES: MASKOP_EVEX 37304 PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37305 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 37306 IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 37307 } 37308 37309 { 37310 ICLASS: VPERMPD 37311 CPL: 3 37312 CATEGORY: AVX512 37313 EXTENSION: AVX512EVEX 37314 ISA_SET: AVX512F_512 37315 EXCEPTIONS: AVX512-E4NF 37316 REAL_OPCODE: Y 37317 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37318 PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37319 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 37320 IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 37321 } 37322 37323 37324 # EMITTING VPERMPS (VPERMPS-512-1) 37325 { 37326 ICLASS: VPERMPS 37327 CPL: 3 37328 CATEGORY: AVX512 37329 EXTENSION: AVX512EVEX 37330 ISA_SET: AVX512F_512 37331 EXCEPTIONS: AVX512-E4NF 37332 REAL_OPCODE: Y 37333 ATTRIBUTES: MASKOP_EVEX 37334 PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37335 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 37336 IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 37337 } 37338 37339 { 37340 ICLASS: VPERMPS 37341 CPL: 3 37342 CATEGORY: AVX512 37343 EXTENSION: AVX512EVEX 37344 ISA_SET: AVX512F_512 37345 EXCEPTIONS: AVX512-E4NF 37346 REAL_OPCODE: Y 37347 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37348 PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37349 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 37350 IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 37351 } 37352 37353 37354 # EMITTING VPERMQ (VPERMQ-512-1) 37355 { 37356 ICLASS: VPERMQ 37357 CPL: 3 37358 CATEGORY: AVX512 37359 EXTENSION: AVX512EVEX 37360 ISA_SET: AVX512F_512 37361 EXCEPTIONS: AVX512-E4NF 37362 REAL_OPCODE: Y 37363 ATTRIBUTES: MASKOP_EVEX 37364 PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 37365 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 37366 IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 37367 } 37368 37369 { 37370 ICLASS: VPERMQ 37371 CPL: 3 37372 CATEGORY: AVX512 37373 EXTENSION: AVX512EVEX 37374 ISA_SET: AVX512F_512 37375 EXCEPTIONS: AVX512-E4NF 37376 REAL_OPCODE: Y 37377 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37378 PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 37379 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 37380 IFORM: VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 37381 } 37382 37383 37384 # EMITTING VPERMQ (VPERMQ-512-2) 37385 { 37386 ICLASS: VPERMQ 37387 CPL: 3 37388 CATEGORY: AVX512 37389 EXTENSION: AVX512EVEX 37390 ISA_SET: AVX512F_512 37391 EXCEPTIONS: AVX512-E4NF 37392 REAL_OPCODE: Y 37393 ATTRIBUTES: MASKOP_EVEX 37394 PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37395 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 37396 IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 37397 } 37398 37399 { 37400 ICLASS: VPERMQ 37401 CPL: 3 37402 CATEGORY: AVX512 37403 EXTENSION: AVX512EVEX 37404 ISA_SET: AVX512F_512 37405 EXCEPTIONS: AVX512-E4NF 37406 REAL_OPCODE: Y 37407 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37408 PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37409 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 37410 IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 37411 } 37412 37413 37414 # EMITTING VPERMT2D (VPERMT2D-512-1) 37415 { 37416 ICLASS: VPERMT2D 37417 CPL: 3 37418 CATEGORY: AVX512 37419 EXTENSION: AVX512EVEX 37420 ISA_SET: AVX512F_512 37421 EXCEPTIONS: AVX512-E4NF 37422 REAL_OPCODE: Y 37423 ATTRIBUTES: MASKOP_EVEX 37424 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37425 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 37426 IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 37427 } 37428 37429 { 37430 ICLASS: VPERMT2D 37431 CPL: 3 37432 CATEGORY: AVX512 37433 EXTENSION: AVX512EVEX 37434 ISA_SET: AVX512F_512 37435 EXCEPTIONS: AVX512-E4NF 37436 REAL_OPCODE: Y 37437 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37438 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37439 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 37440 IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 37441 } 37442 37443 37444 # EMITTING VPERMT2PD (VPERMT2PD-512-1) 37445 { 37446 ICLASS: VPERMT2PD 37447 CPL: 3 37448 CATEGORY: AVX512 37449 EXTENSION: AVX512EVEX 37450 ISA_SET: AVX512F_512 37451 EXCEPTIONS: AVX512-E4NF 37452 REAL_OPCODE: Y 37453 ATTRIBUTES: MASKOP_EVEX 37454 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37455 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 37456 IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 37457 } 37458 37459 { 37460 ICLASS: VPERMT2PD 37461 CPL: 3 37462 CATEGORY: AVX512 37463 EXTENSION: AVX512EVEX 37464 ISA_SET: AVX512F_512 37465 EXCEPTIONS: AVX512-E4NF 37466 REAL_OPCODE: Y 37467 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37468 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37469 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 37470 IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 37471 } 37472 37473 37474 # EMITTING VPERMT2PS (VPERMT2PS-512-1) 37475 { 37476 ICLASS: VPERMT2PS 37477 CPL: 3 37478 CATEGORY: AVX512 37479 EXTENSION: AVX512EVEX 37480 ISA_SET: AVX512F_512 37481 EXCEPTIONS: AVX512-E4NF 37482 REAL_OPCODE: Y 37483 ATTRIBUTES: MASKOP_EVEX 37484 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37485 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 37486 IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 37487 } 37488 37489 { 37490 ICLASS: VPERMT2PS 37491 CPL: 3 37492 CATEGORY: AVX512 37493 EXTENSION: AVX512EVEX 37494 ISA_SET: AVX512F_512 37495 EXCEPTIONS: AVX512-E4NF 37496 REAL_OPCODE: Y 37497 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37498 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37499 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 37500 IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 37501 } 37502 37503 37504 # EMITTING VPERMT2Q (VPERMT2Q-512-1) 37505 { 37506 ICLASS: VPERMT2Q 37507 CPL: 3 37508 CATEGORY: AVX512 37509 EXTENSION: AVX512EVEX 37510 ISA_SET: AVX512F_512 37511 EXCEPTIONS: AVX512-E4NF 37512 REAL_OPCODE: Y 37513 ATTRIBUTES: MASKOP_EVEX 37514 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37515 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 37516 IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 37517 } 37518 37519 { 37520 ICLASS: VPERMT2Q 37521 CPL: 3 37522 CATEGORY: AVX512 37523 EXTENSION: AVX512EVEX 37524 ISA_SET: AVX512F_512 37525 EXCEPTIONS: AVX512-E4NF 37526 REAL_OPCODE: Y 37527 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37528 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37529 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 37530 IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 37531 } 37532 37533 37534 # EMITTING VPEXPANDD (VPEXPANDD-512-1) 37535 { 37536 ICLASS: VPEXPANDD 37537 CPL: 3 37538 CATEGORY: EXPAND 37539 EXTENSION: AVX512EVEX 37540 ISA_SET: AVX512F_512 37541 EXCEPTIONS: AVX512-E4 37542 REAL_OPCODE: Y 37543 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 37544 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 37545 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 37546 IFORM: VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 37547 } 37548 37549 37550 # EMITTING VPEXPANDD (VPEXPANDD-512-2) 37551 { 37552 ICLASS: VPEXPANDD 37553 CPL: 3 37554 CATEGORY: EXPAND 37555 EXTENSION: AVX512EVEX 37556 ISA_SET: AVX512F_512 37557 EXCEPTIONS: AVX512-E4 37558 REAL_OPCODE: Y 37559 ATTRIBUTES: MASKOP_EVEX 37560 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 37561 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 37562 IFORM: VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 37563 } 37564 37565 37566 # EMITTING VPEXPANDQ (VPEXPANDQ-512-1) 37567 { 37568 ICLASS: VPEXPANDQ 37569 CPL: 3 37570 CATEGORY: EXPAND 37571 EXTENSION: AVX512EVEX 37572 ISA_SET: AVX512F_512 37573 EXCEPTIONS: AVX512-E4 37574 REAL_OPCODE: Y 37575 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 37576 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 37577 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 37578 IFORM: VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 37579 } 37580 37581 37582 # EMITTING VPEXPANDQ (VPEXPANDQ-512-2) 37583 { 37584 ICLASS: VPEXPANDQ 37585 CPL: 3 37586 CATEGORY: EXPAND 37587 EXTENSION: AVX512EVEX 37588 ISA_SET: AVX512F_512 37589 EXCEPTIONS: AVX512-E4 37590 REAL_OPCODE: Y 37591 ATTRIBUTES: MASKOP_EVEX 37592 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 37593 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 37594 IFORM: VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 37595 } 37596 37597 37598 # EMITTING VPGATHERDD (VPGATHERDD-512-1) 37599 { 37600 ICLASS: VPGATHERDD 37601 CPL: 3 37602 CATEGORY: GATHER 37603 EXTENSION: AVX512EVEX 37604 ISA_SET: AVX512F_512 37605 EXCEPTIONS: AVX512-E12 37606 REAL_OPCODE: Y 37607 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 37608 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 37609 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u32 37610 IFORM: VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 37611 } 37612 37613 37614 # EMITTING VPGATHERDQ (VPGATHERDQ-512-1) 37615 { 37616 ICLASS: VPGATHERDQ 37617 CPL: 3 37618 CATEGORY: GATHER 37619 EXTENSION: AVX512EVEX 37620 ISA_SET: AVX512F_512 37621 EXCEPTIONS: AVX512-E12 37622 REAL_OPCODE: Y 37623 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 37624 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 37625 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u64 37626 IFORM: VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 37627 } 37628 37629 37630 # EMITTING VPGATHERQD (VPGATHERQD-512-1) 37631 { 37632 ICLASS: VPGATHERQD 37633 CPL: 3 37634 CATEGORY: GATHER 37635 EXTENSION: AVX512EVEX 37636 ISA_SET: AVX512F_512 37637 EXCEPTIONS: AVX512-E12 37638 REAL_OPCODE: Y 37639 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 37640 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 37641 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u32 37642 IFORM: VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 37643 } 37644 37645 37646 # EMITTING VPGATHERQQ (VPGATHERQQ-512-1) 37647 { 37648 ICLASS: VPGATHERQQ 37649 CPL: 3 37650 CATEGORY: GATHER 37651 EXTENSION: AVX512EVEX 37652 ISA_SET: AVX512F_512 37653 EXCEPTIONS: AVX512-E12 37654 REAL_OPCODE: Y 37655 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 37656 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 37657 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:zd:u64 37658 IFORM: VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 37659 } 37660 37661 37662 # EMITTING VPMAXSD (VPMAXSD-512-1) 37663 { 37664 ICLASS: VPMAXSD 37665 CPL: 3 37666 CATEGORY: AVX512 37667 EXTENSION: AVX512EVEX 37668 ISA_SET: AVX512F_512 37669 EXCEPTIONS: AVX512-E4 37670 REAL_OPCODE: Y 37671 ATTRIBUTES: MASKOP_EVEX 37672 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37673 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 37674 IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 37675 } 37676 37677 { 37678 ICLASS: VPMAXSD 37679 CPL: 3 37680 CATEGORY: AVX512 37681 EXTENSION: AVX512EVEX 37682 ISA_SET: AVX512F_512 37683 EXCEPTIONS: AVX512-E4 37684 REAL_OPCODE: Y 37685 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37686 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37687 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR 37688 IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 37689 } 37690 37691 37692 # EMITTING VPMAXSQ (VPMAXSQ-512-1) 37693 { 37694 ICLASS: VPMAXSQ 37695 CPL: 3 37696 CATEGORY: AVX512 37697 EXTENSION: AVX512EVEX 37698 ISA_SET: AVX512F_512 37699 EXCEPTIONS: AVX512-E4 37700 REAL_OPCODE: Y 37701 ATTRIBUTES: MASKOP_EVEX 37702 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37703 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 37704 IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 37705 } 37706 37707 { 37708 ICLASS: VPMAXSQ 37709 CPL: 3 37710 CATEGORY: AVX512 37711 EXTENSION: AVX512EVEX 37712 ISA_SET: AVX512F_512 37713 EXCEPTIONS: AVX512-E4 37714 REAL_OPCODE: Y 37715 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37716 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37717 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR 37718 IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 37719 } 37720 37721 37722 # EMITTING VPMAXUD (VPMAXUD-512-1) 37723 { 37724 ICLASS: VPMAXUD 37725 CPL: 3 37726 CATEGORY: AVX512 37727 EXTENSION: AVX512EVEX 37728 ISA_SET: AVX512F_512 37729 EXCEPTIONS: AVX512-E4 37730 REAL_OPCODE: Y 37731 ATTRIBUTES: MASKOP_EVEX 37732 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37733 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 37734 IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 37735 } 37736 37737 { 37738 ICLASS: VPMAXUD 37739 CPL: 3 37740 CATEGORY: AVX512 37741 EXTENSION: AVX512EVEX 37742 ISA_SET: AVX512F_512 37743 EXCEPTIONS: AVX512-E4 37744 REAL_OPCODE: Y 37745 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37746 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37747 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 37748 IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 37749 } 37750 37751 37752 # EMITTING VPMAXUQ (VPMAXUQ-512-1) 37753 { 37754 ICLASS: VPMAXUQ 37755 CPL: 3 37756 CATEGORY: AVX512 37757 EXTENSION: AVX512EVEX 37758 ISA_SET: AVX512F_512 37759 EXCEPTIONS: AVX512-E4 37760 REAL_OPCODE: Y 37761 ATTRIBUTES: MASKOP_EVEX 37762 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37763 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 37764 IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 37765 } 37766 37767 { 37768 ICLASS: VPMAXUQ 37769 CPL: 3 37770 CATEGORY: AVX512 37771 EXTENSION: AVX512EVEX 37772 ISA_SET: AVX512F_512 37773 EXCEPTIONS: AVX512-E4 37774 REAL_OPCODE: Y 37775 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37776 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37777 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 37778 IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 37779 } 37780 37781 37782 # EMITTING VPMINSD (VPMINSD-512-1) 37783 { 37784 ICLASS: VPMINSD 37785 CPL: 3 37786 CATEGORY: AVX512 37787 EXTENSION: AVX512EVEX 37788 ISA_SET: AVX512F_512 37789 EXCEPTIONS: AVX512-E4 37790 REAL_OPCODE: Y 37791 ATTRIBUTES: MASKOP_EVEX 37792 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37793 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 37794 IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 37795 } 37796 37797 { 37798 ICLASS: VPMINSD 37799 CPL: 3 37800 CATEGORY: AVX512 37801 EXTENSION: AVX512EVEX 37802 ISA_SET: AVX512F_512 37803 EXCEPTIONS: AVX512-E4 37804 REAL_OPCODE: Y 37805 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37806 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37807 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR 37808 IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 37809 } 37810 37811 37812 # EMITTING VPMINSQ (VPMINSQ-512-1) 37813 { 37814 ICLASS: VPMINSQ 37815 CPL: 3 37816 CATEGORY: AVX512 37817 EXTENSION: AVX512EVEX 37818 ISA_SET: AVX512F_512 37819 EXCEPTIONS: AVX512-E4 37820 REAL_OPCODE: Y 37821 ATTRIBUTES: MASKOP_EVEX 37822 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37823 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 37824 IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 37825 } 37826 37827 { 37828 ICLASS: VPMINSQ 37829 CPL: 3 37830 CATEGORY: AVX512 37831 EXTENSION: AVX512EVEX 37832 ISA_SET: AVX512F_512 37833 EXCEPTIONS: AVX512-E4 37834 REAL_OPCODE: Y 37835 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37836 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37837 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR 37838 IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 37839 } 37840 37841 37842 # EMITTING VPMINUD (VPMINUD-512-1) 37843 { 37844 ICLASS: VPMINUD 37845 CPL: 3 37846 CATEGORY: AVX512 37847 EXTENSION: AVX512EVEX 37848 ISA_SET: AVX512F_512 37849 EXCEPTIONS: AVX512-E4 37850 REAL_OPCODE: Y 37851 ATTRIBUTES: MASKOP_EVEX 37852 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37853 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 37854 IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 37855 } 37856 37857 { 37858 ICLASS: VPMINUD 37859 CPL: 3 37860 CATEGORY: AVX512 37861 EXTENSION: AVX512EVEX 37862 ISA_SET: AVX512F_512 37863 EXCEPTIONS: AVX512-E4 37864 REAL_OPCODE: Y 37865 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37866 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 37867 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 37868 IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 37869 } 37870 37871 37872 # EMITTING VPMINUQ (VPMINUQ-512-1) 37873 { 37874 ICLASS: VPMINUQ 37875 CPL: 3 37876 CATEGORY: AVX512 37877 EXTENSION: AVX512EVEX 37878 ISA_SET: AVX512F_512 37879 EXCEPTIONS: AVX512-E4 37880 REAL_OPCODE: Y 37881 ATTRIBUTES: MASKOP_EVEX 37882 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37883 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 37884 IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 37885 } 37886 37887 { 37888 ICLASS: VPMINUQ 37889 CPL: 3 37890 CATEGORY: AVX512 37891 EXTENSION: AVX512EVEX 37892 ISA_SET: AVX512F_512 37893 EXCEPTIONS: AVX512-E4 37894 REAL_OPCODE: Y 37895 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37896 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 37897 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 37898 IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 37899 } 37900 37901 37902 # EMITTING VPMOVDB (VPMOVDB-512-1) 37903 { 37904 ICLASS: VPMOVDB 37905 CPL: 3 37906 CATEGORY: DATAXFER 37907 EXTENSION: AVX512EVEX 37908 ISA_SET: AVX512F_512 37909 EXCEPTIONS: AVX512-E6NF 37910 REAL_OPCODE: Y 37911 ATTRIBUTES: MASKOP_EVEX 37912 PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 37913 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 37914 IFORM: VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 37915 } 37916 37917 37918 # EMITTING VPMOVDB (VPMOVDB-512-2) 37919 { 37920 ICLASS: VPMOVDB 37921 CPL: 3 37922 CATEGORY: DATAXFER 37923 EXTENSION: AVX512EVEX 37924 ISA_SET: AVX512F_512 37925 EXCEPTIONS: AVX512-E6NF 37926 REAL_OPCODE: Y 37927 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 37928 PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 37929 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 37930 IFORM: VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 37931 } 37932 37933 37934 # EMITTING VPMOVDW (VPMOVDW-512-1) 37935 { 37936 ICLASS: VPMOVDW 37937 CPL: 3 37938 CATEGORY: DATAXFER 37939 EXTENSION: AVX512EVEX 37940 ISA_SET: AVX512F_512 37941 EXCEPTIONS: AVX512-E6NF 37942 REAL_OPCODE: Y 37943 ATTRIBUTES: MASKOP_EVEX 37944 PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 37945 OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 37946 IFORM: VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 37947 } 37948 37949 37950 # EMITTING VPMOVDW (VPMOVDW-512-2) 37951 { 37952 ICLASS: VPMOVDW 37953 CPL: 3 37954 CATEGORY: DATAXFER 37955 EXTENSION: AVX512EVEX 37956 ISA_SET: AVX512F_512 37957 EXCEPTIONS: AVX512-E6NF 37958 REAL_OPCODE: Y 37959 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 37960 PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 37961 OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 37962 IFORM: VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 37963 } 37964 37965 37966 # EMITTING VPMOVQB (VPMOVQB-512-1) 37967 { 37968 ICLASS: VPMOVQB 37969 CPL: 3 37970 CATEGORY: DATAXFER 37971 EXTENSION: AVX512EVEX 37972 ISA_SET: AVX512F_512 37973 EXCEPTIONS: AVX512-E6NF 37974 REAL_OPCODE: Y 37975 ATTRIBUTES: MASKOP_EVEX 37976 PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 37977 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 37978 IFORM: VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 37979 } 37980 37981 37982 # EMITTING VPMOVQB (VPMOVQB-512-2) 37983 { 37984 ICLASS: VPMOVQB 37985 CPL: 3 37986 CATEGORY: DATAXFER 37987 EXTENSION: AVX512EVEX 37988 ISA_SET: AVX512F_512 37989 EXCEPTIONS: AVX512-E6NF 37990 REAL_OPCODE: Y 37991 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 37992 PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 37993 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 37994 IFORM: VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 37995 } 37996 37997 37998 # EMITTING VPMOVQD (VPMOVQD-512-1) 37999 { 38000 ICLASS: VPMOVQD 38001 CPL: 3 38002 CATEGORY: DATAXFER 38003 EXTENSION: AVX512EVEX 38004 ISA_SET: AVX512F_512 38005 EXCEPTIONS: AVX512-E6NF 38006 REAL_OPCODE: Y 38007 ATTRIBUTES: MASKOP_EVEX 38008 PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38009 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 38010 IFORM: VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 38011 } 38012 38013 38014 # EMITTING VPMOVQD (VPMOVQD-512-2) 38015 { 38016 ICLASS: VPMOVQD 38017 CPL: 3 38018 CATEGORY: DATAXFER 38019 EXTENSION: AVX512EVEX 38020 ISA_SET: AVX512F_512 38021 EXCEPTIONS: AVX512-E6NF 38022 REAL_OPCODE: Y 38023 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 38024 PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 38025 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 38026 IFORM: VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 38027 } 38028 38029 38030 # EMITTING VPMOVQW (VPMOVQW-512-1) 38031 { 38032 ICLASS: VPMOVQW 38033 CPL: 3 38034 CATEGORY: DATAXFER 38035 EXTENSION: AVX512EVEX 38036 ISA_SET: AVX512F_512 38037 EXCEPTIONS: AVX512-E6NF 38038 REAL_OPCODE: Y 38039 ATTRIBUTES: MASKOP_EVEX 38040 PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38041 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 38042 IFORM: VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 38043 } 38044 38045 38046 # EMITTING VPMOVQW (VPMOVQW-512-2) 38047 { 38048 ICLASS: VPMOVQW 38049 CPL: 3 38050 CATEGORY: DATAXFER 38051 EXTENSION: AVX512EVEX 38052 ISA_SET: AVX512F_512 38053 EXCEPTIONS: AVX512-E6NF 38054 REAL_OPCODE: Y 38055 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 38056 PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 38057 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 38058 IFORM: VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 38059 } 38060 38061 38062 # EMITTING VPMOVSDB (VPMOVSDB-512-1) 38063 { 38064 ICLASS: VPMOVSDB 38065 CPL: 3 38066 CATEGORY: DATAXFER 38067 EXTENSION: AVX512EVEX 38068 ISA_SET: AVX512F_512 38069 EXCEPTIONS: AVX512-E6NF 38070 REAL_OPCODE: Y 38071 ATTRIBUTES: MASKOP_EVEX 38072 PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38073 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 38074 IFORM: VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 38075 } 38076 38077 38078 # EMITTING VPMOVSDB (VPMOVSDB-512-2) 38079 { 38080 ICLASS: VPMOVSDB 38081 CPL: 3 38082 CATEGORY: DATAXFER 38083 EXTENSION: AVX512EVEX 38084 ISA_SET: AVX512F_512 38085 EXCEPTIONS: AVX512-E6NF 38086 REAL_OPCODE: Y 38087 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 38088 PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 38089 OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 38090 IFORM: VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 38091 } 38092 38093 38094 # EMITTING VPMOVSDW (VPMOVSDW-512-1) 38095 { 38096 ICLASS: VPMOVSDW 38097 CPL: 3 38098 CATEGORY: DATAXFER 38099 EXTENSION: AVX512EVEX 38100 ISA_SET: AVX512F_512 38101 EXCEPTIONS: AVX512-E6NF 38102 REAL_OPCODE: Y 38103 ATTRIBUTES: MASKOP_EVEX 38104 PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38105 OPERANDS: REG0=YMM_B3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 38106 IFORM: VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 38107 } 38108 38109 38110 # EMITTING VPMOVSDW (VPMOVSDW-512-2) 38111 { 38112 ICLASS: VPMOVSDW 38113 CPL: 3 38114 CATEGORY: DATAXFER 38115 EXTENSION: AVX512EVEX 38116 ISA_SET: AVX512F_512 38117 EXCEPTIONS: AVX512-E6NF 38118 REAL_OPCODE: Y 38119 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 38120 PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 38121 OPERANDS: MEM0:w:qq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 38122 IFORM: VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 38123 } 38124 38125 38126 # EMITTING VPMOVSQB (VPMOVSQB-512-1) 38127 { 38128 ICLASS: VPMOVSQB 38129 CPL: 3 38130 CATEGORY: DATAXFER 38131 EXTENSION: AVX512EVEX 38132 ISA_SET: AVX512F_512 38133 EXCEPTIONS: AVX512-E6NF 38134 REAL_OPCODE: Y 38135 ATTRIBUTES: MASKOP_EVEX 38136 PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38137 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 38138 IFORM: VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 38139 } 38140 38141 38142 # EMITTING VPMOVSQB (VPMOVSQB-512-2) 38143 { 38144 ICLASS: VPMOVSQB 38145 CPL: 3 38146 CATEGORY: DATAXFER 38147 EXTENSION: AVX512EVEX 38148 ISA_SET: AVX512F_512 38149 EXCEPTIONS: AVX512-E6NF 38150 REAL_OPCODE: Y 38151 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 38152 PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 38153 OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 38154 IFORM: VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 38155 } 38156 38157 38158 # EMITTING VPMOVSQD (VPMOVSQD-512-1) 38159 { 38160 ICLASS: VPMOVSQD 38161 CPL: 3 38162 CATEGORY: DATAXFER 38163 EXTENSION: AVX512EVEX 38164 ISA_SET: AVX512F_512 38165 EXCEPTIONS: AVX512-E6NF 38166 REAL_OPCODE: Y 38167 ATTRIBUTES: MASKOP_EVEX 38168 PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38169 OPERANDS: REG0=YMM_B3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 38170 IFORM: VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 38171 } 38172 38173 38174 # EMITTING VPMOVSQD (VPMOVSQD-512-2) 38175 { 38176 ICLASS: VPMOVSQD 38177 CPL: 3 38178 CATEGORY: DATAXFER 38179 EXTENSION: AVX512EVEX 38180 ISA_SET: AVX512F_512 38181 EXCEPTIONS: AVX512-E6NF 38182 REAL_OPCODE: Y 38183 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 38184 PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 38185 OPERANDS: MEM0:w:qq:i32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 38186 IFORM: VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 38187 } 38188 38189 38190 # EMITTING VPMOVSQW (VPMOVSQW-512-1) 38191 { 38192 ICLASS: VPMOVSQW 38193 CPL: 3 38194 CATEGORY: DATAXFER 38195 EXTENSION: AVX512EVEX 38196 ISA_SET: AVX512F_512 38197 EXCEPTIONS: AVX512-E6NF 38198 REAL_OPCODE: Y 38199 ATTRIBUTES: MASKOP_EVEX 38200 PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38201 OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 38202 IFORM: VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 38203 } 38204 38205 38206 # EMITTING VPMOVSQW (VPMOVSQW-512-2) 38207 { 38208 ICLASS: VPMOVSQW 38209 CPL: 3 38210 CATEGORY: DATAXFER 38211 EXTENSION: AVX512EVEX 38212 ISA_SET: AVX512F_512 38213 EXCEPTIONS: AVX512-E6NF 38214 REAL_OPCODE: Y 38215 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 38216 PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 38217 OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 38218 IFORM: VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 38219 } 38220 38221 38222 # EMITTING VPMOVSXBD (VPMOVSXBD-512-1) 38223 { 38224 ICLASS: VPMOVSXBD 38225 CPL: 3 38226 CATEGORY: DATAXFER 38227 EXTENSION: AVX512EVEX 38228 ISA_SET: AVX512F_512 38229 EXCEPTIONS: AVX512-E5 38230 REAL_OPCODE: Y 38231 ATTRIBUTES: MASKOP_EVEX 38232 PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 38233 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 38234 IFORM: VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 38235 } 38236 38237 { 38238 ICLASS: VPMOVSXBD 38239 CPL: 3 38240 CATEGORY: DATAXFER 38241 EXTENSION: AVX512EVEX 38242 ISA_SET: AVX512F_512 38243 EXCEPTIONS: AVX512-E5 38244 REAL_OPCODE: Y 38245 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 38246 PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 38247 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 38248 IFORM: VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 38249 } 38250 38251 38252 # EMITTING VPMOVSXBQ (VPMOVSXBQ-512-1) 38253 { 38254 ICLASS: VPMOVSXBQ 38255 CPL: 3 38256 CATEGORY: DATAXFER 38257 EXTENSION: AVX512EVEX 38258 ISA_SET: AVX512F_512 38259 EXCEPTIONS: AVX512-E5 38260 REAL_OPCODE: Y 38261 ATTRIBUTES: MASKOP_EVEX 38262 PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 38263 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 38264 IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 38265 } 38266 38267 { 38268 ICLASS: VPMOVSXBQ 38269 CPL: 3 38270 CATEGORY: DATAXFER 38271 EXTENSION: AVX512EVEX 38272 ISA_SET: AVX512F_512 38273 EXCEPTIONS: AVX512-E5 38274 REAL_OPCODE: Y 38275 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 38276 PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 38277 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 38278 IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 38279 } 38280 38281 38282 # EMITTING VPMOVSXDQ (VPMOVSXDQ-512-1) 38283 { 38284 ICLASS: VPMOVSXDQ 38285 CPL: 3 38286 CATEGORY: DATAXFER 38287 EXTENSION: AVX512EVEX 38288 ISA_SET: AVX512F_512 38289 EXCEPTIONS: AVX512-E5 38290 REAL_OPCODE: Y 38291 ATTRIBUTES: MASKOP_EVEX 38292 PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38293 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 38294 IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 38295 } 38296 38297 { 38298 ICLASS: VPMOVSXDQ 38299 CPL: 3 38300 CATEGORY: DATAXFER 38301 EXTENSION: AVX512EVEX 38302 ISA_SET: AVX512F_512 38303 EXCEPTIONS: AVX512-E5 38304 REAL_OPCODE: Y 38305 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 38306 PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 38307 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 38308 IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 38309 } 38310 38311 38312 # EMITTING VPMOVSXWD (VPMOVSXWD-512-1) 38313 { 38314 ICLASS: VPMOVSXWD 38315 CPL: 3 38316 CATEGORY: DATAXFER 38317 EXTENSION: AVX512EVEX 38318 ISA_SET: AVX512F_512 38319 EXCEPTIONS: AVX512-E5 38320 REAL_OPCODE: Y 38321 ATTRIBUTES: MASKOP_EVEX 38322 PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 38323 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 38324 IFORM: VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 38325 } 38326 38327 { 38328 ICLASS: VPMOVSXWD 38329 CPL: 3 38330 CATEGORY: DATAXFER 38331 EXTENSION: AVX512EVEX 38332 ISA_SET: AVX512F_512 38333 EXCEPTIONS: AVX512-E5 38334 REAL_OPCODE: Y 38335 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 38336 PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 38337 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 38338 IFORM: VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 38339 } 38340 38341 38342 # EMITTING VPMOVSXWQ (VPMOVSXWQ-512-1) 38343 { 38344 ICLASS: VPMOVSXWQ 38345 CPL: 3 38346 CATEGORY: DATAXFER 38347 EXTENSION: AVX512EVEX 38348 ISA_SET: AVX512F_512 38349 EXCEPTIONS: AVX512-E5 38350 REAL_OPCODE: Y 38351 ATTRIBUTES: MASKOP_EVEX 38352 PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 38353 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 38354 IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 38355 } 38356 38357 { 38358 ICLASS: VPMOVSXWQ 38359 CPL: 3 38360 CATEGORY: DATAXFER 38361 EXTENSION: AVX512EVEX 38362 ISA_SET: AVX512F_512 38363 EXCEPTIONS: AVX512-E5 38364 REAL_OPCODE: Y 38365 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 38366 PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 38367 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 38368 IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 38369 } 38370 38371 38372 # EMITTING VPMOVUSDB (VPMOVUSDB-512-1) 38373 { 38374 ICLASS: VPMOVUSDB 38375 CPL: 3 38376 CATEGORY: DATAXFER 38377 EXTENSION: AVX512EVEX 38378 ISA_SET: AVX512F_512 38379 EXCEPTIONS: AVX512-E6NF 38380 REAL_OPCODE: Y 38381 ATTRIBUTES: MASKOP_EVEX 38382 PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38383 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 38384 IFORM: VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 38385 } 38386 38387 38388 # EMITTING VPMOVUSDB (VPMOVUSDB-512-2) 38389 { 38390 ICLASS: VPMOVUSDB 38391 CPL: 3 38392 CATEGORY: DATAXFER 38393 EXTENSION: AVX512EVEX 38394 ISA_SET: AVX512F_512 38395 EXCEPTIONS: AVX512-E6NF 38396 REAL_OPCODE: Y 38397 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 38398 PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 38399 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 38400 IFORM: VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 38401 } 38402 38403 38404 # EMITTING VPMOVUSDW (VPMOVUSDW-512-1) 38405 { 38406 ICLASS: VPMOVUSDW 38407 CPL: 3 38408 CATEGORY: DATAXFER 38409 EXTENSION: AVX512EVEX 38410 ISA_SET: AVX512F_512 38411 EXCEPTIONS: AVX512-E6NF 38412 REAL_OPCODE: Y 38413 ATTRIBUTES: MASKOP_EVEX 38414 PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38415 OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 38416 IFORM: VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 38417 } 38418 38419 38420 # EMITTING VPMOVUSDW (VPMOVUSDW-512-2) 38421 { 38422 ICLASS: VPMOVUSDW 38423 CPL: 3 38424 CATEGORY: DATAXFER 38425 EXTENSION: AVX512EVEX 38426 ISA_SET: AVX512F_512 38427 EXCEPTIONS: AVX512-E6NF 38428 REAL_OPCODE: Y 38429 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 38430 PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 38431 OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 38432 IFORM: VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 38433 } 38434 38435 38436 # EMITTING VPMOVUSQB (VPMOVUSQB-512-1) 38437 { 38438 ICLASS: VPMOVUSQB 38439 CPL: 3 38440 CATEGORY: DATAXFER 38441 EXTENSION: AVX512EVEX 38442 ISA_SET: AVX512F_512 38443 EXCEPTIONS: AVX512-E6NF 38444 REAL_OPCODE: Y 38445 ATTRIBUTES: MASKOP_EVEX 38446 PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38447 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 38448 IFORM: VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 38449 } 38450 38451 38452 # EMITTING VPMOVUSQB (VPMOVUSQB-512-2) 38453 { 38454 ICLASS: VPMOVUSQB 38455 CPL: 3 38456 CATEGORY: DATAXFER 38457 EXTENSION: AVX512EVEX 38458 ISA_SET: AVX512F_512 38459 EXCEPTIONS: AVX512-E6NF 38460 REAL_OPCODE: Y 38461 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 38462 PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 38463 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 38464 IFORM: VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 38465 } 38466 38467 38468 # EMITTING VPMOVUSQD (VPMOVUSQD-512-1) 38469 { 38470 ICLASS: VPMOVUSQD 38471 CPL: 3 38472 CATEGORY: DATAXFER 38473 EXTENSION: AVX512EVEX 38474 ISA_SET: AVX512F_512 38475 EXCEPTIONS: AVX512-E6NF 38476 REAL_OPCODE: Y 38477 ATTRIBUTES: MASKOP_EVEX 38478 PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38479 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 38480 IFORM: VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 38481 } 38482 38483 38484 # EMITTING VPMOVUSQD (VPMOVUSQD-512-2) 38485 { 38486 ICLASS: VPMOVUSQD 38487 CPL: 3 38488 CATEGORY: DATAXFER 38489 EXTENSION: AVX512EVEX 38490 ISA_SET: AVX512F_512 38491 EXCEPTIONS: AVX512-E6NF 38492 REAL_OPCODE: Y 38493 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 38494 PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 38495 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 38496 IFORM: VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 38497 } 38498 38499 38500 # EMITTING VPMOVUSQW (VPMOVUSQW-512-1) 38501 { 38502 ICLASS: VPMOVUSQW 38503 CPL: 3 38504 CATEGORY: DATAXFER 38505 EXTENSION: AVX512EVEX 38506 ISA_SET: AVX512F_512 38507 EXCEPTIONS: AVX512-E6NF 38508 REAL_OPCODE: Y 38509 ATTRIBUTES: MASKOP_EVEX 38510 PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38511 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 38512 IFORM: VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 38513 } 38514 38515 38516 # EMITTING VPMOVUSQW (VPMOVUSQW-512-2) 38517 { 38518 ICLASS: VPMOVUSQW 38519 CPL: 3 38520 CATEGORY: DATAXFER 38521 EXTENSION: AVX512EVEX 38522 ISA_SET: AVX512F_512 38523 EXCEPTIONS: AVX512-E6NF 38524 REAL_OPCODE: Y 38525 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 38526 PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 38527 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 38528 IFORM: VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 38529 } 38530 38531 38532 # EMITTING VPMOVZXBD (VPMOVZXBD-512-1) 38533 { 38534 ICLASS: VPMOVZXBD 38535 CPL: 3 38536 CATEGORY: DATAXFER 38537 EXTENSION: AVX512EVEX 38538 ISA_SET: AVX512F_512 38539 EXCEPTIONS: AVX512-E5 38540 REAL_OPCODE: Y 38541 ATTRIBUTES: MASKOP_EVEX 38542 PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 38543 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 38544 IFORM: VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 38545 } 38546 38547 { 38548 ICLASS: VPMOVZXBD 38549 CPL: 3 38550 CATEGORY: DATAXFER 38551 EXTENSION: AVX512EVEX 38552 ISA_SET: AVX512F_512 38553 EXCEPTIONS: AVX512-E5 38554 REAL_OPCODE: Y 38555 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 38556 PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 38557 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 38558 IFORM: VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 38559 } 38560 38561 38562 # EMITTING VPMOVZXBQ (VPMOVZXBQ-512-1) 38563 { 38564 ICLASS: VPMOVZXBQ 38565 CPL: 3 38566 CATEGORY: DATAXFER 38567 EXTENSION: AVX512EVEX 38568 ISA_SET: AVX512F_512 38569 EXCEPTIONS: AVX512-E5 38570 REAL_OPCODE: Y 38571 ATTRIBUTES: MASKOP_EVEX 38572 PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 38573 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 38574 IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 38575 } 38576 38577 { 38578 ICLASS: VPMOVZXBQ 38579 CPL: 3 38580 CATEGORY: DATAXFER 38581 EXTENSION: AVX512EVEX 38582 ISA_SET: AVX512F_512 38583 EXCEPTIONS: AVX512-E5 38584 REAL_OPCODE: Y 38585 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 38586 PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 38587 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 38588 IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 38589 } 38590 38591 38592 # EMITTING VPMOVZXDQ (VPMOVZXDQ-512-1) 38593 { 38594 ICLASS: VPMOVZXDQ 38595 CPL: 3 38596 CATEGORY: DATAXFER 38597 EXTENSION: AVX512EVEX 38598 ISA_SET: AVX512F_512 38599 EXCEPTIONS: AVX512-E5 38600 REAL_OPCODE: Y 38601 ATTRIBUTES: MASKOP_EVEX 38602 PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 38603 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 38604 IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 38605 } 38606 38607 { 38608 ICLASS: VPMOVZXDQ 38609 CPL: 3 38610 CATEGORY: DATAXFER 38611 EXTENSION: AVX512EVEX 38612 ISA_SET: AVX512F_512 38613 EXCEPTIONS: AVX512-E5 38614 REAL_OPCODE: Y 38615 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 38616 PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 38617 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 38618 IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 38619 } 38620 38621 38622 # EMITTING VPMOVZXWD (VPMOVZXWD-512-1) 38623 { 38624 ICLASS: VPMOVZXWD 38625 CPL: 3 38626 CATEGORY: DATAXFER 38627 EXTENSION: AVX512EVEX 38628 ISA_SET: AVX512F_512 38629 EXCEPTIONS: AVX512-E5 38630 REAL_OPCODE: Y 38631 ATTRIBUTES: MASKOP_EVEX 38632 PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 38633 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 38634 IFORM: VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 38635 } 38636 38637 { 38638 ICLASS: VPMOVZXWD 38639 CPL: 3 38640 CATEGORY: DATAXFER 38641 EXTENSION: AVX512EVEX 38642 ISA_SET: AVX512F_512 38643 EXCEPTIONS: AVX512-E5 38644 REAL_OPCODE: Y 38645 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 38646 PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 38647 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 38648 IFORM: VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 38649 } 38650 38651 38652 # EMITTING VPMOVZXWQ (VPMOVZXWQ-512-1) 38653 { 38654 ICLASS: VPMOVZXWQ 38655 CPL: 3 38656 CATEGORY: DATAXFER 38657 EXTENSION: AVX512EVEX 38658 ISA_SET: AVX512F_512 38659 EXCEPTIONS: AVX512-E5 38660 REAL_OPCODE: Y 38661 ATTRIBUTES: MASKOP_EVEX 38662 PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 38663 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 38664 IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 38665 } 38666 38667 { 38668 ICLASS: VPMOVZXWQ 38669 CPL: 3 38670 CATEGORY: DATAXFER 38671 EXTENSION: AVX512EVEX 38672 ISA_SET: AVX512F_512 38673 EXCEPTIONS: AVX512-E5 38674 REAL_OPCODE: Y 38675 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 38676 PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 38677 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 38678 IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 38679 } 38680 38681 38682 # EMITTING VPMULDQ (VPMULDQ-512-1) 38683 { 38684 ICLASS: VPMULDQ 38685 CPL: 3 38686 CATEGORY: AVX512 38687 EXTENSION: AVX512EVEX 38688 ISA_SET: AVX512F_512 38689 EXCEPTIONS: AVX512-E4 38690 REAL_OPCODE: Y 38691 ATTRIBUTES: MASKOP_EVEX 38692 PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 38693 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 38694 IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 38695 } 38696 38697 { 38698 ICLASS: VPMULDQ 38699 CPL: 3 38700 CATEGORY: AVX512 38701 EXTENSION: AVX512EVEX 38702 ISA_SET: AVX512F_512 38703 EXCEPTIONS: AVX512-E4 38704 REAL_OPCODE: Y 38705 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38706 PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 38707 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR 38708 IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 38709 } 38710 38711 38712 # EMITTING VPMULLD (VPMULLD-512-1) 38713 { 38714 ICLASS: VPMULLD 38715 CPL: 3 38716 CATEGORY: AVX512 38717 EXTENSION: AVX512EVEX 38718 ISA_SET: AVX512F_512 38719 EXCEPTIONS: AVX512-E4 38720 REAL_OPCODE: Y 38721 ATTRIBUTES: MASKOP_EVEX 38722 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 38723 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 38724 IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 38725 } 38726 38727 { 38728 ICLASS: VPMULLD 38729 CPL: 3 38730 CATEGORY: AVX512 38731 EXTENSION: AVX512EVEX 38732 ISA_SET: AVX512F_512 38733 EXCEPTIONS: AVX512-E4 38734 REAL_OPCODE: Y 38735 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38736 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 38737 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 38738 IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 38739 } 38740 38741 38742 # EMITTING VPMULUDQ (VPMULUDQ-512-1) 38743 { 38744 ICLASS: VPMULUDQ 38745 CPL: 3 38746 CATEGORY: AVX512 38747 EXTENSION: AVX512EVEX 38748 ISA_SET: AVX512F_512 38749 EXCEPTIONS: AVX512-E4 38750 REAL_OPCODE: Y 38751 ATTRIBUTES: MASKOP_EVEX 38752 PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 38753 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 38754 IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 38755 } 38756 38757 { 38758 ICLASS: VPMULUDQ 38759 CPL: 3 38760 CATEGORY: AVX512 38761 EXTENSION: AVX512EVEX 38762 ISA_SET: AVX512F_512 38763 EXCEPTIONS: AVX512-E4 38764 REAL_OPCODE: Y 38765 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38766 PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 38767 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 38768 IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 38769 } 38770 38771 38772 # EMITTING VPORD (VPORD-512-1) 38773 { 38774 ICLASS: VPORD 38775 CPL: 3 38776 CATEGORY: LOGICAL 38777 EXTENSION: AVX512EVEX 38778 ISA_SET: AVX512F_512 38779 EXCEPTIONS: AVX512-E4 38780 REAL_OPCODE: Y 38781 ATTRIBUTES: MASKOP_EVEX 38782 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 38783 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 38784 IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 38785 } 38786 38787 { 38788 ICLASS: VPORD 38789 CPL: 3 38790 CATEGORY: LOGICAL 38791 EXTENSION: AVX512EVEX 38792 ISA_SET: AVX512F_512 38793 EXCEPTIONS: AVX512-E4 38794 REAL_OPCODE: Y 38795 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38796 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 38797 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 38798 IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 38799 } 38800 38801 38802 # EMITTING VPORQ (VPORQ-512-1) 38803 { 38804 ICLASS: VPORQ 38805 CPL: 3 38806 CATEGORY: LOGICAL 38807 EXTENSION: AVX512EVEX 38808 ISA_SET: AVX512F_512 38809 EXCEPTIONS: AVX512-E4 38810 REAL_OPCODE: Y 38811 ATTRIBUTES: MASKOP_EVEX 38812 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 38813 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 38814 IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 38815 } 38816 38817 { 38818 ICLASS: VPORQ 38819 CPL: 3 38820 CATEGORY: LOGICAL 38821 EXTENSION: AVX512EVEX 38822 ISA_SET: AVX512F_512 38823 EXCEPTIONS: AVX512-E4 38824 REAL_OPCODE: Y 38825 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38826 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 38827 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 38828 IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 38829 } 38830 38831 38832 # EMITTING VPROLD (VPROLD-512-1) 38833 { 38834 ICLASS: VPROLD 38835 CPL: 3 38836 CATEGORY: AVX512 38837 EXTENSION: AVX512EVEX 38838 ISA_SET: AVX512F_512 38839 EXCEPTIONS: AVX512-E4 38840 REAL_OPCODE: Y 38841 ATTRIBUTES: MASKOP_EVEX 38842 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W0 UIMM8() 38843 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 38844 IFORM: VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 38845 } 38846 38847 { 38848 ICLASS: VPROLD 38849 CPL: 3 38850 CATEGORY: AVX512 38851 EXTENSION: AVX512EVEX 38852 ISA_SET: AVX512F_512 38853 EXCEPTIONS: AVX512-E4 38854 REAL_OPCODE: Y 38855 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38856 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 38857 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 38858 IFORM: VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 38859 } 38860 38861 38862 # EMITTING VPROLQ (VPROLQ-512-1) 38863 { 38864 ICLASS: VPROLQ 38865 CPL: 3 38866 CATEGORY: AVX512 38867 EXTENSION: AVX512EVEX 38868 ISA_SET: AVX512F_512 38869 EXCEPTIONS: AVX512-E4 38870 REAL_OPCODE: Y 38871 ATTRIBUTES: MASKOP_EVEX 38872 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W1 UIMM8() 38873 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 38874 IFORM: VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 38875 } 38876 38877 { 38878 ICLASS: VPROLQ 38879 CPL: 3 38880 CATEGORY: AVX512 38881 EXTENSION: AVX512EVEX 38882 ISA_SET: AVX512F_512 38883 EXCEPTIONS: AVX512-E4 38884 REAL_OPCODE: Y 38885 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38886 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 38887 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 38888 IFORM: VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 38889 } 38890 38891 38892 # EMITTING VPROLVD (VPROLVD-512-1) 38893 { 38894 ICLASS: VPROLVD 38895 CPL: 3 38896 CATEGORY: AVX512 38897 EXTENSION: AVX512EVEX 38898 ISA_SET: AVX512F_512 38899 EXCEPTIONS: AVX512-E4 38900 REAL_OPCODE: Y 38901 ATTRIBUTES: MASKOP_EVEX 38902 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 38903 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 38904 IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 38905 } 38906 38907 { 38908 ICLASS: VPROLVD 38909 CPL: 3 38910 CATEGORY: AVX512 38911 EXTENSION: AVX512EVEX 38912 ISA_SET: AVX512F_512 38913 EXCEPTIONS: AVX512-E4 38914 REAL_OPCODE: Y 38915 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38916 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 38917 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 38918 IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 38919 } 38920 38921 38922 # EMITTING VPROLVQ (VPROLVQ-512-1) 38923 { 38924 ICLASS: VPROLVQ 38925 CPL: 3 38926 CATEGORY: AVX512 38927 EXTENSION: AVX512EVEX 38928 ISA_SET: AVX512F_512 38929 EXCEPTIONS: AVX512-E4 38930 REAL_OPCODE: Y 38931 ATTRIBUTES: MASKOP_EVEX 38932 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 38933 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 38934 IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 38935 } 38936 38937 { 38938 ICLASS: VPROLVQ 38939 CPL: 3 38940 CATEGORY: AVX512 38941 EXTENSION: AVX512EVEX 38942 ISA_SET: AVX512F_512 38943 EXCEPTIONS: AVX512-E4 38944 REAL_OPCODE: Y 38945 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38946 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 38947 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 38948 IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 38949 } 38950 38951 38952 # EMITTING VPRORD (VPRORD-512-1) 38953 { 38954 ICLASS: VPRORD 38955 CPL: 3 38956 CATEGORY: AVX512 38957 EXTENSION: AVX512EVEX 38958 ISA_SET: AVX512F_512 38959 EXCEPTIONS: AVX512-E4 38960 REAL_OPCODE: Y 38961 ATTRIBUTES: MASKOP_EVEX 38962 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W0 UIMM8() 38963 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 38964 IFORM: VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 38965 } 38966 38967 { 38968 ICLASS: VPRORD 38969 CPL: 3 38970 CATEGORY: AVX512 38971 EXTENSION: AVX512EVEX 38972 ISA_SET: AVX512F_512 38973 EXCEPTIONS: AVX512-E4 38974 REAL_OPCODE: Y 38975 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38976 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 38977 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 38978 IFORM: VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 38979 } 38980 38981 38982 # EMITTING VPRORQ (VPRORQ-512-1) 38983 { 38984 ICLASS: VPRORQ 38985 CPL: 3 38986 CATEGORY: AVX512 38987 EXTENSION: AVX512EVEX 38988 ISA_SET: AVX512F_512 38989 EXCEPTIONS: AVX512-E4 38990 REAL_OPCODE: Y 38991 ATTRIBUTES: MASKOP_EVEX 38992 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W1 UIMM8() 38993 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 38994 IFORM: VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 38995 } 38996 38997 { 38998 ICLASS: VPRORQ 38999 CPL: 3 39000 CATEGORY: AVX512 39001 EXTENSION: AVX512EVEX 39002 ISA_SET: AVX512F_512 39003 EXCEPTIONS: AVX512-E4 39004 REAL_OPCODE: Y 39005 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39006 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 39007 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 39008 IFORM: VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 39009 } 39010 39011 39012 # EMITTING VPRORVD (VPRORVD-512-1) 39013 { 39014 ICLASS: VPRORVD 39015 CPL: 3 39016 CATEGORY: AVX512 39017 EXTENSION: AVX512EVEX 39018 ISA_SET: AVX512F_512 39019 EXCEPTIONS: AVX512-E4 39020 REAL_OPCODE: Y 39021 ATTRIBUTES: MASKOP_EVEX 39022 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 39023 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 39024 IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 39025 } 39026 39027 { 39028 ICLASS: VPRORVD 39029 CPL: 3 39030 CATEGORY: AVX512 39031 EXTENSION: AVX512EVEX 39032 ISA_SET: AVX512F_512 39033 EXCEPTIONS: AVX512-E4 39034 REAL_OPCODE: Y 39035 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39036 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 39037 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 39038 IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 39039 } 39040 39041 39042 # EMITTING VPRORVQ (VPRORVQ-512-1) 39043 { 39044 ICLASS: VPRORVQ 39045 CPL: 3 39046 CATEGORY: AVX512 39047 EXTENSION: AVX512EVEX 39048 ISA_SET: AVX512F_512 39049 EXCEPTIONS: AVX512-E4 39050 REAL_OPCODE: Y 39051 ATTRIBUTES: MASKOP_EVEX 39052 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 39053 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 39054 IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 39055 } 39056 39057 { 39058 ICLASS: VPRORVQ 39059 CPL: 3 39060 CATEGORY: AVX512 39061 EXTENSION: AVX512EVEX 39062 ISA_SET: AVX512F_512 39063 EXCEPTIONS: AVX512-E4 39064 REAL_OPCODE: Y 39065 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39066 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 39067 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 39068 IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 39069 } 39070 39071 39072 # EMITTING VPSCATTERDD (VPSCATTERDD-512-1) 39073 { 39074 ICLASS: VPSCATTERDD 39075 CPL: 3 39076 CATEGORY: SCATTER 39077 EXTENSION: AVX512EVEX 39078 ISA_SET: AVX512F_512 39079 EXCEPTIONS: AVX512-E12 39080 REAL_OPCODE: Y 39081 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 39082 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 39083 OPERANDS: MEM0:w:zd:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32 39084 IFORM: VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 39085 } 39086 39087 39088 # EMITTING VPSCATTERDQ (VPSCATTERDQ-512-1) 39089 { 39090 ICLASS: VPSCATTERDQ 39091 CPL: 3 39092 CATEGORY: SCATTER 39093 EXTENSION: AVX512EVEX 39094 ISA_SET: AVX512F_512 39095 EXCEPTIONS: AVX512-E12 39096 REAL_OPCODE: Y 39097 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 39098 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 39099 OPERANDS: MEM0:w:zd:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 39100 IFORM: VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 39101 } 39102 39103 39104 # EMITTING VPSCATTERQD (VPSCATTERQD-512-1) 39105 { 39106 ICLASS: VPSCATTERQD 39107 CPL: 3 39108 CATEGORY: SCATTER 39109 EXTENSION: AVX512EVEX 39110 ISA_SET: AVX512F_512 39111 EXCEPTIONS: AVX512-E12 39112 REAL_OPCODE: Y 39113 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 39114 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 39115 OPERANDS: MEM0:w:qq:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 39116 IFORM: VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 39117 } 39118 39119 39120 # EMITTING VPSCATTERQQ (VPSCATTERQQ-512-1) 39121 { 39122 ICLASS: VPSCATTERQQ 39123 CPL: 3 39124 CATEGORY: SCATTER 39125 EXTENSION: AVX512EVEX 39126 ISA_SET: AVX512F_512 39127 EXCEPTIONS: AVX512-E12 39128 REAL_OPCODE: Y 39129 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 39130 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 39131 OPERANDS: MEM0:w:zd:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 39132 IFORM: VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 39133 } 39134 39135 39136 # EMITTING VPSHUFD (VPSHUFD-512-1) 39137 { 39138 ICLASS: VPSHUFD 39139 CPL: 3 39140 CATEGORY: AVX512 39141 EXTENSION: AVX512EVEX 39142 ISA_SET: AVX512F_512 39143 EXCEPTIONS: AVX512-E4NF 39144 REAL_OPCODE: Y 39145 ATTRIBUTES: MASKOP_EVEX 39146 PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 39147 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 39148 IFORM: VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 39149 } 39150 39151 { 39152 ICLASS: VPSHUFD 39153 CPL: 3 39154 CATEGORY: AVX512 39155 EXTENSION: AVX512EVEX 39156 ISA_SET: AVX512F_512 39157 EXCEPTIONS: AVX512-E4NF 39158 REAL_OPCODE: Y 39159 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39160 PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 39161 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 39162 IFORM: VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 39163 } 39164 39165 39166 # EMITTING VPSLLD (VPSLLD-512-1) 39167 { 39168 ICLASS: VPSLLD 39169 CPL: 3 39170 CATEGORY: AVX512 39171 EXTENSION: AVX512EVEX 39172 ISA_SET: AVX512F_512 39173 EXCEPTIONS: AVX512-E4NF 39174 REAL_OPCODE: Y 39175 ATTRIBUTES: MASKOP_EVEX 39176 PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 39177 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 39178 IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 39179 } 39180 39181 { 39182 ICLASS: VPSLLD 39183 CPL: 3 39184 CATEGORY: AVX512 39185 EXTENSION: AVX512EVEX 39186 ISA_SET: AVX512F_512 39187 EXCEPTIONS: AVX512-E4NF 39188 REAL_OPCODE: Y 39189 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 39190 PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() 39191 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 39192 IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 39193 } 39194 39195 39196 # EMITTING VPSLLD (VPSLLD-512-2) 39197 { 39198 ICLASS: VPSLLD 39199 CPL: 3 39200 CATEGORY: AVX512 39201 EXTENSION: AVX512EVEX 39202 ISA_SET: AVX512F_512 39203 EXCEPTIONS: AVX512-E4 39204 REAL_OPCODE: Y 39205 ATTRIBUTES: MASKOP_EVEX 39206 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W0 UIMM8() 39207 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 39208 IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 39209 } 39210 39211 { 39212 ICLASS: VPSLLD 39213 CPL: 3 39214 CATEGORY: AVX512 39215 EXTENSION: AVX512EVEX 39216 ISA_SET: AVX512F_512 39217 EXCEPTIONS: AVX512-E4 39218 REAL_OPCODE: Y 39219 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39220 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 39221 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 39222 IFORM: VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 39223 } 39224 39225 39226 # EMITTING VPSLLQ (VPSLLQ-512-1) 39227 { 39228 ICLASS: VPSLLQ 39229 CPL: 3 39230 CATEGORY: AVX512 39231 EXTENSION: AVX512EVEX 39232 ISA_SET: AVX512F_512 39233 EXCEPTIONS: AVX512-E4NF 39234 REAL_OPCODE: Y 39235 ATTRIBUTES: MASKOP_EVEX 39236 PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 39237 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 39238 IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 39239 } 39240 39241 { 39242 ICLASS: VPSLLQ 39243 CPL: 3 39244 CATEGORY: AVX512 39245 EXTENSION: AVX512EVEX 39246 ISA_SET: AVX512F_512 39247 EXCEPTIONS: AVX512-E4NF 39248 REAL_OPCODE: Y 39249 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 39250 PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() 39251 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 39252 IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 39253 } 39254 39255 39256 # EMITTING VPSLLQ (VPSLLQ-512-2) 39257 { 39258 ICLASS: VPSLLQ 39259 CPL: 3 39260 CATEGORY: AVX512 39261 EXTENSION: AVX512EVEX 39262 ISA_SET: AVX512F_512 39263 EXCEPTIONS: AVX512-E4 39264 REAL_OPCODE: Y 39265 ATTRIBUTES: MASKOP_EVEX 39266 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8() 39267 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 39268 IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 39269 } 39270 39271 { 39272 ICLASS: VPSLLQ 39273 CPL: 3 39274 CATEGORY: AVX512 39275 EXTENSION: AVX512EVEX 39276 ISA_SET: AVX512F_512 39277 EXCEPTIONS: AVX512-E4 39278 REAL_OPCODE: Y 39279 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39280 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 39281 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 39282 IFORM: VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 39283 } 39284 39285 39286 # EMITTING VPSLLVD (VPSLLVD-512-1) 39287 { 39288 ICLASS: VPSLLVD 39289 CPL: 3 39290 CATEGORY: AVX512 39291 EXTENSION: AVX512EVEX 39292 ISA_SET: AVX512F_512 39293 EXCEPTIONS: AVX512-E4 39294 REAL_OPCODE: Y 39295 ATTRIBUTES: MASKOP_EVEX 39296 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 39297 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 39298 IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 39299 } 39300 39301 { 39302 ICLASS: VPSLLVD 39303 CPL: 3 39304 CATEGORY: AVX512 39305 EXTENSION: AVX512EVEX 39306 ISA_SET: AVX512F_512 39307 EXCEPTIONS: AVX512-E4 39308 REAL_OPCODE: Y 39309 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39310 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 39311 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 39312 IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 39313 } 39314 39315 39316 # EMITTING VPSLLVQ (VPSLLVQ-512-1) 39317 { 39318 ICLASS: VPSLLVQ 39319 CPL: 3 39320 CATEGORY: AVX512 39321 EXTENSION: AVX512EVEX 39322 ISA_SET: AVX512F_512 39323 EXCEPTIONS: AVX512-E4 39324 REAL_OPCODE: Y 39325 ATTRIBUTES: MASKOP_EVEX 39326 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 39327 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 39328 IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 39329 } 39330 39331 { 39332 ICLASS: VPSLLVQ 39333 CPL: 3 39334 CATEGORY: AVX512 39335 EXTENSION: AVX512EVEX 39336 ISA_SET: AVX512F_512 39337 EXCEPTIONS: AVX512-E4 39338 REAL_OPCODE: Y 39339 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39340 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 39341 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 39342 IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 39343 } 39344 39345 39346 # EMITTING VPSRAD (VPSRAD-512-1) 39347 { 39348 ICLASS: VPSRAD 39349 CPL: 3 39350 CATEGORY: AVX512 39351 EXTENSION: AVX512EVEX 39352 ISA_SET: AVX512F_512 39353 EXCEPTIONS: AVX512-E4NF 39354 REAL_OPCODE: Y 39355 ATTRIBUTES: MASKOP_EVEX 39356 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 39357 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 39358 IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 39359 } 39360 39361 { 39362 ICLASS: VPSRAD 39363 CPL: 3 39364 CATEGORY: AVX512 39365 EXTENSION: AVX512EVEX 39366 ISA_SET: AVX512F_512 39367 EXCEPTIONS: AVX512-E4NF 39368 REAL_OPCODE: Y 39369 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 39370 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() 39371 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 39372 IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 39373 } 39374 39375 39376 # EMITTING VPSRAD (VPSRAD-512-2) 39377 { 39378 ICLASS: VPSRAD 39379 CPL: 3 39380 CATEGORY: AVX512 39381 EXTENSION: AVX512EVEX 39382 ISA_SET: AVX512F_512 39383 EXCEPTIONS: AVX512-E4 39384 REAL_OPCODE: Y 39385 ATTRIBUTES: MASKOP_EVEX 39386 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W0 UIMM8() 39387 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 39388 IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 39389 } 39390 39391 { 39392 ICLASS: VPSRAD 39393 CPL: 3 39394 CATEGORY: AVX512 39395 EXTENSION: AVX512EVEX 39396 ISA_SET: AVX512F_512 39397 EXCEPTIONS: AVX512-E4 39398 REAL_OPCODE: Y 39399 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39400 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 39401 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 39402 IFORM: VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 39403 } 39404 39405 39406 # EMITTING VPSRAQ (VPSRAQ-512-1) 39407 { 39408 ICLASS: VPSRAQ 39409 CPL: 3 39410 CATEGORY: AVX512 39411 EXTENSION: AVX512EVEX 39412 ISA_SET: AVX512F_512 39413 EXCEPTIONS: AVX512-E4NF 39414 REAL_OPCODE: Y 39415 ATTRIBUTES: MASKOP_EVEX 39416 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 39417 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 39418 IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 39419 } 39420 39421 { 39422 ICLASS: VPSRAQ 39423 CPL: 3 39424 CATEGORY: AVX512 39425 EXTENSION: AVX512EVEX 39426 ISA_SET: AVX512F_512 39427 EXCEPTIONS: AVX512-E4NF 39428 REAL_OPCODE: Y 39429 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 39430 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() 39431 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 39432 IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 39433 } 39434 39435 39436 # EMITTING VPSRAQ (VPSRAQ-512-2) 39437 { 39438 ICLASS: VPSRAQ 39439 CPL: 3 39440 CATEGORY: AVX512 39441 EXTENSION: AVX512EVEX 39442 ISA_SET: AVX512F_512 39443 EXCEPTIONS: AVX512-E4 39444 REAL_OPCODE: Y 39445 ATTRIBUTES: MASKOP_EVEX 39446 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W1 UIMM8() 39447 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 39448 IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 39449 } 39450 39451 { 39452 ICLASS: VPSRAQ 39453 CPL: 3 39454 CATEGORY: AVX512 39455 EXTENSION: AVX512EVEX 39456 ISA_SET: AVX512F_512 39457 EXCEPTIONS: AVX512-E4 39458 REAL_OPCODE: Y 39459 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39460 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 39461 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 39462 IFORM: VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 39463 } 39464 39465 39466 # EMITTING VPSRAVD (VPSRAVD-512-1) 39467 { 39468 ICLASS: VPSRAVD 39469 CPL: 3 39470 CATEGORY: AVX512 39471 EXTENSION: AVX512EVEX 39472 ISA_SET: AVX512F_512 39473 EXCEPTIONS: AVX512-E4 39474 REAL_OPCODE: Y 39475 ATTRIBUTES: MASKOP_EVEX 39476 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 39477 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 39478 IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 39479 } 39480 39481 { 39482 ICLASS: VPSRAVD 39483 CPL: 3 39484 CATEGORY: AVX512 39485 EXTENSION: AVX512EVEX 39486 ISA_SET: AVX512F_512 39487 EXCEPTIONS: AVX512-E4 39488 REAL_OPCODE: Y 39489 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39490 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 39491 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 39492 IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 39493 } 39494 39495 39496 # EMITTING VPSRAVQ (VPSRAVQ-512-1) 39497 { 39498 ICLASS: VPSRAVQ 39499 CPL: 3 39500 CATEGORY: AVX512 39501 EXTENSION: AVX512EVEX 39502 ISA_SET: AVX512F_512 39503 EXCEPTIONS: AVX512-E4 39504 REAL_OPCODE: Y 39505 ATTRIBUTES: MASKOP_EVEX 39506 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 39507 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 39508 IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 39509 } 39510 39511 { 39512 ICLASS: VPSRAVQ 39513 CPL: 3 39514 CATEGORY: AVX512 39515 EXTENSION: AVX512EVEX 39516 ISA_SET: AVX512F_512 39517 EXCEPTIONS: AVX512-E4 39518 REAL_OPCODE: Y 39519 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39520 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 39521 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 39522 IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 39523 } 39524 39525 39526 # EMITTING VPSRLD (VPSRLD-512-1) 39527 { 39528 ICLASS: VPSRLD 39529 CPL: 3 39530 CATEGORY: AVX512 39531 EXTENSION: AVX512EVEX 39532 ISA_SET: AVX512F_512 39533 EXCEPTIONS: AVX512-E4NF 39534 REAL_OPCODE: Y 39535 ATTRIBUTES: MASKOP_EVEX 39536 PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 39537 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 39538 IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 39539 } 39540 39541 { 39542 ICLASS: VPSRLD 39543 CPL: 3 39544 CATEGORY: AVX512 39545 EXTENSION: AVX512EVEX 39546 ISA_SET: AVX512F_512 39547 EXCEPTIONS: AVX512-E4NF 39548 REAL_OPCODE: Y 39549 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 39550 PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() 39551 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 39552 IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 39553 } 39554 39555 39556 # EMITTING VPSRLD (VPSRLD-512-2) 39557 { 39558 ICLASS: VPSRLD 39559 CPL: 3 39560 CATEGORY: AVX512 39561 EXTENSION: AVX512EVEX 39562 ISA_SET: AVX512F_512 39563 EXCEPTIONS: AVX512-E4 39564 REAL_OPCODE: Y 39565 ATTRIBUTES: MASKOP_EVEX 39566 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W0 UIMM8() 39567 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 39568 IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 39569 } 39570 39571 { 39572 ICLASS: VPSRLD 39573 CPL: 3 39574 CATEGORY: AVX512 39575 EXTENSION: AVX512EVEX 39576 ISA_SET: AVX512F_512 39577 EXCEPTIONS: AVX512-E4 39578 REAL_OPCODE: Y 39579 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39580 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 39581 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 39582 IFORM: VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 39583 } 39584 39585 39586 # EMITTING VPSRLQ (VPSRLQ-512-1) 39587 { 39588 ICLASS: VPSRLQ 39589 CPL: 3 39590 CATEGORY: AVX512 39591 EXTENSION: AVX512EVEX 39592 ISA_SET: AVX512F_512 39593 EXCEPTIONS: AVX512-E4NF 39594 REAL_OPCODE: Y 39595 ATTRIBUTES: MASKOP_EVEX 39596 PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 39597 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 39598 IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 39599 } 39600 39601 { 39602 ICLASS: VPSRLQ 39603 CPL: 3 39604 CATEGORY: AVX512 39605 EXTENSION: AVX512EVEX 39606 ISA_SET: AVX512F_512 39607 EXCEPTIONS: AVX512-E4NF 39608 REAL_OPCODE: Y 39609 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 39610 PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() 39611 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 39612 IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 39613 } 39614 39615 39616 # EMITTING VPSRLQ (VPSRLQ-512-2) 39617 { 39618 ICLASS: VPSRLQ 39619 CPL: 3 39620 CATEGORY: AVX512 39621 EXTENSION: AVX512EVEX 39622 ISA_SET: AVX512F_512 39623 EXCEPTIONS: AVX512-E4 39624 REAL_OPCODE: Y 39625 ATTRIBUTES: MASKOP_EVEX 39626 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8() 39627 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 39628 IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 39629 } 39630 39631 { 39632 ICLASS: VPSRLQ 39633 CPL: 3 39634 CATEGORY: AVX512 39635 EXTENSION: AVX512EVEX 39636 ISA_SET: AVX512F_512 39637 EXCEPTIONS: AVX512-E4 39638 REAL_OPCODE: Y 39639 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39640 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 39641 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 39642 IFORM: VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 39643 } 39644 39645 39646 # EMITTING VPSRLVD (VPSRLVD-512-1) 39647 { 39648 ICLASS: VPSRLVD 39649 CPL: 3 39650 CATEGORY: AVX512 39651 EXTENSION: AVX512EVEX 39652 ISA_SET: AVX512F_512 39653 EXCEPTIONS: AVX512-E4 39654 REAL_OPCODE: Y 39655 ATTRIBUTES: MASKOP_EVEX 39656 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 39657 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 39658 IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 39659 } 39660 39661 { 39662 ICLASS: VPSRLVD 39663 CPL: 3 39664 CATEGORY: AVX512 39665 EXTENSION: AVX512EVEX 39666 ISA_SET: AVX512F_512 39667 EXCEPTIONS: AVX512-E4 39668 REAL_OPCODE: Y 39669 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39670 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 39671 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 39672 IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 39673 } 39674 39675 39676 # EMITTING VPSRLVQ (VPSRLVQ-512-1) 39677 { 39678 ICLASS: VPSRLVQ 39679 CPL: 3 39680 CATEGORY: AVX512 39681 EXTENSION: AVX512EVEX 39682 ISA_SET: AVX512F_512 39683 EXCEPTIONS: AVX512-E4 39684 REAL_OPCODE: Y 39685 ATTRIBUTES: MASKOP_EVEX 39686 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 39687 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 39688 IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 39689 } 39690 39691 { 39692 ICLASS: VPSRLVQ 39693 CPL: 3 39694 CATEGORY: AVX512 39695 EXTENSION: AVX512EVEX 39696 ISA_SET: AVX512F_512 39697 EXCEPTIONS: AVX512-E4 39698 REAL_OPCODE: Y 39699 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39700 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 39701 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 39702 IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 39703 } 39704 39705 39706 # EMITTING VPSUBD (VPSUBD-512-1) 39707 { 39708 ICLASS: VPSUBD 39709 CPL: 3 39710 CATEGORY: AVX512 39711 EXTENSION: AVX512EVEX 39712 ISA_SET: AVX512F_512 39713 EXCEPTIONS: AVX512-E4 39714 REAL_OPCODE: Y 39715 ATTRIBUTES: MASKOP_EVEX 39716 PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 39717 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 39718 IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 39719 } 39720 39721 { 39722 ICLASS: VPSUBD 39723 CPL: 3 39724 CATEGORY: AVX512 39725 EXTENSION: AVX512EVEX 39726 ISA_SET: AVX512F_512 39727 EXCEPTIONS: AVX512-E4 39728 REAL_OPCODE: Y 39729 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39730 PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 39731 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 39732 IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 39733 } 39734 39735 39736 # EMITTING VPSUBQ (VPSUBQ-512-1) 39737 { 39738 ICLASS: VPSUBQ 39739 CPL: 3 39740 CATEGORY: AVX512 39741 EXTENSION: AVX512EVEX 39742 ISA_SET: AVX512F_512 39743 EXCEPTIONS: AVX512-E4 39744 REAL_OPCODE: Y 39745 ATTRIBUTES: MASKOP_EVEX 39746 PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 39747 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 39748 IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 39749 } 39750 39751 { 39752 ICLASS: VPSUBQ 39753 CPL: 3 39754 CATEGORY: AVX512 39755 EXTENSION: AVX512EVEX 39756 ISA_SET: AVX512F_512 39757 EXCEPTIONS: AVX512-E4 39758 REAL_OPCODE: Y 39759 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39760 PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 39761 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 39762 IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 39763 } 39764 39765 39766 # EMITTING VPTERNLOGD (VPTERNLOGD-512-1) 39767 { 39768 ICLASS: VPTERNLOGD 39769 CPL: 3 39770 CATEGORY: LOGICAL 39771 EXTENSION: AVX512EVEX 39772 ISA_SET: AVX512F_512 39773 EXCEPTIONS: AVX512-E4 39774 REAL_OPCODE: Y 39775 ATTRIBUTES: MASKOP_EVEX 39776 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 39777 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b 39778 IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 39779 } 39780 39781 { 39782 ICLASS: VPTERNLOGD 39783 CPL: 3 39784 CATEGORY: LOGICAL 39785 EXTENSION: AVX512EVEX 39786 ISA_SET: AVX512F_512 39787 EXCEPTIONS: AVX512-E4 39788 REAL_OPCODE: Y 39789 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39790 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 39791 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 39792 IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 39793 } 39794 39795 39796 # EMITTING VPTERNLOGQ (VPTERNLOGQ-512-1) 39797 { 39798 ICLASS: VPTERNLOGQ 39799 CPL: 3 39800 CATEGORY: LOGICAL 39801 EXTENSION: AVX512EVEX 39802 ISA_SET: AVX512F_512 39803 EXCEPTIONS: AVX512-E4 39804 REAL_OPCODE: Y 39805 ATTRIBUTES: MASKOP_EVEX 39806 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 39807 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b 39808 IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 39809 } 39810 39811 { 39812 ICLASS: VPTERNLOGQ 39813 CPL: 3 39814 CATEGORY: LOGICAL 39815 EXTENSION: AVX512EVEX 39816 ISA_SET: AVX512F_512 39817 EXCEPTIONS: AVX512-E4 39818 REAL_OPCODE: Y 39819 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39820 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 39821 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 39822 IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 39823 } 39824 39825 39826 # EMITTING VPTESTMD (VPTESTMD-512-1) 39827 { 39828 ICLASS: VPTESTMD 39829 CPL: 3 39830 CATEGORY: LOGICAL 39831 EXTENSION: AVX512EVEX 39832 ISA_SET: AVX512F_512 39833 EXCEPTIONS: AVX512-E4 39834 REAL_OPCODE: Y 39835 ATTRIBUTES: MASKOP_EVEX 39836 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 39837 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 39838 IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 39839 } 39840 39841 { 39842 ICLASS: VPTESTMD 39843 CPL: 3 39844 CATEGORY: LOGICAL 39845 EXTENSION: AVX512EVEX 39846 ISA_SET: AVX512F_512 39847 EXCEPTIONS: AVX512-E4 39848 REAL_OPCODE: Y 39849 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39850 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 39851 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 39852 IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 39853 } 39854 39855 39856 # EMITTING VPTESTMQ (VPTESTMQ-512-1) 39857 { 39858 ICLASS: VPTESTMQ 39859 CPL: 3 39860 CATEGORY: LOGICAL 39861 EXTENSION: AVX512EVEX 39862 ISA_SET: AVX512F_512 39863 EXCEPTIONS: AVX512-E4 39864 REAL_OPCODE: Y 39865 ATTRIBUTES: MASKOP_EVEX 39866 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 39867 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 39868 IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 39869 } 39870 39871 { 39872 ICLASS: VPTESTMQ 39873 CPL: 3 39874 CATEGORY: LOGICAL 39875 EXTENSION: AVX512EVEX 39876 ISA_SET: AVX512F_512 39877 EXCEPTIONS: AVX512-E4 39878 REAL_OPCODE: Y 39879 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39880 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 39881 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 39882 IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 39883 } 39884 39885 39886 # EMITTING VPTESTNMD (VPTESTNMD-512-1) 39887 { 39888 ICLASS: VPTESTNMD 39889 CPL: 3 39890 CATEGORY: LOGICAL 39891 EXTENSION: AVX512EVEX 39892 ISA_SET: AVX512F_512 39893 EXCEPTIONS: AVX512-E4 39894 REAL_OPCODE: Y 39895 ATTRIBUTES: MASKOP_EVEX 39896 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 39897 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 39898 IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 39899 } 39900 39901 { 39902 ICLASS: VPTESTNMD 39903 CPL: 3 39904 CATEGORY: LOGICAL 39905 EXTENSION: AVX512EVEX 39906 ISA_SET: AVX512F_512 39907 EXCEPTIONS: AVX512-E4 39908 REAL_OPCODE: Y 39909 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39910 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 39911 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 39912 IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 39913 } 39914 39915 39916 # EMITTING VPTESTNMQ (VPTESTNMQ-512-1) 39917 { 39918 ICLASS: VPTESTNMQ 39919 CPL: 3 39920 CATEGORY: LOGICAL 39921 EXTENSION: AVX512EVEX 39922 ISA_SET: AVX512F_512 39923 EXCEPTIONS: AVX512-E4 39924 REAL_OPCODE: Y 39925 ATTRIBUTES: MASKOP_EVEX 39926 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 39927 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 39928 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 39929 } 39930 39931 { 39932 ICLASS: VPTESTNMQ 39933 CPL: 3 39934 CATEGORY: LOGICAL 39935 EXTENSION: AVX512EVEX 39936 ISA_SET: AVX512F_512 39937 EXCEPTIONS: AVX512-E4 39938 REAL_OPCODE: Y 39939 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39940 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 39941 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 39942 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 39943 } 39944 39945 39946 # EMITTING VPUNPCKHDQ (VPUNPCKHDQ-512-1) 39947 { 39948 ICLASS: VPUNPCKHDQ 39949 CPL: 3 39950 CATEGORY: AVX512 39951 EXTENSION: AVX512EVEX 39952 ISA_SET: AVX512F_512 39953 EXCEPTIONS: AVX512-E4NF 39954 REAL_OPCODE: Y 39955 ATTRIBUTES: MASKOP_EVEX 39956 PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 39957 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 39958 IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 39959 } 39960 39961 { 39962 ICLASS: VPUNPCKHDQ 39963 CPL: 3 39964 CATEGORY: AVX512 39965 EXTENSION: AVX512EVEX 39966 ISA_SET: AVX512F_512 39967 EXCEPTIONS: AVX512-E4NF 39968 REAL_OPCODE: Y 39969 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39970 PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 39971 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 39972 IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 39973 } 39974 39975 39976 # EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-512-1) 39977 { 39978 ICLASS: VPUNPCKHQDQ 39979 CPL: 3 39980 CATEGORY: AVX512 39981 EXTENSION: AVX512EVEX 39982 ISA_SET: AVX512F_512 39983 EXCEPTIONS: AVX512-E4NF 39984 REAL_OPCODE: Y 39985 ATTRIBUTES: MASKOP_EVEX 39986 PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 39987 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 39988 IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 39989 } 39990 39991 { 39992 ICLASS: VPUNPCKHQDQ 39993 CPL: 3 39994 CATEGORY: AVX512 39995 EXTENSION: AVX512EVEX 39996 ISA_SET: AVX512F_512 39997 EXCEPTIONS: AVX512-E4NF 39998 REAL_OPCODE: Y 39999 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40000 PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 40001 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 40002 IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 40003 } 40004 40005 40006 # EMITTING VPUNPCKLDQ (VPUNPCKLDQ-512-1) 40007 { 40008 ICLASS: VPUNPCKLDQ 40009 CPL: 3 40010 CATEGORY: AVX512 40011 EXTENSION: AVX512EVEX 40012 ISA_SET: AVX512F_512 40013 EXCEPTIONS: AVX512-E4NF 40014 REAL_OPCODE: Y 40015 ATTRIBUTES: MASKOP_EVEX 40016 PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 40017 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 40018 IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 40019 } 40020 40021 { 40022 ICLASS: VPUNPCKLDQ 40023 CPL: 3 40024 CATEGORY: AVX512 40025 EXTENSION: AVX512EVEX 40026 ISA_SET: AVX512F_512 40027 EXCEPTIONS: AVX512-E4NF 40028 REAL_OPCODE: Y 40029 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40030 PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 40031 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 40032 IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 40033 } 40034 40035 40036 # EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-512-1) 40037 { 40038 ICLASS: VPUNPCKLQDQ 40039 CPL: 3 40040 CATEGORY: AVX512 40041 EXTENSION: AVX512EVEX 40042 ISA_SET: AVX512F_512 40043 EXCEPTIONS: AVX512-E4NF 40044 REAL_OPCODE: Y 40045 ATTRIBUTES: MASKOP_EVEX 40046 PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 40047 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 40048 IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 40049 } 40050 40051 { 40052 ICLASS: VPUNPCKLQDQ 40053 CPL: 3 40054 CATEGORY: AVX512 40055 EXTENSION: AVX512EVEX 40056 ISA_SET: AVX512F_512 40057 EXCEPTIONS: AVX512-E4NF 40058 REAL_OPCODE: Y 40059 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40060 PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 40061 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 40062 IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 40063 } 40064 40065 40066 # EMITTING VPXORD (VPXORD-512-1) 40067 { 40068 ICLASS: VPXORD 40069 CPL: 3 40070 CATEGORY: LOGICAL 40071 EXTENSION: AVX512EVEX 40072 ISA_SET: AVX512F_512 40073 EXCEPTIONS: AVX512-E4 40074 REAL_OPCODE: Y 40075 ATTRIBUTES: MASKOP_EVEX 40076 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 40077 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 40078 IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 40079 } 40080 40081 { 40082 ICLASS: VPXORD 40083 CPL: 3 40084 CATEGORY: LOGICAL 40085 EXTENSION: AVX512EVEX 40086 ISA_SET: AVX512F_512 40087 EXCEPTIONS: AVX512-E4 40088 REAL_OPCODE: Y 40089 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40090 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 40091 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 40092 IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 40093 } 40094 40095 40096 # EMITTING VPXORQ (VPXORQ-512-1) 40097 { 40098 ICLASS: VPXORQ 40099 CPL: 3 40100 CATEGORY: LOGICAL 40101 EXTENSION: AVX512EVEX 40102 ISA_SET: AVX512F_512 40103 EXCEPTIONS: AVX512-E4 40104 REAL_OPCODE: Y 40105 ATTRIBUTES: MASKOP_EVEX 40106 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 40107 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 40108 IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 40109 } 40110 40111 { 40112 ICLASS: VPXORQ 40113 CPL: 3 40114 CATEGORY: LOGICAL 40115 EXTENSION: AVX512EVEX 40116 ISA_SET: AVX512F_512 40117 EXCEPTIONS: AVX512-E4 40118 REAL_OPCODE: Y 40119 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40120 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 40121 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 40122 IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 40123 } 40124 40125 40126 # EMITTING VRCP14PD (VRCP14PD-512-1) 40127 { 40128 ICLASS: VRCP14PD 40129 CPL: 3 40130 CATEGORY: AVX512 40131 EXTENSION: AVX512EVEX 40132 ISA_SET: AVX512F_512 40133 EXCEPTIONS: AVX512-E4 40134 REAL_OPCODE: Y 40135 ATTRIBUTES: MXCSR MASKOP_EVEX 40136 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 40137 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 40138 IFORM: VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 40139 } 40140 40141 { 40142 ICLASS: VRCP14PD 40143 CPL: 3 40144 CATEGORY: AVX512 40145 EXTENSION: AVX512EVEX 40146 ISA_SET: AVX512F_512 40147 EXCEPTIONS: AVX512-E4 40148 REAL_OPCODE: Y 40149 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40150 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 40151 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 40152 IFORM: VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 40153 } 40154 40155 40156 # EMITTING VRCP14PS (VRCP14PS-512-1) 40157 { 40158 ICLASS: VRCP14PS 40159 CPL: 3 40160 CATEGORY: AVX512 40161 EXTENSION: AVX512EVEX 40162 ISA_SET: AVX512F_512 40163 EXCEPTIONS: AVX512-E4 40164 REAL_OPCODE: Y 40165 ATTRIBUTES: MXCSR MASKOP_EVEX 40166 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 40167 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 40168 IFORM: VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 40169 } 40170 40171 { 40172 ICLASS: VRCP14PS 40173 CPL: 3 40174 CATEGORY: AVX512 40175 EXTENSION: AVX512EVEX 40176 ISA_SET: AVX512F_512 40177 EXCEPTIONS: AVX512-E4 40178 REAL_OPCODE: Y 40179 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40180 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 40181 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 40182 IFORM: VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 40183 } 40184 40185 40186 # EMITTING VRCP14SD (VRCP14SD-128-1) 40187 { 40188 ICLASS: VRCP14SD 40189 CPL: 3 40190 CATEGORY: AVX512 40191 EXTENSION: AVX512EVEX 40192 ISA_SET: AVX512F_SCALAR 40193 EXCEPTIONS: AVX512-E10 40194 REAL_OPCODE: Y 40195 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40196 PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 40197 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 40198 IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 40199 } 40200 40201 { 40202 ICLASS: VRCP14SD 40203 CPL: 3 40204 CATEGORY: AVX512 40205 EXTENSION: AVX512EVEX 40206 ISA_SET: AVX512F_SCALAR 40207 EXCEPTIONS: AVX512-E10 40208 REAL_OPCODE: Y 40209 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 40210 PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 40211 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 40212 IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 40213 } 40214 40215 40216 # EMITTING VRCP14SS (VRCP14SS-128-1) 40217 { 40218 ICLASS: VRCP14SS 40219 CPL: 3 40220 CATEGORY: AVX512 40221 EXTENSION: AVX512EVEX 40222 ISA_SET: AVX512F_SCALAR 40223 EXCEPTIONS: AVX512-E10 40224 REAL_OPCODE: Y 40225 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40226 PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 40227 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 40228 IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 40229 } 40230 40231 { 40232 ICLASS: VRCP14SS 40233 CPL: 3 40234 CATEGORY: AVX512 40235 EXTENSION: AVX512EVEX 40236 ISA_SET: AVX512F_SCALAR 40237 EXCEPTIONS: AVX512-E10 40238 REAL_OPCODE: Y 40239 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 40240 PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 40241 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 40242 IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 40243 } 40244 40245 40246 # EMITTING VRNDSCALEPD (VRNDSCALEPD-512-1) 40247 { 40248 ICLASS: VRNDSCALEPD 40249 CPL: 3 40250 CATEGORY: AVX512 40251 EXTENSION: AVX512EVEX 40252 ISA_SET: AVX512F_512 40253 EXCEPTIONS: AVX512-E2 40254 REAL_OPCODE: Y 40255 ATTRIBUTES: MXCSR MASKOP_EVEX 40256 PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 40257 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 40258 IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 40259 } 40260 40261 { 40262 ICLASS: VRNDSCALEPD 40263 CPL: 3 40264 CATEGORY: AVX512 40265 EXTENSION: AVX512EVEX 40266 ISA_SET: AVX512F_512 40267 EXCEPTIONS: AVX512-E2 40268 REAL_OPCODE: Y 40269 ATTRIBUTES: MXCSR MASKOP_EVEX 40270 PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() 40271 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 40272 IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 40273 } 40274 40275 { 40276 ICLASS: VRNDSCALEPD 40277 CPL: 3 40278 CATEGORY: AVX512 40279 EXTENSION: AVX512EVEX 40280 ISA_SET: AVX512F_512 40281 EXCEPTIONS: AVX512-E2 40282 REAL_OPCODE: Y 40283 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40284 PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 40285 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 40286 IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 40287 } 40288 40289 40290 # EMITTING VRNDSCALEPS (VRNDSCALEPS-512-1) 40291 { 40292 ICLASS: VRNDSCALEPS 40293 CPL: 3 40294 CATEGORY: AVX512 40295 EXTENSION: AVX512EVEX 40296 ISA_SET: AVX512F_512 40297 EXCEPTIONS: AVX512-E2 40298 REAL_OPCODE: Y 40299 ATTRIBUTES: MXCSR MASKOP_EVEX 40300 PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 40301 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 40302 IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 40303 } 40304 40305 { 40306 ICLASS: VRNDSCALEPS 40307 CPL: 3 40308 CATEGORY: AVX512 40309 EXTENSION: AVX512EVEX 40310 ISA_SET: AVX512F_512 40311 EXCEPTIONS: AVX512-E2 40312 REAL_OPCODE: Y 40313 ATTRIBUTES: MXCSR MASKOP_EVEX 40314 PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() 40315 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 40316 IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 40317 } 40318 40319 { 40320 ICLASS: VRNDSCALEPS 40321 CPL: 3 40322 CATEGORY: AVX512 40323 EXTENSION: AVX512EVEX 40324 ISA_SET: AVX512F_512 40325 EXCEPTIONS: AVX512-E2 40326 REAL_OPCODE: Y 40327 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40328 PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 40329 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 40330 IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 40331 } 40332 40333 40334 # EMITTING VRNDSCALESD (VRNDSCALESD-128-1) 40335 { 40336 ICLASS: VRNDSCALESD 40337 CPL: 3 40338 CATEGORY: AVX512 40339 EXTENSION: AVX512EVEX 40340 ISA_SET: AVX512F_SCALAR 40341 EXCEPTIONS: AVX512-E3 40342 REAL_OPCODE: Y 40343 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40344 PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() 40345 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 40346 IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 40347 } 40348 40349 { 40350 ICLASS: VRNDSCALESD 40351 CPL: 3 40352 CATEGORY: AVX512 40353 EXTENSION: AVX512EVEX 40354 ISA_SET: AVX512F_SCALAR 40355 EXCEPTIONS: AVX512-E3 40356 REAL_OPCODE: Y 40357 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40358 PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() 40359 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 40360 IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 40361 } 40362 40363 { 40364 ICLASS: VRNDSCALESD 40365 CPL: 3 40366 CATEGORY: AVX512 40367 EXTENSION: AVX512EVEX 40368 ISA_SET: AVX512F_SCALAR 40369 EXCEPTIONS: AVX512-E3 40370 REAL_OPCODE: Y 40371 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 40372 PATTERN: EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 40373 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 40374 IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 40375 } 40376 40377 40378 # EMITTING VRNDSCALESS (VRNDSCALESS-128-1) 40379 { 40380 ICLASS: VRNDSCALESS 40381 CPL: 3 40382 CATEGORY: AVX512 40383 EXTENSION: AVX512EVEX 40384 ISA_SET: AVX512F_SCALAR 40385 EXCEPTIONS: AVX512-E3 40386 REAL_OPCODE: Y 40387 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40388 PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() 40389 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 40390 IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 40391 } 40392 40393 { 40394 ICLASS: VRNDSCALESS 40395 CPL: 3 40396 CATEGORY: AVX512 40397 EXTENSION: AVX512EVEX 40398 ISA_SET: AVX512F_SCALAR 40399 EXCEPTIONS: AVX512-E3 40400 REAL_OPCODE: Y 40401 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40402 PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() 40403 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 40404 IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 40405 } 40406 40407 { 40408 ICLASS: VRNDSCALESS 40409 CPL: 3 40410 CATEGORY: AVX512 40411 EXTENSION: AVX512EVEX 40412 ISA_SET: AVX512F_SCALAR 40413 EXCEPTIONS: AVX512-E3 40414 REAL_OPCODE: Y 40415 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 40416 PATTERN: EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 40417 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 40418 IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 40419 } 40420 40421 40422 # EMITTING VRSQRT14PD (VRSQRT14PD-512-1) 40423 { 40424 ICLASS: VRSQRT14PD 40425 CPL: 3 40426 CATEGORY: AVX512 40427 EXTENSION: AVX512EVEX 40428 ISA_SET: AVX512F_512 40429 EXCEPTIONS: AVX512-E4 40430 REAL_OPCODE: Y 40431 ATTRIBUTES: MXCSR MASKOP_EVEX 40432 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 40433 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 40434 IFORM: VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 40435 } 40436 40437 { 40438 ICLASS: VRSQRT14PD 40439 CPL: 3 40440 CATEGORY: AVX512 40441 EXTENSION: AVX512EVEX 40442 ISA_SET: AVX512F_512 40443 EXCEPTIONS: AVX512-E4 40444 REAL_OPCODE: Y 40445 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40446 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 40447 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 40448 IFORM: VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 40449 } 40450 40451 40452 # EMITTING VRSQRT14PS (VRSQRT14PS-512-1) 40453 { 40454 ICLASS: VRSQRT14PS 40455 CPL: 3 40456 CATEGORY: AVX512 40457 EXTENSION: AVX512EVEX 40458 ISA_SET: AVX512F_512 40459 EXCEPTIONS: AVX512-E4 40460 REAL_OPCODE: Y 40461 ATTRIBUTES: MXCSR MASKOP_EVEX 40462 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 40463 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 40464 IFORM: VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 40465 } 40466 40467 { 40468 ICLASS: VRSQRT14PS 40469 CPL: 3 40470 CATEGORY: AVX512 40471 EXTENSION: AVX512EVEX 40472 ISA_SET: AVX512F_512 40473 EXCEPTIONS: AVX512-E4 40474 REAL_OPCODE: Y 40475 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40476 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 40477 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 40478 IFORM: VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 40479 } 40480 40481 40482 # EMITTING VRSQRT14SD (VRSQRT14SD-128-1) 40483 { 40484 ICLASS: VRSQRT14SD 40485 CPL: 3 40486 CATEGORY: AVX512 40487 EXTENSION: AVX512EVEX 40488 ISA_SET: AVX512F_SCALAR 40489 EXCEPTIONS: AVX512-E10 40490 REAL_OPCODE: Y 40491 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40492 PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 40493 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 40494 IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 40495 } 40496 40497 { 40498 ICLASS: VRSQRT14SD 40499 CPL: 3 40500 CATEGORY: AVX512 40501 EXTENSION: AVX512EVEX 40502 ISA_SET: AVX512F_SCALAR 40503 EXCEPTIONS: AVX512-E10 40504 REAL_OPCODE: Y 40505 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 40506 PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 40507 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 40508 IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 40509 } 40510 40511 40512 # EMITTING VRSQRT14SS (VRSQRT14SS-128-1) 40513 { 40514 ICLASS: VRSQRT14SS 40515 CPL: 3 40516 CATEGORY: AVX512 40517 EXTENSION: AVX512EVEX 40518 ISA_SET: AVX512F_SCALAR 40519 EXCEPTIONS: AVX512-E10 40520 REAL_OPCODE: Y 40521 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40522 PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 40523 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 40524 IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 40525 } 40526 40527 { 40528 ICLASS: VRSQRT14SS 40529 CPL: 3 40530 CATEGORY: AVX512 40531 EXTENSION: AVX512EVEX 40532 ISA_SET: AVX512F_SCALAR 40533 EXCEPTIONS: AVX512-E10 40534 REAL_OPCODE: Y 40535 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 40536 PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 40537 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 40538 IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 40539 } 40540 40541 40542 # EMITTING VSCALEFPD (VSCALEFPD-512-1) 40543 { 40544 ICLASS: VSCALEFPD 40545 CPL: 3 40546 CATEGORY: AVX512 40547 EXTENSION: AVX512EVEX 40548 ISA_SET: AVX512F_512 40549 EXCEPTIONS: AVX512-E2 40550 REAL_OPCODE: Y 40551 ATTRIBUTES: MXCSR MASKOP_EVEX 40552 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 40553 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 40554 IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 40555 } 40556 40557 { 40558 ICLASS: VSCALEFPD 40559 CPL: 3 40560 CATEGORY: AVX512 40561 EXTENSION: AVX512EVEX 40562 ISA_SET: AVX512F_512 40563 EXCEPTIONS: AVX512-E2 40564 REAL_OPCODE: Y 40565 ATTRIBUTES: MXCSR MASKOP_EVEX 40566 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 40567 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 40568 IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 40569 } 40570 40571 { 40572 ICLASS: VSCALEFPD 40573 CPL: 3 40574 CATEGORY: AVX512 40575 EXTENSION: AVX512EVEX 40576 ISA_SET: AVX512F_512 40577 EXCEPTIONS: AVX512-E2 40578 REAL_OPCODE: Y 40579 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40580 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 40581 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 40582 IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 40583 } 40584 40585 40586 # EMITTING VSCALEFPS (VSCALEFPS-512-1) 40587 { 40588 ICLASS: VSCALEFPS 40589 CPL: 3 40590 CATEGORY: AVX512 40591 EXTENSION: AVX512EVEX 40592 ISA_SET: AVX512F_512 40593 EXCEPTIONS: AVX512-E2 40594 REAL_OPCODE: Y 40595 ATTRIBUTES: MXCSR MASKOP_EVEX 40596 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 40597 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 40598 IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 40599 } 40600 40601 { 40602 ICLASS: VSCALEFPS 40603 CPL: 3 40604 CATEGORY: AVX512 40605 EXTENSION: AVX512EVEX 40606 ISA_SET: AVX512F_512 40607 EXCEPTIONS: AVX512-E2 40608 REAL_OPCODE: Y 40609 ATTRIBUTES: MXCSR MASKOP_EVEX 40610 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 40611 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 40612 IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 40613 } 40614 40615 { 40616 ICLASS: VSCALEFPS 40617 CPL: 3 40618 CATEGORY: AVX512 40619 EXTENSION: AVX512EVEX 40620 ISA_SET: AVX512F_512 40621 EXCEPTIONS: AVX512-E2 40622 REAL_OPCODE: Y 40623 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40624 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 40625 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 40626 IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 40627 } 40628 40629 40630 # EMITTING VSCALEFSD (VSCALEFSD-128-1) 40631 { 40632 ICLASS: VSCALEFSD 40633 CPL: 3 40634 CATEGORY: AVX512 40635 EXTENSION: AVX512EVEX 40636 ISA_SET: AVX512F_SCALAR 40637 EXCEPTIONS: AVX512-E3 40638 REAL_OPCODE: Y 40639 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40640 PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 40641 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 40642 IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 40643 } 40644 40645 { 40646 ICLASS: VSCALEFSD 40647 CPL: 3 40648 CATEGORY: AVX512 40649 EXTENSION: AVX512EVEX 40650 ISA_SET: AVX512F_SCALAR 40651 EXCEPTIONS: AVX512-E3 40652 REAL_OPCODE: Y 40653 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40654 PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 40655 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 40656 IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 40657 } 40658 40659 { 40660 ICLASS: VSCALEFSD 40661 CPL: 3 40662 CATEGORY: AVX512 40663 EXTENSION: AVX512EVEX 40664 ISA_SET: AVX512F_SCALAR 40665 EXCEPTIONS: AVX512-E3 40666 REAL_OPCODE: Y 40667 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 40668 PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 40669 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 40670 IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 40671 } 40672 40673 40674 # EMITTING VSCALEFSS (VSCALEFSS-128-1) 40675 { 40676 ICLASS: VSCALEFSS 40677 CPL: 3 40678 CATEGORY: AVX512 40679 EXTENSION: AVX512EVEX 40680 ISA_SET: AVX512F_SCALAR 40681 EXCEPTIONS: AVX512-E3 40682 REAL_OPCODE: Y 40683 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40684 PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 40685 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 40686 IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 40687 } 40688 40689 { 40690 ICLASS: VSCALEFSS 40691 CPL: 3 40692 CATEGORY: AVX512 40693 EXTENSION: AVX512EVEX 40694 ISA_SET: AVX512F_SCALAR 40695 EXCEPTIONS: AVX512-E3 40696 REAL_OPCODE: Y 40697 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 40698 PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 40699 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 40700 IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 40701 } 40702 40703 { 40704 ICLASS: VSCALEFSS 40705 CPL: 3 40706 CATEGORY: AVX512 40707 EXTENSION: AVX512EVEX 40708 ISA_SET: AVX512F_SCALAR 40709 EXCEPTIONS: AVX512-E3 40710 REAL_OPCODE: Y 40711 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 40712 PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 40713 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 40714 IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 40715 } 40716 40717 40718 # EMITTING VSCATTERDPD (VSCATTERDPD-512-1) 40719 { 40720 ICLASS: VSCATTERDPD 40721 CPL: 3 40722 CATEGORY: SCATTER 40723 EXTENSION: AVX512EVEX 40724 ISA_SET: AVX512F_512 40725 EXCEPTIONS: AVX512-E12 40726 REAL_OPCODE: Y 40727 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 40728 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 40729 OPERANDS: MEM0:w:zd:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 40730 IFORM: VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 40731 } 40732 40733 40734 # EMITTING VSCATTERDPS (VSCATTERDPS-512-1) 40735 { 40736 ICLASS: VSCATTERDPS 40737 CPL: 3 40738 CATEGORY: SCATTER 40739 EXTENSION: AVX512EVEX 40740 ISA_SET: AVX512F_512 40741 EXCEPTIONS: AVX512-E12 40742 REAL_OPCODE: Y 40743 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 40744 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 40745 OPERANDS: MEM0:w:zd:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32 40746 IFORM: VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 40747 } 40748 40749 40750 # EMITTING VSCATTERQPD (VSCATTERQPD-512-1) 40751 { 40752 ICLASS: VSCATTERQPD 40753 CPL: 3 40754 CATEGORY: SCATTER 40755 EXTENSION: AVX512EVEX 40756 ISA_SET: AVX512F_512 40757 EXCEPTIONS: AVX512-E12 40758 REAL_OPCODE: Y 40759 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 40760 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 40761 OPERANDS: MEM0:w:zd:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 40762 IFORM: VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 40763 } 40764 40765 40766 # EMITTING VSCATTERQPS (VSCATTERQPS-512-1) 40767 { 40768 ICLASS: VSCATTERQPS 40769 CPL: 3 40770 CATEGORY: SCATTER 40771 EXTENSION: AVX512EVEX 40772 ISA_SET: AVX512F_512 40773 EXCEPTIONS: AVX512-E12 40774 REAL_OPCODE: Y 40775 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 40776 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 40777 OPERANDS: MEM0:w:qq:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 40778 IFORM: VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 40779 } 40780 40781 40782 # EMITTING VSHUFF32X4 (VSHUFF32X4-512-1) 40783 { 40784 ICLASS: VSHUFF32X4 40785 CPL: 3 40786 CATEGORY: AVX512 40787 EXTENSION: AVX512EVEX 40788 ISA_SET: AVX512F_512 40789 EXCEPTIONS: AVX512-E4NF 40790 REAL_OPCODE: Y 40791 ATTRIBUTES: MASKOP_EVEX 40792 PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 40793 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 40794 IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 40795 } 40796 40797 { 40798 ICLASS: VSHUFF32X4 40799 CPL: 3 40800 CATEGORY: AVX512 40801 EXTENSION: AVX512EVEX 40802 ISA_SET: AVX512F_512 40803 EXCEPTIONS: AVX512-E4NF 40804 REAL_OPCODE: Y 40805 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40806 PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 40807 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 40808 IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 40809 } 40810 40811 40812 # EMITTING VSHUFF64X2 (VSHUFF64X2-512-1) 40813 { 40814 ICLASS: VSHUFF64X2 40815 CPL: 3 40816 CATEGORY: AVX512 40817 EXTENSION: AVX512EVEX 40818 ISA_SET: AVX512F_512 40819 EXCEPTIONS: AVX512-E4NF 40820 REAL_OPCODE: Y 40821 ATTRIBUTES: MASKOP_EVEX 40822 PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 40823 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 40824 IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 40825 } 40826 40827 { 40828 ICLASS: VSHUFF64X2 40829 CPL: 3 40830 CATEGORY: AVX512 40831 EXTENSION: AVX512EVEX 40832 ISA_SET: AVX512F_512 40833 EXCEPTIONS: AVX512-E4NF 40834 REAL_OPCODE: Y 40835 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40836 PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 40837 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 40838 IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 40839 } 40840 40841 40842 # EMITTING VSHUFI32X4 (VSHUFI32X4-512-1) 40843 { 40844 ICLASS: VSHUFI32X4 40845 CPL: 3 40846 CATEGORY: AVX512 40847 EXTENSION: AVX512EVEX 40848 ISA_SET: AVX512F_512 40849 EXCEPTIONS: AVX512-E4NF 40850 REAL_OPCODE: Y 40851 ATTRIBUTES: MASKOP_EVEX 40852 PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 40853 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b 40854 IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 40855 } 40856 40857 { 40858 ICLASS: VSHUFI32X4 40859 CPL: 3 40860 CATEGORY: AVX512 40861 EXTENSION: AVX512EVEX 40862 ISA_SET: AVX512F_512 40863 EXCEPTIONS: AVX512-E4NF 40864 REAL_OPCODE: Y 40865 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40866 PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 40867 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 40868 IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 40869 } 40870 40871 40872 # EMITTING VSHUFI64X2 (VSHUFI64X2-512-1) 40873 { 40874 ICLASS: VSHUFI64X2 40875 CPL: 3 40876 CATEGORY: AVX512 40877 EXTENSION: AVX512EVEX 40878 ISA_SET: AVX512F_512 40879 EXCEPTIONS: AVX512-E4NF 40880 REAL_OPCODE: Y 40881 ATTRIBUTES: MASKOP_EVEX 40882 PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 40883 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b 40884 IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 40885 } 40886 40887 { 40888 ICLASS: VSHUFI64X2 40889 CPL: 3 40890 CATEGORY: AVX512 40891 EXTENSION: AVX512EVEX 40892 ISA_SET: AVX512F_512 40893 EXCEPTIONS: AVX512-E4NF 40894 REAL_OPCODE: Y 40895 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40896 PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 40897 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 40898 IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 40899 } 40900 40901 40902 # EMITTING VSHUFPD (VSHUFPD-512-1) 40903 { 40904 ICLASS: VSHUFPD 40905 CPL: 3 40906 CATEGORY: AVX512 40907 EXTENSION: AVX512EVEX 40908 ISA_SET: AVX512F_512 40909 EXCEPTIONS: AVX512-E4NF 40910 REAL_OPCODE: Y 40911 ATTRIBUTES: MASKOP_EVEX 40912 PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 40913 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 40914 IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 40915 } 40916 40917 { 40918 ICLASS: VSHUFPD 40919 CPL: 3 40920 CATEGORY: AVX512 40921 EXTENSION: AVX512EVEX 40922 ISA_SET: AVX512F_512 40923 EXCEPTIONS: AVX512-E4NF 40924 REAL_OPCODE: Y 40925 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40926 PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 40927 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 40928 IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 40929 } 40930 40931 40932 # EMITTING VSHUFPS (VSHUFPS-512-1) 40933 { 40934 ICLASS: VSHUFPS 40935 CPL: 3 40936 CATEGORY: AVX512 40937 EXTENSION: AVX512EVEX 40938 ISA_SET: AVX512F_512 40939 EXCEPTIONS: AVX512-E4NF 40940 REAL_OPCODE: Y 40941 ATTRIBUTES: MASKOP_EVEX 40942 PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 40943 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 40944 IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 40945 } 40946 40947 { 40948 ICLASS: VSHUFPS 40949 CPL: 3 40950 CATEGORY: AVX512 40951 EXTENSION: AVX512EVEX 40952 ISA_SET: AVX512F_512 40953 EXCEPTIONS: AVX512-E4NF 40954 REAL_OPCODE: Y 40955 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40956 PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 40957 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 40958 IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 40959 } 40960 40961 40962 # EMITTING VSQRTPD (VSQRTPD-512-1) 40963 { 40964 ICLASS: VSQRTPD 40965 CPL: 3 40966 CATEGORY: AVX512 40967 EXTENSION: AVX512EVEX 40968 ISA_SET: AVX512F_512 40969 EXCEPTIONS: AVX512-E2 40970 REAL_OPCODE: Y 40971 ATTRIBUTES: MXCSR MASKOP_EVEX 40972 PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 40973 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 40974 IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 40975 } 40976 40977 { 40978 ICLASS: VSQRTPD 40979 CPL: 3 40980 CATEGORY: AVX512 40981 EXTENSION: AVX512EVEX 40982 ISA_SET: AVX512F_512 40983 EXCEPTIONS: AVX512-E2 40984 REAL_OPCODE: Y 40985 ATTRIBUTES: MXCSR MASKOP_EVEX 40986 PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 40987 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 40988 IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 40989 } 40990 40991 { 40992 ICLASS: VSQRTPD 40993 CPL: 3 40994 CATEGORY: AVX512 40995 EXTENSION: AVX512EVEX 40996 ISA_SET: AVX512F_512 40997 EXCEPTIONS: AVX512-E2 40998 REAL_OPCODE: Y 40999 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41000 PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 41001 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 41002 IFORM: VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 41003 } 41004 41005 41006 # EMITTING VSQRTPS (VSQRTPS-512-1) 41007 { 41008 ICLASS: VSQRTPS 41009 CPL: 3 41010 CATEGORY: AVX512 41011 EXTENSION: AVX512EVEX 41012 ISA_SET: AVX512F_512 41013 EXCEPTIONS: AVX512-E2 41014 REAL_OPCODE: Y 41015 ATTRIBUTES: MXCSR MASKOP_EVEX 41016 PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 41017 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 41018 IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 41019 } 41020 41021 { 41022 ICLASS: VSQRTPS 41023 CPL: 3 41024 CATEGORY: AVX512 41025 EXTENSION: AVX512EVEX 41026 ISA_SET: AVX512F_512 41027 EXCEPTIONS: AVX512-E2 41028 REAL_OPCODE: Y 41029 ATTRIBUTES: MXCSR MASKOP_EVEX 41030 PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 41031 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 41032 IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 41033 } 41034 41035 { 41036 ICLASS: VSQRTPS 41037 CPL: 3 41038 CATEGORY: AVX512 41039 EXTENSION: AVX512EVEX 41040 ISA_SET: AVX512F_512 41041 EXCEPTIONS: AVX512-E2 41042 REAL_OPCODE: Y 41043 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41044 PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 41045 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 41046 IFORM: VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 41047 } 41048 41049 41050 # EMITTING VSQRTSD (VSQRTSD-128-1) 41051 { 41052 ICLASS: VSQRTSD 41053 CPL: 3 41054 CATEGORY: AVX512 41055 EXTENSION: AVX512EVEX 41056 ISA_SET: AVX512F_SCALAR 41057 EXCEPTIONS: AVX512-E3 41058 REAL_OPCODE: Y 41059 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 41060 PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 41061 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 41062 IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 41063 } 41064 41065 { 41066 ICLASS: VSQRTSD 41067 CPL: 3 41068 CATEGORY: AVX512 41069 EXTENSION: AVX512EVEX 41070 ISA_SET: AVX512F_SCALAR 41071 EXCEPTIONS: AVX512-E3 41072 REAL_OPCODE: Y 41073 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 41074 PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 41075 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 41076 IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 41077 } 41078 41079 { 41080 ICLASS: VSQRTSD 41081 CPL: 3 41082 CATEGORY: AVX512 41083 EXTENSION: AVX512EVEX 41084 ISA_SET: AVX512F_SCALAR 41085 EXCEPTIONS: AVX512-E3 41086 REAL_OPCODE: Y 41087 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 41088 PATTERN: EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 41089 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 41090 IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 41091 } 41092 41093 41094 # EMITTING VSQRTSS (VSQRTSS-128-1) 41095 { 41096 ICLASS: VSQRTSS 41097 CPL: 3 41098 CATEGORY: AVX512 41099 EXTENSION: AVX512EVEX 41100 ISA_SET: AVX512F_SCALAR 41101 EXCEPTIONS: AVX512-E3 41102 REAL_OPCODE: Y 41103 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 41104 PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 41105 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 41106 IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 41107 } 41108 41109 { 41110 ICLASS: VSQRTSS 41111 CPL: 3 41112 CATEGORY: AVX512 41113 EXTENSION: AVX512EVEX 41114 ISA_SET: AVX512F_SCALAR 41115 EXCEPTIONS: AVX512-E3 41116 REAL_OPCODE: Y 41117 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 41118 PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 41119 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 41120 IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 41121 } 41122 41123 { 41124 ICLASS: VSQRTSS 41125 CPL: 3 41126 CATEGORY: AVX512 41127 EXTENSION: AVX512EVEX 41128 ISA_SET: AVX512F_SCALAR 41129 EXCEPTIONS: AVX512-E3 41130 REAL_OPCODE: Y 41131 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 41132 PATTERN: EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 41133 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 41134 IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 41135 } 41136 41137 41138 # EMITTING VSUBPD (VSUBPD-512-1) 41139 { 41140 ICLASS: VSUBPD 41141 CPL: 3 41142 CATEGORY: AVX512 41143 EXTENSION: AVX512EVEX 41144 ISA_SET: AVX512F_512 41145 EXCEPTIONS: AVX512-E2 41146 REAL_OPCODE: Y 41147 ATTRIBUTES: MXCSR MASKOP_EVEX 41148 PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 41149 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 41150 IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 41151 } 41152 41153 { 41154 ICLASS: VSUBPD 41155 CPL: 3 41156 CATEGORY: AVX512 41157 EXTENSION: AVX512EVEX 41158 ISA_SET: AVX512F_512 41159 EXCEPTIONS: AVX512-E2 41160 REAL_OPCODE: Y 41161 ATTRIBUTES: MXCSR MASKOP_EVEX 41162 PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 41163 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 41164 IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 41165 } 41166 41167 { 41168 ICLASS: VSUBPD 41169 CPL: 3 41170 CATEGORY: AVX512 41171 EXTENSION: AVX512EVEX 41172 ISA_SET: AVX512F_512 41173 EXCEPTIONS: AVX512-E2 41174 REAL_OPCODE: Y 41175 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41176 PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 41177 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 41178 IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 41179 } 41180 41181 41182 # EMITTING VSUBPS (VSUBPS-512-1) 41183 { 41184 ICLASS: VSUBPS 41185 CPL: 3 41186 CATEGORY: AVX512 41187 EXTENSION: AVX512EVEX 41188 ISA_SET: AVX512F_512 41189 EXCEPTIONS: AVX512-E2 41190 REAL_OPCODE: Y 41191 ATTRIBUTES: MXCSR MASKOP_EVEX 41192 PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 41193 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 41194 IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 41195 } 41196 41197 { 41198 ICLASS: VSUBPS 41199 CPL: 3 41200 CATEGORY: AVX512 41201 EXTENSION: AVX512EVEX 41202 ISA_SET: AVX512F_512 41203 EXCEPTIONS: AVX512-E2 41204 REAL_OPCODE: Y 41205 ATTRIBUTES: MXCSR MASKOP_EVEX 41206 PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 41207 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 41208 IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 41209 } 41210 41211 { 41212 ICLASS: VSUBPS 41213 CPL: 3 41214 CATEGORY: AVX512 41215 EXTENSION: AVX512EVEX 41216 ISA_SET: AVX512F_512 41217 EXCEPTIONS: AVX512-E2 41218 REAL_OPCODE: Y 41219 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41220 PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 41221 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 41222 IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 41223 } 41224 41225 41226 # EMITTING VSUBSD (VSUBSD-128-1) 41227 { 41228 ICLASS: VSUBSD 41229 CPL: 3 41230 CATEGORY: AVX512 41231 EXTENSION: AVX512EVEX 41232 ISA_SET: AVX512F_SCALAR 41233 EXCEPTIONS: AVX512-E3 41234 REAL_OPCODE: Y 41235 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 41236 PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 41237 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 41238 IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 41239 } 41240 41241 { 41242 ICLASS: VSUBSD 41243 CPL: 3 41244 CATEGORY: AVX512 41245 EXTENSION: AVX512EVEX 41246 ISA_SET: AVX512F_SCALAR 41247 EXCEPTIONS: AVX512-E3 41248 REAL_OPCODE: Y 41249 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 41250 PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 41251 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 41252 IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 41253 } 41254 41255 { 41256 ICLASS: VSUBSD 41257 CPL: 3 41258 CATEGORY: AVX512 41259 EXTENSION: AVX512EVEX 41260 ISA_SET: AVX512F_SCALAR 41261 EXCEPTIONS: AVX512-E3 41262 REAL_OPCODE: Y 41263 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 41264 PATTERN: EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 41265 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 41266 IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 41267 } 41268 41269 41270 # EMITTING VSUBSS (VSUBSS-128-1) 41271 { 41272 ICLASS: VSUBSS 41273 CPL: 3 41274 CATEGORY: AVX512 41275 EXTENSION: AVX512EVEX 41276 ISA_SET: AVX512F_SCALAR 41277 EXCEPTIONS: AVX512-E3 41278 REAL_OPCODE: Y 41279 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 41280 PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 41281 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 41282 IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 41283 } 41284 41285 { 41286 ICLASS: VSUBSS 41287 CPL: 3 41288 CATEGORY: AVX512 41289 EXTENSION: AVX512EVEX 41290 ISA_SET: AVX512F_SCALAR 41291 EXCEPTIONS: AVX512-E3 41292 REAL_OPCODE: Y 41293 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 41294 PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 41295 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 41296 IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 41297 } 41298 41299 { 41300 ICLASS: VSUBSS 41301 CPL: 3 41302 CATEGORY: AVX512 41303 EXTENSION: AVX512EVEX 41304 ISA_SET: AVX512F_SCALAR 41305 EXCEPTIONS: AVX512-E3 41306 REAL_OPCODE: Y 41307 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 41308 PATTERN: EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 41309 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 41310 IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 41311 } 41312 41313 41314 # EMITTING VUCOMISD (VUCOMISD-128-1) 41315 { 41316 ICLASS: VUCOMISD 41317 CPL: 3 41318 CATEGORY: AVX512 41319 EXTENSION: AVX512EVEX 41320 ISA_SET: AVX512F_SCALAR 41321 EXCEPTIONS: AVX512-E3NF 41322 REAL_OPCODE: Y 41323 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 41324 ATTRIBUTES: MXCSR SIMD_SCALAR 41325 PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 41326 OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 41327 IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 41328 } 41329 41330 { 41331 ICLASS: VUCOMISD 41332 CPL: 3 41333 CATEGORY: AVX512 41334 EXTENSION: AVX512EVEX 41335 ISA_SET: AVX512F_SCALAR 41336 EXCEPTIONS: AVX512-E3NF 41337 REAL_OPCODE: Y 41338 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 41339 ATTRIBUTES: MXCSR SIMD_SCALAR 41340 PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 41341 OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 41342 IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 41343 } 41344 41345 { 41346 ICLASS: VUCOMISD 41347 CPL: 3 41348 CATEGORY: AVX512 41349 EXTENSION: AVX512EVEX 41350 ISA_SET: AVX512F_SCALAR 41351 EXCEPTIONS: AVX512-E3NF 41352 REAL_OPCODE: Y 41353 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 41354 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR 41355 PATTERN: EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 41356 OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 41357 IFORM: VUCOMISD_XMMf64_MEMf64_AVX512 41358 } 41359 41360 41361 # EMITTING VUCOMISS (VUCOMISS-128-1) 41362 { 41363 ICLASS: VUCOMISS 41364 CPL: 3 41365 CATEGORY: AVX512 41366 EXTENSION: AVX512EVEX 41367 ISA_SET: AVX512F_SCALAR 41368 EXCEPTIONS: AVX512-E3NF 41369 REAL_OPCODE: Y 41370 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 41371 ATTRIBUTES: MXCSR SIMD_SCALAR 41372 PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 41373 OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 41374 IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 41375 } 41376 41377 { 41378 ICLASS: VUCOMISS 41379 CPL: 3 41380 CATEGORY: AVX512 41381 EXTENSION: AVX512EVEX 41382 ISA_SET: AVX512F_SCALAR 41383 EXCEPTIONS: AVX512-E3NF 41384 REAL_OPCODE: Y 41385 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 41386 ATTRIBUTES: MXCSR SIMD_SCALAR 41387 PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 41388 OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 41389 IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 41390 } 41391 41392 { 41393 ICLASS: VUCOMISS 41394 CPL: 3 41395 CATEGORY: AVX512 41396 EXTENSION: AVX512EVEX 41397 ISA_SET: AVX512F_SCALAR 41398 EXCEPTIONS: AVX512-E3NF 41399 REAL_OPCODE: Y 41400 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 41401 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR 41402 PATTERN: EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() 41403 OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 41404 IFORM: VUCOMISS_XMMf32_MEMf32_AVX512 41405 } 41406 41407 41408 # EMITTING VUNPCKHPD (VUNPCKHPD-512-1) 41409 { 41410 ICLASS: VUNPCKHPD 41411 CPL: 3 41412 CATEGORY: AVX512 41413 EXTENSION: AVX512EVEX 41414 ISA_SET: AVX512F_512 41415 EXCEPTIONS: AVX512-E4NF 41416 REAL_OPCODE: Y 41417 ATTRIBUTES: MASKOP_EVEX 41418 PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 41419 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 41420 IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 41421 } 41422 41423 { 41424 ICLASS: VUNPCKHPD 41425 CPL: 3 41426 CATEGORY: AVX512 41427 EXTENSION: AVX512EVEX 41428 ISA_SET: AVX512F_512 41429 EXCEPTIONS: AVX512-E4NF 41430 REAL_OPCODE: Y 41431 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41432 PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 41433 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 41434 IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 41435 } 41436 41437 41438 # EMITTING VUNPCKHPS (VUNPCKHPS-512-1) 41439 { 41440 ICLASS: VUNPCKHPS 41441 CPL: 3 41442 CATEGORY: AVX512 41443 EXTENSION: AVX512EVEX 41444 ISA_SET: AVX512F_512 41445 EXCEPTIONS: AVX512-E4NF 41446 REAL_OPCODE: Y 41447 ATTRIBUTES: MASKOP_EVEX 41448 PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 41449 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 41450 IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 41451 } 41452 41453 { 41454 ICLASS: VUNPCKHPS 41455 CPL: 3 41456 CATEGORY: AVX512 41457 EXTENSION: AVX512EVEX 41458 ISA_SET: AVX512F_512 41459 EXCEPTIONS: AVX512-E4NF 41460 REAL_OPCODE: Y 41461 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41462 PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 41463 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 41464 IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 41465 } 41466 41467 41468 # EMITTING VUNPCKLPD (VUNPCKLPD-512-1) 41469 { 41470 ICLASS: VUNPCKLPD 41471 CPL: 3 41472 CATEGORY: AVX512 41473 EXTENSION: AVX512EVEX 41474 ISA_SET: AVX512F_512 41475 EXCEPTIONS: AVX512-E4NF 41476 REAL_OPCODE: Y 41477 ATTRIBUTES: MASKOP_EVEX 41478 PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 41479 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 41480 IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 41481 } 41482 41483 { 41484 ICLASS: VUNPCKLPD 41485 CPL: 3 41486 CATEGORY: AVX512 41487 EXTENSION: AVX512EVEX 41488 ISA_SET: AVX512F_512 41489 EXCEPTIONS: AVX512-E4NF 41490 REAL_OPCODE: Y 41491 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41492 PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 41493 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 41494 IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 41495 } 41496 41497 41498 # EMITTING VUNPCKLPS (VUNPCKLPS-512-1) 41499 { 41500 ICLASS: VUNPCKLPS 41501 CPL: 3 41502 CATEGORY: AVX512 41503 EXTENSION: AVX512EVEX 41504 ISA_SET: AVX512F_512 41505 EXCEPTIONS: AVX512-E4NF 41506 REAL_OPCODE: Y 41507 ATTRIBUTES: MASKOP_EVEX 41508 PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 41509 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 41510 IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 41511 } 41512 41513 { 41514 ICLASS: VUNPCKLPS 41515 CPL: 3 41516 CATEGORY: AVX512 41517 EXTENSION: AVX512EVEX 41518 ISA_SET: AVX512F_512 41519 EXCEPTIONS: AVX512-E4NF 41520 REAL_OPCODE: Y 41521 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41522 PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 41523 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 41524 IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 41525 } 41526 41527 41528 AVX_INSTRUCTIONS():: 41529 # EMITTING KANDNW (KANDNW-256-1) 41530 { 41531 ICLASS: KANDNW 41532 CPL: 3 41533 CATEGORY: KMASK 41534 EXTENSION: AVX512VEX 41535 ISA_SET: AVX512F_KOP 41536 EXCEPTIONS: AVX512-K20 41537 REAL_OPCODE: Y 41538 ATTRIBUTES: KMASK 41539 PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 41540 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 41541 IFORM: KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 41542 } 41543 41544 41545 # EMITTING KANDW (KANDW-256-1) 41546 { 41547 ICLASS: KANDW 41548 CPL: 3 41549 CATEGORY: KMASK 41550 EXTENSION: AVX512VEX 41551 ISA_SET: AVX512F_KOP 41552 EXCEPTIONS: AVX512-K20 41553 REAL_OPCODE: Y 41554 ATTRIBUTES: KMASK 41555 PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 41556 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 41557 IFORM: KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 41558 } 41559 41560 41561 # EMITTING KMOVW (KMOVW-128-1) 41562 { 41563 ICLASS: KMOVW 41564 CPL: 3 41565 CATEGORY: KMASK 41566 EXTENSION: AVX512VEX 41567 ISA_SET: AVX512F_KOP 41568 EXCEPTIONS: AVX512-K21 41569 REAL_OPCODE: Y 41570 ATTRIBUTES: KMASK 41571 PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 41572 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16 41573 IFORM: KMOVW_MASKmskw_MASKu16_AVX512 41574 } 41575 41576 { 41577 ICLASS: KMOVW 41578 CPL: 3 41579 CATEGORY: KMASK 41580 EXTENSION: AVX512VEX 41581 ISA_SET: AVX512F_KOP 41582 EXCEPTIONS: AVX512-K21 41583 REAL_OPCODE: Y 41584 ATTRIBUTES: KMASK 41585 PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR 41586 OPERANDS: REG0=MASK_R():w:mskw MEM0:r:wrd:u16 41587 IFORM: KMOVW_MASKmskw_MEMu16_AVX512 41588 } 41589 41590 41591 # EMITTING KMOVW (KMOVW-128-2) 41592 { 41593 ICLASS: KMOVW 41594 CPL: 3 41595 CATEGORY: KMASK 41596 EXTENSION: AVX512VEX 41597 ISA_SET: AVX512F_KOP 41598 EXCEPTIONS: AVX512-K21 41599 REAL_OPCODE: Y 41600 ATTRIBUTES: KMASK 41601 PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR 41602 OPERANDS: MEM0:w:wrd:u16 REG0=MASK_R():r:mskw 41603 IFORM: KMOVW_MEMu16_MASKmskw_AVX512 41604 } 41605 41606 41607 # EMITTING KMOVW (KMOVW-128-3) 41608 { 41609 ICLASS: KMOVW 41610 CPL: 3 41611 CATEGORY: KMASK 41612 EXTENSION: AVX512VEX 41613 ISA_SET: AVX512F_KOP 41614 EXCEPTIONS: AVX512-K21 41615 REAL_OPCODE: Y 41616 ATTRIBUTES: KMASK 41617 PATTERN: VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 41618 OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 41619 IFORM: KMOVW_MASKmskw_GPR32u32_AVX512 41620 } 41621 41622 41623 # EMITTING KMOVW (KMOVW-128-4) 41624 { 41625 ICLASS: KMOVW 41626 CPL: 3 41627 CATEGORY: KMASK 41628 EXTENSION: AVX512VEX 41629 ISA_SET: AVX512F_KOP 41630 EXCEPTIONS: AVX512-K20 41631 REAL_OPCODE: Y 41632 ATTRIBUTES: KMASK 41633 PATTERN: VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 41634 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw 41635 IFORM: KMOVW_GPR32u32_MASKmskw_AVX512 41636 } 41637 41638 41639 # EMITTING KNOTW (KNOTW-128-1) 41640 { 41641 ICLASS: KNOTW 41642 CPL: 3 41643 CATEGORY: KMASK 41644 EXTENSION: AVX512VEX 41645 ISA_SET: AVX512F_KOP 41646 EXCEPTIONS: AVX512-K20 41647 REAL_OPCODE: Y 41648 ATTRIBUTES: KMASK 41649 PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 41650 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw 41651 IFORM: KNOTW_MASKmskw_MASKmskw_AVX512 41652 } 41653 41654 41655 # EMITTING KORTESTW (KORTESTW-128-1) 41656 { 41657 ICLASS: KORTESTW 41658 CPL: 3 41659 CATEGORY: KMASK 41660 EXTENSION: AVX512VEX 41661 ISA_SET: AVX512F_KOP 41662 EXCEPTIONS: AVX512-K20 41663 REAL_OPCODE: Y 41664 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 41665 ATTRIBUTES: KMASK 41666 PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 41667 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 41668 IFORM: KORTESTW_MASKmskw_MASKmskw_AVX512 41669 } 41670 41671 41672 # EMITTING KORW (KORW-256-1) 41673 { 41674 ICLASS: KORW 41675 CPL: 3 41676 CATEGORY: KMASK 41677 EXTENSION: AVX512VEX 41678 ISA_SET: AVX512F_KOP 41679 EXCEPTIONS: AVX512-K20 41680 REAL_OPCODE: Y 41681 ATTRIBUTES: KMASK 41682 PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 41683 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 41684 IFORM: KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 41685 } 41686 41687 41688 # EMITTING KSHIFTLW (KSHIFTLW-128-1) 41689 { 41690 ICLASS: KSHIFTLW 41691 CPL: 3 41692 CATEGORY: KMASK 41693 EXTENSION: AVX512VEX 41694 ISA_SET: AVX512F_KOP 41695 EXCEPTIONS: AVX512-K20 41696 REAL_OPCODE: Y 41697 ATTRIBUTES: KMASK 41698 PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() 41699 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 41700 IFORM: KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 41701 } 41702 41703 41704 # EMITTING KSHIFTRW (KSHIFTRW-128-1) 41705 { 41706 ICLASS: KSHIFTRW 41707 CPL: 3 41708 CATEGORY: KMASK 41709 EXTENSION: AVX512VEX 41710 ISA_SET: AVX512F_KOP 41711 EXCEPTIONS: AVX512-K20 41712 REAL_OPCODE: Y 41713 ATTRIBUTES: KMASK 41714 PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() 41715 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 41716 IFORM: KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 41717 } 41718 41719 41720 # EMITTING KUNPCKBW (KUNPCKBW-256-1) 41721 { 41722 ICLASS: KUNPCKBW 41723 CPL: 3 41724 CATEGORY: KMASK 41725 EXTENSION: AVX512VEX 41726 ISA_SET: AVX512F_KOP 41727 EXCEPTIONS: AVX512-K20 41728 REAL_OPCODE: Y 41729 ATTRIBUTES: KMASK 41730 PATTERN: VV1 0x4B V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 41731 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 41732 IFORM: KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 41733 } 41734 41735 41736 # EMITTING KXNORW (KXNORW-256-1) 41737 { 41738 ICLASS: KXNORW 41739 CPL: 3 41740 CATEGORY: KMASK 41741 EXTENSION: AVX512VEX 41742 ISA_SET: AVX512F_KOP 41743 EXCEPTIONS: AVX512-K20 41744 REAL_OPCODE: Y 41745 ATTRIBUTES: KMASK 41746 PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 41747 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 41748 IFORM: KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 41749 } 41750 41751 41752 # EMITTING KXORW (KXORW-256-1) 41753 { 41754 ICLASS: KXORW 41755 CPL: 3 41756 CATEGORY: KMASK 41757 EXTENSION: AVX512VEX 41758 ISA_SET: AVX512F_KOP 41759 EXCEPTIONS: AVX512-K20 41760 REAL_OPCODE: Y 41761 ATTRIBUTES: KMASK 41762 PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 41763 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 41764 IFORM: KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 41765 } 41766 41767 41768 41769 41770 ###FILE: ../xed/datafiles/avx512cd/vconflict-isa.xed.txt 41771 41772 #BEGIN_LEGAL 41773 # 41774 #Copyright (c) 2016 Intel Corporation 41775 # 41776 # Licensed under the Apache License, Version 2.0 (the "License"); 41777 # you may not use this file except in compliance with the License. 41778 # You may obtain a copy of the License at 41779 # 41780 # http://www.apache.org/licenses/LICENSE-2.0 41781 # 41782 # Unless required by applicable law or agreed to in writing, software 41783 # distributed under the License is distributed on an "AS IS" BASIS, 41784 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41785 # See the License for the specific language governing permissions and 41786 # limitations under the License. 41787 # 41788 #END_LEGAL 41789 # 41790 # 41791 # 41792 # ***** GENERATED FILE -- DO NOT EDIT! ***** 41793 # ***** GENERATED FILE -- DO NOT EDIT! ***** 41794 # ***** GENERATED FILE -- DO NOT EDIT! ***** 41795 # 41796 # 41797 # 41798 EVEX_INSTRUCTIONS():: 41799 # EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-512-1) 41800 { 41801 ICLASS: VPBROADCASTMB2Q 41802 CPL: 3 41803 CATEGORY: BROADCAST 41804 EXTENSION: AVX512EVEX 41805 ISA_SET: AVX512CD_512 41806 EXCEPTIONS: AVX512-E6NF 41807 REAL_OPCODE: Y 41808 PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 41809 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO8_8 41810 IFORM: VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD 41811 } 41812 41813 41814 # EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-512-1) 41815 { 41816 ICLASS: VPBROADCASTMW2D 41817 CPL: 3 41818 CATEGORY: BROADCAST 41819 EXTENSION: AVX512EVEX 41820 ISA_SET: AVX512CD_512 41821 EXCEPTIONS: AVX512-E6NF 41822 REAL_OPCODE: Y 41823 PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 41824 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO16_16 41825 IFORM: VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD 41826 } 41827 41828 41829 # EMITTING VPCONFLICTD (VPCONFLICTD-512-1) 41830 { 41831 ICLASS: VPCONFLICTD 41832 CPL: 3 41833 CATEGORY: CONFLICT 41834 EXTENSION: AVX512EVEX 41835 ISA_SET: AVX512CD_512 41836 EXCEPTIONS: AVX512-E4 41837 REAL_OPCODE: Y 41838 ATTRIBUTES: MASKOP_EVEX 41839 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 41840 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 41841 IFORM: VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD 41842 } 41843 41844 { 41845 ICLASS: VPCONFLICTD 41846 CPL: 3 41847 CATEGORY: CONFLICT 41848 EXTENSION: AVX512EVEX 41849 ISA_SET: AVX512CD_512 41850 EXCEPTIONS: AVX512-E4 41851 REAL_OPCODE: Y 41852 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41853 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 41854 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 41855 IFORM: VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD 41856 } 41857 41858 41859 # EMITTING VPCONFLICTQ (VPCONFLICTQ-512-1) 41860 { 41861 ICLASS: VPCONFLICTQ 41862 CPL: 3 41863 CATEGORY: CONFLICT 41864 EXTENSION: AVX512EVEX 41865 ISA_SET: AVX512CD_512 41866 EXCEPTIONS: AVX512-E4 41867 REAL_OPCODE: Y 41868 ATTRIBUTES: MASKOP_EVEX 41869 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 41870 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 41871 IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD 41872 } 41873 41874 { 41875 ICLASS: VPCONFLICTQ 41876 CPL: 3 41877 CATEGORY: CONFLICT 41878 EXTENSION: AVX512EVEX 41879 ISA_SET: AVX512CD_512 41880 EXCEPTIONS: AVX512-E4 41881 REAL_OPCODE: Y 41882 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41883 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 41884 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 41885 IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD 41886 } 41887 41888 41889 # EMITTING VPLZCNTD (VPLZCNTD-512-1) 41890 { 41891 ICLASS: VPLZCNTD 41892 CPL: 3 41893 CATEGORY: CONFLICT 41894 EXTENSION: AVX512EVEX 41895 ISA_SET: AVX512CD_512 41896 EXCEPTIONS: AVX512-E4 41897 REAL_OPCODE: Y 41898 ATTRIBUTES: MASKOP_EVEX 41899 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 41900 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 41901 IFORM: VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD 41902 } 41903 41904 { 41905 ICLASS: VPLZCNTD 41906 CPL: 3 41907 CATEGORY: CONFLICT 41908 EXTENSION: AVX512EVEX 41909 ISA_SET: AVX512CD_512 41910 EXCEPTIONS: AVX512-E4 41911 REAL_OPCODE: Y 41912 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41913 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 41914 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 41915 IFORM: VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD 41916 } 41917 41918 41919 # EMITTING VPLZCNTQ (VPLZCNTQ-512-1) 41920 { 41921 ICLASS: VPLZCNTQ 41922 CPL: 3 41923 CATEGORY: CONFLICT 41924 EXTENSION: AVX512EVEX 41925 ISA_SET: AVX512CD_512 41926 EXCEPTIONS: AVX512-E4 41927 REAL_OPCODE: Y 41928 ATTRIBUTES: MASKOP_EVEX 41929 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 41930 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 41931 IFORM: VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD 41932 } 41933 41934 { 41935 ICLASS: VPLZCNTQ 41936 CPL: 3 41937 CATEGORY: CONFLICT 41938 EXTENSION: AVX512EVEX 41939 ISA_SET: AVX512CD_512 41940 EXCEPTIONS: AVX512-E4 41941 REAL_OPCODE: Y 41942 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41943 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 41944 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 41945 IFORM: VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD 41946 } 41947 41948 41949 41950 41951 ###FILE: ../xed/datafiles/avx512-skx/skx-isa.xed.txt 41952 41953 #BEGIN_LEGAL 41954 # 41955 #Copyright (c) 2016 Intel Corporation 41956 # 41957 # Licensed under the Apache License, Version 2.0 (the "License"); 41958 # you may not use this file except in compliance with the License. 41959 # You may obtain a copy of the License at 41960 # 41961 # http://www.apache.org/licenses/LICENSE-2.0 41962 # 41963 # Unless required by applicable law or agreed to in writing, software 41964 # distributed under the License is distributed on an "AS IS" BASIS, 41965 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41966 # See the License for the specific language governing permissions and 41967 # limitations under the License. 41968 # 41969 #END_LEGAL 41970 # 41971 # 41972 # 41973 # ***** GENERATED FILE -- DO NOT EDIT! ***** 41974 # ***** GENERATED FILE -- DO NOT EDIT! ***** 41975 # ***** GENERATED FILE -- DO NOT EDIT! ***** 41976 # 41977 # 41978 # 41979 EVEX_INSTRUCTIONS():: 41980 # EMITTING VADDPD (VADDPD-128-1) 41981 { 41982 ICLASS: VADDPD 41983 CPL: 3 41984 CATEGORY: AVX512 41985 EXTENSION: AVX512EVEX 41986 ISA_SET: AVX512F_128 41987 EXCEPTIONS: AVX512-E2 41988 REAL_OPCODE: Y 41989 ATTRIBUTES: MXCSR MASKOP_EVEX 41990 PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 41991 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 41992 IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 41993 } 41994 41995 { 41996 ICLASS: VADDPD 41997 CPL: 3 41998 CATEGORY: AVX512 41999 EXTENSION: AVX512EVEX 42000 ISA_SET: AVX512F_128 42001 EXCEPTIONS: AVX512-E2 42002 REAL_OPCODE: Y 42003 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42004 PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 42005 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 42006 IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 42007 } 42008 42009 42010 # EMITTING VADDPD (VADDPD-256-1) 42011 { 42012 ICLASS: VADDPD 42013 CPL: 3 42014 CATEGORY: AVX512 42015 EXTENSION: AVX512EVEX 42016 ISA_SET: AVX512F_256 42017 EXCEPTIONS: AVX512-E2 42018 REAL_OPCODE: Y 42019 ATTRIBUTES: MXCSR MASKOP_EVEX 42020 PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 42021 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 42022 IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 42023 } 42024 42025 { 42026 ICLASS: VADDPD 42027 CPL: 3 42028 CATEGORY: AVX512 42029 EXTENSION: AVX512EVEX 42030 ISA_SET: AVX512F_256 42031 EXCEPTIONS: AVX512-E2 42032 REAL_OPCODE: Y 42033 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42034 PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 42035 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 42036 IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 42037 } 42038 42039 42040 # EMITTING VADDPS (VADDPS-128-1) 42041 { 42042 ICLASS: VADDPS 42043 CPL: 3 42044 CATEGORY: AVX512 42045 EXTENSION: AVX512EVEX 42046 ISA_SET: AVX512F_128 42047 EXCEPTIONS: AVX512-E2 42048 REAL_OPCODE: Y 42049 ATTRIBUTES: MXCSR MASKOP_EVEX 42050 PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 42051 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 42052 IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 42053 } 42054 42055 { 42056 ICLASS: VADDPS 42057 CPL: 3 42058 CATEGORY: AVX512 42059 EXTENSION: AVX512EVEX 42060 ISA_SET: AVX512F_128 42061 EXCEPTIONS: AVX512-E2 42062 REAL_OPCODE: Y 42063 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42064 PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 42065 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 42066 IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 42067 } 42068 42069 42070 # EMITTING VADDPS (VADDPS-256-1) 42071 { 42072 ICLASS: VADDPS 42073 CPL: 3 42074 CATEGORY: AVX512 42075 EXTENSION: AVX512EVEX 42076 ISA_SET: AVX512F_256 42077 EXCEPTIONS: AVX512-E2 42078 REAL_OPCODE: Y 42079 ATTRIBUTES: MXCSR MASKOP_EVEX 42080 PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 42081 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 42082 IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 42083 } 42084 42085 { 42086 ICLASS: VADDPS 42087 CPL: 3 42088 CATEGORY: AVX512 42089 EXTENSION: AVX512EVEX 42090 ISA_SET: AVX512F_256 42091 EXCEPTIONS: AVX512-E2 42092 REAL_OPCODE: Y 42093 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42094 PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 42095 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 42096 IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 42097 } 42098 42099 42100 # EMITTING VALIGND (VALIGND-128-1) 42101 { 42102 ICLASS: VALIGND 42103 CPL: 3 42104 CATEGORY: AVX512 42105 EXTENSION: AVX512EVEX 42106 ISA_SET: AVX512F_128 42107 EXCEPTIONS: AVX512-E4NF 42108 REAL_OPCODE: Y 42109 ATTRIBUTES: MASKOP_EVEX 42110 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 42111 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 42112 IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 42113 } 42114 42115 { 42116 ICLASS: VALIGND 42117 CPL: 3 42118 CATEGORY: AVX512 42119 EXTENSION: AVX512EVEX 42120 ISA_SET: AVX512F_128 42121 EXCEPTIONS: AVX512-E4NF 42122 REAL_OPCODE: Y 42123 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42124 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 42125 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 42126 IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 42127 } 42128 42129 42130 # EMITTING VALIGND (VALIGND-256-1) 42131 { 42132 ICLASS: VALIGND 42133 CPL: 3 42134 CATEGORY: AVX512 42135 EXTENSION: AVX512EVEX 42136 ISA_SET: AVX512F_256 42137 EXCEPTIONS: AVX512-E4NF 42138 REAL_OPCODE: Y 42139 ATTRIBUTES: MASKOP_EVEX 42140 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 42141 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 42142 IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 42143 } 42144 42145 { 42146 ICLASS: VALIGND 42147 CPL: 3 42148 CATEGORY: AVX512 42149 EXTENSION: AVX512EVEX 42150 ISA_SET: AVX512F_256 42151 EXCEPTIONS: AVX512-E4NF 42152 REAL_OPCODE: Y 42153 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42154 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 42155 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 42156 IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 42157 } 42158 42159 42160 # EMITTING VALIGNQ (VALIGNQ-128-1) 42161 { 42162 ICLASS: VALIGNQ 42163 CPL: 3 42164 CATEGORY: AVX512 42165 EXTENSION: AVX512EVEX 42166 ISA_SET: AVX512F_128 42167 EXCEPTIONS: AVX512-E4NF 42168 REAL_OPCODE: Y 42169 ATTRIBUTES: MASKOP_EVEX 42170 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 42171 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 42172 IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 42173 } 42174 42175 { 42176 ICLASS: VALIGNQ 42177 CPL: 3 42178 CATEGORY: AVX512 42179 EXTENSION: AVX512EVEX 42180 ISA_SET: AVX512F_128 42181 EXCEPTIONS: AVX512-E4NF 42182 REAL_OPCODE: Y 42183 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42184 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 42185 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 42186 IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 42187 } 42188 42189 42190 # EMITTING VALIGNQ (VALIGNQ-256-1) 42191 { 42192 ICLASS: VALIGNQ 42193 CPL: 3 42194 CATEGORY: AVX512 42195 EXTENSION: AVX512EVEX 42196 ISA_SET: AVX512F_256 42197 EXCEPTIONS: AVX512-E4NF 42198 REAL_OPCODE: Y 42199 ATTRIBUTES: MASKOP_EVEX 42200 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 42201 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 42202 IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 42203 } 42204 42205 { 42206 ICLASS: VALIGNQ 42207 CPL: 3 42208 CATEGORY: AVX512 42209 EXTENSION: AVX512EVEX 42210 ISA_SET: AVX512F_256 42211 EXCEPTIONS: AVX512-E4NF 42212 REAL_OPCODE: Y 42213 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42214 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 42215 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 42216 IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 42217 } 42218 42219 42220 # EMITTING VANDNPD (VANDNPD-128-1) 42221 { 42222 ICLASS: VANDNPD 42223 CPL: 3 42224 CATEGORY: LOGICAL_FP 42225 EXTENSION: AVX512EVEX 42226 ISA_SET: AVX512DQ_128 42227 EXCEPTIONS: AVX512-E4 42228 REAL_OPCODE: Y 42229 ATTRIBUTES: MASKOP_EVEX 42230 PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 42231 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 42232 IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 42233 } 42234 42235 { 42236 ICLASS: VANDNPD 42237 CPL: 3 42238 CATEGORY: LOGICAL_FP 42239 EXTENSION: AVX512EVEX 42240 ISA_SET: AVX512DQ_128 42241 EXCEPTIONS: AVX512-E4 42242 REAL_OPCODE: Y 42243 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42244 PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 42245 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 42246 IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 42247 } 42248 42249 42250 # EMITTING VANDNPD (VANDNPD-256-1) 42251 { 42252 ICLASS: VANDNPD 42253 CPL: 3 42254 CATEGORY: LOGICAL_FP 42255 EXTENSION: AVX512EVEX 42256 ISA_SET: AVX512DQ_256 42257 EXCEPTIONS: AVX512-E4 42258 REAL_OPCODE: Y 42259 ATTRIBUTES: MASKOP_EVEX 42260 PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 42261 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 42262 IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 42263 } 42264 42265 { 42266 ICLASS: VANDNPD 42267 CPL: 3 42268 CATEGORY: LOGICAL_FP 42269 EXTENSION: AVX512EVEX 42270 ISA_SET: AVX512DQ_256 42271 EXCEPTIONS: AVX512-E4 42272 REAL_OPCODE: Y 42273 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42274 PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 42275 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 42276 IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 42277 } 42278 42279 42280 # EMITTING VANDNPD (VANDNPD-512-1) 42281 { 42282 ICLASS: VANDNPD 42283 CPL: 3 42284 CATEGORY: LOGICAL_FP 42285 EXTENSION: AVX512EVEX 42286 ISA_SET: AVX512DQ_512 42287 EXCEPTIONS: AVX512-E4 42288 REAL_OPCODE: Y 42289 ATTRIBUTES: MASKOP_EVEX 42290 PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 42291 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 42292 IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 42293 } 42294 42295 { 42296 ICLASS: VANDNPD 42297 CPL: 3 42298 CATEGORY: LOGICAL_FP 42299 EXTENSION: AVX512EVEX 42300 ISA_SET: AVX512DQ_512 42301 EXCEPTIONS: AVX512-E4 42302 REAL_OPCODE: Y 42303 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42304 PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 42305 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 42306 IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 42307 } 42308 42309 42310 # EMITTING VANDNPS (VANDNPS-128-1) 42311 { 42312 ICLASS: VANDNPS 42313 CPL: 3 42314 CATEGORY: LOGICAL_FP 42315 EXTENSION: AVX512EVEX 42316 ISA_SET: AVX512DQ_128 42317 EXCEPTIONS: AVX512-E4 42318 REAL_OPCODE: Y 42319 ATTRIBUTES: MASKOP_EVEX 42320 PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 42321 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 42322 IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 42323 } 42324 42325 { 42326 ICLASS: VANDNPS 42327 CPL: 3 42328 CATEGORY: LOGICAL_FP 42329 EXTENSION: AVX512EVEX 42330 ISA_SET: AVX512DQ_128 42331 EXCEPTIONS: AVX512-E4 42332 REAL_OPCODE: Y 42333 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42334 PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 42335 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 42336 IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 42337 } 42338 42339 42340 # EMITTING VANDNPS (VANDNPS-256-1) 42341 { 42342 ICLASS: VANDNPS 42343 CPL: 3 42344 CATEGORY: LOGICAL_FP 42345 EXTENSION: AVX512EVEX 42346 ISA_SET: AVX512DQ_256 42347 EXCEPTIONS: AVX512-E4 42348 REAL_OPCODE: Y 42349 ATTRIBUTES: MASKOP_EVEX 42350 PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 42351 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 42352 IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 42353 } 42354 42355 { 42356 ICLASS: VANDNPS 42357 CPL: 3 42358 CATEGORY: LOGICAL_FP 42359 EXTENSION: AVX512EVEX 42360 ISA_SET: AVX512DQ_256 42361 EXCEPTIONS: AVX512-E4 42362 REAL_OPCODE: Y 42363 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42364 PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 42365 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 42366 IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 42367 } 42368 42369 42370 # EMITTING VANDNPS (VANDNPS-512-1) 42371 { 42372 ICLASS: VANDNPS 42373 CPL: 3 42374 CATEGORY: LOGICAL_FP 42375 EXTENSION: AVX512EVEX 42376 ISA_SET: AVX512DQ_512 42377 EXCEPTIONS: AVX512-E4 42378 REAL_OPCODE: Y 42379 ATTRIBUTES: MASKOP_EVEX 42380 PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 42381 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 42382 IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 42383 } 42384 42385 { 42386 ICLASS: VANDNPS 42387 CPL: 3 42388 CATEGORY: LOGICAL_FP 42389 EXTENSION: AVX512EVEX 42390 ISA_SET: AVX512DQ_512 42391 EXCEPTIONS: AVX512-E4 42392 REAL_OPCODE: Y 42393 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42394 PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 42395 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 42396 IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 42397 } 42398 42399 42400 # EMITTING VANDPD (VANDPD-128-1) 42401 { 42402 ICLASS: VANDPD 42403 CPL: 3 42404 CATEGORY: LOGICAL_FP 42405 EXTENSION: AVX512EVEX 42406 ISA_SET: AVX512DQ_128 42407 EXCEPTIONS: AVX512-E4 42408 REAL_OPCODE: Y 42409 ATTRIBUTES: MASKOP_EVEX 42410 PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 42411 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 42412 IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 42413 } 42414 42415 { 42416 ICLASS: VANDPD 42417 CPL: 3 42418 CATEGORY: LOGICAL_FP 42419 EXTENSION: AVX512EVEX 42420 ISA_SET: AVX512DQ_128 42421 EXCEPTIONS: AVX512-E4 42422 REAL_OPCODE: Y 42423 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42424 PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 42425 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 42426 IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 42427 } 42428 42429 42430 # EMITTING VANDPD (VANDPD-256-1) 42431 { 42432 ICLASS: VANDPD 42433 CPL: 3 42434 CATEGORY: LOGICAL_FP 42435 EXTENSION: AVX512EVEX 42436 ISA_SET: AVX512DQ_256 42437 EXCEPTIONS: AVX512-E4 42438 REAL_OPCODE: Y 42439 ATTRIBUTES: MASKOP_EVEX 42440 PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 42441 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 42442 IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 42443 } 42444 42445 { 42446 ICLASS: VANDPD 42447 CPL: 3 42448 CATEGORY: LOGICAL_FP 42449 EXTENSION: AVX512EVEX 42450 ISA_SET: AVX512DQ_256 42451 EXCEPTIONS: AVX512-E4 42452 REAL_OPCODE: Y 42453 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42454 PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 42455 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 42456 IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 42457 } 42458 42459 42460 # EMITTING VANDPD (VANDPD-512-1) 42461 { 42462 ICLASS: VANDPD 42463 CPL: 3 42464 CATEGORY: LOGICAL_FP 42465 EXTENSION: AVX512EVEX 42466 ISA_SET: AVX512DQ_512 42467 EXCEPTIONS: AVX512-E4 42468 REAL_OPCODE: Y 42469 ATTRIBUTES: MASKOP_EVEX 42470 PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 42471 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 42472 IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 42473 } 42474 42475 { 42476 ICLASS: VANDPD 42477 CPL: 3 42478 CATEGORY: LOGICAL_FP 42479 EXTENSION: AVX512EVEX 42480 ISA_SET: AVX512DQ_512 42481 EXCEPTIONS: AVX512-E4 42482 REAL_OPCODE: Y 42483 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42484 PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 42485 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 42486 IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 42487 } 42488 42489 42490 # EMITTING VANDPS (VANDPS-128-1) 42491 { 42492 ICLASS: VANDPS 42493 CPL: 3 42494 CATEGORY: LOGICAL_FP 42495 EXTENSION: AVX512EVEX 42496 ISA_SET: AVX512DQ_128 42497 EXCEPTIONS: AVX512-E4 42498 REAL_OPCODE: Y 42499 ATTRIBUTES: MASKOP_EVEX 42500 PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 42501 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 42502 IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 42503 } 42504 42505 { 42506 ICLASS: VANDPS 42507 CPL: 3 42508 CATEGORY: LOGICAL_FP 42509 EXTENSION: AVX512EVEX 42510 ISA_SET: AVX512DQ_128 42511 EXCEPTIONS: AVX512-E4 42512 REAL_OPCODE: Y 42513 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42514 PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 42515 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 42516 IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 42517 } 42518 42519 42520 # EMITTING VANDPS (VANDPS-256-1) 42521 { 42522 ICLASS: VANDPS 42523 CPL: 3 42524 CATEGORY: LOGICAL_FP 42525 EXTENSION: AVX512EVEX 42526 ISA_SET: AVX512DQ_256 42527 EXCEPTIONS: AVX512-E4 42528 REAL_OPCODE: Y 42529 ATTRIBUTES: MASKOP_EVEX 42530 PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 42531 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 42532 IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 42533 } 42534 42535 { 42536 ICLASS: VANDPS 42537 CPL: 3 42538 CATEGORY: LOGICAL_FP 42539 EXTENSION: AVX512EVEX 42540 ISA_SET: AVX512DQ_256 42541 EXCEPTIONS: AVX512-E4 42542 REAL_OPCODE: Y 42543 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42544 PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 42545 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 42546 IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 42547 } 42548 42549 42550 # EMITTING VANDPS (VANDPS-512-1) 42551 { 42552 ICLASS: VANDPS 42553 CPL: 3 42554 CATEGORY: LOGICAL_FP 42555 EXTENSION: AVX512EVEX 42556 ISA_SET: AVX512DQ_512 42557 EXCEPTIONS: AVX512-E4 42558 REAL_OPCODE: Y 42559 ATTRIBUTES: MASKOP_EVEX 42560 PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 42561 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 42562 IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 42563 } 42564 42565 { 42566 ICLASS: VANDPS 42567 CPL: 3 42568 CATEGORY: LOGICAL_FP 42569 EXTENSION: AVX512EVEX 42570 ISA_SET: AVX512DQ_512 42571 EXCEPTIONS: AVX512-E4 42572 REAL_OPCODE: Y 42573 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42574 PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 42575 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 42576 IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 42577 } 42578 42579 42580 # EMITTING VBLENDMPD (VBLENDMPD-128-1) 42581 { 42582 ICLASS: VBLENDMPD 42583 CPL: 3 42584 CATEGORY: BLEND 42585 EXTENSION: AVX512EVEX 42586 ISA_SET: AVX512F_128 42587 EXCEPTIONS: AVX512-E4 42588 REAL_OPCODE: Y 42589 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 42590 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 42591 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 42592 IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 42593 } 42594 42595 { 42596 ICLASS: VBLENDMPD 42597 CPL: 3 42598 CATEGORY: BLEND 42599 EXTENSION: AVX512EVEX 42600 ISA_SET: AVX512F_128 42601 EXCEPTIONS: AVX512-E4 42602 REAL_OPCODE: Y 42603 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 42604 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 42605 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 42606 IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 42607 } 42608 42609 42610 # EMITTING VBLENDMPD (VBLENDMPD-256-1) 42611 { 42612 ICLASS: VBLENDMPD 42613 CPL: 3 42614 CATEGORY: BLEND 42615 EXTENSION: AVX512EVEX 42616 ISA_SET: AVX512F_256 42617 EXCEPTIONS: AVX512-E4 42618 REAL_OPCODE: Y 42619 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 42620 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 42621 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 42622 IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 42623 } 42624 42625 { 42626 ICLASS: VBLENDMPD 42627 CPL: 3 42628 CATEGORY: BLEND 42629 EXTENSION: AVX512EVEX 42630 ISA_SET: AVX512F_256 42631 EXCEPTIONS: AVX512-E4 42632 REAL_OPCODE: Y 42633 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 42634 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 42635 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 42636 IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 42637 } 42638 42639 42640 # EMITTING VBLENDMPS (VBLENDMPS-128-1) 42641 { 42642 ICLASS: VBLENDMPS 42643 CPL: 3 42644 CATEGORY: BLEND 42645 EXTENSION: AVX512EVEX 42646 ISA_SET: AVX512F_128 42647 EXCEPTIONS: AVX512-E4 42648 REAL_OPCODE: Y 42649 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 42650 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 42651 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 42652 IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 42653 } 42654 42655 { 42656 ICLASS: VBLENDMPS 42657 CPL: 3 42658 CATEGORY: BLEND 42659 EXTENSION: AVX512EVEX 42660 ISA_SET: AVX512F_128 42661 EXCEPTIONS: AVX512-E4 42662 REAL_OPCODE: Y 42663 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 42664 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 42665 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 42666 IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 42667 } 42668 42669 42670 # EMITTING VBLENDMPS (VBLENDMPS-256-1) 42671 { 42672 ICLASS: VBLENDMPS 42673 CPL: 3 42674 CATEGORY: BLEND 42675 EXTENSION: AVX512EVEX 42676 ISA_SET: AVX512F_256 42677 EXCEPTIONS: AVX512-E4 42678 REAL_OPCODE: Y 42679 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 42680 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 42681 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 42682 IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 42683 } 42684 42685 { 42686 ICLASS: VBLENDMPS 42687 CPL: 3 42688 CATEGORY: BLEND 42689 EXTENSION: AVX512EVEX 42690 ISA_SET: AVX512F_256 42691 EXCEPTIONS: AVX512-E4 42692 REAL_OPCODE: Y 42693 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 42694 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 42695 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 42696 IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 42697 } 42698 42699 42700 # EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-256-1) 42701 { 42702 ICLASS: VBROADCASTF32X2 42703 CPL: 3 42704 CATEGORY: BROADCAST 42705 EXTENSION: AVX512EVEX 42706 ISA_SET: AVX512DQ_256 42707 EXCEPTIONS: AVX512-E6 42708 REAL_OPCODE: Y 42709 ATTRIBUTES: MASKOP_EVEX 42710 PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 42711 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO8_32 42712 IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 42713 } 42714 42715 { 42716 ICLASS: VBROADCASTF32X2 42717 CPL: 3 42718 CATEGORY: BROADCAST 42719 EXTENSION: AVX512EVEX 42720 ISA_SET: AVX512DQ_256 42721 EXCEPTIONS: AVX512-E6 42722 REAL_OPCODE: Y 42723 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 42724 PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() 42725 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO8_32 42726 IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 42727 } 42728 42729 42730 # EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-512-1) 42731 { 42732 ICLASS: VBROADCASTF32X2 42733 CPL: 3 42734 CATEGORY: BROADCAST 42735 EXTENSION: AVX512EVEX 42736 ISA_SET: AVX512DQ_512 42737 EXCEPTIONS: AVX512-E6 42738 REAL_OPCODE: Y 42739 ATTRIBUTES: MASKOP_EVEX 42740 PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 42741 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO16_32 42742 IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 42743 } 42744 42745 { 42746 ICLASS: VBROADCASTF32X2 42747 CPL: 3 42748 CATEGORY: BROADCAST 42749 EXTENSION: AVX512EVEX 42750 ISA_SET: AVX512DQ_512 42751 EXCEPTIONS: AVX512-E6 42752 REAL_OPCODE: Y 42753 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 42754 PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() 42755 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO16_32 42756 IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 42757 } 42758 42759 42760 # EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-256-1) 42761 { 42762 ICLASS: VBROADCASTF32X4 42763 CPL: 3 42764 CATEGORY: BROADCAST 42765 EXTENSION: AVX512EVEX 42766 ISA_SET: AVX512F_256 42767 EXCEPTIONS: AVX512-E6 42768 REAL_OPCODE: Y 42769 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 42770 PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() 42771 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO8_32 42772 IFORM: VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 42773 } 42774 42775 42776 # EMITTING VBROADCASTF32X8 (VBROADCASTF32X8-512-1) 42777 { 42778 ICLASS: VBROADCASTF32X8 42779 CPL: 3 42780 CATEGORY: BROADCAST 42781 EXTENSION: AVX512EVEX 42782 ISA_SET: AVX512DQ_512 42783 EXCEPTIONS: AVX512-E6 42784 REAL_OPCODE: Y 42785 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 42786 PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() 42787 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 EMX_BROADCAST_8TO16_32 42788 IFORM: VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 42789 } 42790 42791 42792 # EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-256-1) 42793 { 42794 ICLASS: VBROADCASTF64X2 42795 CPL: 3 42796 CATEGORY: BROADCAST 42797 EXTENSION: AVX512EVEX 42798 ISA_SET: AVX512DQ_256 42799 EXCEPTIONS: AVX512-E6 42800 REAL_OPCODE: Y 42801 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 42802 PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() 42803 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 42804 IFORM: VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 42805 } 42806 42807 42808 # EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-512-1) 42809 { 42810 ICLASS: VBROADCASTF64X2 42811 CPL: 3 42812 CATEGORY: BROADCAST 42813 EXTENSION: AVX512EVEX 42814 ISA_SET: AVX512DQ_512 42815 EXCEPTIONS: AVX512-E6 42816 REAL_OPCODE: Y 42817 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 42818 PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() 42819 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO8_64 42820 IFORM: VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 42821 } 42822 42823 42824 # EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-128-1) 42825 { 42826 ICLASS: VBROADCASTI32X2 42827 CPL: 3 42828 CATEGORY: BROADCAST 42829 EXTENSION: AVX512EVEX 42830 ISA_SET: AVX512DQ_128 42831 EXCEPTIONS: AVX512-E6 42832 REAL_OPCODE: Y 42833 ATTRIBUTES: MASKOP_EVEX 42834 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 42835 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO4_32 42836 IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 42837 } 42838 42839 { 42840 ICLASS: VBROADCASTI32X2 42841 CPL: 3 42842 CATEGORY: BROADCAST 42843 EXTENSION: AVX512EVEX 42844 ISA_SET: AVX512DQ_128 42845 EXCEPTIONS: AVX512-E6 42846 REAL_OPCODE: Y 42847 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 42848 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() 42849 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO4_32 42850 IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 42851 } 42852 42853 42854 # EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-256-1) 42855 { 42856 ICLASS: VBROADCASTI32X2 42857 CPL: 3 42858 CATEGORY: BROADCAST 42859 EXTENSION: AVX512EVEX 42860 ISA_SET: AVX512DQ_256 42861 EXCEPTIONS: AVX512-E6 42862 REAL_OPCODE: Y 42863 ATTRIBUTES: MASKOP_EVEX 42864 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 42865 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO8_32 42866 IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 42867 } 42868 42869 { 42870 ICLASS: VBROADCASTI32X2 42871 CPL: 3 42872 CATEGORY: BROADCAST 42873 EXTENSION: AVX512EVEX 42874 ISA_SET: AVX512DQ_256 42875 EXCEPTIONS: AVX512-E6 42876 REAL_OPCODE: Y 42877 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 42878 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() 42879 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO8_32 42880 IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 42881 } 42882 42883 42884 # EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-512-1) 42885 { 42886 ICLASS: VBROADCASTI32X2 42887 CPL: 3 42888 CATEGORY: BROADCAST 42889 EXTENSION: AVX512EVEX 42890 ISA_SET: AVX512DQ_512 42891 EXCEPTIONS: AVX512-E6 42892 REAL_OPCODE: Y 42893 ATTRIBUTES: MASKOP_EVEX 42894 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 42895 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO16_32 42896 IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 42897 } 42898 42899 { 42900 ICLASS: VBROADCASTI32X2 42901 CPL: 3 42902 CATEGORY: BROADCAST 42903 EXTENSION: AVX512EVEX 42904 ISA_SET: AVX512DQ_512 42905 EXCEPTIONS: AVX512-E6 42906 REAL_OPCODE: Y 42907 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 42908 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() 42909 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO16_32 42910 IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 42911 } 42912 42913 42914 # EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-256-1) 42915 { 42916 ICLASS: VBROADCASTI32X4 42917 CPL: 3 42918 CATEGORY: BROADCAST 42919 EXTENSION: AVX512EVEX 42920 ISA_SET: AVX512F_256 42921 EXCEPTIONS: AVX512-E6 42922 REAL_OPCODE: Y 42923 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 42924 PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() 42925 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO8_32 42926 IFORM: VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 42927 } 42928 42929 42930 # EMITTING VBROADCASTI32X8 (VBROADCASTI32X8-512-1) 42931 { 42932 ICLASS: VBROADCASTI32X8 42933 CPL: 3 42934 CATEGORY: BROADCAST 42935 EXTENSION: AVX512EVEX 42936 ISA_SET: AVX512DQ_512 42937 EXCEPTIONS: AVX512-E6 42938 REAL_OPCODE: Y 42939 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 42940 PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() 42941 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 EMX_BROADCAST_8TO16_32 42942 IFORM: VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 42943 } 42944 42945 42946 # EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-256-1) 42947 { 42948 ICLASS: VBROADCASTI64X2 42949 CPL: 3 42950 CATEGORY: BROADCAST 42951 EXTENSION: AVX512EVEX 42952 ISA_SET: AVX512DQ_256 42953 EXCEPTIONS: AVX512-E6 42954 REAL_OPCODE: Y 42955 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 42956 PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() 42957 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO4_64 42958 IFORM: VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 42959 } 42960 42961 42962 # EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-512-1) 42963 { 42964 ICLASS: VBROADCASTI64X2 42965 CPL: 3 42966 CATEGORY: BROADCAST 42967 EXTENSION: AVX512EVEX 42968 ISA_SET: AVX512DQ_512 42969 EXCEPTIONS: AVX512-E6 42970 REAL_OPCODE: Y 42971 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 42972 PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() 42973 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO8_64 42974 IFORM: VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 42975 } 42976 42977 42978 # EMITTING VBROADCASTSD (VBROADCASTSD-256-1) 42979 { 42980 ICLASS: VBROADCASTSD 42981 CPL: 3 42982 CATEGORY: BROADCAST 42983 EXTENSION: AVX512EVEX 42984 ISA_SET: AVX512F_256 42985 EXCEPTIONS: AVX512-E6 42986 REAL_OPCODE: Y 42987 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 42988 PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() 42989 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 42990 IFORM: VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 42991 } 42992 42993 42994 # EMITTING VBROADCASTSD (VBROADCASTSD-256-2) 42995 { 42996 ICLASS: VBROADCASTSD 42997 CPL: 3 42998 CATEGORY: BROADCAST 42999 EXTENSION: AVX512EVEX 43000 ISA_SET: AVX512F_256 43001 EXCEPTIONS: AVX512-E6 43002 REAL_OPCODE: Y 43003 ATTRIBUTES: MASKOP_EVEX 43004 PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 43005 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO4_64 43006 IFORM: VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 43007 } 43008 43009 43010 # EMITTING VBROADCASTSS (VBROADCASTSS-128-1) 43011 { 43012 ICLASS: VBROADCASTSS 43013 CPL: 3 43014 CATEGORY: BROADCAST 43015 EXTENSION: AVX512EVEX 43016 ISA_SET: AVX512F_128 43017 EXCEPTIONS: AVX512-E6 43018 REAL_OPCODE: Y 43019 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 43020 PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 43021 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 43022 IFORM: VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 43023 } 43024 43025 43026 # EMITTING VBROADCASTSS (VBROADCASTSS-128-2) 43027 { 43028 ICLASS: VBROADCASTSS 43029 CPL: 3 43030 CATEGORY: BROADCAST 43031 EXTENSION: AVX512EVEX 43032 ISA_SET: AVX512F_128 43033 EXCEPTIONS: AVX512-E6 43034 REAL_OPCODE: Y 43035 ATTRIBUTES: MASKOP_EVEX 43036 PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43037 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO4_32 43038 IFORM: VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 43039 } 43040 43041 43042 # EMITTING VBROADCASTSS (VBROADCASTSS-256-1) 43043 { 43044 ICLASS: VBROADCASTSS 43045 CPL: 3 43046 CATEGORY: BROADCAST 43047 EXTENSION: AVX512EVEX 43048 ISA_SET: AVX512F_256 43049 EXCEPTIONS: AVX512-E6 43050 REAL_OPCODE: Y 43051 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 43052 PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 43053 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 43054 IFORM: VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 43055 } 43056 43057 43058 # EMITTING VBROADCASTSS (VBROADCASTSS-256-2) 43059 { 43060 ICLASS: VBROADCASTSS 43061 CPL: 3 43062 CATEGORY: BROADCAST 43063 EXTENSION: AVX512EVEX 43064 ISA_SET: AVX512F_256 43065 EXCEPTIONS: AVX512-E6 43066 REAL_OPCODE: Y 43067 ATTRIBUTES: MASKOP_EVEX 43068 PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43069 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO8_32 43070 IFORM: VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 43071 } 43072 43073 43074 # EMITTING VCMPPD (VCMPPD-128-1) 43075 { 43076 ICLASS: VCMPPD 43077 CPL: 3 43078 CATEGORY: AVX512 43079 EXTENSION: AVX512EVEX 43080 ISA_SET: AVX512F_128 43081 EXCEPTIONS: AVX512-E2 43082 REAL_OPCODE: Y 43083 ATTRIBUTES: MXCSR MASKOP_EVEX 43084 PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() 43085 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 43086 IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 43087 } 43088 43089 { 43090 ICLASS: VCMPPD 43091 CPL: 3 43092 CATEGORY: AVX512 43093 EXTENSION: AVX512EVEX 43094 ISA_SET: AVX512F_128 43095 EXCEPTIONS: AVX512-E2 43096 REAL_OPCODE: Y 43097 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43098 PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 43099 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 43100 IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 43101 } 43102 43103 43104 # EMITTING VCMPPD (VCMPPD-256-1) 43105 { 43106 ICLASS: VCMPPD 43107 CPL: 3 43108 CATEGORY: AVX512 43109 EXTENSION: AVX512EVEX 43110 ISA_SET: AVX512F_256 43111 EXCEPTIONS: AVX512-E2 43112 REAL_OPCODE: Y 43113 ATTRIBUTES: MXCSR MASKOP_EVEX 43114 PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() 43115 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 43116 IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 43117 } 43118 43119 { 43120 ICLASS: VCMPPD 43121 CPL: 3 43122 CATEGORY: AVX512 43123 EXTENSION: AVX512EVEX 43124 ISA_SET: AVX512F_256 43125 EXCEPTIONS: AVX512-E2 43126 REAL_OPCODE: Y 43127 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43128 PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 43129 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 43130 IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 43131 } 43132 43133 43134 # EMITTING VCMPPS (VCMPPS-128-1) 43135 { 43136 ICLASS: VCMPPS 43137 CPL: 3 43138 CATEGORY: AVX512 43139 EXTENSION: AVX512EVEX 43140 ISA_SET: AVX512F_128 43141 EXCEPTIONS: AVX512-E2 43142 REAL_OPCODE: Y 43143 ATTRIBUTES: MXCSR MASKOP_EVEX 43144 PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() 43145 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 43146 IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 43147 } 43148 43149 { 43150 ICLASS: VCMPPS 43151 CPL: 3 43152 CATEGORY: AVX512 43153 EXTENSION: AVX512EVEX 43154 ISA_SET: AVX512F_128 43155 EXCEPTIONS: AVX512-E2 43156 REAL_OPCODE: Y 43157 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43158 PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 43159 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 43160 IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 43161 } 43162 43163 43164 # EMITTING VCMPPS (VCMPPS-256-1) 43165 { 43166 ICLASS: VCMPPS 43167 CPL: 3 43168 CATEGORY: AVX512 43169 EXTENSION: AVX512EVEX 43170 ISA_SET: AVX512F_256 43171 EXCEPTIONS: AVX512-E2 43172 REAL_OPCODE: Y 43173 ATTRIBUTES: MXCSR MASKOP_EVEX 43174 PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() 43175 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 43176 IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 43177 } 43178 43179 { 43180 ICLASS: VCMPPS 43181 CPL: 3 43182 CATEGORY: AVX512 43183 EXTENSION: AVX512EVEX 43184 ISA_SET: AVX512F_256 43185 EXCEPTIONS: AVX512-E2 43186 REAL_OPCODE: Y 43187 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43188 PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 43189 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 43190 IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 43191 } 43192 43193 43194 # EMITTING VCOMPRESSPD (VCOMPRESSPD-128-1) 43195 { 43196 ICLASS: VCOMPRESSPD 43197 CPL: 3 43198 CATEGORY: COMPRESS 43199 EXTENSION: AVX512EVEX 43200 ISA_SET: AVX512F_128 43201 EXCEPTIONS: AVX512-E4 43202 REAL_OPCODE: Y 43203 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 43204 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 43205 OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 43206 IFORM: VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 43207 } 43208 43209 43210 # EMITTING VCOMPRESSPD (VCOMPRESSPD-128-2) 43211 { 43212 ICLASS: VCOMPRESSPD 43213 CPL: 3 43214 CATEGORY: COMPRESS 43215 EXTENSION: AVX512EVEX 43216 ISA_SET: AVX512F_128 43217 EXCEPTIONS: AVX512-E4 43218 REAL_OPCODE: Y 43219 ATTRIBUTES: MASKOP_EVEX 43220 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 43221 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 43222 IFORM: VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 43223 } 43224 43225 43226 # EMITTING VCOMPRESSPD (VCOMPRESSPD-256-1) 43227 { 43228 ICLASS: VCOMPRESSPD 43229 CPL: 3 43230 CATEGORY: COMPRESS 43231 EXTENSION: AVX512EVEX 43232 ISA_SET: AVX512F_256 43233 EXCEPTIONS: AVX512-E4 43234 REAL_OPCODE: Y 43235 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 43236 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 43237 OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 43238 IFORM: VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 43239 } 43240 43241 43242 # EMITTING VCOMPRESSPD (VCOMPRESSPD-256-2) 43243 { 43244 ICLASS: VCOMPRESSPD 43245 CPL: 3 43246 CATEGORY: COMPRESS 43247 EXTENSION: AVX512EVEX 43248 ISA_SET: AVX512F_256 43249 EXCEPTIONS: AVX512-E4 43250 REAL_OPCODE: Y 43251 ATTRIBUTES: MASKOP_EVEX 43252 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 43253 OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 43254 IFORM: VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 43255 } 43256 43257 43258 # EMITTING VCOMPRESSPS (VCOMPRESSPS-128-1) 43259 { 43260 ICLASS: VCOMPRESSPS 43261 CPL: 3 43262 CATEGORY: COMPRESS 43263 EXTENSION: AVX512EVEX 43264 ISA_SET: AVX512F_128 43265 EXCEPTIONS: AVX512-E4 43266 REAL_OPCODE: Y 43267 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 43268 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 43269 OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 43270 IFORM: VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 43271 } 43272 43273 43274 # EMITTING VCOMPRESSPS (VCOMPRESSPS-128-2) 43275 { 43276 ICLASS: VCOMPRESSPS 43277 CPL: 3 43278 CATEGORY: COMPRESS 43279 EXTENSION: AVX512EVEX 43280 ISA_SET: AVX512F_128 43281 EXCEPTIONS: AVX512-E4 43282 REAL_OPCODE: Y 43283 ATTRIBUTES: MASKOP_EVEX 43284 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43285 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 43286 IFORM: VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 43287 } 43288 43289 43290 # EMITTING VCOMPRESSPS (VCOMPRESSPS-256-1) 43291 { 43292 ICLASS: VCOMPRESSPS 43293 CPL: 3 43294 CATEGORY: COMPRESS 43295 EXTENSION: AVX512EVEX 43296 ISA_SET: AVX512F_256 43297 EXCEPTIONS: AVX512-E4 43298 REAL_OPCODE: Y 43299 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 43300 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 43301 OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 43302 IFORM: VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 43303 } 43304 43305 43306 # EMITTING VCOMPRESSPS (VCOMPRESSPS-256-2) 43307 { 43308 ICLASS: VCOMPRESSPS 43309 CPL: 3 43310 CATEGORY: COMPRESS 43311 EXTENSION: AVX512EVEX 43312 ISA_SET: AVX512F_256 43313 EXCEPTIONS: AVX512-E4 43314 REAL_OPCODE: Y 43315 ATTRIBUTES: MASKOP_EVEX 43316 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43317 OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 43318 IFORM: VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 43319 } 43320 43321 43322 # EMITTING VCVTDQ2PD (VCVTDQ2PD-128-1) 43323 { 43324 ICLASS: VCVTDQ2PD 43325 CPL: 3 43326 CATEGORY: CONVERT 43327 EXTENSION: AVX512EVEX 43328 ISA_SET: AVX512F_128 43329 EXCEPTIONS: AVX512-E5 43330 REAL_OPCODE: Y 43331 ATTRIBUTES: MASKOP_EVEX 43332 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43333 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 43334 IFORM: VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 43335 } 43336 43337 { 43338 ICLASS: VCVTDQ2PD 43339 CPL: 3 43340 CATEGORY: CONVERT 43341 EXTENSION: AVX512EVEX 43342 ISA_SET: AVX512F_128 43343 EXCEPTIONS: AVX512-E5 43344 REAL_OPCODE: Y 43345 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 43346 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 43347 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 43348 IFORM: VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 43349 } 43350 43351 43352 # EMITTING VCVTDQ2PD (VCVTDQ2PD-256-1) 43353 { 43354 ICLASS: VCVTDQ2PD 43355 CPL: 3 43356 CATEGORY: CONVERT 43357 EXTENSION: AVX512EVEX 43358 ISA_SET: AVX512F_256 43359 EXCEPTIONS: AVX512-E5 43360 REAL_OPCODE: Y 43361 ATTRIBUTES: MASKOP_EVEX 43362 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43363 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 43364 IFORM: VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 43365 } 43366 43367 { 43368 ICLASS: VCVTDQ2PD 43369 CPL: 3 43370 CATEGORY: CONVERT 43371 EXTENSION: AVX512EVEX 43372 ISA_SET: AVX512F_256 43373 EXCEPTIONS: AVX512-E5 43374 REAL_OPCODE: Y 43375 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 43376 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 43377 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 43378 IFORM: VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 43379 } 43380 43381 43382 # EMITTING VCVTDQ2PS (VCVTDQ2PS-128-1) 43383 { 43384 ICLASS: VCVTDQ2PS 43385 CPL: 3 43386 CATEGORY: CONVERT 43387 EXTENSION: AVX512EVEX 43388 ISA_SET: AVX512F_128 43389 EXCEPTIONS: AVX512-E2 43390 REAL_OPCODE: Y 43391 ATTRIBUTES: MXCSR MASKOP_EVEX 43392 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43393 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 43394 IFORM: VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 43395 } 43396 43397 { 43398 ICLASS: VCVTDQ2PS 43399 CPL: 3 43400 CATEGORY: CONVERT 43401 EXTENSION: AVX512EVEX 43402 ISA_SET: AVX512F_128 43403 EXCEPTIONS: AVX512-E2 43404 REAL_OPCODE: Y 43405 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43406 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 43407 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 43408 IFORM: VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 43409 } 43410 43411 43412 # EMITTING VCVTDQ2PS (VCVTDQ2PS-256-1) 43413 { 43414 ICLASS: VCVTDQ2PS 43415 CPL: 3 43416 CATEGORY: CONVERT 43417 EXTENSION: AVX512EVEX 43418 ISA_SET: AVX512F_256 43419 EXCEPTIONS: AVX512-E2 43420 REAL_OPCODE: Y 43421 ATTRIBUTES: MXCSR MASKOP_EVEX 43422 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43423 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 43424 IFORM: VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 43425 } 43426 43427 { 43428 ICLASS: VCVTDQ2PS 43429 CPL: 3 43430 CATEGORY: CONVERT 43431 EXTENSION: AVX512EVEX 43432 ISA_SET: AVX512F_256 43433 EXCEPTIONS: AVX512-E2 43434 REAL_OPCODE: Y 43435 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43436 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 43437 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 43438 IFORM: VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 43439 } 43440 43441 43442 # EMITTING VCVTPD2DQ (VCVTPD2DQ-128-1) 43443 { 43444 ICLASS: VCVTPD2DQ 43445 CPL: 3 43446 CATEGORY: CONVERT 43447 EXTENSION: AVX512EVEX 43448 ISA_SET: AVX512F_128 43449 EXCEPTIONS: AVX512-E2 43450 REAL_OPCODE: Y 43451 ATTRIBUTES: MXCSR MASKOP_EVEX 43452 PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 43453 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 43454 IFORM: VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 43455 } 43456 43457 { 43458 ICLASS: VCVTPD2DQ 43459 CPL: 3 43460 CATEGORY: CONVERT 43461 EXTENSION: AVX512EVEX 43462 ISA_SET: AVX512F_128 43463 EXCEPTIONS: AVX512-E2 43464 REAL_OPCODE: Y 43465 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43466 PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43467 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43468 IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 43469 } 43470 43471 43472 # EMITTING VCVTPD2DQ (VCVTPD2DQ-256-1) 43473 { 43474 ICLASS: VCVTPD2DQ 43475 CPL: 3 43476 CATEGORY: CONVERT 43477 EXTENSION: AVX512EVEX 43478 ISA_SET: AVX512F_256 43479 EXCEPTIONS: AVX512-E2 43480 REAL_OPCODE: Y 43481 ATTRIBUTES: MXCSR MASKOP_EVEX 43482 PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 43483 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 43484 IFORM: VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 43485 } 43486 43487 { 43488 ICLASS: VCVTPD2DQ 43489 CPL: 3 43490 CATEGORY: CONVERT 43491 EXTENSION: AVX512EVEX 43492 ISA_SET: AVX512F_256 43493 EXCEPTIONS: AVX512-E2 43494 REAL_OPCODE: Y 43495 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43496 PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43497 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43498 IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 43499 } 43500 43501 43502 # EMITTING VCVTPD2PS (VCVTPD2PS-128-1) 43503 { 43504 ICLASS: VCVTPD2PS 43505 CPL: 3 43506 CATEGORY: CONVERT 43507 EXTENSION: AVX512EVEX 43508 ISA_SET: AVX512F_128 43509 EXCEPTIONS: AVX512-E2 43510 REAL_OPCODE: Y 43511 ATTRIBUTES: MXCSR MASKOP_EVEX 43512 PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 43513 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 43514 IFORM: VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 43515 } 43516 43517 { 43518 ICLASS: VCVTPD2PS 43519 CPL: 3 43520 CATEGORY: CONVERT 43521 EXTENSION: AVX512EVEX 43522 ISA_SET: AVX512F_128 43523 EXCEPTIONS: AVX512-E2 43524 REAL_OPCODE: Y 43525 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43526 PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43527 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43528 IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 43529 } 43530 43531 43532 # EMITTING VCVTPD2PS (VCVTPD2PS-256-1) 43533 { 43534 ICLASS: VCVTPD2PS 43535 CPL: 3 43536 CATEGORY: CONVERT 43537 EXTENSION: AVX512EVEX 43538 ISA_SET: AVX512F_256 43539 EXCEPTIONS: AVX512-E2 43540 REAL_OPCODE: Y 43541 ATTRIBUTES: MXCSR MASKOP_EVEX 43542 PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 43543 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 43544 IFORM: VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 43545 } 43546 43547 { 43548 ICLASS: VCVTPD2PS 43549 CPL: 3 43550 CATEGORY: CONVERT 43551 EXTENSION: AVX512EVEX 43552 ISA_SET: AVX512F_256 43553 EXCEPTIONS: AVX512-E2 43554 REAL_OPCODE: Y 43555 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43556 PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43557 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43558 IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 43559 } 43560 43561 43562 # EMITTING VCVTPD2QQ (VCVTPD2QQ-128-1) 43563 { 43564 ICLASS: VCVTPD2QQ 43565 CPL: 3 43566 CATEGORY: CONVERT 43567 EXTENSION: AVX512EVEX 43568 ISA_SET: AVX512DQ_128 43569 EXCEPTIONS: AVX512-E2 43570 REAL_OPCODE: Y 43571 ATTRIBUTES: MXCSR MASKOP_EVEX 43572 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 43573 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 43574 IFORM: VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 43575 } 43576 43577 { 43578 ICLASS: VCVTPD2QQ 43579 CPL: 3 43580 CATEGORY: CONVERT 43581 EXTENSION: AVX512EVEX 43582 ISA_SET: AVX512DQ_128 43583 EXCEPTIONS: AVX512-E2 43584 REAL_OPCODE: Y 43585 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43586 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43587 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43588 IFORM: VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 43589 } 43590 43591 43592 # EMITTING VCVTPD2QQ (VCVTPD2QQ-256-1) 43593 { 43594 ICLASS: VCVTPD2QQ 43595 CPL: 3 43596 CATEGORY: CONVERT 43597 EXTENSION: AVX512EVEX 43598 ISA_SET: AVX512DQ_256 43599 EXCEPTIONS: AVX512-E2 43600 REAL_OPCODE: Y 43601 ATTRIBUTES: MXCSR MASKOP_EVEX 43602 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 43603 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 43604 IFORM: VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 43605 } 43606 43607 { 43608 ICLASS: VCVTPD2QQ 43609 CPL: 3 43610 CATEGORY: CONVERT 43611 EXTENSION: AVX512EVEX 43612 ISA_SET: AVX512DQ_256 43613 EXCEPTIONS: AVX512-E2 43614 REAL_OPCODE: Y 43615 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43616 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43617 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43618 IFORM: VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 43619 } 43620 43621 43622 # EMITTING VCVTPD2QQ (VCVTPD2QQ-512-1) 43623 { 43624 ICLASS: VCVTPD2QQ 43625 CPL: 3 43626 CATEGORY: CONVERT 43627 EXTENSION: AVX512EVEX 43628 ISA_SET: AVX512DQ_512 43629 EXCEPTIONS: AVX512-E2 43630 REAL_OPCODE: Y 43631 ATTRIBUTES: MXCSR MASKOP_EVEX 43632 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 43633 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 43634 IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 43635 } 43636 43637 { 43638 ICLASS: VCVTPD2QQ 43639 CPL: 3 43640 CATEGORY: CONVERT 43641 EXTENSION: AVX512EVEX 43642 ISA_SET: AVX512DQ_512 43643 EXCEPTIONS: AVX512-E2 43644 REAL_OPCODE: Y 43645 ATTRIBUTES: MXCSR MASKOP_EVEX 43646 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 43647 OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 43648 IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 43649 } 43650 43651 { 43652 ICLASS: VCVTPD2QQ 43653 CPL: 3 43654 CATEGORY: CONVERT 43655 EXTENSION: AVX512EVEX 43656 ISA_SET: AVX512DQ_512 43657 EXCEPTIONS: AVX512-E2 43658 REAL_OPCODE: Y 43659 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43660 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43661 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43662 IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 43663 } 43664 43665 43666 # EMITTING VCVTPD2UDQ (VCVTPD2UDQ-128-1) 43667 { 43668 ICLASS: VCVTPD2UDQ 43669 CPL: 3 43670 CATEGORY: CONVERT 43671 EXTENSION: AVX512EVEX 43672 ISA_SET: AVX512F_128 43673 EXCEPTIONS: AVX512-E2 43674 REAL_OPCODE: Y 43675 ATTRIBUTES: MXCSR MASKOP_EVEX 43676 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 43677 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 43678 IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 43679 } 43680 43681 { 43682 ICLASS: VCVTPD2UDQ 43683 CPL: 3 43684 CATEGORY: CONVERT 43685 EXTENSION: AVX512EVEX 43686 ISA_SET: AVX512F_128 43687 EXCEPTIONS: AVX512-E2 43688 REAL_OPCODE: Y 43689 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43690 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43691 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43692 IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 43693 } 43694 43695 43696 # EMITTING VCVTPD2UDQ (VCVTPD2UDQ-256-1) 43697 { 43698 ICLASS: VCVTPD2UDQ 43699 CPL: 3 43700 CATEGORY: CONVERT 43701 EXTENSION: AVX512EVEX 43702 ISA_SET: AVX512F_256 43703 EXCEPTIONS: AVX512-E2 43704 REAL_OPCODE: Y 43705 ATTRIBUTES: MXCSR MASKOP_EVEX 43706 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 43707 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 43708 IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 43709 } 43710 43711 { 43712 ICLASS: VCVTPD2UDQ 43713 CPL: 3 43714 CATEGORY: CONVERT 43715 EXTENSION: AVX512EVEX 43716 ISA_SET: AVX512F_256 43717 EXCEPTIONS: AVX512-E2 43718 REAL_OPCODE: Y 43719 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43720 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43721 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43722 IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 43723 } 43724 43725 43726 # EMITTING VCVTPD2UQQ (VCVTPD2UQQ-128-1) 43727 { 43728 ICLASS: VCVTPD2UQQ 43729 CPL: 3 43730 CATEGORY: CONVERT 43731 EXTENSION: AVX512EVEX 43732 ISA_SET: AVX512DQ_128 43733 EXCEPTIONS: AVX512-E2 43734 REAL_OPCODE: Y 43735 ATTRIBUTES: MXCSR MASKOP_EVEX 43736 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 43737 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 43738 IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 43739 } 43740 43741 { 43742 ICLASS: VCVTPD2UQQ 43743 CPL: 3 43744 CATEGORY: CONVERT 43745 EXTENSION: AVX512EVEX 43746 ISA_SET: AVX512DQ_128 43747 EXCEPTIONS: AVX512-E2 43748 REAL_OPCODE: Y 43749 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43750 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43751 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43752 IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 43753 } 43754 43755 43756 # EMITTING VCVTPD2UQQ (VCVTPD2UQQ-256-1) 43757 { 43758 ICLASS: VCVTPD2UQQ 43759 CPL: 3 43760 CATEGORY: CONVERT 43761 EXTENSION: AVX512EVEX 43762 ISA_SET: AVX512DQ_256 43763 EXCEPTIONS: AVX512-E2 43764 REAL_OPCODE: Y 43765 ATTRIBUTES: MXCSR MASKOP_EVEX 43766 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 43767 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 43768 IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 43769 } 43770 43771 { 43772 ICLASS: VCVTPD2UQQ 43773 CPL: 3 43774 CATEGORY: CONVERT 43775 EXTENSION: AVX512EVEX 43776 ISA_SET: AVX512DQ_256 43777 EXCEPTIONS: AVX512-E2 43778 REAL_OPCODE: Y 43779 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43780 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43781 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43782 IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 43783 } 43784 43785 43786 # EMITTING VCVTPD2UQQ (VCVTPD2UQQ-512-1) 43787 { 43788 ICLASS: VCVTPD2UQQ 43789 CPL: 3 43790 CATEGORY: CONVERT 43791 EXTENSION: AVX512EVEX 43792 ISA_SET: AVX512DQ_512 43793 EXCEPTIONS: AVX512-E2 43794 REAL_OPCODE: Y 43795 ATTRIBUTES: MXCSR MASKOP_EVEX 43796 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 43797 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 43798 IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 43799 } 43800 43801 { 43802 ICLASS: VCVTPD2UQQ 43803 CPL: 3 43804 CATEGORY: CONVERT 43805 EXTENSION: AVX512EVEX 43806 ISA_SET: AVX512DQ_512 43807 EXCEPTIONS: AVX512-E2 43808 REAL_OPCODE: Y 43809 ATTRIBUTES: MXCSR MASKOP_EVEX 43810 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 43811 OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 43812 IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 43813 } 43814 43815 { 43816 ICLASS: VCVTPD2UQQ 43817 CPL: 3 43818 CATEGORY: CONVERT 43819 EXTENSION: AVX512EVEX 43820 ISA_SET: AVX512DQ_512 43821 EXCEPTIONS: AVX512-E2 43822 REAL_OPCODE: Y 43823 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43824 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 43825 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 43826 IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 43827 } 43828 43829 43830 # EMITTING VCVTPH2PS (VCVTPH2PS-128-1) 43831 { 43832 ICLASS: VCVTPH2PS 43833 CPL: 3 43834 CATEGORY: CONVERT 43835 EXTENSION: AVX512EVEX 43836 ISA_SET: AVX512F_128 43837 EXCEPTIONS: AVX512-E11 43838 REAL_OPCODE: Y 43839 ATTRIBUTES: MXCSR MASKOP_EVEX 43840 PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43841 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 43842 IFORM: VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 43843 } 43844 43845 { 43846 ICLASS: VCVTPH2PS 43847 CPL: 3 43848 CATEGORY: CONVERT 43849 EXTENSION: AVX512EVEX 43850 ISA_SET: AVX512F_128 43851 EXCEPTIONS: AVX512-E11 43852 REAL_OPCODE: Y 43853 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43854 PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 43855 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16 43856 IFORM: VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 43857 } 43858 43859 43860 # EMITTING VCVTPH2PS (VCVTPH2PS-256-1) 43861 { 43862 ICLASS: VCVTPH2PS 43863 CPL: 3 43864 CATEGORY: CONVERT 43865 EXTENSION: AVX512EVEX 43866 ISA_SET: AVX512F_256 43867 EXCEPTIONS: AVX512-E11 43868 REAL_OPCODE: Y 43869 ATTRIBUTES: MXCSR MASKOP_EVEX 43870 PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43871 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 43872 IFORM: VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 43873 } 43874 43875 { 43876 ICLASS: VCVTPH2PS 43877 CPL: 3 43878 CATEGORY: CONVERT 43879 EXTENSION: AVX512EVEX 43880 ISA_SET: AVX512F_256 43881 EXCEPTIONS: AVX512-E11 43882 REAL_OPCODE: Y 43883 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43884 PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 43885 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16 43886 IFORM: VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 43887 } 43888 43889 43890 # EMITTING VCVTPS2DQ (VCVTPS2DQ-128-1) 43891 { 43892 ICLASS: VCVTPS2DQ 43893 CPL: 3 43894 CATEGORY: CONVERT 43895 EXTENSION: AVX512EVEX 43896 ISA_SET: AVX512F_128 43897 EXCEPTIONS: AVX512-E2 43898 REAL_OPCODE: Y 43899 ATTRIBUTES: MXCSR MASKOP_EVEX 43900 PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43901 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 43902 IFORM: VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 43903 } 43904 43905 { 43906 ICLASS: VCVTPS2DQ 43907 CPL: 3 43908 CATEGORY: CONVERT 43909 EXTENSION: AVX512EVEX 43910 ISA_SET: AVX512F_128 43911 EXCEPTIONS: AVX512-E2 43912 REAL_OPCODE: Y 43913 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43914 PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 43915 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 43916 IFORM: VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 43917 } 43918 43919 43920 # EMITTING VCVTPS2DQ (VCVTPS2DQ-256-1) 43921 { 43922 ICLASS: VCVTPS2DQ 43923 CPL: 3 43924 CATEGORY: CONVERT 43925 EXTENSION: AVX512EVEX 43926 ISA_SET: AVX512F_256 43927 EXCEPTIONS: AVX512-E2 43928 REAL_OPCODE: Y 43929 ATTRIBUTES: MXCSR MASKOP_EVEX 43930 PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43931 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 43932 IFORM: VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 43933 } 43934 43935 { 43936 ICLASS: VCVTPS2DQ 43937 CPL: 3 43938 CATEGORY: CONVERT 43939 EXTENSION: AVX512EVEX 43940 ISA_SET: AVX512F_256 43941 EXCEPTIONS: AVX512-E2 43942 REAL_OPCODE: Y 43943 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 43944 PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 43945 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 43946 IFORM: VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 43947 } 43948 43949 43950 # EMITTING VCVTPS2PD (VCVTPS2PD-128-1) 43951 { 43952 ICLASS: VCVTPS2PD 43953 CPL: 3 43954 CATEGORY: CONVERT 43955 EXTENSION: AVX512EVEX 43956 ISA_SET: AVX512F_128 43957 EXCEPTIONS: AVX512-E3 43958 REAL_OPCODE: Y 43959 ATTRIBUTES: MXCSR MASKOP_EVEX 43960 PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43961 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 43962 IFORM: VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 43963 } 43964 43965 { 43966 ICLASS: VCVTPS2PD 43967 CPL: 3 43968 CATEGORY: CONVERT 43969 EXTENSION: AVX512EVEX 43970 ISA_SET: AVX512F_128 43971 EXCEPTIONS: AVX512-E3 43972 REAL_OPCODE: Y 43973 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 43974 PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 43975 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 43976 IFORM: VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 43977 } 43978 43979 43980 # EMITTING VCVTPS2PD (VCVTPS2PD-256-1) 43981 { 43982 ICLASS: VCVTPS2PD 43983 CPL: 3 43984 CATEGORY: CONVERT 43985 EXTENSION: AVX512EVEX 43986 ISA_SET: AVX512F_256 43987 EXCEPTIONS: AVX512-E3 43988 REAL_OPCODE: Y 43989 ATTRIBUTES: MXCSR MASKOP_EVEX 43990 PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43991 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 43992 IFORM: VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 43993 } 43994 43995 { 43996 ICLASS: VCVTPS2PD 43997 CPL: 3 43998 CATEGORY: CONVERT 43999 EXTENSION: AVX512EVEX 44000 ISA_SET: AVX512F_256 44001 EXCEPTIONS: AVX512-E3 44002 REAL_OPCODE: Y 44003 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 44004 PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 44005 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44006 IFORM: VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 44007 } 44008 44009 44010 # EMITTING VCVTPS2PH (VCVTPS2PH-128-1) 44011 { 44012 ICLASS: VCVTPS2PH 44013 CPL: 3 44014 CATEGORY: CONVERT 44015 EXTENSION: AVX512EVEX 44016 ISA_SET: AVX512F_128 44017 EXCEPTIONS: AVX512-E11NF 44018 REAL_OPCODE: Y 44019 ATTRIBUTES: MXCSR MASKOP_EVEX 44020 PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 44021 OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 IMM0:r:b 44022 IFORM: VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 44023 } 44024 44025 44026 # EMITTING VCVTPS2PH (VCVTPS2PH-128-2) 44027 { 44028 ICLASS: VCVTPS2PH 44029 CPL: 3 44030 CATEGORY: CONVERT 44031 EXTENSION: AVX512EVEX 44032 ISA_SET: AVX512F_128 44033 EXCEPTIONS: AVX512-E11NF 44034 REAL_OPCODE: Y 44035 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44036 PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() 44037 OPERANDS: MEM0:w:q:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 IMM0:r:b 44038 IFORM: VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 44039 } 44040 44041 44042 # EMITTING VCVTPS2PH (VCVTPS2PH-256-1) 44043 { 44044 ICLASS: VCVTPS2PH 44045 CPL: 3 44046 CATEGORY: CONVERT 44047 EXTENSION: AVX512EVEX 44048 ISA_SET: AVX512F_256 44049 EXCEPTIONS: AVX512-E11NF 44050 REAL_OPCODE: Y 44051 ATTRIBUTES: MXCSR MASKOP_EVEX 44052 PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 44053 OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b 44054 IFORM: VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 44055 } 44056 44057 44058 # EMITTING VCVTPS2PH (VCVTPS2PH-256-2) 44059 { 44060 ICLASS: VCVTPS2PH 44061 CPL: 3 44062 CATEGORY: CONVERT 44063 EXTENSION: AVX512EVEX 44064 ISA_SET: AVX512F_256 44065 EXCEPTIONS: AVX512-E11NF 44066 REAL_OPCODE: Y 44067 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44068 PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() 44069 OPERANDS: MEM0:w:dq:f16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b 44070 IFORM: VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 44071 } 44072 44073 44074 # EMITTING VCVTPS2QQ (VCVTPS2QQ-128-1) 44075 { 44076 ICLASS: VCVTPS2QQ 44077 CPL: 3 44078 CATEGORY: CONVERT 44079 EXTENSION: AVX512EVEX 44080 ISA_SET: AVX512DQ_128 44081 EXCEPTIONS: AVX512-E3 44082 REAL_OPCODE: Y 44083 ATTRIBUTES: MXCSR MASKOP_EVEX 44084 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44085 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 44086 IFORM: VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 44087 } 44088 44089 { 44090 ICLASS: VCVTPS2QQ 44091 CPL: 3 44092 CATEGORY: CONVERT 44093 EXTENSION: AVX512EVEX 44094 ISA_SET: AVX512DQ_128 44095 EXCEPTIONS: AVX512-E3 44096 REAL_OPCODE: Y 44097 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 44098 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 44099 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44100 IFORM: VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 44101 } 44102 44103 44104 # EMITTING VCVTPS2QQ (VCVTPS2QQ-256-1) 44105 { 44106 ICLASS: VCVTPS2QQ 44107 CPL: 3 44108 CATEGORY: CONVERT 44109 EXTENSION: AVX512EVEX 44110 ISA_SET: AVX512DQ_256 44111 EXCEPTIONS: AVX512-E3 44112 REAL_OPCODE: Y 44113 ATTRIBUTES: MXCSR MASKOP_EVEX 44114 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44115 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 44116 IFORM: VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 44117 } 44118 44119 { 44120 ICLASS: VCVTPS2QQ 44121 CPL: 3 44122 CATEGORY: CONVERT 44123 EXTENSION: AVX512EVEX 44124 ISA_SET: AVX512DQ_256 44125 EXCEPTIONS: AVX512-E3 44126 REAL_OPCODE: Y 44127 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 44128 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 44129 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44130 IFORM: VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 44131 } 44132 44133 44134 # EMITTING VCVTPS2QQ (VCVTPS2QQ-512-1) 44135 { 44136 ICLASS: VCVTPS2QQ 44137 CPL: 3 44138 CATEGORY: CONVERT 44139 EXTENSION: AVX512EVEX 44140 ISA_SET: AVX512DQ_512 44141 EXCEPTIONS: AVX512-E3 44142 REAL_OPCODE: Y 44143 ATTRIBUTES: MXCSR MASKOP_EVEX 44144 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 44145 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 44146 IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 44147 } 44148 44149 { 44150 ICLASS: VCVTPS2QQ 44151 CPL: 3 44152 CATEGORY: CONVERT 44153 EXTENSION: AVX512EVEX 44154 ISA_SET: AVX512DQ_512 44155 EXCEPTIONS: AVX512-E3 44156 REAL_OPCODE: Y 44157 ATTRIBUTES: MXCSR MASKOP_EVEX 44158 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 44159 OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 44160 IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 44161 } 44162 44163 { 44164 ICLASS: VCVTPS2QQ 44165 CPL: 3 44166 CATEGORY: CONVERT 44167 EXTENSION: AVX512EVEX 44168 ISA_SET: AVX512DQ_512 44169 EXCEPTIONS: AVX512-E3 44170 REAL_OPCODE: Y 44171 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 44172 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 44173 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44174 IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 44175 } 44176 44177 44178 # EMITTING VCVTPS2UDQ (VCVTPS2UDQ-128-1) 44179 { 44180 ICLASS: VCVTPS2UDQ 44181 CPL: 3 44182 CATEGORY: CONVERT 44183 EXTENSION: AVX512EVEX 44184 ISA_SET: AVX512F_128 44185 EXCEPTIONS: AVX512-E2 44186 REAL_OPCODE: Y 44187 ATTRIBUTES: MXCSR MASKOP_EVEX 44188 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44189 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 44190 IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 44191 } 44192 44193 { 44194 ICLASS: VCVTPS2UDQ 44195 CPL: 3 44196 CATEGORY: CONVERT 44197 EXTENSION: AVX512EVEX 44198 ISA_SET: AVX512F_128 44199 EXCEPTIONS: AVX512-E2 44200 REAL_OPCODE: Y 44201 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44202 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 44203 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44204 IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 44205 } 44206 44207 44208 # EMITTING VCVTPS2UDQ (VCVTPS2UDQ-256-1) 44209 { 44210 ICLASS: VCVTPS2UDQ 44211 CPL: 3 44212 CATEGORY: CONVERT 44213 EXTENSION: AVX512EVEX 44214 ISA_SET: AVX512F_256 44215 EXCEPTIONS: AVX512-E2 44216 REAL_OPCODE: Y 44217 ATTRIBUTES: MXCSR MASKOP_EVEX 44218 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44219 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 44220 IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 44221 } 44222 44223 { 44224 ICLASS: VCVTPS2UDQ 44225 CPL: 3 44226 CATEGORY: CONVERT 44227 EXTENSION: AVX512EVEX 44228 ISA_SET: AVX512F_256 44229 EXCEPTIONS: AVX512-E2 44230 REAL_OPCODE: Y 44231 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44232 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 44233 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44234 IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 44235 } 44236 44237 44238 # EMITTING VCVTPS2UQQ (VCVTPS2UQQ-128-1) 44239 { 44240 ICLASS: VCVTPS2UQQ 44241 CPL: 3 44242 CATEGORY: CONVERT 44243 EXTENSION: AVX512EVEX 44244 ISA_SET: AVX512DQ_128 44245 EXCEPTIONS: AVX512-E3 44246 REAL_OPCODE: Y 44247 ATTRIBUTES: MXCSR MASKOP_EVEX 44248 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44249 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 44250 IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 44251 } 44252 44253 { 44254 ICLASS: VCVTPS2UQQ 44255 CPL: 3 44256 CATEGORY: CONVERT 44257 EXTENSION: AVX512EVEX 44258 ISA_SET: AVX512DQ_128 44259 EXCEPTIONS: AVX512-E3 44260 REAL_OPCODE: Y 44261 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 44262 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 44263 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44264 IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 44265 } 44266 44267 44268 # EMITTING VCVTPS2UQQ (VCVTPS2UQQ-256-1) 44269 { 44270 ICLASS: VCVTPS2UQQ 44271 CPL: 3 44272 CATEGORY: CONVERT 44273 EXTENSION: AVX512EVEX 44274 ISA_SET: AVX512DQ_256 44275 EXCEPTIONS: AVX512-E3 44276 REAL_OPCODE: Y 44277 ATTRIBUTES: MXCSR MASKOP_EVEX 44278 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44279 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 44280 IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 44281 } 44282 44283 { 44284 ICLASS: VCVTPS2UQQ 44285 CPL: 3 44286 CATEGORY: CONVERT 44287 EXTENSION: AVX512EVEX 44288 ISA_SET: AVX512DQ_256 44289 EXCEPTIONS: AVX512-E3 44290 REAL_OPCODE: Y 44291 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 44292 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 44293 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44294 IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 44295 } 44296 44297 44298 # EMITTING VCVTPS2UQQ (VCVTPS2UQQ-512-1) 44299 { 44300 ICLASS: VCVTPS2UQQ 44301 CPL: 3 44302 CATEGORY: CONVERT 44303 EXTENSION: AVX512EVEX 44304 ISA_SET: AVX512DQ_512 44305 EXCEPTIONS: AVX512-E3 44306 REAL_OPCODE: Y 44307 ATTRIBUTES: MXCSR MASKOP_EVEX 44308 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 44309 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 44310 IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 44311 } 44312 44313 { 44314 ICLASS: VCVTPS2UQQ 44315 CPL: 3 44316 CATEGORY: CONVERT 44317 EXTENSION: AVX512EVEX 44318 ISA_SET: AVX512DQ_512 44319 EXCEPTIONS: AVX512-E3 44320 REAL_OPCODE: Y 44321 ATTRIBUTES: MXCSR MASKOP_EVEX 44322 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 44323 OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 44324 IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 44325 } 44326 44327 { 44328 ICLASS: VCVTPS2UQQ 44329 CPL: 3 44330 CATEGORY: CONVERT 44331 EXTENSION: AVX512EVEX 44332 ISA_SET: AVX512DQ_512 44333 EXCEPTIONS: AVX512-E3 44334 REAL_OPCODE: Y 44335 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 44336 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 44337 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44338 IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 44339 } 44340 44341 44342 # EMITTING VCVTQQ2PD (VCVTQQ2PD-128-1) 44343 { 44344 ICLASS: VCVTQQ2PD 44345 CPL: 3 44346 CATEGORY: CONVERT 44347 EXTENSION: AVX512EVEX 44348 ISA_SET: AVX512DQ_128 44349 EXCEPTIONS: AVX512-E2 44350 REAL_OPCODE: Y 44351 ATTRIBUTES: MXCSR MASKOP_EVEX 44352 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 44353 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 44354 IFORM: VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 44355 } 44356 44357 { 44358 ICLASS: VCVTQQ2PD 44359 CPL: 3 44360 CATEGORY: CONVERT 44361 EXTENSION: AVX512EVEX 44362 ISA_SET: AVX512DQ_128 44363 EXCEPTIONS: AVX512-E2 44364 REAL_OPCODE: Y 44365 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44366 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44367 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44368 IFORM: VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 44369 } 44370 44371 44372 # EMITTING VCVTQQ2PD (VCVTQQ2PD-256-1) 44373 { 44374 ICLASS: VCVTQQ2PD 44375 CPL: 3 44376 CATEGORY: CONVERT 44377 EXTENSION: AVX512EVEX 44378 ISA_SET: AVX512DQ_256 44379 EXCEPTIONS: AVX512-E2 44380 REAL_OPCODE: Y 44381 ATTRIBUTES: MXCSR MASKOP_EVEX 44382 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 44383 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 44384 IFORM: VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 44385 } 44386 44387 { 44388 ICLASS: VCVTQQ2PD 44389 CPL: 3 44390 CATEGORY: CONVERT 44391 EXTENSION: AVX512EVEX 44392 ISA_SET: AVX512DQ_256 44393 EXCEPTIONS: AVX512-E2 44394 REAL_OPCODE: Y 44395 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44396 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44397 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44398 IFORM: VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 44399 } 44400 44401 44402 # EMITTING VCVTQQ2PD (VCVTQQ2PD-512-1) 44403 { 44404 ICLASS: VCVTQQ2PD 44405 CPL: 3 44406 CATEGORY: CONVERT 44407 EXTENSION: AVX512EVEX 44408 ISA_SET: AVX512DQ_512 44409 EXCEPTIONS: AVX512-E2 44410 REAL_OPCODE: Y 44411 ATTRIBUTES: MXCSR MASKOP_EVEX 44412 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 44413 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 44414 IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 44415 } 44416 44417 { 44418 ICLASS: VCVTQQ2PD 44419 CPL: 3 44420 CATEGORY: CONVERT 44421 EXTENSION: AVX512EVEX 44422 ISA_SET: AVX512DQ_512 44423 EXCEPTIONS: AVX512-E2 44424 REAL_OPCODE: Y 44425 ATTRIBUTES: MXCSR MASKOP_EVEX 44426 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 44427 OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 44428 IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 44429 } 44430 44431 { 44432 ICLASS: VCVTQQ2PD 44433 CPL: 3 44434 CATEGORY: CONVERT 44435 EXTENSION: AVX512EVEX 44436 ISA_SET: AVX512DQ_512 44437 EXCEPTIONS: AVX512-E2 44438 REAL_OPCODE: Y 44439 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44440 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44441 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44442 IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 44443 } 44444 44445 44446 # EMITTING VCVTQQ2PS (VCVTQQ2PS-128-1) 44447 { 44448 ICLASS: VCVTQQ2PS 44449 CPL: 3 44450 CATEGORY: CONVERT 44451 EXTENSION: AVX512EVEX 44452 ISA_SET: AVX512DQ_128 44453 EXCEPTIONS: AVX512-E2 44454 REAL_OPCODE: Y 44455 ATTRIBUTES: MXCSR MASKOP_EVEX 44456 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 44457 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 44458 IFORM: VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 44459 } 44460 44461 { 44462 ICLASS: VCVTQQ2PS 44463 CPL: 3 44464 CATEGORY: CONVERT 44465 EXTENSION: AVX512EVEX 44466 ISA_SET: AVX512DQ_128 44467 EXCEPTIONS: AVX512-E2 44468 REAL_OPCODE: Y 44469 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44470 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44471 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 44472 IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 44473 } 44474 44475 44476 # EMITTING VCVTQQ2PS (VCVTQQ2PS-256-1) 44477 { 44478 ICLASS: VCVTQQ2PS 44479 CPL: 3 44480 CATEGORY: CONVERT 44481 EXTENSION: AVX512EVEX 44482 ISA_SET: AVX512DQ_256 44483 EXCEPTIONS: AVX512-E2 44484 REAL_OPCODE: Y 44485 ATTRIBUTES: MXCSR MASKOP_EVEX 44486 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 44487 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 44488 IFORM: VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 44489 } 44490 44491 { 44492 ICLASS: VCVTQQ2PS 44493 CPL: 3 44494 CATEGORY: CONVERT 44495 EXTENSION: AVX512EVEX 44496 ISA_SET: AVX512DQ_256 44497 EXCEPTIONS: AVX512-E2 44498 REAL_OPCODE: Y 44499 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44500 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44501 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 44502 IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 44503 } 44504 44505 44506 # EMITTING VCVTQQ2PS (VCVTQQ2PS-512-1) 44507 { 44508 ICLASS: VCVTQQ2PS 44509 CPL: 3 44510 CATEGORY: CONVERT 44511 EXTENSION: AVX512EVEX 44512 ISA_SET: AVX512DQ_512 44513 EXCEPTIONS: AVX512-E2 44514 REAL_OPCODE: Y 44515 ATTRIBUTES: MXCSR MASKOP_EVEX 44516 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 44517 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 44518 IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 44519 } 44520 44521 { 44522 ICLASS: VCVTQQ2PS 44523 CPL: 3 44524 CATEGORY: CONVERT 44525 EXTENSION: AVX512EVEX 44526 ISA_SET: AVX512DQ_512 44527 EXCEPTIONS: AVX512-E2 44528 REAL_OPCODE: Y 44529 ATTRIBUTES: MXCSR MASKOP_EVEX 44530 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 44531 OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 44532 IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 44533 } 44534 44535 { 44536 ICLASS: VCVTQQ2PS 44537 CPL: 3 44538 CATEGORY: CONVERT 44539 EXTENSION: AVX512EVEX 44540 ISA_SET: AVX512DQ_512 44541 EXCEPTIONS: AVX512-E2 44542 REAL_OPCODE: Y 44543 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44544 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44545 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 44546 IFORM: VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 44547 } 44548 44549 44550 # EMITTING VCVTTPD2DQ (VCVTTPD2DQ-128-1) 44551 { 44552 ICLASS: VCVTTPD2DQ 44553 CPL: 3 44554 CATEGORY: CONVERT 44555 EXTENSION: AVX512EVEX 44556 ISA_SET: AVX512F_128 44557 EXCEPTIONS: AVX512-E2 44558 REAL_OPCODE: Y 44559 ATTRIBUTES: MXCSR MASKOP_EVEX 44560 PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 44561 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 44562 IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 44563 } 44564 44565 { 44566 ICLASS: VCVTTPD2DQ 44567 CPL: 3 44568 CATEGORY: CONVERT 44569 EXTENSION: AVX512EVEX 44570 ISA_SET: AVX512F_128 44571 EXCEPTIONS: AVX512-E2 44572 REAL_OPCODE: Y 44573 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44574 PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44575 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44576 IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 44577 } 44578 44579 44580 # EMITTING VCVTTPD2DQ (VCVTTPD2DQ-256-1) 44581 { 44582 ICLASS: VCVTTPD2DQ 44583 CPL: 3 44584 CATEGORY: CONVERT 44585 EXTENSION: AVX512EVEX 44586 ISA_SET: AVX512F_256 44587 EXCEPTIONS: AVX512-E2 44588 REAL_OPCODE: Y 44589 ATTRIBUTES: MXCSR MASKOP_EVEX 44590 PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 44591 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 44592 IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 44593 } 44594 44595 { 44596 ICLASS: VCVTTPD2DQ 44597 CPL: 3 44598 CATEGORY: CONVERT 44599 EXTENSION: AVX512EVEX 44600 ISA_SET: AVX512F_256 44601 EXCEPTIONS: AVX512-E2 44602 REAL_OPCODE: Y 44603 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44604 PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44605 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44606 IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 44607 } 44608 44609 44610 # EMITTING VCVTTPD2QQ (VCVTTPD2QQ-128-1) 44611 { 44612 ICLASS: VCVTTPD2QQ 44613 CPL: 3 44614 CATEGORY: CONVERT 44615 EXTENSION: AVX512EVEX 44616 ISA_SET: AVX512DQ_128 44617 EXCEPTIONS: AVX512-E2 44618 REAL_OPCODE: Y 44619 ATTRIBUTES: MXCSR MASKOP_EVEX 44620 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 44621 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 44622 IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 44623 } 44624 44625 { 44626 ICLASS: VCVTTPD2QQ 44627 CPL: 3 44628 CATEGORY: CONVERT 44629 EXTENSION: AVX512EVEX 44630 ISA_SET: AVX512DQ_128 44631 EXCEPTIONS: AVX512-E2 44632 REAL_OPCODE: Y 44633 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44634 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44635 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44636 IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 44637 } 44638 44639 44640 # EMITTING VCVTTPD2QQ (VCVTTPD2QQ-256-1) 44641 { 44642 ICLASS: VCVTTPD2QQ 44643 CPL: 3 44644 CATEGORY: CONVERT 44645 EXTENSION: AVX512EVEX 44646 ISA_SET: AVX512DQ_256 44647 EXCEPTIONS: AVX512-E2 44648 REAL_OPCODE: Y 44649 ATTRIBUTES: MXCSR MASKOP_EVEX 44650 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 44651 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 44652 IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 44653 } 44654 44655 { 44656 ICLASS: VCVTTPD2QQ 44657 CPL: 3 44658 CATEGORY: CONVERT 44659 EXTENSION: AVX512EVEX 44660 ISA_SET: AVX512DQ_256 44661 EXCEPTIONS: AVX512-E2 44662 REAL_OPCODE: Y 44663 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44664 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44665 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44666 IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 44667 } 44668 44669 44670 # EMITTING VCVTTPD2QQ (VCVTTPD2QQ-512-1) 44671 { 44672 ICLASS: VCVTTPD2QQ 44673 CPL: 3 44674 CATEGORY: CONVERT 44675 EXTENSION: AVX512EVEX 44676 ISA_SET: AVX512DQ_512 44677 EXCEPTIONS: AVX512-E2 44678 REAL_OPCODE: Y 44679 ATTRIBUTES: MXCSR MASKOP_EVEX 44680 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 44681 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 44682 IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 44683 } 44684 44685 { 44686 ICLASS: VCVTTPD2QQ 44687 CPL: 3 44688 CATEGORY: CONVERT 44689 EXTENSION: AVX512EVEX 44690 ISA_SET: AVX512DQ_512 44691 EXCEPTIONS: AVX512-E2 44692 REAL_OPCODE: Y 44693 ATTRIBUTES: MXCSR MASKOP_EVEX 44694 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 44695 OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 44696 IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 44697 } 44698 44699 { 44700 ICLASS: VCVTTPD2QQ 44701 CPL: 3 44702 CATEGORY: CONVERT 44703 EXTENSION: AVX512EVEX 44704 ISA_SET: AVX512DQ_512 44705 EXCEPTIONS: AVX512-E2 44706 REAL_OPCODE: Y 44707 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44708 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44709 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44710 IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 44711 } 44712 44713 44714 # EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-128-1) 44715 { 44716 ICLASS: VCVTTPD2UDQ 44717 CPL: 3 44718 CATEGORY: CONVERT 44719 EXTENSION: AVX512EVEX 44720 ISA_SET: AVX512F_128 44721 EXCEPTIONS: AVX512-E2 44722 REAL_OPCODE: Y 44723 ATTRIBUTES: MXCSR MASKOP_EVEX 44724 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 44725 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 44726 IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 44727 } 44728 44729 { 44730 ICLASS: VCVTTPD2UDQ 44731 CPL: 3 44732 CATEGORY: CONVERT 44733 EXTENSION: AVX512EVEX 44734 ISA_SET: AVX512F_128 44735 EXCEPTIONS: AVX512-E2 44736 REAL_OPCODE: Y 44737 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44738 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44739 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44740 IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 44741 } 44742 44743 44744 # EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-256-1) 44745 { 44746 ICLASS: VCVTTPD2UDQ 44747 CPL: 3 44748 CATEGORY: CONVERT 44749 EXTENSION: AVX512EVEX 44750 ISA_SET: AVX512F_256 44751 EXCEPTIONS: AVX512-E2 44752 REAL_OPCODE: Y 44753 ATTRIBUTES: MXCSR MASKOP_EVEX 44754 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 44755 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 44756 IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 44757 } 44758 44759 { 44760 ICLASS: VCVTTPD2UDQ 44761 CPL: 3 44762 CATEGORY: CONVERT 44763 EXTENSION: AVX512EVEX 44764 ISA_SET: AVX512F_256 44765 EXCEPTIONS: AVX512-E2 44766 REAL_OPCODE: Y 44767 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44768 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44769 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44770 IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 44771 } 44772 44773 44774 # EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-128-1) 44775 { 44776 ICLASS: VCVTTPD2UQQ 44777 CPL: 3 44778 CATEGORY: CONVERT 44779 EXTENSION: AVX512EVEX 44780 ISA_SET: AVX512DQ_128 44781 EXCEPTIONS: AVX512-E2 44782 REAL_OPCODE: Y 44783 ATTRIBUTES: MXCSR MASKOP_EVEX 44784 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 44785 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 44786 IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 44787 } 44788 44789 { 44790 ICLASS: VCVTTPD2UQQ 44791 CPL: 3 44792 CATEGORY: CONVERT 44793 EXTENSION: AVX512EVEX 44794 ISA_SET: AVX512DQ_128 44795 EXCEPTIONS: AVX512-E2 44796 REAL_OPCODE: Y 44797 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44798 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44799 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44800 IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 44801 } 44802 44803 44804 # EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-256-1) 44805 { 44806 ICLASS: VCVTTPD2UQQ 44807 CPL: 3 44808 CATEGORY: CONVERT 44809 EXTENSION: AVX512EVEX 44810 ISA_SET: AVX512DQ_256 44811 EXCEPTIONS: AVX512-E2 44812 REAL_OPCODE: Y 44813 ATTRIBUTES: MXCSR MASKOP_EVEX 44814 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 44815 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 44816 IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 44817 } 44818 44819 { 44820 ICLASS: VCVTTPD2UQQ 44821 CPL: 3 44822 CATEGORY: CONVERT 44823 EXTENSION: AVX512EVEX 44824 ISA_SET: AVX512DQ_256 44825 EXCEPTIONS: AVX512-E2 44826 REAL_OPCODE: Y 44827 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44828 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44829 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44830 IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 44831 } 44832 44833 44834 # EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-512-1) 44835 { 44836 ICLASS: VCVTTPD2UQQ 44837 CPL: 3 44838 CATEGORY: CONVERT 44839 EXTENSION: AVX512EVEX 44840 ISA_SET: AVX512DQ_512 44841 EXCEPTIONS: AVX512-E2 44842 REAL_OPCODE: Y 44843 ATTRIBUTES: MXCSR MASKOP_EVEX 44844 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 44845 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 44846 IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 44847 } 44848 44849 { 44850 ICLASS: VCVTTPD2UQQ 44851 CPL: 3 44852 CATEGORY: CONVERT 44853 EXTENSION: AVX512EVEX 44854 ISA_SET: AVX512DQ_512 44855 EXCEPTIONS: AVX512-E2 44856 REAL_OPCODE: Y 44857 ATTRIBUTES: MXCSR MASKOP_EVEX 44858 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 44859 OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 44860 IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 44861 } 44862 44863 { 44864 ICLASS: VCVTTPD2UQQ 44865 CPL: 3 44866 CATEGORY: CONVERT 44867 EXTENSION: AVX512EVEX 44868 ISA_SET: AVX512DQ_512 44869 EXCEPTIONS: AVX512-E2 44870 REAL_OPCODE: Y 44871 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44872 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 44873 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 44874 IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 44875 } 44876 44877 44878 # EMITTING VCVTTPS2DQ (VCVTTPS2DQ-128-1) 44879 { 44880 ICLASS: VCVTTPS2DQ 44881 CPL: 3 44882 CATEGORY: CONVERT 44883 EXTENSION: AVX512EVEX 44884 ISA_SET: AVX512F_128 44885 EXCEPTIONS: AVX512-E2 44886 REAL_OPCODE: Y 44887 ATTRIBUTES: MXCSR MASKOP_EVEX 44888 PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44889 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 44890 IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 44891 } 44892 44893 { 44894 ICLASS: VCVTTPS2DQ 44895 CPL: 3 44896 CATEGORY: CONVERT 44897 EXTENSION: AVX512EVEX 44898 ISA_SET: AVX512F_128 44899 EXCEPTIONS: AVX512-E2 44900 REAL_OPCODE: Y 44901 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44902 PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 44903 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44904 IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 44905 } 44906 44907 44908 # EMITTING VCVTTPS2DQ (VCVTTPS2DQ-256-1) 44909 { 44910 ICLASS: VCVTTPS2DQ 44911 CPL: 3 44912 CATEGORY: CONVERT 44913 EXTENSION: AVX512EVEX 44914 ISA_SET: AVX512F_256 44915 EXCEPTIONS: AVX512-E2 44916 REAL_OPCODE: Y 44917 ATTRIBUTES: MXCSR MASKOP_EVEX 44918 PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44919 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 44920 IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 44921 } 44922 44923 { 44924 ICLASS: VCVTTPS2DQ 44925 CPL: 3 44926 CATEGORY: CONVERT 44927 EXTENSION: AVX512EVEX 44928 ISA_SET: AVX512F_256 44929 EXCEPTIONS: AVX512-E2 44930 REAL_OPCODE: Y 44931 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 44932 PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 44933 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44934 IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 44935 } 44936 44937 44938 # EMITTING VCVTTPS2QQ (VCVTTPS2QQ-128-1) 44939 { 44940 ICLASS: VCVTTPS2QQ 44941 CPL: 3 44942 CATEGORY: CONVERT 44943 EXTENSION: AVX512EVEX 44944 ISA_SET: AVX512DQ_128 44945 EXCEPTIONS: AVX512-E3 44946 REAL_OPCODE: Y 44947 ATTRIBUTES: MXCSR MASKOP_EVEX 44948 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44949 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 44950 IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 44951 } 44952 44953 { 44954 ICLASS: VCVTTPS2QQ 44955 CPL: 3 44956 CATEGORY: CONVERT 44957 EXTENSION: AVX512EVEX 44958 ISA_SET: AVX512DQ_128 44959 EXCEPTIONS: AVX512-E3 44960 REAL_OPCODE: Y 44961 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 44962 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 44963 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44964 IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 44965 } 44966 44967 44968 # EMITTING VCVTTPS2QQ (VCVTTPS2QQ-256-1) 44969 { 44970 ICLASS: VCVTTPS2QQ 44971 CPL: 3 44972 CATEGORY: CONVERT 44973 EXTENSION: AVX512EVEX 44974 ISA_SET: AVX512DQ_256 44975 EXCEPTIONS: AVX512-E3 44976 REAL_OPCODE: Y 44977 ATTRIBUTES: MXCSR MASKOP_EVEX 44978 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44979 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 44980 IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 44981 } 44982 44983 { 44984 ICLASS: VCVTTPS2QQ 44985 CPL: 3 44986 CATEGORY: CONVERT 44987 EXTENSION: AVX512EVEX 44988 ISA_SET: AVX512DQ_256 44989 EXCEPTIONS: AVX512-E3 44990 REAL_OPCODE: Y 44991 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 44992 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 44993 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 44994 IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 44995 } 44996 44997 44998 # EMITTING VCVTTPS2QQ (VCVTTPS2QQ-512-1) 44999 { 45000 ICLASS: VCVTTPS2QQ 45001 CPL: 3 45002 CATEGORY: CONVERT 45003 EXTENSION: AVX512EVEX 45004 ISA_SET: AVX512DQ_512 45005 EXCEPTIONS: AVX512-E3 45006 REAL_OPCODE: Y 45007 ATTRIBUTES: MXCSR MASKOP_EVEX 45008 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 45009 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 45010 IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 45011 } 45012 45013 { 45014 ICLASS: VCVTTPS2QQ 45015 CPL: 3 45016 CATEGORY: CONVERT 45017 EXTENSION: AVX512EVEX 45018 ISA_SET: AVX512DQ_512 45019 EXCEPTIONS: AVX512-E3 45020 REAL_OPCODE: Y 45021 ATTRIBUTES: MXCSR MASKOP_EVEX 45022 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 45023 OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 45024 IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 45025 } 45026 45027 { 45028 ICLASS: VCVTTPS2QQ 45029 CPL: 3 45030 CATEGORY: CONVERT 45031 EXTENSION: AVX512EVEX 45032 ISA_SET: AVX512DQ_512 45033 EXCEPTIONS: AVX512-E3 45034 REAL_OPCODE: Y 45035 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 45036 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 45037 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 45038 IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 45039 } 45040 45041 45042 # EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-128-1) 45043 { 45044 ICLASS: VCVTTPS2UDQ 45045 CPL: 3 45046 CATEGORY: CONVERT 45047 EXTENSION: AVX512EVEX 45048 ISA_SET: AVX512F_128 45049 EXCEPTIONS: AVX512-E2 45050 REAL_OPCODE: Y 45051 ATTRIBUTES: MXCSR MASKOP_EVEX 45052 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 45053 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 45054 IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 45055 } 45056 45057 { 45058 ICLASS: VCVTTPS2UDQ 45059 CPL: 3 45060 CATEGORY: CONVERT 45061 EXTENSION: AVX512EVEX 45062 ISA_SET: AVX512F_128 45063 EXCEPTIONS: AVX512-E2 45064 REAL_OPCODE: Y 45065 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45066 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 45067 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 45068 IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 45069 } 45070 45071 45072 # EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-256-1) 45073 { 45074 ICLASS: VCVTTPS2UDQ 45075 CPL: 3 45076 CATEGORY: CONVERT 45077 EXTENSION: AVX512EVEX 45078 ISA_SET: AVX512F_256 45079 EXCEPTIONS: AVX512-E2 45080 REAL_OPCODE: Y 45081 ATTRIBUTES: MXCSR MASKOP_EVEX 45082 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 45083 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 45084 IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 45085 } 45086 45087 { 45088 ICLASS: VCVTTPS2UDQ 45089 CPL: 3 45090 CATEGORY: CONVERT 45091 EXTENSION: AVX512EVEX 45092 ISA_SET: AVX512F_256 45093 EXCEPTIONS: AVX512-E2 45094 REAL_OPCODE: Y 45095 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45096 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 45097 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 45098 IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 45099 } 45100 45101 45102 # EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-128-1) 45103 { 45104 ICLASS: VCVTTPS2UQQ 45105 CPL: 3 45106 CATEGORY: CONVERT 45107 EXTENSION: AVX512EVEX 45108 ISA_SET: AVX512DQ_128 45109 EXCEPTIONS: AVX512-E3 45110 REAL_OPCODE: Y 45111 ATTRIBUTES: MXCSR MASKOP_EVEX 45112 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 45113 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 45114 IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 45115 } 45116 45117 { 45118 ICLASS: VCVTTPS2UQQ 45119 CPL: 3 45120 CATEGORY: CONVERT 45121 EXTENSION: AVX512EVEX 45122 ISA_SET: AVX512DQ_128 45123 EXCEPTIONS: AVX512-E3 45124 REAL_OPCODE: Y 45125 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 45126 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 45127 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 45128 IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 45129 } 45130 45131 45132 # EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-256-1) 45133 { 45134 ICLASS: VCVTTPS2UQQ 45135 CPL: 3 45136 CATEGORY: CONVERT 45137 EXTENSION: AVX512EVEX 45138 ISA_SET: AVX512DQ_256 45139 EXCEPTIONS: AVX512-E3 45140 REAL_OPCODE: Y 45141 ATTRIBUTES: MXCSR MASKOP_EVEX 45142 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 45143 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 45144 IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 45145 } 45146 45147 { 45148 ICLASS: VCVTTPS2UQQ 45149 CPL: 3 45150 CATEGORY: CONVERT 45151 EXTENSION: AVX512EVEX 45152 ISA_SET: AVX512DQ_256 45153 EXCEPTIONS: AVX512-E3 45154 REAL_OPCODE: Y 45155 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 45156 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 45157 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 45158 IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 45159 } 45160 45161 45162 # EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-512-1) 45163 { 45164 ICLASS: VCVTTPS2UQQ 45165 CPL: 3 45166 CATEGORY: CONVERT 45167 EXTENSION: AVX512EVEX 45168 ISA_SET: AVX512DQ_512 45169 EXCEPTIONS: AVX512-E3 45170 REAL_OPCODE: Y 45171 ATTRIBUTES: MXCSR MASKOP_EVEX 45172 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 45173 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 45174 IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 45175 } 45176 45177 { 45178 ICLASS: VCVTTPS2UQQ 45179 CPL: 3 45180 CATEGORY: CONVERT 45181 EXTENSION: AVX512EVEX 45182 ISA_SET: AVX512DQ_512 45183 EXCEPTIONS: AVX512-E3 45184 REAL_OPCODE: Y 45185 ATTRIBUTES: MXCSR MASKOP_EVEX 45186 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 45187 OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 45188 IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 45189 } 45190 45191 { 45192 ICLASS: VCVTTPS2UQQ 45193 CPL: 3 45194 CATEGORY: CONVERT 45195 EXTENSION: AVX512EVEX 45196 ISA_SET: AVX512DQ_512 45197 EXCEPTIONS: AVX512-E3 45198 REAL_OPCODE: Y 45199 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 45200 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 45201 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 45202 IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 45203 } 45204 45205 45206 # EMITTING VCVTUDQ2PD (VCVTUDQ2PD-128-1) 45207 { 45208 ICLASS: VCVTUDQ2PD 45209 CPL: 3 45210 CATEGORY: CONVERT 45211 EXTENSION: AVX512EVEX 45212 ISA_SET: AVX512F_128 45213 EXCEPTIONS: AVX512-E5 45214 REAL_OPCODE: Y 45215 ATTRIBUTES: MASKOP_EVEX 45216 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 45217 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 45218 IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 45219 } 45220 45221 { 45222 ICLASS: VCVTUDQ2PD 45223 CPL: 3 45224 CATEGORY: CONVERT 45225 EXTENSION: AVX512EVEX 45226 ISA_SET: AVX512F_128 45227 EXCEPTIONS: AVX512-E5 45228 REAL_OPCODE: Y 45229 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 45230 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 45231 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 45232 IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 45233 } 45234 45235 45236 # EMITTING VCVTUDQ2PD (VCVTUDQ2PD-256-1) 45237 { 45238 ICLASS: VCVTUDQ2PD 45239 CPL: 3 45240 CATEGORY: CONVERT 45241 EXTENSION: AVX512EVEX 45242 ISA_SET: AVX512F_256 45243 EXCEPTIONS: AVX512-E5 45244 REAL_OPCODE: Y 45245 ATTRIBUTES: MASKOP_EVEX 45246 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 45247 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 45248 IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 45249 } 45250 45251 { 45252 ICLASS: VCVTUDQ2PD 45253 CPL: 3 45254 CATEGORY: CONVERT 45255 EXTENSION: AVX512EVEX 45256 ISA_SET: AVX512F_256 45257 EXCEPTIONS: AVX512-E5 45258 REAL_OPCODE: Y 45259 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 45260 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 45261 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 45262 IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 45263 } 45264 45265 45266 # EMITTING VCVTUDQ2PS (VCVTUDQ2PS-128-1) 45267 { 45268 ICLASS: VCVTUDQ2PS 45269 CPL: 3 45270 CATEGORY: CONVERT 45271 EXTENSION: AVX512EVEX 45272 ISA_SET: AVX512F_128 45273 EXCEPTIONS: AVX512-E2 45274 REAL_OPCODE: Y 45275 ATTRIBUTES: MXCSR MASKOP_EVEX 45276 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 45277 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 45278 IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 45279 } 45280 45281 { 45282 ICLASS: VCVTUDQ2PS 45283 CPL: 3 45284 CATEGORY: CONVERT 45285 EXTENSION: AVX512EVEX 45286 ISA_SET: AVX512F_128 45287 EXCEPTIONS: AVX512-E2 45288 REAL_OPCODE: Y 45289 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45290 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 45291 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 45292 IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 45293 } 45294 45295 45296 # EMITTING VCVTUDQ2PS (VCVTUDQ2PS-256-1) 45297 { 45298 ICLASS: VCVTUDQ2PS 45299 CPL: 3 45300 CATEGORY: CONVERT 45301 EXTENSION: AVX512EVEX 45302 ISA_SET: AVX512F_256 45303 EXCEPTIONS: AVX512-E2 45304 REAL_OPCODE: Y 45305 ATTRIBUTES: MXCSR MASKOP_EVEX 45306 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 45307 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 45308 IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 45309 } 45310 45311 { 45312 ICLASS: VCVTUDQ2PS 45313 CPL: 3 45314 CATEGORY: CONVERT 45315 EXTENSION: AVX512EVEX 45316 ISA_SET: AVX512F_256 45317 EXCEPTIONS: AVX512-E2 45318 REAL_OPCODE: Y 45319 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45320 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 45321 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 45322 IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 45323 } 45324 45325 45326 # EMITTING VCVTUQQ2PD (VCVTUQQ2PD-128-1) 45327 { 45328 ICLASS: VCVTUQQ2PD 45329 CPL: 3 45330 CATEGORY: CONVERT 45331 EXTENSION: AVX512EVEX 45332 ISA_SET: AVX512DQ_128 45333 EXCEPTIONS: AVX512-E2 45334 REAL_OPCODE: Y 45335 ATTRIBUTES: MXCSR MASKOP_EVEX 45336 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 45337 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 45338 IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 45339 } 45340 45341 { 45342 ICLASS: VCVTUQQ2PD 45343 CPL: 3 45344 CATEGORY: CONVERT 45345 EXTENSION: AVX512EVEX 45346 ISA_SET: AVX512DQ_128 45347 EXCEPTIONS: AVX512-E2 45348 REAL_OPCODE: Y 45349 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45350 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 45351 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 45352 IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 45353 } 45354 45355 45356 # EMITTING VCVTUQQ2PD (VCVTUQQ2PD-256-1) 45357 { 45358 ICLASS: VCVTUQQ2PD 45359 CPL: 3 45360 CATEGORY: CONVERT 45361 EXTENSION: AVX512EVEX 45362 ISA_SET: AVX512DQ_256 45363 EXCEPTIONS: AVX512-E2 45364 REAL_OPCODE: Y 45365 ATTRIBUTES: MXCSR MASKOP_EVEX 45366 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 45367 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 45368 IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 45369 } 45370 45371 { 45372 ICLASS: VCVTUQQ2PD 45373 CPL: 3 45374 CATEGORY: CONVERT 45375 EXTENSION: AVX512EVEX 45376 ISA_SET: AVX512DQ_256 45377 EXCEPTIONS: AVX512-E2 45378 REAL_OPCODE: Y 45379 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45380 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 45381 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 45382 IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 45383 } 45384 45385 45386 # EMITTING VCVTUQQ2PD (VCVTUQQ2PD-512-1) 45387 { 45388 ICLASS: VCVTUQQ2PD 45389 CPL: 3 45390 CATEGORY: CONVERT 45391 EXTENSION: AVX512EVEX 45392 ISA_SET: AVX512DQ_512 45393 EXCEPTIONS: AVX512-E2 45394 REAL_OPCODE: Y 45395 ATTRIBUTES: MXCSR MASKOP_EVEX 45396 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 45397 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 45398 IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 45399 } 45400 45401 { 45402 ICLASS: VCVTUQQ2PD 45403 CPL: 3 45404 CATEGORY: CONVERT 45405 EXTENSION: AVX512EVEX 45406 ISA_SET: AVX512DQ_512 45407 EXCEPTIONS: AVX512-E2 45408 REAL_OPCODE: Y 45409 ATTRIBUTES: MXCSR MASKOP_EVEX 45410 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 45411 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 45412 IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 45413 } 45414 45415 { 45416 ICLASS: VCVTUQQ2PD 45417 CPL: 3 45418 CATEGORY: CONVERT 45419 EXTENSION: AVX512EVEX 45420 ISA_SET: AVX512DQ_512 45421 EXCEPTIONS: AVX512-E2 45422 REAL_OPCODE: Y 45423 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45424 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 45425 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 45426 IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 45427 } 45428 45429 45430 # EMITTING VCVTUQQ2PS (VCVTUQQ2PS-128-1) 45431 { 45432 ICLASS: VCVTUQQ2PS 45433 CPL: 3 45434 CATEGORY: CONVERT 45435 EXTENSION: AVX512EVEX 45436 ISA_SET: AVX512DQ_128 45437 EXCEPTIONS: AVX512-E2 45438 REAL_OPCODE: Y 45439 ATTRIBUTES: MXCSR MASKOP_EVEX 45440 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 45441 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 45442 IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 45443 } 45444 45445 { 45446 ICLASS: VCVTUQQ2PS 45447 CPL: 3 45448 CATEGORY: CONVERT 45449 EXTENSION: AVX512EVEX 45450 ISA_SET: AVX512DQ_128 45451 EXCEPTIONS: AVX512-E2 45452 REAL_OPCODE: Y 45453 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45454 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 45455 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 45456 IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 45457 } 45458 45459 45460 # EMITTING VCVTUQQ2PS (VCVTUQQ2PS-256-1) 45461 { 45462 ICLASS: VCVTUQQ2PS 45463 CPL: 3 45464 CATEGORY: CONVERT 45465 EXTENSION: AVX512EVEX 45466 ISA_SET: AVX512DQ_256 45467 EXCEPTIONS: AVX512-E2 45468 REAL_OPCODE: Y 45469 ATTRIBUTES: MXCSR MASKOP_EVEX 45470 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 45471 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 45472 IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 45473 } 45474 45475 { 45476 ICLASS: VCVTUQQ2PS 45477 CPL: 3 45478 CATEGORY: CONVERT 45479 EXTENSION: AVX512EVEX 45480 ISA_SET: AVX512DQ_256 45481 EXCEPTIONS: AVX512-E2 45482 REAL_OPCODE: Y 45483 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45484 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 45485 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 45486 IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 45487 } 45488 45489 45490 # EMITTING VCVTUQQ2PS (VCVTUQQ2PS-512-1) 45491 { 45492 ICLASS: VCVTUQQ2PS 45493 CPL: 3 45494 CATEGORY: CONVERT 45495 EXTENSION: AVX512EVEX 45496 ISA_SET: AVX512DQ_512 45497 EXCEPTIONS: AVX512-E2 45498 REAL_OPCODE: Y 45499 ATTRIBUTES: MXCSR MASKOP_EVEX 45500 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 45501 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 45502 IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 45503 } 45504 45505 { 45506 ICLASS: VCVTUQQ2PS 45507 CPL: 3 45508 CATEGORY: CONVERT 45509 EXTENSION: AVX512EVEX 45510 ISA_SET: AVX512DQ_512 45511 EXCEPTIONS: AVX512-E2 45512 REAL_OPCODE: Y 45513 ATTRIBUTES: MXCSR MASKOP_EVEX 45514 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 45515 OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 45516 IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 45517 } 45518 45519 { 45520 ICLASS: VCVTUQQ2PS 45521 CPL: 3 45522 CATEGORY: CONVERT 45523 EXTENSION: AVX512EVEX 45524 ISA_SET: AVX512DQ_512 45525 EXCEPTIONS: AVX512-E2 45526 REAL_OPCODE: Y 45527 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45528 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 45529 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 45530 IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 45531 } 45532 45533 45534 # EMITTING VDBPSADBW (VDBPSADBW-128-1) 45535 { 45536 ICLASS: VDBPSADBW 45537 CPL: 3 45538 CATEGORY: AVX512 45539 EXTENSION: AVX512EVEX 45540 ISA_SET: AVX512BW_128 45541 EXCEPTIONS: AVX512-E4 45542 REAL_OPCODE: Y 45543 ATTRIBUTES: MASKOP_EVEX 45544 PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 45545 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b 45546 IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 45547 } 45548 45549 { 45550 ICLASS: VDBPSADBW 45551 CPL: 3 45552 CATEGORY: AVX512 45553 EXTENSION: AVX512EVEX 45554 ISA_SET: AVX512BW_128 45555 EXCEPTIONS: AVX512-E4 45556 REAL_OPCODE: Y 45557 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 45558 PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 45559 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b 45560 IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 45561 } 45562 45563 45564 # EMITTING VDBPSADBW (VDBPSADBW-256-1) 45565 { 45566 ICLASS: VDBPSADBW 45567 CPL: 3 45568 CATEGORY: AVX512 45569 EXTENSION: AVX512EVEX 45570 ISA_SET: AVX512BW_256 45571 EXCEPTIONS: AVX512-E4 45572 REAL_OPCODE: Y 45573 ATTRIBUTES: MASKOP_EVEX 45574 PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 45575 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b 45576 IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 45577 } 45578 45579 { 45580 ICLASS: VDBPSADBW 45581 CPL: 3 45582 CATEGORY: AVX512 45583 EXTENSION: AVX512EVEX 45584 ISA_SET: AVX512BW_256 45585 EXCEPTIONS: AVX512-E4 45586 REAL_OPCODE: Y 45587 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 45588 PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 45589 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b 45590 IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 45591 } 45592 45593 45594 # EMITTING VDBPSADBW (VDBPSADBW-512-1) 45595 { 45596 ICLASS: VDBPSADBW 45597 CPL: 3 45598 CATEGORY: AVX512 45599 EXTENSION: AVX512EVEX 45600 ISA_SET: AVX512BW_512 45601 EXCEPTIONS: AVX512-E4 45602 REAL_OPCODE: Y 45603 ATTRIBUTES: MASKOP_EVEX 45604 PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 45605 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b 45606 IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 45607 } 45608 45609 { 45610 ICLASS: VDBPSADBW 45611 CPL: 3 45612 CATEGORY: AVX512 45613 EXTENSION: AVX512EVEX 45614 ISA_SET: AVX512BW_512 45615 EXCEPTIONS: AVX512-E4 45616 REAL_OPCODE: Y 45617 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 45618 PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 45619 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b 45620 IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 45621 } 45622 45623 45624 # EMITTING VDIVPD (VDIVPD-128-1) 45625 { 45626 ICLASS: VDIVPD 45627 CPL: 3 45628 CATEGORY: AVX512 45629 EXTENSION: AVX512EVEX 45630 ISA_SET: AVX512F_128 45631 EXCEPTIONS: AVX512-E2 45632 REAL_OPCODE: Y 45633 ATTRIBUTES: MXCSR MASKOP_EVEX 45634 PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 45635 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 45636 IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 45637 } 45638 45639 { 45640 ICLASS: VDIVPD 45641 CPL: 3 45642 CATEGORY: AVX512 45643 EXTENSION: AVX512EVEX 45644 ISA_SET: AVX512F_128 45645 EXCEPTIONS: AVX512-E2 45646 REAL_OPCODE: Y 45647 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45648 PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 45649 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 45650 IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 45651 } 45652 45653 45654 # EMITTING VDIVPD (VDIVPD-256-1) 45655 { 45656 ICLASS: VDIVPD 45657 CPL: 3 45658 CATEGORY: AVX512 45659 EXTENSION: AVX512EVEX 45660 ISA_SET: AVX512F_256 45661 EXCEPTIONS: AVX512-E2 45662 REAL_OPCODE: Y 45663 ATTRIBUTES: MXCSR MASKOP_EVEX 45664 PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 45665 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 45666 IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 45667 } 45668 45669 { 45670 ICLASS: VDIVPD 45671 CPL: 3 45672 CATEGORY: AVX512 45673 EXTENSION: AVX512EVEX 45674 ISA_SET: AVX512F_256 45675 EXCEPTIONS: AVX512-E2 45676 REAL_OPCODE: Y 45677 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45678 PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 45679 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 45680 IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 45681 } 45682 45683 45684 # EMITTING VDIVPS (VDIVPS-128-1) 45685 { 45686 ICLASS: VDIVPS 45687 CPL: 3 45688 CATEGORY: AVX512 45689 EXTENSION: AVX512EVEX 45690 ISA_SET: AVX512F_128 45691 EXCEPTIONS: AVX512-E2 45692 REAL_OPCODE: Y 45693 ATTRIBUTES: MXCSR MASKOP_EVEX 45694 PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 45695 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 45696 IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 45697 } 45698 45699 { 45700 ICLASS: VDIVPS 45701 CPL: 3 45702 CATEGORY: AVX512 45703 EXTENSION: AVX512EVEX 45704 ISA_SET: AVX512F_128 45705 EXCEPTIONS: AVX512-E2 45706 REAL_OPCODE: Y 45707 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45708 PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 45709 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 45710 IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 45711 } 45712 45713 45714 # EMITTING VDIVPS (VDIVPS-256-1) 45715 { 45716 ICLASS: VDIVPS 45717 CPL: 3 45718 CATEGORY: AVX512 45719 EXTENSION: AVX512EVEX 45720 ISA_SET: AVX512F_256 45721 EXCEPTIONS: AVX512-E2 45722 REAL_OPCODE: Y 45723 ATTRIBUTES: MXCSR MASKOP_EVEX 45724 PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 45725 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 45726 IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 45727 } 45728 45729 { 45730 ICLASS: VDIVPS 45731 CPL: 3 45732 CATEGORY: AVX512 45733 EXTENSION: AVX512EVEX 45734 ISA_SET: AVX512F_256 45735 EXCEPTIONS: AVX512-E2 45736 REAL_OPCODE: Y 45737 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45738 PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 45739 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 45740 IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 45741 } 45742 45743 45744 # EMITTING VEXPANDPD (VEXPANDPD-128-1) 45745 { 45746 ICLASS: VEXPANDPD 45747 CPL: 3 45748 CATEGORY: EXPAND 45749 EXTENSION: AVX512EVEX 45750 ISA_SET: AVX512F_128 45751 EXCEPTIONS: AVX512-E4 45752 REAL_OPCODE: Y 45753 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 45754 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 45755 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 45756 IFORM: VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 45757 } 45758 45759 45760 # EMITTING VEXPANDPD (VEXPANDPD-128-2) 45761 { 45762 ICLASS: VEXPANDPD 45763 CPL: 3 45764 CATEGORY: EXPAND 45765 EXTENSION: AVX512EVEX 45766 ISA_SET: AVX512F_128 45767 EXCEPTIONS: AVX512-E4 45768 REAL_OPCODE: Y 45769 ATTRIBUTES: MASKOP_EVEX 45770 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 45771 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 45772 IFORM: VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 45773 } 45774 45775 45776 # EMITTING VEXPANDPD (VEXPANDPD-256-1) 45777 { 45778 ICLASS: VEXPANDPD 45779 CPL: 3 45780 CATEGORY: EXPAND 45781 EXTENSION: AVX512EVEX 45782 ISA_SET: AVX512F_256 45783 EXCEPTIONS: AVX512-E4 45784 REAL_OPCODE: Y 45785 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 45786 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 45787 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 45788 IFORM: VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 45789 } 45790 45791 45792 # EMITTING VEXPANDPD (VEXPANDPD-256-2) 45793 { 45794 ICLASS: VEXPANDPD 45795 CPL: 3 45796 CATEGORY: EXPAND 45797 EXTENSION: AVX512EVEX 45798 ISA_SET: AVX512F_256 45799 EXCEPTIONS: AVX512-E4 45800 REAL_OPCODE: Y 45801 ATTRIBUTES: MASKOP_EVEX 45802 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 45803 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 45804 IFORM: VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 45805 } 45806 45807 45808 # EMITTING VEXPANDPS (VEXPANDPS-128-1) 45809 { 45810 ICLASS: VEXPANDPS 45811 CPL: 3 45812 CATEGORY: EXPAND 45813 EXTENSION: AVX512EVEX 45814 ISA_SET: AVX512F_128 45815 EXCEPTIONS: AVX512-E4 45816 REAL_OPCODE: Y 45817 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 45818 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 45819 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 45820 IFORM: VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 45821 } 45822 45823 45824 # EMITTING VEXPANDPS (VEXPANDPS-128-2) 45825 { 45826 ICLASS: VEXPANDPS 45827 CPL: 3 45828 CATEGORY: EXPAND 45829 EXTENSION: AVX512EVEX 45830 ISA_SET: AVX512F_128 45831 EXCEPTIONS: AVX512-E4 45832 REAL_OPCODE: Y 45833 ATTRIBUTES: MASKOP_EVEX 45834 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 45835 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 45836 IFORM: VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 45837 } 45838 45839 45840 # EMITTING VEXPANDPS (VEXPANDPS-256-1) 45841 { 45842 ICLASS: VEXPANDPS 45843 CPL: 3 45844 CATEGORY: EXPAND 45845 EXTENSION: AVX512EVEX 45846 ISA_SET: AVX512F_256 45847 EXCEPTIONS: AVX512-E4 45848 REAL_OPCODE: Y 45849 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 45850 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 45851 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 45852 IFORM: VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 45853 } 45854 45855 45856 # EMITTING VEXPANDPS (VEXPANDPS-256-2) 45857 { 45858 ICLASS: VEXPANDPS 45859 CPL: 3 45860 CATEGORY: EXPAND 45861 EXTENSION: AVX512EVEX 45862 ISA_SET: AVX512F_256 45863 EXCEPTIONS: AVX512-E4 45864 REAL_OPCODE: Y 45865 ATTRIBUTES: MASKOP_EVEX 45866 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 45867 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 45868 IFORM: VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 45869 } 45870 45871 45872 # EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-1) 45873 { 45874 ICLASS: VEXTRACTF32X4 45875 CPL: 3 45876 CATEGORY: AVX512 45877 EXTENSION: AVX512EVEX 45878 ISA_SET: AVX512F_256 45879 EXCEPTIONS: AVX512-E6NF 45880 REAL_OPCODE: Y 45881 ATTRIBUTES: MASKOP_EVEX 45882 PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 45883 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b 45884 IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 45885 } 45886 45887 45888 # EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-2) 45889 { 45890 ICLASS: VEXTRACTF32X4 45891 CPL: 3 45892 CATEGORY: AVX512 45893 EXTENSION: AVX512EVEX 45894 ISA_SET: AVX512F_256 45895 EXCEPTIONS: AVX512-E6NF 45896 REAL_OPCODE: Y 45897 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 45898 PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 45899 OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b 45900 IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 45901 } 45902 45903 45904 # EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-1) 45905 { 45906 ICLASS: VEXTRACTF32X8 45907 CPL: 3 45908 CATEGORY: AVX512 45909 EXTENSION: AVX512EVEX 45910 ISA_SET: AVX512DQ_512 45911 EXCEPTIONS: AVX512-E6NF 45912 REAL_OPCODE: Y 45913 ATTRIBUTES: MASKOP_EVEX 45914 PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 45915 OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b 45916 IFORM: VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 45917 } 45918 45919 45920 # EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-2) 45921 { 45922 ICLASS: VEXTRACTF32X8 45923 CPL: 3 45924 CATEGORY: AVX512 45925 EXTENSION: AVX512EVEX 45926 ISA_SET: AVX512DQ_512 45927 EXCEPTIONS: AVX512-E6NF 45928 REAL_OPCODE: Y 45929 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 45930 PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() 45931 OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b 45932 IFORM: VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 45933 } 45934 45935 45936 # EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-1) 45937 { 45938 ICLASS: VEXTRACTF64X2 45939 CPL: 3 45940 CATEGORY: AVX512 45941 EXTENSION: AVX512EVEX 45942 ISA_SET: AVX512DQ_256 45943 EXCEPTIONS: AVX512-E6NF 45944 REAL_OPCODE: Y 45945 ATTRIBUTES: MASKOP_EVEX 45946 PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 45947 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 IMM0:r:b 45948 IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 45949 } 45950 45951 45952 # EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-2) 45953 { 45954 ICLASS: VEXTRACTF64X2 45955 CPL: 3 45956 CATEGORY: AVX512 45957 EXTENSION: AVX512EVEX 45958 ISA_SET: AVX512DQ_256 45959 EXCEPTIONS: AVX512-E6NF 45960 REAL_OPCODE: Y 45961 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 45962 PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 45963 OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 IMM0:r:b 45964 IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 45965 } 45966 45967 45968 # EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-1) 45969 { 45970 ICLASS: VEXTRACTF64X2 45971 CPL: 3 45972 CATEGORY: AVX512 45973 EXTENSION: AVX512EVEX 45974 ISA_SET: AVX512DQ_512 45975 EXCEPTIONS: AVX512-E6NF 45976 REAL_OPCODE: Y 45977 ATTRIBUTES: MASKOP_EVEX 45978 PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 45979 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b 45980 IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 45981 } 45982 45983 45984 # EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-2) 45985 { 45986 ICLASS: VEXTRACTF64X2 45987 CPL: 3 45988 CATEGORY: AVX512 45989 EXTENSION: AVX512EVEX 45990 ISA_SET: AVX512DQ_512 45991 EXCEPTIONS: AVX512-E6NF 45992 REAL_OPCODE: Y 45993 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 45994 PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 45995 OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b 45996 IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 45997 } 45998 45999 46000 # EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-1) 46001 { 46002 ICLASS: VEXTRACTI32X4 46003 CPL: 3 46004 CATEGORY: AVX512 46005 EXTENSION: AVX512EVEX 46006 ISA_SET: AVX512F_256 46007 EXCEPTIONS: AVX512-E6NF 46008 REAL_OPCODE: Y 46009 ATTRIBUTES: MASKOP_EVEX 46010 PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 46011 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 IMM0:r:b 46012 IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 46013 } 46014 46015 46016 # EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-2) 46017 { 46018 ICLASS: VEXTRACTI32X4 46019 CPL: 3 46020 CATEGORY: AVX512 46021 EXTENSION: AVX512EVEX 46022 ISA_SET: AVX512F_256 46023 EXCEPTIONS: AVX512-E6NF 46024 REAL_OPCODE: Y 46025 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 46026 PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 46027 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 IMM0:r:b 46028 IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 46029 } 46030 46031 46032 # EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-1) 46033 { 46034 ICLASS: VEXTRACTI32X8 46035 CPL: 3 46036 CATEGORY: AVX512 46037 EXTENSION: AVX512EVEX 46038 ISA_SET: AVX512DQ_512 46039 EXCEPTIONS: AVX512-E6NF 46040 REAL_OPCODE: Y 46041 ATTRIBUTES: MASKOP_EVEX 46042 PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 46043 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b 46044 IFORM: VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 46045 } 46046 46047 46048 # EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-2) 46049 { 46050 ICLASS: VEXTRACTI32X8 46051 CPL: 3 46052 CATEGORY: AVX512 46053 EXTENSION: AVX512EVEX 46054 ISA_SET: AVX512DQ_512 46055 EXCEPTIONS: AVX512-E6NF 46056 REAL_OPCODE: Y 46057 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 46058 PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() 46059 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b 46060 IFORM: VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 46061 } 46062 46063 46064 # EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-1) 46065 { 46066 ICLASS: VEXTRACTI64X2 46067 CPL: 3 46068 CATEGORY: AVX512 46069 EXTENSION: AVX512EVEX 46070 ISA_SET: AVX512DQ_256 46071 EXCEPTIONS: AVX512-E6NF 46072 REAL_OPCODE: Y 46073 ATTRIBUTES: MASKOP_EVEX 46074 PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 46075 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 IMM0:r:b 46076 IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 46077 } 46078 46079 46080 # EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-2) 46081 { 46082 ICLASS: VEXTRACTI64X2 46083 CPL: 3 46084 CATEGORY: AVX512 46085 EXTENSION: AVX512EVEX 46086 ISA_SET: AVX512DQ_256 46087 EXCEPTIONS: AVX512-E6NF 46088 REAL_OPCODE: Y 46089 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 46090 PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 46091 OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b 46092 IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 46093 } 46094 46095 46096 # EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-1) 46097 { 46098 ICLASS: VEXTRACTI64X2 46099 CPL: 3 46100 CATEGORY: AVX512 46101 EXTENSION: AVX512EVEX 46102 ISA_SET: AVX512DQ_512 46103 EXCEPTIONS: AVX512-E6NF 46104 REAL_OPCODE: Y 46105 ATTRIBUTES: MASKOP_EVEX 46106 PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 46107 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b 46108 IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 46109 } 46110 46111 46112 # EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-2) 46113 { 46114 ICLASS: VEXTRACTI64X2 46115 CPL: 3 46116 CATEGORY: AVX512 46117 EXTENSION: AVX512EVEX 46118 ISA_SET: AVX512DQ_512 46119 EXCEPTIONS: AVX512-E6NF 46120 REAL_OPCODE: Y 46121 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 46122 PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 46123 OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b 46124 IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 46125 } 46126 46127 46128 # EMITTING VFIXUPIMMPD (VFIXUPIMMPD-128-1) 46129 { 46130 ICLASS: VFIXUPIMMPD 46131 CPL: 3 46132 CATEGORY: AVX512 46133 EXTENSION: AVX512EVEX 46134 ISA_SET: AVX512F_128 46135 EXCEPTIONS: AVX512-E2 46136 REAL_OPCODE: Y 46137 ATTRIBUTES: MXCSR MASKOP_EVEX 46138 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 46139 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 46140 IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 46141 } 46142 46143 { 46144 ICLASS: VFIXUPIMMPD 46145 CPL: 3 46146 CATEGORY: AVX512 46147 EXTENSION: AVX512EVEX 46148 ISA_SET: AVX512F_128 46149 EXCEPTIONS: AVX512-E2 46150 REAL_OPCODE: Y 46151 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46152 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 46153 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 46154 IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 46155 } 46156 46157 46158 # EMITTING VFIXUPIMMPD (VFIXUPIMMPD-256-1) 46159 { 46160 ICLASS: VFIXUPIMMPD 46161 CPL: 3 46162 CATEGORY: AVX512 46163 EXTENSION: AVX512EVEX 46164 ISA_SET: AVX512F_256 46165 EXCEPTIONS: AVX512-E2 46166 REAL_OPCODE: Y 46167 ATTRIBUTES: MXCSR MASKOP_EVEX 46168 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 46169 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 46170 IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 46171 } 46172 46173 { 46174 ICLASS: VFIXUPIMMPD 46175 CPL: 3 46176 CATEGORY: AVX512 46177 EXTENSION: AVX512EVEX 46178 ISA_SET: AVX512F_256 46179 EXCEPTIONS: AVX512-E2 46180 REAL_OPCODE: Y 46181 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46182 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 46183 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 46184 IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 46185 } 46186 46187 46188 # EMITTING VFIXUPIMMPS (VFIXUPIMMPS-128-1) 46189 { 46190 ICLASS: VFIXUPIMMPS 46191 CPL: 3 46192 CATEGORY: AVX512 46193 EXTENSION: AVX512EVEX 46194 ISA_SET: AVX512F_128 46195 EXCEPTIONS: AVX512-E2 46196 REAL_OPCODE: Y 46197 ATTRIBUTES: MXCSR MASKOP_EVEX 46198 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 46199 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 46200 IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 46201 } 46202 46203 { 46204 ICLASS: VFIXUPIMMPS 46205 CPL: 3 46206 CATEGORY: AVX512 46207 EXTENSION: AVX512EVEX 46208 ISA_SET: AVX512F_128 46209 EXCEPTIONS: AVX512-E2 46210 REAL_OPCODE: Y 46211 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46212 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 46213 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 46214 IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 46215 } 46216 46217 46218 # EMITTING VFIXUPIMMPS (VFIXUPIMMPS-256-1) 46219 { 46220 ICLASS: VFIXUPIMMPS 46221 CPL: 3 46222 CATEGORY: AVX512 46223 EXTENSION: AVX512EVEX 46224 ISA_SET: AVX512F_256 46225 EXCEPTIONS: AVX512-E2 46226 REAL_OPCODE: Y 46227 ATTRIBUTES: MXCSR MASKOP_EVEX 46228 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 46229 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 46230 IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 46231 } 46232 46233 { 46234 ICLASS: VFIXUPIMMPS 46235 CPL: 3 46236 CATEGORY: AVX512 46237 EXTENSION: AVX512EVEX 46238 ISA_SET: AVX512F_256 46239 EXCEPTIONS: AVX512-E2 46240 REAL_OPCODE: Y 46241 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46242 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 46243 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 46244 IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 46245 } 46246 46247 46248 # EMITTING VFMADD132PD (VFMADD132PD-128-1) 46249 { 46250 ICLASS: VFMADD132PD 46251 CPL: 3 46252 CATEGORY: VFMA 46253 EXTENSION: AVX512EVEX 46254 ISA_SET: AVX512F_128 46255 EXCEPTIONS: AVX512-E2 46256 REAL_OPCODE: Y 46257 ATTRIBUTES: MXCSR MASKOP_EVEX 46258 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 46259 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 46260 IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 46261 } 46262 46263 { 46264 ICLASS: VFMADD132PD 46265 CPL: 3 46266 CATEGORY: VFMA 46267 EXTENSION: AVX512EVEX 46268 ISA_SET: AVX512F_128 46269 EXCEPTIONS: AVX512-E2 46270 REAL_OPCODE: Y 46271 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46272 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 46273 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46274 IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 46275 } 46276 46277 46278 # EMITTING VFMADD132PD (VFMADD132PD-256-1) 46279 { 46280 ICLASS: VFMADD132PD 46281 CPL: 3 46282 CATEGORY: VFMA 46283 EXTENSION: AVX512EVEX 46284 ISA_SET: AVX512F_256 46285 EXCEPTIONS: AVX512-E2 46286 REAL_OPCODE: Y 46287 ATTRIBUTES: MXCSR MASKOP_EVEX 46288 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 46289 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 46290 IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 46291 } 46292 46293 { 46294 ICLASS: VFMADD132PD 46295 CPL: 3 46296 CATEGORY: VFMA 46297 EXTENSION: AVX512EVEX 46298 ISA_SET: AVX512F_256 46299 EXCEPTIONS: AVX512-E2 46300 REAL_OPCODE: Y 46301 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46302 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 46303 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46304 IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 46305 } 46306 46307 46308 # EMITTING VFMADD132PS (VFMADD132PS-128-1) 46309 { 46310 ICLASS: VFMADD132PS 46311 CPL: 3 46312 CATEGORY: VFMA 46313 EXTENSION: AVX512EVEX 46314 ISA_SET: AVX512F_128 46315 EXCEPTIONS: AVX512-E2 46316 REAL_OPCODE: Y 46317 ATTRIBUTES: MXCSR MASKOP_EVEX 46318 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 46319 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 46320 IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 46321 } 46322 46323 { 46324 ICLASS: VFMADD132PS 46325 CPL: 3 46326 CATEGORY: VFMA 46327 EXTENSION: AVX512EVEX 46328 ISA_SET: AVX512F_128 46329 EXCEPTIONS: AVX512-E2 46330 REAL_OPCODE: Y 46331 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46332 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 46333 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46334 IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 46335 } 46336 46337 46338 # EMITTING VFMADD132PS (VFMADD132PS-256-1) 46339 { 46340 ICLASS: VFMADD132PS 46341 CPL: 3 46342 CATEGORY: VFMA 46343 EXTENSION: AVX512EVEX 46344 ISA_SET: AVX512F_256 46345 EXCEPTIONS: AVX512-E2 46346 REAL_OPCODE: Y 46347 ATTRIBUTES: MXCSR MASKOP_EVEX 46348 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 46349 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 46350 IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 46351 } 46352 46353 { 46354 ICLASS: VFMADD132PS 46355 CPL: 3 46356 CATEGORY: VFMA 46357 EXTENSION: AVX512EVEX 46358 ISA_SET: AVX512F_256 46359 EXCEPTIONS: AVX512-E2 46360 REAL_OPCODE: Y 46361 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46362 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 46363 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46364 IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 46365 } 46366 46367 46368 # EMITTING VFMADD213PD (VFMADD213PD-128-1) 46369 { 46370 ICLASS: VFMADD213PD 46371 CPL: 3 46372 CATEGORY: VFMA 46373 EXTENSION: AVX512EVEX 46374 ISA_SET: AVX512F_128 46375 EXCEPTIONS: AVX512-E2 46376 REAL_OPCODE: Y 46377 ATTRIBUTES: MXCSR MASKOP_EVEX 46378 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 46379 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 46380 IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 46381 } 46382 46383 { 46384 ICLASS: VFMADD213PD 46385 CPL: 3 46386 CATEGORY: VFMA 46387 EXTENSION: AVX512EVEX 46388 ISA_SET: AVX512F_128 46389 EXCEPTIONS: AVX512-E2 46390 REAL_OPCODE: Y 46391 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46392 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 46393 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46394 IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 46395 } 46396 46397 46398 # EMITTING VFMADD213PD (VFMADD213PD-256-1) 46399 { 46400 ICLASS: VFMADD213PD 46401 CPL: 3 46402 CATEGORY: VFMA 46403 EXTENSION: AVX512EVEX 46404 ISA_SET: AVX512F_256 46405 EXCEPTIONS: AVX512-E2 46406 REAL_OPCODE: Y 46407 ATTRIBUTES: MXCSR MASKOP_EVEX 46408 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 46409 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 46410 IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 46411 } 46412 46413 { 46414 ICLASS: VFMADD213PD 46415 CPL: 3 46416 CATEGORY: VFMA 46417 EXTENSION: AVX512EVEX 46418 ISA_SET: AVX512F_256 46419 EXCEPTIONS: AVX512-E2 46420 REAL_OPCODE: Y 46421 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46422 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 46423 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46424 IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 46425 } 46426 46427 46428 # EMITTING VFMADD213PS (VFMADD213PS-128-1) 46429 { 46430 ICLASS: VFMADD213PS 46431 CPL: 3 46432 CATEGORY: VFMA 46433 EXTENSION: AVX512EVEX 46434 ISA_SET: AVX512F_128 46435 EXCEPTIONS: AVX512-E2 46436 REAL_OPCODE: Y 46437 ATTRIBUTES: MXCSR MASKOP_EVEX 46438 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 46439 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 46440 IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 46441 } 46442 46443 { 46444 ICLASS: VFMADD213PS 46445 CPL: 3 46446 CATEGORY: VFMA 46447 EXTENSION: AVX512EVEX 46448 ISA_SET: AVX512F_128 46449 EXCEPTIONS: AVX512-E2 46450 REAL_OPCODE: Y 46451 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46452 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 46453 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46454 IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 46455 } 46456 46457 46458 # EMITTING VFMADD213PS (VFMADD213PS-256-1) 46459 { 46460 ICLASS: VFMADD213PS 46461 CPL: 3 46462 CATEGORY: VFMA 46463 EXTENSION: AVX512EVEX 46464 ISA_SET: AVX512F_256 46465 EXCEPTIONS: AVX512-E2 46466 REAL_OPCODE: Y 46467 ATTRIBUTES: MXCSR MASKOP_EVEX 46468 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 46469 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 46470 IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 46471 } 46472 46473 { 46474 ICLASS: VFMADD213PS 46475 CPL: 3 46476 CATEGORY: VFMA 46477 EXTENSION: AVX512EVEX 46478 ISA_SET: AVX512F_256 46479 EXCEPTIONS: AVX512-E2 46480 REAL_OPCODE: Y 46481 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46482 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 46483 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46484 IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 46485 } 46486 46487 46488 # EMITTING VFMADD231PD (VFMADD231PD-128-1) 46489 { 46490 ICLASS: VFMADD231PD 46491 CPL: 3 46492 CATEGORY: VFMA 46493 EXTENSION: AVX512EVEX 46494 ISA_SET: AVX512F_128 46495 EXCEPTIONS: AVX512-E2 46496 REAL_OPCODE: Y 46497 ATTRIBUTES: MXCSR MASKOP_EVEX 46498 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 46499 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 46500 IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 46501 } 46502 46503 { 46504 ICLASS: VFMADD231PD 46505 CPL: 3 46506 CATEGORY: VFMA 46507 EXTENSION: AVX512EVEX 46508 ISA_SET: AVX512F_128 46509 EXCEPTIONS: AVX512-E2 46510 REAL_OPCODE: Y 46511 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46512 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 46513 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46514 IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 46515 } 46516 46517 46518 # EMITTING VFMADD231PD (VFMADD231PD-256-1) 46519 { 46520 ICLASS: VFMADD231PD 46521 CPL: 3 46522 CATEGORY: VFMA 46523 EXTENSION: AVX512EVEX 46524 ISA_SET: AVX512F_256 46525 EXCEPTIONS: AVX512-E2 46526 REAL_OPCODE: Y 46527 ATTRIBUTES: MXCSR MASKOP_EVEX 46528 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 46529 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 46530 IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 46531 } 46532 46533 { 46534 ICLASS: VFMADD231PD 46535 CPL: 3 46536 CATEGORY: VFMA 46537 EXTENSION: AVX512EVEX 46538 ISA_SET: AVX512F_256 46539 EXCEPTIONS: AVX512-E2 46540 REAL_OPCODE: Y 46541 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46542 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 46543 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46544 IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 46545 } 46546 46547 46548 # EMITTING VFMADD231PS (VFMADD231PS-128-1) 46549 { 46550 ICLASS: VFMADD231PS 46551 CPL: 3 46552 CATEGORY: VFMA 46553 EXTENSION: AVX512EVEX 46554 ISA_SET: AVX512F_128 46555 EXCEPTIONS: AVX512-E2 46556 REAL_OPCODE: Y 46557 ATTRIBUTES: MXCSR MASKOP_EVEX 46558 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 46559 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 46560 IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 46561 } 46562 46563 { 46564 ICLASS: VFMADD231PS 46565 CPL: 3 46566 CATEGORY: VFMA 46567 EXTENSION: AVX512EVEX 46568 ISA_SET: AVX512F_128 46569 EXCEPTIONS: AVX512-E2 46570 REAL_OPCODE: Y 46571 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46572 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 46573 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46574 IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 46575 } 46576 46577 46578 # EMITTING VFMADD231PS (VFMADD231PS-256-1) 46579 { 46580 ICLASS: VFMADD231PS 46581 CPL: 3 46582 CATEGORY: VFMA 46583 EXTENSION: AVX512EVEX 46584 ISA_SET: AVX512F_256 46585 EXCEPTIONS: AVX512-E2 46586 REAL_OPCODE: Y 46587 ATTRIBUTES: MXCSR MASKOP_EVEX 46588 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 46589 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 46590 IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 46591 } 46592 46593 { 46594 ICLASS: VFMADD231PS 46595 CPL: 3 46596 CATEGORY: VFMA 46597 EXTENSION: AVX512EVEX 46598 ISA_SET: AVX512F_256 46599 EXCEPTIONS: AVX512-E2 46600 REAL_OPCODE: Y 46601 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46602 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 46603 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46604 IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 46605 } 46606 46607 46608 # EMITTING VFMADDSUB132PD (VFMADDSUB132PD-128-1) 46609 { 46610 ICLASS: VFMADDSUB132PD 46611 CPL: 3 46612 CATEGORY: VFMA 46613 EXTENSION: AVX512EVEX 46614 ISA_SET: AVX512F_128 46615 EXCEPTIONS: AVX512-E2 46616 REAL_OPCODE: Y 46617 ATTRIBUTES: MXCSR MASKOP_EVEX 46618 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 46619 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 46620 IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 46621 } 46622 46623 { 46624 ICLASS: VFMADDSUB132PD 46625 CPL: 3 46626 CATEGORY: VFMA 46627 EXTENSION: AVX512EVEX 46628 ISA_SET: AVX512F_128 46629 EXCEPTIONS: AVX512-E2 46630 REAL_OPCODE: Y 46631 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46632 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 46633 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46634 IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 46635 } 46636 46637 46638 # EMITTING VFMADDSUB132PD (VFMADDSUB132PD-256-1) 46639 { 46640 ICLASS: VFMADDSUB132PD 46641 CPL: 3 46642 CATEGORY: VFMA 46643 EXTENSION: AVX512EVEX 46644 ISA_SET: AVX512F_256 46645 EXCEPTIONS: AVX512-E2 46646 REAL_OPCODE: Y 46647 ATTRIBUTES: MXCSR MASKOP_EVEX 46648 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 46649 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 46650 IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 46651 } 46652 46653 { 46654 ICLASS: VFMADDSUB132PD 46655 CPL: 3 46656 CATEGORY: VFMA 46657 EXTENSION: AVX512EVEX 46658 ISA_SET: AVX512F_256 46659 EXCEPTIONS: AVX512-E2 46660 REAL_OPCODE: Y 46661 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46662 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 46663 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46664 IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 46665 } 46666 46667 46668 # EMITTING VFMADDSUB132PS (VFMADDSUB132PS-128-1) 46669 { 46670 ICLASS: VFMADDSUB132PS 46671 CPL: 3 46672 CATEGORY: VFMA 46673 EXTENSION: AVX512EVEX 46674 ISA_SET: AVX512F_128 46675 EXCEPTIONS: AVX512-E2 46676 REAL_OPCODE: Y 46677 ATTRIBUTES: MXCSR MASKOP_EVEX 46678 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 46679 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 46680 IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 46681 } 46682 46683 { 46684 ICLASS: VFMADDSUB132PS 46685 CPL: 3 46686 CATEGORY: VFMA 46687 EXTENSION: AVX512EVEX 46688 ISA_SET: AVX512F_128 46689 EXCEPTIONS: AVX512-E2 46690 REAL_OPCODE: Y 46691 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46692 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 46693 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46694 IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 46695 } 46696 46697 46698 # EMITTING VFMADDSUB132PS (VFMADDSUB132PS-256-1) 46699 { 46700 ICLASS: VFMADDSUB132PS 46701 CPL: 3 46702 CATEGORY: VFMA 46703 EXTENSION: AVX512EVEX 46704 ISA_SET: AVX512F_256 46705 EXCEPTIONS: AVX512-E2 46706 REAL_OPCODE: Y 46707 ATTRIBUTES: MXCSR MASKOP_EVEX 46708 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 46709 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 46710 IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 46711 } 46712 46713 { 46714 ICLASS: VFMADDSUB132PS 46715 CPL: 3 46716 CATEGORY: VFMA 46717 EXTENSION: AVX512EVEX 46718 ISA_SET: AVX512F_256 46719 EXCEPTIONS: AVX512-E2 46720 REAL_OPCODE: Y 46721 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46722 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 46723 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46724 IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 46725 } 46726 46727 46728 # EMITTING VFMADDSUB213PD (VFMADDSUB213PD-128-1) 46729 { 46730 ICLASS: VFMADDSUB213PD 46731 CPL: 3 46732 CATEGORY: VFMA 46733 EXTENSION: AVX512EVEX 46734 ISA_SET: AVX512F_128 46735 EXCEPTIONS: AVX512-E2 46736 REAL_OPCODE: Y 46737 ATTRIBUTES: MXCSR MASKOP_EVEX 46738 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 46739 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 46740 IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 46741 } 46742 46743 { 46744 ICLASS: VFMADDSUB213PD 46745 CPL: 3 46746 CATEGORY: VFMA 46747 EXTENSION: AVX512EVEX 46748 ISA_SET: AVX512F_128 46749 EXCEPTIONS: AVX512-E2 46750 REAL_OPCODE: Y 46751 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46752 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 46753 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46754 IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 46755 } 46756 46757 46758 # EMITTING VFMADDSUB213PD (VFMADDSUB213PD-256-1) 46759 { 46760 ICLASS: VFMADDSUB213PD 46761 CPL: 3 46762 CATEGORY: VFMA 46763 EXTENSION: AVX512EVEX 46764 ISA_SET: AVX512F_256 46765 EXCEPTIONS: AVX512-E2 46766 REAL_OPCODE: Y 46767 ATTRIBUTES: MXCSR MASKOP_EVEX 46768 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 46769 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 46770 IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 46771 } 46772 46773 { 46774 ICLASS: VFMADDSUB213PD 46775 CPL: 3 46776 CATEGORY: VFMA 46777 EXTENSION: AVX512EVEX 46778 ISA_SET: AVX512F_256 46779 EXCEPTIONS: AVX512-E2 46780 REAL_OPCODE: Y 46781 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46782 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 46783 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46784 IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 46785 } 46786 46787 46788 # EMITTING VFMADDSUB213PS (VFMADDSUB213PS-128-1) 46789 { 46790 ICLASS: VFMADDSUB213PS 46791 CPL: 3 46792 CATEGORY: VFMA 46793 EXTENSION: AVX512EVEX 46794 ISA_SET: AVX512F_128 46795 EXCEPTIONS: AVX512-E2 46796 REAL_OPCODE: Y 46797 ATTRIBUTES: MXCSR MASKOP_EVEX 46798 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 46799 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 46800 IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 46801 } 46802 46803 { 46804 ICLASS: VFMADDSUB213PS 46805 CPL: 3 46806 CATEGORY: VFMA 46807 EXTENSION: AVX512EVEX 46808 ISA_SET: AVX512F_128 46809 EXCEPTIONS: AVX512-E2 46810 REAL_OPCODE: Y 46811 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46812 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 46813 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46814 IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 46815 } 46816 46817 46818 # EMITTING VFMADDSUB213PS (VFMADDSUB213PS-256-1) 46819 { 46820 ICLASS: VFMADDSUB213PS 46821 CPL: 3 46822 CATEGORY: VFMA 46823 EXTENSION: AVX512EVEX 46824 ISA_SET: AVX512F_256 46825 EXCEPTIONS: AVX512-E2 46826 REAL_OPCODE: Y 46827 ATTRIBUTES: MXCSR MASKOP_EVEX 46828 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 46829 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 46830 IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 46831 } 46832 46833 { 46834 ICLASS: VFMADDSUB213PS 46835 CPL: 3 46836 CATEGORY: VFMA 46837 EXTENSION: AVX512EVEX 46838 ISA_SET: AVX512F_256 46839 EXCEPTIONS: AVX512-E2 46840 REAL_OPCODE: Y 46841 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46842 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 46843 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46844 IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 46845 } 46846 46847 46848 # EMITTING VFMADDSUB231PD (VFMADDSUB231PD-128-1) 46849 { 46850 ICLASS: VFMADDSUB231PD 46851 CPL: 3 46852 CATEGORY: VFMA 46853 EXTENSION: AVX512EVEX 46854 ISA_SET: AVX512F_128 46855 EXCEPTIONS: AVX512-E2 46856 REAL_OPCODE: Y 46857 ATTRIBUTES: MXCSR MASKOP_EVEX 46858 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 46859 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 46860 IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 46861 } 46862 46863 { 46864 ICLASS: VFMADDSUB231PD 46865 CPL: 3 46866 CATEGORY: VFMA 46867 EXTENSION: AVX512EVEX 46868 ISA_SET: AVX512F_128 46869 EXCEPTIONS: AVX512-E2 46870 REAL_OPCODE: Y 46871 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46872 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 46873 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46874 IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 46875 } 46876 46877 46878 # EMITTING VFMADDSUB231PD (VFMADDSUB231PD-256-1) 46879 { 46880 ICLASS: VFMADDSUB231PD 46881 CPL: 3 46882 CATEGORY: VFMA 46883 EXTENSION: AVX512EVEX 46884 ISA_SET: AVX512F_256 46885 EXCEPTIONS: AVX512-E2 46886 REAL_OPCODE: Y 46887 ATTRIBUTES: MXCSR MASKOP_EVEX 46888 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 46889 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 46890 IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 46891 } 46892 46893 { 46894 ICLASS: VFMADDSUB231PD 46895 CPL: 3 46896 CATEGORY: VFMA 46897 EXTENSION: AVX512EVEX 46898 ISA_SET: AVX512F_256 46899 EXCEPTIONS: AVX512-E2 46900 REAL_OPCODE: Y 46901 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46902 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 46903 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46904 IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 46905 } 46906 46907 46908 # EMITTING VFMADDSUB231PS (VFMADDSUB231PS-128-1) 46909 { 46910 ICLASS: VFMADDSUB231PS 46911 CPL: 3 46912 CATEGORY: VFMA 46913 EXTENSION: AVX512EVEX 46914 ISA_SET: AVX512F_128 46915 EXCEPTIONS: AVX512-E2 46916 REAL_OPCODE: Y 46917 ATTRIBUTES: MXCSR MASKOP_EVEX 46918 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 46919 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 46920 IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 46921 } 46922 46923 { 46924 ICLASS: VFMADDSUB231PS 46925 CPL: 3 46926 CATEGORY: VFMA 46927 EXTENSION: AVX512EVEX 46928 ISA_SET: AVX512F_128 46929 EXCEPTIONS: AVX512-E2 46930 REAL_OPCODE: Y 46931 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46932 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 46933 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46934 IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 46935 } 46936 46937 46938 # EMITTING VFMADDSUB231PS (VFMADDSUB231PS-256-1) 46939 { 46940 ICLASS: VFMADDSUB231PS 46941 CPL: 3 46942 CATEGORY: VFMA 46943 EXTENSION: AVX512EVEX 46944 ISA_SET: AVX512F_256 46945 EXCEPTIONS: AVX512-E2 46946 REAL_OPCODE: Y 46947 ATTRIBUTES: MXCSR MASKOP_EVEX 46948 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 46949 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 46950 IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 46951 } 46952 46953 { 46954 ICLASS: VFMADDSUB231PS 46955 CPL: 3 46956 CATEGORY: VFMA 46957 EXTENSION: AVX512EVEX 46958 ISA_SET: AVX512F_256 46959 EXCEPTIONS: AVX512-E2 46960 REAL_OPCODE: Y 46961 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46962 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 46963 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 46964 IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 46965 } 46966 46967 46968 # EMITTING VFMSUB132PD (VFMSUB132PD-128-1) 46969 { 46970 ICLASS: VFMSUB132PD 46971 CPL: 3 46972 CATEGORY: VFMA 46973 EXTENSION: AVX512EVEX 46974 ISA_SET: AVX512F_128 46975 EXCEPTIONS: AVX512-E2 46976 REAL_OPCODE: Y 46977 ATTRIBUTES: MXCSR MASKOP_EVEX 46978 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 46979 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 46980 IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 46981 } 46982 46983 { 46984 ICLASS: VFMSUB132PD 46985 CPL: 3 46986 CATEGORY: VFMA 46987 EXTENSION: AVX512EVEX 46988 ISA_SET: AVX512F_128 46989 EXCEPTIONS: AVX512-E2 46990 REAL_OPCODE: Y 46991 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46992 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 46993 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 46994 IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 46995 } 46996 46997 46998 # EMITTING VFMSUB132PD (VFMSUB132PD-256-1) 46999 { 47000 ICLASS: VFMSUB132PD 47001 CPL: 3 47002 CATEGORY: VFMA 47003 EXTENSION: AVX512EVEX 47004 ISA_SET: AVX512F_256 47005 EXCEPTIONS: AVX512-E2 47006 REAL_OPCODE: Y 47007 ATTRIBUTES: MXCSR MASKOP_EVEX 47008 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47009 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 47010 IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 47011 } 47012 47013 { 47014 ICLASS: VFMSUB132PD 47015 CPL: 3 47016 CATEGORY: VFMA 47017 EXTENSION: AVX512EVEX 47018 ISA_SET: AVX512F_256 47019 EXCEPTIONS: AVX512-E2 47020 REAL_OPCODE: Y 47021 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47022 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47023 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47024 IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 47025 } 47026 47027 47028 # EMITTING VFMSUB132PS (VFMSUB132PS-128-1) 47029 { 47030 ICLASS: VFMSUB132PS 47031 CPL: 3 47032 CATEGORY: VFMA 47033 EXTENSION: AVX512EVEX 47034 ISA_SET: AVX512F_128 47035 EXCEPTIONS: AVX512-E2 47036 REAL_OPCODE: Y 47037 ATTRIBUTES: MXCSR MASKOP_EVEX 47038 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47039 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 47040 IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 47041 } 47042 47043 { 47044 ICLASS: VFMSUB132PS 47045 CPL: 3 47046 CATEGORY: VFMA 47047 EXTENSION: AVX512EVEX 47048 ISA_SET: AVX512F_128 47049 EXCEPTIONS: AVX512-E2 47050 REAL_OPCODE: Y 47051 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47052 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 47053 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47054 IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 47055 } 47056 47057 47058 # EMITTING VFMSUB132PS (VFMSUB132PS-256-1) 47059 { 47060 ICLASS: VFMSUB132PS 47061 CPL: 3 47062 CATEGORY: VFMA 47063 EXTENSION: AVX512EVEX 47064 ISA_SET: AVX512F_256 47065 EXCEPTIONS: AVX512-E2 47066 REAL_OPCODE: Y 47067 ATTRIBUTES: MXCSR MASKOP_EVEX 47068 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47069 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 47070 IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 47071 } 47072 47073 { 47074 ICLASS: VFMSUB132PS 47075 CPL: 3 47076 CATEGORY: VFMA 47077 EXTENSION: AVX512EVEX 47078 ISA_SET: AVX512F_256 47079 EXCEPTIONS: AVX512-E2 47080 REAL_OPCODE: Y 47081 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47082 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 47083 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47084 IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 47085 } 47086 47087 47088 # EMITTING VFMSUB213PD (VFMSUB213PD-128-1) 47089 { 47090 ICLASS: VFMSUB213PD 47091 CPL: 3 47092 CATEGORY: VFMA 47093 EXTENSION: AVX512EVEX 47094 ISA_SET: AVX512F_128 47095 EXCEPTIONS: AVX512-E2 47096 REAL_OPCODE: Y 47097 ATTRIBUTES: MXCSR MASKOP_EVEX 47098 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47099 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 47100 IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 47101 } 47102 47103 { 47104 ICLASS: VFMSUB213PD 47105 CPL: 3 47106 CATEGORY: VFMA 47107 EXTENSION: AVX512EVEX 47108 ISA_SET: AVX512F_128 47109 EXCEPTIONS: AVX512-E2 47110 REAL_OPCODE: Y 47111 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47112 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 47113 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47114 IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 47115 } 47116 47117 47118 # EMITTING VFMSUB213PD (VFMSUB213PD-256-1) 47119 { 47120 ICLASS: VFMSUB213PD 47121 CPL: 3 47122 CATEGORY: VFMA 47123 EXTENSION: AVX512EVEX 47124 ISA_SET: AVX512F_256 47125 EXCEPTIONS: AVX512-E2 47126 REAL_OPCODE: Y 47127 ATTRIBUTES: MXCSR MASKOP_EVEX 47128 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47129 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 47130 IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 47131 } 47132 47133 { 47134 ICLASS: VFMSUB213PD 47135 CPL: 3 47136 CATEGORY: VFMA 47137 EXTENSION: AVX512EVEX 47138 ISA_SET: AVX512F_256 47139 EXCEPTIONS: AVX512-E2 47140 REAL_OPCODE: Y 47141 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47142 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47143 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47144 IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 47145 } 47146 47147 47148 # EMITTING VFMSUB213PS (VFMSUB213PS-128-1) 47149 { 47150 ICLASS: VFMSUB213PS 47151 CPL: 3 47152 CATEGORY: VFMA 47153 EXTENSION: AVX512EVEX 47154 ISA_SET: AVX512F_128 47155 EXCEPTIONS: AVX512-E2 47156 REAL_OPCODE: Y 47157 ATTRIBUTES: MXCSR MASKOP_EVEX 47158 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47159 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 47160 IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 47161 } 47162 47163 { 47164 ICLASS: VFMSUB213PS 47165 CPL: 3 47166 CATEGORY: VFMA 47167 EXTENSION: AVX512EVEX 47168 ISA_SET: AVX512F_128 47169 EXCEPTIONS: AVX512-E2 47170 REAL_OPCODE: Y 47171 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47172 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 47173 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47174 IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 47175 } 47176 47177 47178 # EMITTING VFMSUB213PS (VFMSUB213PS-256-1) 47179 { 47180 ICLASS: VFMSUB213PS 47181 CPL: 3 47182 CATEGORY: VFMA 47183 EXTENSION: AVX512EVEX 47184 ISA_SET: AVX512F_256 47185 EXCEPTIONS: AVX512-E2 47186 REAL_OPCODE: Y 47187 ATTRIBUTES: MXCSR MASKOP_EVEX 47188 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47189 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 47190 IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 47191 } 47192 47193 { 47194 ICLASS: VFMSUB213PS 47195 CPL: 3 47196 CATEGORY: VFMA 47197 EXTENSION: AVX512EVEX 47198 ISA_SET: AVX512F_256 47199 EXCEPTIONS: AVX512-E2 47200 REAL_OPCODE: Y 47201 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47202 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 47203 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47204 IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 47205 } 47206 47207 47208 # EMITTING VFMSUB231PD (VFMSUB231PD-128-1) 47209 { 47210 ICLASS: VFMSUB231PD 47211 CPL: 3 47212 CATEGORY: VFMA 47213 EXTENSION: AVX512EVEX 47214 ISA_SET: AVX512F_128 47215 EXCEPTIONS: AVX512-E2 47216 REAL_OPCODE: Y 47217 ATTRIBUTES: MXCSR MASKOP_EVEX 47218 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47219 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 47220 IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 47221 } 47222 47223 { 47224 ICLASS: VFMSUB231PD 47225 CPL: 3 47226 CATEGORY: VFMA 47227 EXTENSION: AVX512EVEX 47228 ISA_SET: AVX512F_128 47229 EXCEPTIONS: AVX512-E2 47230 REAL_OPCODE: Y 47231 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47232 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 47233 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47234 IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 47235 } 47236 47237 47238 # EMITTING VFMSUB231PD (VFMSUB231PD-256-1) 47239 { 47240 ICLASS: VFMSUB231PD 47241 CPL: 3 47242 CATEGORY: VFMA 47243 EXTENSION: AVX512EVEX 47244 ISA_SET: AVX512F_256 47245 EXCEPTIONS: AVX512-E2 47246 REAL_OPCODE: Y 47247 ATTRIBUTES: MXCSR MASKOP_EVEX 47248 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47249 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 47250 IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 47251 } 47252 47253 { 47254 ICLASS: VFMSUB231PD 47255 CPL: 3 47256 CATEGORY: VFMA 47257 EXTENSION: AVX512EVEX 47258 ISA_SET: AVX512F_256 47259 EXCEPTIONS: AVX512-E2 47260 REAL_OPCODE: Y 47261 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47262 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47263 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47264 IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 47265 } 47266 47267 47268 # EMITTING VFMSUB231PS (VFMSUB231PS-128-1) 47269 { 47270 ICLASS: VFMSUB231PS 47271 CPL: 3 47272 CATEGORY: VFMA 47273 EXTENSION: AVX512EVEX 47274 ISA_SET: AVX512F_128 47275 EXCEPTIONS: AVX512-E2 47276 REAL_OPCODE: Y 47277 ATTRIBUTES: MXCSR MASKOP_EVEX 47278 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47279 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 47280 IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 47281 } 47282 47283 { 47284 ICLASS: VFMSUB231PS 47285 CPL: 3 47286 CATEGORY: VFMA 47287 EXTENSION: AVX512EVEX 47288 ISA_SET: AVX512F_128 47289 EXCEPTIONS: AVX512-E2 47290 REAL_OPCODE: Y 47291 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47292 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 47293 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47294 IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 47295 } 47296 47297 47298 # EMITTING VFMSUB231PS (VFMSUB231PS-256-1) 47299 { 47300 ICLASS: VFMSUB231PS 47301 CPL: 3 47302 CATEGORY: VFMA 47303 EXTENSION: AVX512EVEX 47304 ISA_SET: AVX512F_256 47305 EXCEPTIONS: AVX512-E2 47306 REAL_OPCODE: Y 47307 ATTRIBUTES: MXCSR MASKOP_EVEX 47308 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47309 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 47310 IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 47311 } 47312 47313 { 47314 ICLASS: VFMSUB231PS 47315 CPL: 3 47316 CATEGORY: VFMA 47317 EXTENSION: AVX512EVEX 47318 ISA_SET: AVX512F_256 47319 EXCEPTIONS: AVX512-E2 47320 REAL_OPCODE: Y 47321 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47322 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 47323 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47324 IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 47325 } 47326 47327 47328 # EMITTING VFMSUBADD132PD (VFMSUBADD132PD-128-1) 47329 { 47330 ICLASS: VFMSUBADD132PD 47331 CPL: 3 47332 CATEGORY: VFMA 47333 EXTENSION: AVX512EVEX 47334 ISA_SET: AVX512F_128 47335 EXCEPTIONS: AVX512-E2 47336 REAL_OPCODE: Y 47337 ATTRIBUTES: MXCSR MASKOP_EVEX 47338 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47339 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 47340 IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 47341 } 47342 47343 { 47344 ICLASS: VFMSUBADD132PD 47345 CPL: 3 47346 CATEGORY: VFMA 47347 EXTENSION: AVX512EVEX 47348 ISA_SET: AVX512F_128 47349 EXCEPTIONS: AVX512-E2 47350 REAL_OPCODE: Y 47351 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47352 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 47353 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47354 IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 47355 } 47356 47357 47358 # EMITTING VFMSUBADD132PD (VFMSUBADD132PD-256-1) 47359 { 47360 ICLASS: VFMSUBADD132PD 47361 CPL: 3 47362 CATEGORY: VFMA 47363 EXTENSION: AVX512EVEX 47364 ISA_SET: AVX512F_256 47365 EXCEPTIONS: AVX512-E2 47366 REAL_OPCODE: Y 47367 ATTRIBUTES: MXCSR MASKOP_EVEX 47368 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47369 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 47370 IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 47371 } 47372 47373 { 47374 ICLASS: VFMSUBADD132PD 47375 CPL: 3 47376 CATEGORY: VFMA 47377 EXTENSION: AVX512EVEX 47378 ISA_SET: AVX512F_256 47379 EXCEPTIONS: AVX512-E2 47380 REAL_OPCODE: Y 47381 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47382 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47383 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47384 IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 47385 } 47386 47387 47388 # EMITTING VFMSUBADD132PS (VFMSUBADD132PS-128-1) 47389 { 47390 ICLASS: VFMSUBADD132PS 47391 CPL: 3 47392 CATEGORY: VFMA 47393 EXTENSION: AVX512EVEX 47394 ISA_SET: AVX512F_128 47395 EXCEPTIONS: AVX512-E2 47396 REAL_OPCODE: Y 47397 ATTRIBUTES: MXCSR MASKOP_EVEX 47398 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47399 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 47400 IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 47401 } 47402 47403 { 47404 ICLASS: VFMSUBADD132PS 47405 CPL: 3 47406 CATEGORY: VFMA 47407 EXTENSION: AVX512EVEX 47408 ISA_SET: AVX512F_128 47409 EXCEPTIONS: AVX512-E2 47410 REAL_OPCODE: Y 47411 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47412 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 47413 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47414 IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 47415 } 47416 47417 47418 # EMITTING VFMSUBADD132PS (VFMSUBADD132PS-256-1) 47419 { 47420 ICLASS: VFMSUBADD132PS 47421 CPL: 3 47422 CATEGORY: VFMA 47423 EXTENSION: AVX512EVEX 47424 ISA_SET: AVX512F_256 47425 EXCEPTIONS: AVX512-E2 47426 REAL_OPCODE: Y 47427 ATTRIBUTES: MXCSR MASKOP_EVEX 47428 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47429 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 47430 IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 47431 } 47432 47433 { 47434 ICLASS: VFMSUBADD132PS 47435 CPL: 3 47436 CATEGORY: VFMA 47437 EXTENSION: AVX512EVEX 47438 ISA_SET: AVX512F_256 47439 EXCEPTIONS: AVX512-E2 47440 REAL_OPCODE: Y 47441 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47442 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 47443 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47444 IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 47445 } 47446 47447 47448 # EMITTING VFMSUBADD213PD (VFMSUBADD213PD-128-1) 47449 { 47450 ICLASS: VFMSUBADD213PD 47451 CPL: 3 47452 CATEGORY: VFMA 47453 EXTENSION: AVX512EVEX 47454 ISA_SET: AVX512F_128 47455 EXCEPTIONS: AVX512-E2 47456 REAL_OPCODE: Y 47457 ATTRIBUTES: MXCSR MASKOP_EVEX 47458 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47459 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 47460 IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 47461 } 47462 47463 { 47464 ICLASS: VFMSUBADD213PD 47465 CPL: 3 47466 CATEGORY: VFMA 47467 EXTENSION: AVX512EVEX 47468 ISA_SET: AVX512F_128 47469 EXCEPTIONS: AVX512-E2 47470 REAL_OPCODE: Y 47471 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47472 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 47473 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47474 IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 47475 } 47476 47477 47478 # EMITTING VFMSUBADD213PD (VFMSUBADD213PD-256-1) 47479 { 47480 ICLASS: VFMSUBADD213PD 47481 CPL: 3 47482 CATEGORY: VFMA 47483 EXTENSION: AVX512EVEX 47484 ISA_SET: AVX512F_256 47485 EXCEPTIONS: AVX512-E2 47486 REAL_OPCODE: Y 47487 ATTRIBUTES: MXCSR MASKOP_EVEX 47488 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47489 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 47490 IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 47491 } 47492 47493 { 47494 ICLASS: VFMSUBADD213PD 47495 CPL: 3 47496 CATEGORY: VFMA 47497 EXTENSION: AVX512EVEX 47498 ISA_SET: AVX512F_256 47499 EXCEPTIONS: AVX512-E2 47500 REAL_OPCODE: Y 47501 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47502 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47503 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47504 IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 47505 } 47506 47507 47508 # EMITTING VFMSUBADD213PS (VFMSUBADD213PS-128-1) 47509 { 47510 ICLASS: VFMSUBADD213PS 47511 CPL: 3 47512 CATEGORY: VFMA 47513 EXTENSION: AVX512EVEX 47514 ISA_SET: AVX512F_128 47515 EXCEPTIONS: AVX512-E2 47516 REAL_OPCODE: Y 47517 ATTRIBUTES: MXCSR MASKOP_EVEX 47518 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47519 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 47520 IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 47521 } 47522 47523 { 47524 ICLASS: VFMSUBADD213PS 47525 CPL: 3 47526 CATEGORY: VFMA 47527 EXTENSION: AVX512EVEX 47528 ISA_SET: AVX512F_128 47529 EXCEPTIONS: AVX512-E2 47530 REAL_OPCODE: Y 47531 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47532 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 47533 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47534 IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 47535 } 47536 47537 47538 # EMITTING VFMSUBADD213PS (VFMSUBADD213PS-256-1) 47539 { 47540 ICLASS: VFMSUBADD213PS 47541 CPL: 3 47542 CATEGORY: VFMA 47543 EXTENSION: AVX512EVEX 47544 ISA_SET: AVX512F_256 47545 EXCEPTIONS: AVX512-E2 47546 REAL_OPCODE: Y 47547 ATTRIBUTES: MXCSR MASKOP_EVEX 47548 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47549 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 47550 IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 47551 } 47552 47553 { 47554 ICLASS: VFMSUBADD213PS 47555 CPL: 3 47556 CATEGORY: VFMA 47557 EXTENSION: AVX512EVEX 47558 ISA_SET: AVX512F_256 47559 EXCEPTIONS: AVX512-E2 47560 REAL_OPCODE: Y 47561 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47562 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 47563 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47564 IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 47565 } 47566 47567 47568 # EMITTING VFMSUBADD231PD (VFMSUBADD231PD-128-1) 47569 { 47570 ICLASS: VFMSUBADD231PD 47571 CPL: 3 47572 CATEGORY: VFMA 47573 EXTENSION: AVX512EVEX 47574 ISA_SET: AVX512F_128 47575 EXCEPTIONS: AVX512-E2 47576 REAL_OPCODE: Y 47577 ATTRIBUTES: MXCSR MASKOP_EVEX 47578 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47579 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 47580 IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 47581 } 47582 47583 { 47584 ICLASS: VFMSUBADD231PD 47585 CPL: 3 47586 CATEGORY: VFMA 47587 EXTENSION: AVX512EVEX 47588 ISA_SET: AVX512F_128 47589 EXCEPTIONS: AVX512-E2 47590 REAL_OPCODE: Y 47591 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47592 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 47593 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47594 IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 47595 } 47596 47597 47598 # EMITTING VFMSUBADD231PD (VFMSUBADD231PD-256-1) 47599 { 47600 ICLASS: VFMSUBADD231PD 47601 CPL: 3 47602 CATEGORY: VFMA 47603 EXTENSION: AVX512EVEX 47604 ISA_SET: AVX512F_256 47605 EXCEPTIONS: AVX512-E2 47606 REAL_OPCODE: Y 47607 ATTRIBUTES: MXCSR MASKOP_EVEX 47608 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47609 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 47610 IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 47611 } 47612 47613 { 47614 ICLASS: VFMSUBADD231PD 47615 CPL: 3 47616 CATEGORY: VFMA 47617 EXTENSION: AVX512EVEX 47618 ISA_SET: AVX512F_256 47619 EXCEPTIONS: AVX512-E2 47620 REAL_OPCODE: Y 47621 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47622 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47623 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47624 IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 47625 } 47626 47627 47628 # EMITTING VFMSUBADD231PS (VFMSUBADD231PS-128-1) 47629 { 47630 ICLASS: VFMSUBADD231PS 47631 CPL: 3 47632 CATEGORY: VFMA 47633 EXTENSION: AVX512EVEX 47634 ISA_SET: AVX512F_128 47635 EXCEPTIONS: AVX512-E2 47636 REAL_OPCODE: Y 47637 ATTRIBUTES: MXCSR MASKOP_EVEX 47638 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47639 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 47640 IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 47641 } 47642 47643 { 47644 ICLASS: VFMSUBADD231PS 47645 CPL: 3 47646 CATEGORY: VFMA 47647 EXTENSION: AVX512EVEX 47648 ISA_SET: AVX512F_128 47649 EXCEPTIONS: AVX512-E2 47650 REAL_OPCODE: Y 47651 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47652 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 47653 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47654 IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 47655 } 47656 47657 47658 # EMITTING VFMSUBADD231PS (VFMSUBADD231PS-256-1) 47659 { 47660 ICLASS: VFMSUBADD231PS 47661 CPL: 3 47662 CATEGORY: VFMA 47663 EXTENSION: AVX512EVEX 47664 ISA_SET: AVX512F_256 47665 EXCEPTIONS: AVX512-E2 47666 REAL_OPCODE: Y 47667 ATTRIBUTES: MXCSR MASKOP_EVEX 47668 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47669 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 47670 IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 47671 } 47672 47673 { 47674 ICLASS: VFMSUBADD231PS 47675 CPL: 3 47676 CATEGORY: VFMA 47677 EXTENSION: AVX512EVEX 47678 ISA_SET: AVX512F_256 47679 EXCEPTIONS: AVX512-E2 47680 REAL_OPCODE: Y 47681 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47682 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 47683 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47684 IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 47685 } 47686 47687 47688 # EMITTING VFNMADD132PD (VFNMADD132PD-128-1) 47689 { 47690 ICLASS: VFNMADD132PD 47691 CPL: 3 47692 CATEGORY: VFMA 47693 EXTENSION: AVX512EVEX 47694 ISA_SET: AVX512F_128 47695 EXCEPTIONS: AVX512-E2 47696 REAL_OPCODE: Y 47697 ATTRIBUTES: MXCSR MASKOP_EVEX 47698 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47699 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 47700 IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 47701 } 47702 47703 { 47704 ICLASS: VFNMADD132PD 47705 CPL: 3 47706 CATEGORY: VFMA 47707 EXTENSION: AVX512EVEX 47708 ISA_SET: AVX512F_128 47709 EXCEPTIONS: AVX512-E2 47710 REAL_OPCODE: Y 47711 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47712 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 47713 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47714 IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 47715 } 47716 47717 47718 # EMITTING VFNMADD132PD (VFNMADD132PD-256-1) 47719 { 47720 ICLASS: VFNMADD132PD 47721 CPL: 3 47722 CATEGORY: VFMA 47723 EXTENSION: AVX512EVEX 47724 ISA_SET: AVX512F_256 47725 EXCEPTIONS: AVX512-E2 47726 REAL_OPCODE: Y 47727 ATTRIBUTES: MXCSR MASKOP_EVEX 47728 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47729 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 47730 IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 47731 } 47732 47733 { 47734 ICLASS: VFNMADD132PD 47735 CPL: 3 47736 CATEGORY: VFMA 47737 EXTENSION: AVX512EVEX 47738 ISA_SET: AVX512F_256 47739 EXCEPTIONS: AVX512-E2 47740 REAL_OPCODE: Y 47741 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47742 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47743 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47744 IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 47745 } 47746 47747 47748 # EMITTING VFNMADD132PS (VFNMADD132PS-128-1) 47749 { 47750 ICLASS: VFNMADD132PS 47751 CPL: 3 47752 CATEGORY: VFMA 47753 EXTENSION: AVX512EVEX 47754 ISA_SET: AVX512F_128 47755 EXCEPTIONS: AVX512-E2 47756 REAL_OPCODE: Y 47757 ATTRIBUTES: MXCSR MASKOP_EVEX 47758 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47759 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 47760 IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 47761 } 47762 47763 { 47764 ICLASS: VFNMADD132PS 47765 CPL: 3 47766 CATEGORY: VFMA 47767 EXTENSION: AVX512EVEX 47768 ISA_SET: AVX512F_128 47769 EXCEPTIONS: AVX512-E2 47770 REAL_OPCODE: Y 47771 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47772 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 47773 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47774 IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 47775 } 47776 47777 47778 # EMITTING VFNMADD132PS (VFNMADD132PS-256-1) 47779 { 47780 ICLASS: VFNMADD132PS 47781 CPL: 3 47782 CATEGORY: VFMA 47783 EXTENSION: AVX512EVEX 47784 ISA_SET: AVX512F_256 47785 EXCEPTIONS: AVX512-E2 47786 REAL_OPCODE: Y 47787 ATTRIBUTES: MXCSR MASKOP_EVEX 47788 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47789 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 47790 IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 47791 } 47792 47793 { 47794 ICLASS: VFNMADD132PS 47795 CPL: 3 47796 CATEGORY: VFMA 47797 EXTENSION: AVX512EVEX 47798 ISA_SET: AVX512F_256 47799 EXCEPTIONS: AVX512-E2 47800 REAL_OPCODE: Y 47801 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47802 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 47803 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47804 IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 47805 } 47806 47807 47808 # EMITTING VFNMADD213PD (VFNMADD213PD-128-1) 47809 { 47810 ICLASS: VFNMADD213PD 47811 CPL: 3 47812 CATEGORY: VFMA 47813 EXTENSION: AVX512EVEX 47814 ISA_SET: AVX512F_128 47815 EXCEPTIONS: AVX512-E2 47816 REAL_OPCODE: Y 47817 ATTRIBUTES: MXCSR MASKOP_EVEX 47818 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47819 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 47820 IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 47821 } 47822 47823 { 47824 ICLASS: VFNMADD213PD 47825 CPL: 3 47826 CATEGORY: VFMA 47827 EXTENSION: AVX512EVEX 47828 ISA_SET: AVX512F_128 47829 EXCEPTIONS: AVX512-E2 47830 REAL_OPCODE: Y 47831 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47832 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 47833 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47834 IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 47835 } 47836 47837 47838 # EMITTING VFNMADD213PD (VFNMADD213PD-256-1) 47839 { 47840 ICLASS: VFNMADD213PD 47841 CPL: 3 47842 CATEGORY: VFMA 47843 EXTENSION: AVX512EVEX 47844 ISA_SET: AVX512F_256 47845 EXCEPTIONS: AVX512-E2 47846 REAL_OPCODE: Y 47847 ATTRIBUTES: MXCSR MASKOP_EVEX 47848 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47849 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 47850 IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 47851 } 47852 47853 { 47854 ICLASS: VFNMADD213PD 47855 CPL: 3 47856 CATEGORY: VFMA 47857 EXTENSION: AVX512EVEX 47858 ISA_SET: AVX512F_256 47859 EXCEPTIONS: AVX512-E2 47860 REAL_OPCODE: Y 47861 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47862 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47863 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47864 IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 47865 } 47866 47867 47868 # EMITTING VFNMADD213PS (VFNMADD213PS-128-1) 47869 { 47870 ICLASS: VFNMADD213PS 47871 CPL: 3 47872 CATEGORY: VFMA 47873 EXTENSION: AVX512EVEX 47874 ISA_SET: AVX512F_128 47875 EXCEPTIONS: AVX512-E2 47876 REAL_OPCODE: Y 47877 ATTRIBUTES: MXCSR MASKOP_EVEX 47878 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47879 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 47880 IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 47881 } 47882 47883 { 47884 ICLASS: VFNMADD213PS 47885 CPL: 3 47886 CATEGORY: VFMA 47887 EXTENSION: AVX512EVEX 47888 ISA_SET: AVX512F_128 47889 EXCEPTIONS: AVX512-E2 47890 REAL_OPCODE: Y 47891 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47892 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 47893 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47894 IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 47895 } 47896 47897 47898 # EMITTING VFNMADD213PS (VFNMADD213PS-256-1) 47899 { 47900 ICLASS: VFNMADD213PS 47901 CPL: 3 47902 CATEGORY: VFMA 47903 EXTENSION: AVX512EVEX 47904 ISA_SET: AVX512F_256 47905 EXCEPTIONS: AVX512-E2 47906 REAL_OPCODE: Y 47907 ATTRIBUTES: MXCSR MASKOP_EVEX 47908 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47909 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 47910 IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 47911 } 47912 47913 { 47914 ICLASS: VFNMADD213PS 47915 CPL: 3 47916 CATEGORY: VFMA 47917 EXTENSION: AVX512EVEX 47918 ISA_SET: AVX512F_256 47919 EXCEPTIONS: AVX512-E2 47920 REAL_OPCODE: Y 47921 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47922 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 47923 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 47924 IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 47925 } 47926 47927 47928 # EMITTING VFNMADD231PD (VFNMADD231PD-128-1) 47929 { 47930 ICLASS: VFNMADD231PD 47931 CPL: 3 47932 CATEGORY: VFMA 47933 EXTENSION: AVX512EVEX 47934 ISA_SET: AVX512F_128 47935 EXCEPTIONS: AVX512-E2 47936 REAL_OPCODE: Y 47937 ATTRIBUTES: MXCSR MASKOP_EVEX 47938 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47939 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 47940 IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 47941 } 47942 47943 { 47944 ICLASS: VFNMADD231PD 47945 CPL: 3 47946 CATEGORY: VFMA 47947 EXTENSION: AVX512EVEX 47948 ISA_SET: AVX512F_128 47949 EXCEPTIONS: AVX512-E2 47950 REAL_OPCODE: Y 47951 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47952 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 47953 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47954 IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 47955 } 47956 47957 47958 # EMITTING VFNMADD231PD (VFNMADD231PD-256-1) 47959 { 47960 ICLASS: VFNMADD231PD 47961 CPL: 3 47962 CATEGORY: VFMA 47963 EXTENSION: AVX512EVEX 47964 ISA_SET: AVX512F_256 47965 EXCEPTIONS: AVX512-E2 47966 REAL_OPCODE: Y 47967 ATTRIBUTES: MXCSR MASKOP_EVEX 47968 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47969 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 47970 IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 47971 } 47972 47973 { 47974 ICLASS: VFNMADD231PD 47975 CPL: 3 47976 CATEGORY: VFMA 47977 EXTENSION: AVX512EVEX 47978 ISA_SET: AVX512F_256 47979 EXCEPTIONS: AVX512-E2 47980 REAL_OPCODE: Y 47981 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47982 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47983 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 47984 IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 47985 } 47986 47987 47988 # EMITTING VFNMADD231PS (VFNMADD231PS-128-1) 47989 { 47990 ICLASS: VFNMADD231PS 47991 CPL: 3 47992 CATEGORY: VFMA 47993 EXTENSION: AVX512EVEX 47994 ISA_SET: AVX512F_128 47995 EXCEPTIONS: AVX512-E2 47996 REAL_OPCODE: Y 47997 ATTRIBUTES: MXCSR MASKOP_EVEX 47998 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47999 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 48000 IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 48001 } 48002 48003 { 48004 ICLASS: VFNMADD231PS 48005 CPL: 3 48006 CATEGORY: VFMA 48007 EXTENSION: AVX512EVEX 48008 ISA_SET: AVX512F_128 48009 EXCEPTIONS: AVX512-E2 48010 REAL_OPCODE: Y 48011 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48012 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 48013 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 48014 IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 48015 } 48016 48017 48018 # EMITTING VFNMADD231PS (VFNMADD231PS-256-1) 48019 { 48020 ICLASS: VFNMADD231PS 48021 CPL: 3 48022 CATEGORY: VFMA 48023 EXTENSION: AVX512EVEX 48024 ISA_SET: AVX512F_256 48025 EXCEPTIONS: AVX512-E2 48026 REAL_OPCODE: Y 48027 ATTRIBUTES: MXCSR MASKOP_EVEX 48028 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 48029 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 48030 IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 48031 } 48032 48033 { 48034 ICLASS: VFNMADD231PS 48035 CPL: 3 48036 CATEGORY: VFMA 48037 EXTENSION: AVX512EVEX 48038 ISA_SET: AVX512F_256 48039 EXCEPTIONS: AVX512-E2 48040 REAL_OPCODE: Y 48041 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48042 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 48043 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 48044 IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 48045 } 48046 48047 48048 # EMITTING VFNMSUB132PD (VFNMSUB132PD-128-1) 48049 { 48050 ICLASS: VFNMSUB132PD 48051 CPL: 3 48052 CATEGORY: VFMA 48053 EXTENSION: AVX512EVEX 48054 ISA_SET: AVX512F_128 48055 EXCEPTIONS: AVX512-E2 48056 REAL_OPCODE: Y 48057 ATTRIBUTES: MXCSR MASKOP_EVEX 48058 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 48059 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 48060 IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 48061 } 48062 48063 { 48064 ICLASS: VFNMSUB132PD 48065 CPL: 3 48066 CATEGORY: VFMA 48067 EXTENSION: AVX512EVEX 48068 ISA_SET: AVX512F_128 48069 EXCEPTIONS: AVX512-E2 48070 REAL_OPCODE: Y 48071 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48072 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 48073 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 48074 IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 48075 } 48076 48077 48078 # EMITTING VFNMSUB132PD (VFNMSUB132PD-256-1) 48079 { 48080 ICLASS: VFNMSUB132PD 48081 CPL: 3 48082 CATEGORY: VFMA 48083 EXTENSION: AVX512EVEX 48084 ISA_SET: AVX512F_256 48085 EXCEPTIONS: AVX512-E2 48086 REAL_OPCODE: Y 48087 ATTRIBUTES: MXCSR MASKOP_EVEX 48088 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 48089 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 48090 IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 48091 } 48092 48093 { 48094 ICLASS: VFNMSUB132PD 48095 CPL: 3 48096 CATEGORY: VFMA 48097 EXTENSION: AVX512EVEX 48098 ISA_SET: AVX512F_256 48099 EXCEPTIONS: AVX512-E2 48100 REAL_OPCODE: Y 48101 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48102 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 48103 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 48104 IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 48105 } 48106 48107 48108 # EMITTING VFNMSUB132PS (VFNMSUB132PS-128-1) 48109 { 48110 ICLASS: VFNMSUB132PS 48111 CPL: 3 48112 CATEGORY: VFMA 48113 EXTENSION: AVX512EVEX 48114 ISA_SET: AVX512F_128 48115 EXCEPTIONS: AVX512-E2 48116 REAL_OPCODE: Y 48117 ATTRIBUTES: MXCSR MASKOP_EVEX 48118 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 48119 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 48120 IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 48121 } 48122 48123 { 48124 ICLASS: VFNMSUB132PS 48125 CPL: 3 48126 CATEGORY: VFMA 48127 EXTENSION: AVX512EVEX 48128 ISA_SET: AVX512F_128 48129 EXCEPTIONS: AVX512-E2 48130 REAL_OPCODE: Y 48131 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48132 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 48133 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 48134 IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 48135 } 48136 48137 48138 # EMITTING VFNMSUB132PS (VFNMSUB132PS-256-1) 48139 { 48140 ICLASS: VFNMSUB132PS 48141 CPL: 3 48142 CATEGORY: VFMA 48143 EXTENSION: AVX512EVEX 48144 ISA_SET: AVX512F_256 48145 EXCEPTIONS: AVX512-E2 48146 REAL_OPCODE: Y 48147 ATTRIBUTES: MXCSR MASKOP_EVEX 48148 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 48149 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 48150 IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 48151 } 48152 48153 { 48154 ICLASS: VFNMSUB132PS 48155 CPL: 3 48156 CATEGORY: VFMA 48157 EXTENSION: AVX512EVEX 48158 ISA_SET: AVX512F_256 48159 EXCEPTIONS: AVX512-E2 48160 REAL_OPCODE: Y 48161 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48162 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 48163 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 48164 IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 48165 } 48166 48167 48168 # EMITTING VFNMSUB213PD (VFNMSUB213PD-128-1) 48169 { 48170 ICLASS: VFNMSUB213PD 48171 CPL: 3 48172 CATEGORY: VFMA 48173 EXTENSION: AVX512EVEX 48174 ISA_SET: AVX512F_128 48175 EXCEPTIONS: AVX512-E2 48176 REAL_OPCODE: Y 48177 ATTRIBUTES: MXCSR MASKOP_EVEX 48178 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 48179 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 48180 IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 48181 } 48182 48183 { 48184 ICLASS: VFNMSUB213PD 48185 CPL: 3 48186 CATEGORY: VFMA 48187 EXTENSION: AVX512EVEX 48188 ISA_SET: AVX512F_128 48189 EXCEPTIONS: AVX512-E2 48190 REAL_OPCODE: Y 48191 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48192 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 48193 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 48194 IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 48195 } 48196 48197 48198 # EMITTING VFNMSUB213PD (VFNMSUB213PD-256-1) 48199 { 48200 ICLASS: VFNMSUB213PD 48201 CPL: 3 48202 CATEGORY: VFMA 48203 EXTENSION: AVX512EVEX 48204 ISA_SET: AVX512F_256 48205 EXCEPTIONS: AVX512-E2 48206 REAL_OPCODE: Y 48207 ATTRIBUTES: MXCSR MASKOP_EVEX 48208 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 48209 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 48210 IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 48211 } 48212 48213 { 48214 ICLASS: VFNMSUB213PD 48215 CPL: 3 48216 CATEGORY: VFMA 48217 EXTENSION: AVX512EVEX 48218 ISA_SET: AVX512F_256 48219 EXCEPTIONS: AVX512-E2 48220 REAL_OPCODE: Y 48221 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48222 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 48223 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 48224 IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 48225 } 48226 48227 48228 # EMITTING VFNMSUB213PS (VFNMSUB213PS-128-1) 48229 { 48230 ICLASS: VFNMSUB213PS 48231 CPL: 3 48232 CATEGORY: VFMA 48233 EXTENSION: AVX512EVEX 48234 ISA_SET: AVX512F_128 48235 EXCEPTIONS: AVX512-E2 48236 REAL_OPCODE: Y 48237 ATTRIBUTES: MXCSR MASKOP_EVEX 48238 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 48239 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 48240 IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 48241 } 48242 48243 { 48244 ICLASS: VFNMSUB213PS 48245 CPL: 3 48246 CATEGORY: VFMA 48247 EXTENSION: AVX512EVEX 48248 ISA_SET: AVX512F_128 48249 EXCEPTIONS: AVX512-E2 48250 REAL_OPCODE: Y 48251 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48252 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 48253 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 48254 IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 48255 } 48256 48257 48258 # EMITTING VFNMSUB213PS (VFNMSUB213PS-256-1) 48259 { 48260 ICLASS: VFNMSUB213PS 48261 CPL: 3 48262 CATEGORY: VFMA 48263 EXTENSION: AVX512EVEX 48264 ISA_SET: AVX512F_256 48265 EXCEPTIONS: AVX512-E2 48266 REAL_OPCODE: Y 48267 ATTRIBUTES: MXCSR MASKOP_EVEX 48268 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 48269 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 48270 IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 48271 } 48272 48273 { 48274 ICLASS: VFNMSUB213PS 48275 CPL: 3 48276 CATEGORY: VFMA 48277 EXTENSION: AVX512EVEX 48278 ISA_SET: AVX512F_256 48279 EXCEPTIONS: AVX512-E2 48280 REAL_OPCODE: Y 48281 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48282 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 48283 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 48284 IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 48285 } 48286 48287 48288 # EMITTING VFNMSUB231PD (VFNMSUB231PD-128-1) 48289 { 48290 ICLASS: VFNMSUB231PD 48291 CPL: 3 48292 CATEGORY: VFMA 48293 EXTENSION: AVX512EVEX 48294 ISA_SET: AVX512F_128 48295 EXCEPTIONS: AVX512-E2 48296 REAL_OPCODE: Y 48297 ATTRIBUTES: MXCSR MASKOP_EVEX 48298 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 48299 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 48300 IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 48301 } 48302 48303 { 48304 ICLASS: VFNMSUB231PD 48305 CPL: 3 48306 CATEGORY: VFMA 48307 EXTENSION: AVX512EVEX 48308 ISA_SET: AVX512F_128 48309 EXCEPTIONS: AVX512-E2 48310 REAL_OPCODE: Y 48311 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48312 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 48313 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 48314 IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 48315 } 48316 48317 48318 # EMITTING VFNMSUB231PD (VFNMSUB231PD-256-1) 48319 { 48320 ICLASS: VFNMSUB231PD 48321 CPL: 3 48322 CATEGORY: VFMA 48323 EXTENSION: AVX512EVEX 48324 ISA_SET: AVX512F_256 48325 EXCEPTIONS: AVX512-E2 48326 REAL_OPCODE: Y 48327 ATTRIBUTES: MXCSR MASKOP_EVEX 48328 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 48329 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 48330 IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 48331 } 48332 48333 { 48334 ICLASS: VFNMSUB231PD 48335 CPL: 3 48336 CATEGORY: VFMA 48337 EXTENSION: AVX512EVEX 48338 ISA_SET: AVX512F_256 48339 EXCEPTIONS: AVX512-E2 48340 REAL_OPCODE: Y 48341 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48342 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 48343 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 48344 IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 48345 } 48346 48347 48348 # EMITTING VFNMSUB231PS (VFNMSUB231PS-128-1) 48349 { 48350 ICLASS: VFNMSUB231PS 48351 CPL: 3 48352 CATEGORY: VFMA 48353 EXTENSION: AVX512EVEX 48354 ISA_SET: AVX512F_128 48355 EXCEPTIONS: AVX512-E2 48356 REAL_OPCODE: Y 48357 ATTRIBUTES: MXCSR MASKOP_EVEX 48358 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 48359 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 48360 IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 48361 } 48362 48363 { 48364 ICLASS: VFNMSUB231PS 48365 CPL: 3 48366 CATEGORY: VFMA 48367 EXTENSION: AVX512EVEX 48368 ISA_SET: AVX512F_128 48369 EXCEPTIONS: AVX512-E2 48370 REAL_OPCODE: Y 48371 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48372 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 48373 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 48374 IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 48375 } 48376 48377 48378 # EMITTING VFNMSUB231PS (VFNMSUB231PS-256-1) 48379 { 48380 ICLASS: VFNMSUB231PS 48381 CPL: 3 48382 CATEGORY: VFMA 48383 EXTENSION: AVX512EVEX 48384 ISA_SET: AVX512F_256 48385 EXCEPTIONS: AVX512-E2 48386 REAL_OPCODE: Y 48387 ATTRIBUTES: MXCSR MASKOP_EVEX 48388 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 48389 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 48390 IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 48391 } 48392 48393 { 48394 ICLASS: VFNMSUB231PS 48395 CPL: 3 48396 CATEGORY: VFMA 48397 EXTENSION: AVX512EVEX 48398 ISA_SET: AVX512F_256 48399 EXCEPTIONS: AVX512-E2 48400 REAL_OPCODE: Y 48401 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48402 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 48403 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 48404 IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 48405 } 48406 48407 48408 # EMITTING VFPCLASSPD (VFPCLASSPD-128-1) 48409 { 48410 ICLASS: VFPCLASSPD 48411 CPL: 3 48412 CATEGORY: AVX512 48413 EXTENSION: AVX512EVEX 48414 ISA_SET: AVX512DQ_128 48415 EXCEPTIONS: AVX512-E4 48416 REAL_OPCODE: Y 48417 ATTRIBUTES: MXCSR MASKOP_EVEX 48418 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8() 48419 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b 48420 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 48421 } 48422 48423 { 48424 ICLASS: VFPCLASSPD 48425 CPL: 3 48426 CATEGORY: AVX512 48427 EXTENSION: AVX512EVEX 48428 ISA_SET: AVX512DQ_128 48429 EXCEPTIONS: AVX512-E4 48430 REAL_OPCODE: Y 48431 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48432 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 48433 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 48434 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 48435 } 48436 48437 48438 # EMITTING VFPCLASSPD (VFPCLASSPD-256-1) 48439 { 48440 ICLASS: VFPCLASSPD 48441 CPL: 3 48442 CATEGORY: AVX512 48443 EXTENSION: AVX512EVEX 48444 ISA_SET: AVX512DQ_256 48445 EXCEPTIONS: AVX512-E4 48446 REAL_OPCODE: Y 48447 ATTRIBUTES: MXCSR MASKOP_EVEX 48448 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8() 48449 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b 48450 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 48451 } 48452 48453 { 48454 ICLASS: VFPCLASSPD 48455 CPL: 3 48456 CATEGORY: AVX512 48457 EXTENSION: AVX512EVEX 48458 ISA_SET: AVX512DQ_256 48459 EXCEPTIONS: AVX512-E4 48460 REAL_OPCODE: Y 48461 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48462 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 48463 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 48464 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 48465 } 48466 48467 48468 # EMITTING VFPCLASSPD (VFPCLASSPD-512-1) 48469 { 48470 ICLASS: VFPCLASSPD 48471 CPL: 3 48472 CATEGORY: AVX512 48473 EXTENSION: AVX512EVEX 48474 ISA_SET: AVX512DQ_512 48475 EXCEPTIONS: AVX512-E4 48476 REAL_OPCODE: Y 48477 ATTRIBUTES: MXCSR MASKOP_EVEX 48478 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8() 48479 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b 48480 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 48481 } 48482 48483 { 48484 ICLASS: VFPCLASSPD 48485 CPL: 3 48486 CATEGORY: AVX512 48487 EXTENSION: AVX512EVEX 48488 ISA_SET: AVX512DQ_512 48489 EXCEPTIONS: AVX512-E4 48490 REAL_OPCODE: Y 48491 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48492 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 48493 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 48494 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 48495 } 48496 48497 48498 # EMITTING VFPCLASSPS (VFPCLASSPS-128-1) 48499 { 48500 ICLASS: VFPCLASSPS 48501 CPL: 3 48502 CATEGORY: AVX512 48503 EXTENSION: AVX512EVEX 48504 ISA_SET: AVX512DQ_128 48505 EXCEPTIONS: AVX512-E4 48506 REAL_OPCODE: Y 48507 ATTRIBUTES: MXCSR MASKOP_EVEX 48508 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() 48509 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b 48510 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 48511 } 48512 48513 { 48514 ICLASS: VFPCLASSPS 48515 CPL: 3 48516 CATEGORY: AVX512 48517 EXTENSION: AVX512EVEX 48518 ISA_SET: AVX512DQ_128 48519 EXCEPTIONS: AVX512-E4 48520 REAL_OPCODE: Y 48521 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48522 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 48523 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 48524 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 48525 } 48526 48527 48528 # EMITTING VFPCLASSPS (VFPCLASSPS-256-1) 48529 { 48530 ICLASS: VFPCLASSPS 48531 CPL: 3 48532 CATEGORY: AVX512 48533 EXTENSION: AVX512EVEX 48534 ISA_SET: AVX512DQ_256 48535 EXCEPTIONS: AVX512-E4 48536 REAL_OPCODE: Y 48537 ATTRIBUTES: MXCSR MASKOP_EVEX 48538 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() 48539 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f32 IMM0:r:b 48540 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 48541 } 48542 48543 { 48544 ICLASS: VFPCLASSPS 48545 CPL: 3 48546 CATEGORY: AVX512 48547 EXTENSION: AVX512EVEX 48548 ISA_SET: AVX512DQ_256 48549 EXCEPTIONS: AVX512-E4 48550 REAL_OPCODE: Y 48551 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48552 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 48553 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 48554 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 48555 } 48556 48557 48558 # EMITTING VFPCLASSPS (VFPCLASSPS-512-1) 48559 { 48560 ICLASS: VFPCLASSPS 48561 CPL: 3 48562 CATEGORY: AVX512 48563 EXTENSION: AVX512EVEX 48564 ISA_SET: AVX512DQ_512 48565 EXCEPTIONS: AVX512-E4 48566 REAL_OPCODE: Y 48567 ATTRIBUTES: MXCSR MASKOP_EVEX 48568 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() 48569 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b 48570 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 48571 } 48572 48573 { 48574 ICLASS: VFPCLASSPS 48575 CPL: 3 48576 CATEGORY: AVX512 48577 EXTENSION: AVX512EVEX 48578 ISA_SET: AVX512DQ_512 48579 EXCEPTIONS: AVX512-E4 48580 REAL_OPCODE: Y 48581 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48582 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 48583 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 48584 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 48585 } 48586 48587 48588 # EMITTING VFPCLASSSD (VFPCLASSSD-128-1) 48589 { 48590 ICLASS: VFPCLASSSD 48591 CPL: 3 48592 CATEGORY: AVX512 48593 EXTENSION: AVX512EVEX 48594 ISA_SET: AVX512DQ_SCALAR 48595 EXCEPTIONS: AVX512-E6 48596 REAL_OPCODE: Y 48597 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 48598 PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8() 48599 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b 48600 IFORM: VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 48601 } 48602 48603 { 48604 ICLASS: VFPCLASSSD 48605 CPL: 3 48606 CATEGORY: AVX512 48607 EXTENSION: AVX512EVEX 48608 ISA_SET: AVX512DQ_SCALAR 48609 EXCEPTIONS: AVX512-E6 48610 REAL_OPCODE: Y 48611 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 48612 PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 48613 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:q:f64 IMM0:r:b 48614 IFORM: VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 48615 } 48616 48617 48618 # EMITTING VFPCLASSSS (VFPCLASSSS-128-1) 48619 { 48620 ICLASS: VFPCLASSSS 48621 CPL: 3 48622 CATEGORY: AVX512 48623 EXTENSION: AVX512EVEX 48624 ISA_SET: AVX512DQ_SCALAR 48625 EXCEPTIONS: AVX512-E6 48626 REAL_OPCODE: Y 48627 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 48628 PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8() 48629 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b 48630 IFORM: VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 48631 } 48632 48633 { 48634 ICLASS: VFPCLASSSS 48635 CPL: 3 48636 CATEGORY: AVX512 48637 EXTENSION: AVX512EVEX 48638 ISA_SET: AVX512DQ_SCALAR 48639 EXCEPTIONS: AVX512-E6 48640 REAL_OPCODE: Y 48641 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 48642 PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 48643 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:d:f32 IMM0:r:b 48644 IFORM: VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 48645 } 48646 48647 48648 # EMITTING VGATHERDPD (VGATHERDPD-128-1) 48649 { 48650 ICLASS: VGATHERDPD 48651 CPL: 3 48652 CATEGORY: GATHER 48653 EXTENSION: AVX512EVEX 48654 ISA_SET: AVX512F_128 48655 EXCEPTIONS: AVX512-E12 48656 REAL_OPCODE: Y 48657 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 48658 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 48659 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f64 48660 IFORM: VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 48661 } 48662 48663 48664 # EMITTING VGATHERDPD (VGATHERDPD-256-1) 48665 { 48666 ICLASS: VGATHERDPD 48667 CPL: 3 48668 CATEGORY: GATHER 48669 EXTENSION: AVX512EVEX 48670 ISA_SET: AVX512F_256 48671 EXCEPTIONS: AVX512-E12 48672 REAL_OPCODE: Y 48673 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 48674 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 48675 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f64 48676 IFORM: VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 48677 } 48678 48679 48680 # EMITTING VGATHERDPS (VGATHERDPS-128-1) 48681 { 48682 ICLASS: VGATHERDPS 48683 CPL: 3 48684 CATEGORY: GATHER 48685 EXTENSION: AVX512EVEX 48686 ISA_SET: AVX512F_128 48687 EXCEPTIONS: AVX512-E12 48688 REAL_OPCODE: Y 48689 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 48690 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 48691 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f32 48692 IFORM: VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 48693 } 48694 48695 48696 # EMITTING VGATHERDPS (VGATHERDPS-256-1) 48697 { 48698 ICLASS: VGATHERDPS 48699 CPL: 3 48700 CATEGORY: GATHER 48701 EXTENSION: AVX512EVEX 48702 ISA_SET: AVX512F_256 48703 EXCEPTIONS: AVX512-E12 48704 REAL_OPCODE: Y 48705 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 48706 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 48707 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f32 48708 IFORM: VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 48709 } 48710 48711 48712 # EMITTING VGATHERQPD (VGATHERQPD-128-1) 48713 { 48714 ICLASS: VGATHERQPD 48715 CPL: 3 48716 CATEGORY: GATHER 48717 EXTENSION: AVX512EVEX 48718 ISA_SET: AVX512F_128 48719 EXCEPTIONS: AVX512-E12 48720 REAL_OPCODE: Y 48721 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 48722 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 48723 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f64 48724 IFORM: VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 48725 } 48726 48727 48728 # EMITTING VGATHERQPD (VGATHERQPD-256-1) 48729 { 48730 ICLASS: VGATHERQPD 48731 CPL: 3 48732 CATEGORY: GATHER 48733 EXTENSION: AVX512EVEX 48734 ISA_SET: AVX512F_256 48735 EXCEPTIONS: AVX512-E12 48736 REAL_OPCODE: Y 48737 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 48738 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 48739 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:f64 48740 IFORM: VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 48741 } 48742 48743 48744 # EMITTING VGATHERQPS (VGATHERQPS-128-1) 48745 { 48746 ICLASS: VGATHERQPS 48747 CPL: 3 48748 CATEGORY: GATHER 48749 EXTENSION: AVX512EVEX 48750 ISA_SET: AVX512F_128 48751 EXCEPTIONS: AVX512-E12 48752 REAL_OPCODE: Y 48753 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 48754 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 48755 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:q:f32 48756 IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 48757 } 48758 48759 48760 # EMITTING VGATHERQPS (VGATHERQPS-256-1) 48761 { 48762 ICLASS: VGATHERQPS 48763 CPL: 3 48764 CATEGORY: GATHER 48765 EXTENSION: AVX512EVEX 48766 ISA_SET: AVX512F_256 48767 EXCEPTIONS: AVX512-E12 48768 REAL_OPCODE: Y 48769 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 48770 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 48771 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:f32 48772 IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 48773 } 48774 48775 48776 # EMITTING VGETEXPPD (VGETEXPPD-128-1) 48777 { 48778 ICLASS: VGETEXPPD 48779 CPL: 3 48780 CATEGORY: AVX512 48781 EXTENSION: AVX512EVEX 48782 ISA_SET: AVX512F_128 48783 EXCEPTIONS: AVX512-E2 48784 REAL_OPCODE: Y 48785 ATTRIBUTES: MXCSR MASKOP_EVEX 48786 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 48787 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 48788 IFORM: VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 48789 } 48790 48791 { 48792 ICLASS: VGETEXPPD 48793 CPL: 3 48794 CATEGORY: AVX512 48795 EXTENSION: AVX512EVEX 48796 ISA_SET: AVX512F_128 48797 EXCEPTIONS: AVX512-E2 48798 REAL_OPCODE: Y 48799 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48800 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 48801 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 48802 IFORM: VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 48803 } 48804 48805 48806 # EMITTING VGETEXPPD (VGETEXPPD-256-1) 48807 { 48808 ICLASS: VGETEXPPD 48809 CPL: 3 48810 CATEGORY: AVX512 48811 EXTENSION: AVX512EVEX 48812 ISA_SET: AVX512F_256 48813 EXCEPTIONS: AVX512-E2 48814 REAL_OPCODE: Y 48815 ATTRIBUTES: MXCSR MASKOP_EVEX 48816 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 48817 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 48818 IFORM: VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 48819 } 48820 48821 { 48822 ICLASS: VGETEXPPD 48823 CPL: 3 48824 CATEGORY: AVX512 48825 EXTENSION: AVX512EVEX 48826 ISA_SET: AVX512F_256 48827 EXCEPTIONS: AVX512-E2 48828 REAL_OPCODE: Y 48829 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48830 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 48831 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 48832 IFORM: VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 48833 } 48834 48835 48836 # EMITTING VGETEXPPS (VGETEXPPS-128-1) 48837 { 48838 ICLASS: VGETEXPPS 48839 CPL: 3 48840 CATEGORY: AVX512 48841 EXTENSION: AVX512EVEX 48842 ISA_SET: AVX512F_128 48843 EXCEPTIONS: AVX512-E2 48844 REAL_OPCODE: Y 48845 ATTRIBUTES: MXCSR MASKOP_EVEX 48846 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 48847 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 48848 IFORM: VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 48849 } 48850 48851 { 48852 ICLASS: VGETEXPPS 48853 CPL: 3 48854 CATEGORY: AVX512 48855 EXTENSION: AVX512EVEX 48856 ISA_SET: AVX512F_128 48857 EXCEPTIONS: AVX512-E2 48858 REAL_OPCODE: Y 48859 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48860 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 48861 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 48862 IFORM: VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 48863 } 48864 48865 48866 # EMITTING VGETEXPPS (VGETEXPPS-256-1) 48867 { 48868 ICLASS: VGETEXPPS 48869 CPL: 3 48870 CATEGORY: AVX512 48871 EXTENSION: AVX512EVEX 48872 ISA_SET: AVX512F_256 48873 EXCEPTIONS: AVX512-E2 48874 REAL_OPCODE: Y 48875 ATTRIBUTES: MXCSR MASKOP_EVEX 48876 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 48877 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 48878 IFORM: VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 48879 } 48880 48881 { 48882 ICLASS: VGETEXPPS 48883 CPL: 3 48884 CATEGORY: AVX512 48885 EXTENSION: AVX512EVEX 48886 ISA_SET: AVX512F_256 48887 EXCEPTIONS: AVX512-E2 48888 REAL_OPCODE: Y 48889 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48890 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 48891 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 48892 IFORM: VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 48893 } 48894 48895 48896 # EMITTING VGETMANTPD (VGETMANTPD-128-1) 48897 { 48898 ICLASS: VGETMANTPD 48899 CPL: 3 48900 CATEGORY: AVX512 48901 EXTENSION: AVX512EVEX 48902 ISA_SET: AVX512F_128 48903 EXCEPTIONS: AVX512-E2 48904 REAL_OPCODE: Y 48905 ATTRIBUTES: MXCSR MASKOP_EVEX 48906 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() 48907 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b 48908 IFORM: VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 48909 } 48910 48911 { 48912 ICLASS: VGETMANTPD 48913 CPL: 3 48914 CATEGORY: AVX512 48915 EXTENSION: AVX512EVEX 48916 ISA_SET: AVX512F_128 48917 EXCEPTIONS: AVX512-E2 48918 REAL_OPCODE: Y 48919 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48920 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 48921 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 48922 IFORM: VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 48923 } 48924 48925 48926 # EMITTING VGETMANTPD (VGETMANTPD-256-1) 48927 { 48928 ICLASS: VGETMANTPD 48929 CPL: 3 48930 CATEGORY: AVX512 48931 EXTENSION: AVX512EVEX 48932 ISA_SET: AVX512F_256 48933 EXCEPTIONS: AVX512-E2 48934 REAL_OPCODE: Y 48935 ATTRIBUTES: MXCSR MASKOP_EVEX 48936 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 48937 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b 48938 IFORM: VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 48939 } 48940 48941 { 48942 ICLASS: VGETMANTPD 48943 CPL: 3 48944 CATEGORY: AVX512 48945 EXTENSION: AVX512EVEX 48946 ISA_SET: AVX512F_256 48947 EXCEPTIONS: AVX512-E2 48948 REAL_OPCODE: Y 48949 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48950 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 48951 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 48952 IFORM: VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 48953 } 48954 48955 48956 # EMITTING VGETMANTPS (VGETMANTPS-128-1) 48957 { 48958 ICLASS: VGETMANTPS 48959 CPL: 3 48960 CATEGORY: AVX512 48961 EXTENSION: AVX512EVEX 48962 ISA_SET: AVX512F_128 48963 EXCEPTIONS: AVX512-E2 48964 REAL_OPCODE: Y 48965 ATTRIBUTES: MXCSR MASKOP_EVEX 48966 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 48967 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b 48968 IFORM: VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 48969 } 48970 48971 { 48972 ICLASS: VGETMANTPS 48973 CPL: 3 48974 CATEGORY: AVX512 48975 EXTENSION: AVX512EVEX 48976 ISA_SET: AVX512F_128 48977 EXCEPTIONS: AVX512-E2 48978 REAL_OPCODE: Y 48979 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48980 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 48981 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 48982 IFORM: VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 48983 } 48984 48985 48986 # EMITTING VGETMANTPS (VGETMANTPS-256-1) 48987 { 48988 ICLASS: VGETMANTPS 48989 CPL: 3 48990 CATEGORY: AVX512 48991 EXTENSION: AVX512EVEX 48992 ISA_SET: AVX512F_256 48993 EXCEPTIONS: AVX512-E2 48994 REAL_OPCODE: Y 48995 ATTRIBUTES: MXCSR MASKOP_EVEX 48996 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 48997 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b 48998 IFORM: VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 48999 } 49000 49001 { 49002 ICLASS: VGETMANTPS 49003 CPL: 3 49004 CATEGORY: AVX512 49005 EXTENSION: AVX512EVEX 49006 ISA_SET: AVX512F_256 49007 EXCEPTIONS: AVX512-E2 49008 REAL_OPCODE: Y 49009 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49010 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 49011 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 49012 IFORM: VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 49013 } 49014 49015 49016 # EMITTING VINSERTF32X4 (VINSERTF32X4-256-1) 49017 { 49018 ICLASS: VINSERTF32X4 49019 CPL: 3 49020 CATEGORY: AVX512 49021 EXTENSION: AVX512EVEX 49022 ISA_SET: AVX512F_256 49023 EXCEPTIONS: AVX512-E6NF 49024 REAL_OPCODE: Y 49025 ATTRIBUTES: MASKOP_EVEX 49026 PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 49027 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 49028 IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 49029 } 49030 49031 { 49032 ICLASS: VINSERTF32X4 49033 CPL: 3 49034 CATEGORY: AVX512 49035 EXTENSION: AVX512EVEX 49036 ISA_SET: AVX512F_256 49037 EXCEPTIONS: AVX512-E6NF 49038 REAL_OPCODE: Y 49039 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 49040 PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 49041 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:dq:f32 IMM0:r:b 49042 IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 49043 } 49044 49045 49046 # EMITTING VINSERTF32X8 (VINSERTF32X8-512-1) 49047 { 49048 ICLASS: VINSERTF32X8 49049 CPL: 3 49050 CATEGORY: AVX512 49051 EXTENSION: AVX512EVEX 49052 ISA_SET: AVX512DQ_512 49053 EXCEPTIONS: AVX512-E6NF 49054 REAL_OPCODE: Y 49055 ATTRIBUTES: MASKOP_EVEX 49056 PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 49057 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 49058 IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 49059 } 49060 49061 { 49062 ICLASS: VINSERTF32X8 49063 CPL: 3 49064 CATEGORY: AVX512 49065 EXTENSION: AVX512EVEX 49066 ISA_SET: AVX512DQ_512 49067 EXCEPTIONS: AVX512-E6NF 49068 REAL_OPCODE: Y 49069 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 49070 PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() 49071 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:qq:f32 IMM0:r:b 49072 IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 49073 } 49074 49075 49076 # EMITTING VINSERTF64X2 (VINSERTF64X2-256-1) 49077 { 49078 ICLASS: VINSERTF64X2 49079 CPL: 3 49080 CATEGORY: AVX512 49081 EXTENSION: AVX512EVEX 49082 ISA_SET: AVX512DQ_256 49083 EXCEPTIONS: AVX512-E6NF 49084 REAL_OPCODE: Y 49085 ATTRIBUTES: MASKOP_EVEX 49086 PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 49087 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 49088 IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 49089 } 49090 49091 { 49092 ICLASS: VINSERTF64X2 49093 CPL: 3 49094 CATEGORY: AVX512 49095 EXTENSION: AVX512EVEX 49096 ISA_SET: AVX512DQ_256 49097 EXCEPTIONS: AVX512-E6NF 49098 REAL_OPCODE: Y 49099 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 49100 PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 49101 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b 49102 IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 49103 } 49104 49105 49106 # EMITTING VINSERTF64X2 (VINSERTF64X2-512-1) 49107 { 49108 ICLASS: VINSERTF64X2 49109 CPL: 3 49110 CATEGORY: AVX512 49111 EXTENSION: AVX512EVEX 49112 ISA_SET: AVX512DQ_512 49113 EXCEPTIONS: AVX512-E6NF 49114 REAL_OPCODE: Y 49115 ATTRIBUTES: MASKOP_EVEX 49116 PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 49117 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 49118 IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 49119 } 49120 49121 { 49122 ICLASS: VINSERTF64X2 49123 CPL: 3 49124 CATEGORY: AVX512 49125 EXTENSION: AVX512EVEX 49126 ISA_SET: AVX512DQ_512 49127 EXCEPTIONS: AVX512-E6NF 49128 REAL_OPCODE: Y 49129 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 49130 PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 49131 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:dq:f64 IMM0:r:b 49132 IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 49133 } 49134 49135 49136 # EMITTING VINSERTI32X4 (VINSERTI32X4-256-1) 49137 { 49138 ICLASS: VINSERTI32X4 49139 CPL: 3 49140 CATEGORY: AVX512 49141 EXTENSION: AVX512EVEX 49142 ISA_SET: AVX512F_256 49143 EXCEPTIONS: AVX512-E6NF 49144 REAL_OPCODE: Y 49145 ATTRIBUTES: MASKOP_EVEX 49146 PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 49147 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 49148 IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 49149 } 49150 49151 { 49152 ICLASS: VINSERTI32X4 49153 CPL: 3 49154 CATEGORY: AVX512 49155 EXTENSION: AVX512EVEX 49156 ISA_SET: AVX512F_256 49157 EXCEPTIONS: AVX512-E6NF 49158 REAL_OPCODE: Y 49159 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 49160 PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 49161 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 IMM0:r:b 49162 IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 49163 } 49164 49165 49166 # EMITTING VINSERTI32X8 (VINSERTI32X8-512-1) 49167 { 49168 ICLASS: VINSERTI32X8 49169 CPL: 3 49170 CATEGORY: AVX512 49171 EXTENSION: AVX512EVEX 49172 ISA_SET: AVX512DQ_512 49173 EXCEPTIONS: AVX512-E6NF 49174 REAL_OPCODE: Y 49175 ATTRIBUTES: MASKOP_EVEX 49176 PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 49177 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 49178 IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 49179 } 49180 49181 { 49182 ICLASS: VINSERTI32X8 49183 CPL: 3 49184 CATEGORY: AVX512 49185 EXTENSION: AVX512EVEX 49186 ISA_SET: AVX512DQ_512 49187 EXCEPTIONS: AVX512-E6NF 49188 REAL_OPCODE: Y 49189 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 49190 PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() 49191 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:qq:u32 IMM0:r:b 49192 IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 49193 } 49194 49195 49196 # EMITTING VINSERTI64X2 (VINSERTI64X2-256-1) 49197 { 49198 ICLASS: VINSERTI64X2 49199 CPL: 3 49200 CATEGORY: AVX512 49201 EXTENSION: AVX512EVEX 49202 ISA_SET: AVX512DQ_256 49203 EXCEPTIONS: AVX512-E6NF 49204 REAL_OPCODE: Y 49205 ATTRIBUTES: MASKOP_EVEX 49206 PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 49207 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 49208 IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 49209 } 49210 49211 { 49212 ICLASS: VINSERTI64X2 49213 CPL: 3 49214 CATEGORY: AVX512 49215 EXTENSION: AVX512EVEX 49216 ISA_SET: AVX512DQ_256 49217 EXCEPTIONS: AVX512-E6NF 49218 REAL_OPCODE: Y 49219 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 49220 PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 49221 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 IMM0:r:b 49222 IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 49223 } 49224 49225 49226 # EMITTING VINSERTI64X2 (VINSERTI64X2-512-1) 49227 { 49228 ICLASS: VINSERTI64X2 49229 CPL: 3 49230 CATEGORY: AVX512 49231 EXTENSION: AVX512EVEX 49232 ISA_SET: AVX512DQ_512 49233 EXCEPTIONS: AVX512-E6NF 49234 REAL_OPCODE: Y 49235 ATTRIBUTES: MASKOP_EVEX 49236 PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 49237 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 49238 IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 49239 } 49240 49241 { 49242 ICLASS: VINSERTI64X2 49243 CPL: 3 49244 CATEGORY: AVX512 49245 EXTENSION: AVX512EVEX 49246 ISA_SET: AVX512DQ_512 49247 EXCEPTIONS: AVX512-E6NF 49248 REAL_OPCODE: Y 49249 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 49250 PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 49251 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 IMM0:r:b 49252 IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 49253 } 49254 49255 49256 # EMITTING VMAXPD (VMAXPD-128-1) 49257 { 49258 ICLASS: VMAXPD 49259 CPL: 3 49260 CATEGORY: AVX512 49261 EXTENSION: AVX512EVEX 49262 ISA_SET: AVX512F_128 49263 EXCEPTIONS: AVX512-E2 49264 REAL_OPCODE: Y 49265 ATTRIBUTES: MXCSR MASKOP_EVEX 49266 PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 49267 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 49268 IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 49269 } 49270 49271 { 49272 ICLASS: VMAXPD 49273 CPL: 3 49274 CATEGORY: AVX512 49275 EXTENSION: AVX512EVEX 49276 ISA_SET: AVX512F_128 49277 EXCEPTIONS: AVX512-E2 49278 REAL_OPCODE: Y 49279 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49280 PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 49281 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 49282 IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 49283 } 49284 49285 49286 # EMITTING VMAXPD (VMAXPD-256-1) 49287 { 49288 ICLASS: VMAXPD 49289 CPL: 3 49290 CATEGORY: AVX512 49291 EXTENSION: AVX512EVEX 49292 ISA_SET: AVX512F_256 49293 EXCEPTIONS: AVX512-E2 49294 REAL_OPCODE: Y 49295 ATTRIBUTES: MXCSR MASKOP_EVEX 49296 PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 49297 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 49298 IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 49299 } 49300 49301 { 49302 ICLASS: VMAXPD 49303 CPL: 3 49304 CATEGORY: AVX512 49305 EXTENSION: AVX512EVEX 49306 ISA_SET: AVX512F_256 49307 EXCEPTIONS: AVX512-E2 49308 REAL_OPCODE: Y 49309 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49310 PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 49311 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 49312 IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 49313 } 49314 49315 49316 # EMITTING VMAXPS (VMAXPS-128-1) 49317 { 49318 ICLASS: VMAXPS 49319 CPL: 3 49320 CATEGORY: AVX512 49321 EXTENSION: AVX512EVEX 49322 ISA_SET: AVX512F_128 49323 EXCEPTIONS: AVX512-E2 49324 REAL_OPCODE: Y 49325 ATTRIBUTES: MXCSR MASKOP_EVEX 49326 PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 49327 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 49328 IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 49329 } 49330 49331 { 49332 ICLASS: VMAXPS 49333 CPL: 3 49334 CATEGORY: AVX512 49335 EXTENSION: AVX512EVEX 49336 ISA_SET: AVX512F_128 49337 EXCEPTIONS: AVX512-E2 49338 REAL_OPCODE: Y 49339 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49340 PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 49341 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 49342 IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 49343 } 49344 49345 49346 # EMITTING VMAXPS (VMAXPS-256-1) 49347 { 49348 ICLASS: VMAXPS 49349 CPL: 3 49350 CATEGORY: AVX512 49351 EXTENSION: AVX512EVEX 49352 ISA_SET: AVX512F_256 49353 EXCEPTIONS: AVX512-E2 49354 REAL_OPCODE: Y 49355 ATTRIBUTES: MXCSR MASKOP_EVEX 49356 PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 49357 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 49358 IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 49359 } 49360 49361 { 49362 ICLASS: VMAXPS 49363 CPL: 3 49364 CATEGORY: AVX512 49365 EXTENSION: AVX512EVEX 49366 ISA_SET: AVX512F_256 49367 EXCEPTIONS: AVX512-E2 49368 REAL_OPCODE: Y 49369 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49370 PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 49371 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 49372 IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 49373 } 49374 49375 49376 # EMITTING VMINPD (VMINPD-128-1) 49377 { 49378 ICLASS: VMINPD 49379 CPL: 3 49380 CATEGORY: AVX512 49381 EXTENSION: AVX512EVEX 49382 ISA_SET: AVX512F_128 49383 EXCEPTIONS: AVX512-E2 49384 REAL_OPCODE: Y 49385 ATTRIBUTES: MXCSR MASKOP_EVEX 49386 PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 49387 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 49388 IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 49389 } 49390 49391 { 49392 ICLASS: VMINPD 49393 CPL: 3 49394 CATEGORY: AVX512 49395 EXTENSION: AVX512EVEX 49396 ISA_SET: AVX512F_128 49397 EXCEPTIONS: AVX512-E2 49398 REAL_OPCODE: Y 49399 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49400 PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 49401 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 49402 IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 49403 } 49404 49405 49406 # EMITTING VMINPD (VMINPD-256-1) 49407 { 49408 ICLASS: VMINPD 49409 CPL: 3 49410 CATEGORY: AVX512 49411 EXTENSION: AVX512EVEX 49412 ISA_SET: AVX512F_256 49413 EXCEPTIONS: AVX512-E2 49414 REAL_OPCODE: Y 49415 ATTRIBUTES: MXCSR MASKOP_EVEX 49416 PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 49417 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 49418 IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 49419 } 49420 49421 { 49422 ICLASS: VMINPD 49423 CPL: 3 49424 CATEGORY: AVX512 49425 EXTENSION: AVX512EVEX 49426 ISA_SET: AVX512F_256 49427 EXCEPTIONS: AVX512-E2 49428 REAL_OPCODE: Y 49429 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49430 PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 49431 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 49432 IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 49433 } 49434 49435 49436 # EMITTING VMINPS (VMINPS-128-1) 49437 { 49438 ICLASS: VMINPS 49439 CPL: 3 49440 CATEGORY: AVX512 49441 EXTENSION: AVX512EVEX 49442 ISA_SET: AVX512F_128 49443 EXCEPTIONS: AVX512-E2 49444 REAL_OPCODE: Y 49445 ATTRIBUTES: MXCSR MASKOP_EVEX 49446 PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 49447 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 49448 IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 49449 } 49450 49451 { 49452 ICLASS: VMINPS 49453 CPL: 3 49454 CATEGORY: AVX512 49455 EXTENSION: AVX512EVEX 49456 ISA_SET: AVX512F_128 49457 EXCEPTIONS: AVX512-E2 49458 REAL_OPCODE: Y 49459 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49460 PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 49461 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 49462 IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 49463 } 49464 49465 49466 # EMITTING VMINPS (VMINPS-256-1) 49467 { 49468 ICLASS: VMINPS 49469 CPL: 3 49470 CATEGORY: AVX512 49471 EXTENSION: AVX512EVEX 49472 ISA_SET: AVX512F_256 49473 EXCEPTIONS: AVX512-E2 49474 REAL_OPCODE: Y 49475 ATTRIBUTES: MXCSR MASKOP_EVEX 49476 PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 49477 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 49478 IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 49479 } 49480 49481 { 49482 ICLASS: VMINPS 49483 CPL: 3 49484 CATEGORY: AVX512 49485 EXTENSION: AVX512EVEX 49486 ISA_SET: AVX512F_256 49487 EXCEPTIONS: AVX512-E2 49488 REAL_OPCODE: Y 49489 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49490 PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 49491 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 49492 IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 49493 } 49494 49495 49496 # EMITTING VMOVAPD (VMOVAPD-128-1) 49497 { 49498 ICLASS: VMOVAPD 49499 CPL: 3 49500 CATEGORY: DATAXFER 49501 EXTENSION: AVX512EVEX 49502 ISA_SET: AVX512F_128 49503 EXCEPTIONS: AVX512-E1 49504 REAL_OPCODE: Y 49505 ATTRIBUTES: MASKOP_EVEX 49506 PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 49507 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 49508 IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 49509 } 49510 49511 { 49512 ICLASS: VMOVAPD 49513 CPL: 3 49514 CATEGORY: DATAXFER 49515 EXTENSION: AVX512EVEX 49516 ISA_SET: AVX512F_128 49517 EXCEPTIONS: AVX512-E1 49518 REAL_OPCODE: Y 49519 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49520 PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 49521 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 49522 IFORM: VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 49523 } 49524 49525 49526 # EMITTING VMOVAPD (VMOVAPD-128-2) 49527 { 49528 ICLASS: VMOVAPD 49529 CPL: 3 49530 CATEGORY: DATAXFER 49531 EXTENSION: AVX512EVEX 49532 ISA_SET: AVX512F_128 49533 EXCEPTIONS: AVX512-E1 49534 REAL_OPCODE: Y 49535 ATTRIBUTES: MASKOP_EVEX 49536 PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 49537 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 49538 IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 49539 } 49540 49541 49542 # EMITTING VMOVAPD (VMOVAPD-128-3) 49543 { 49544 ICLASS: VMOVAPD 49545 CPL: 3 49546 CATEGORY: DATAXFER 49547 EXTENSION: AVX512EVEX 49548 ISA_SET: AVX512F_128 49549 EXCEPTIONS: AVX512-E1 49550 REAL_OPCODE: Y 49551 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49552 PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 49553 OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 49554 IFORM: VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 49555 } 49556 49557 49558 # EMITTING VMOVAPD (VMOVAPD-256-1) 49559 { 49560 ICLASS: VMOVAPD 49561 CPL: 3 49562 CATEGORY: DATAXFER 49563 EXTENSION: AVX512EVEX 49564 ISA_SET: AVX512F_256 49565 EXCEPTIONS: AVX512-E1 49566 REAL_OPCODE: Y 49567 ATTRIBUTES: MASKOP_EVEX 49568 PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 49569 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 49570 IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 49571 } 49572 49573 { 49574 ICLASS: VMOVAPD 49575 CPL: 3 49576 CATEGORY: DATAXFER 49577 EXTENSION: AVX512EVEX 49578 ISA_SET: AVX512F_256 49579 EXCEPTIONS: AVX512-E1 49580 REAL_OPCODE: Y 49581 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49582 PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 49583 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 49584 IFORM: VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 49585 } 49586 49587 49588 # EMITTING VMOVAPD (VMOVAPD-256-2) 49589 { 49590 ICLASS: VMOVAPD 49591 CPL: 3 49592 CATEGORY: DATAXFER 49593 EXTENSION: AVX512EVEX 49594 ISA_SET: AVX512F_256 49595 EXCEPTIONS: AVX512-E1 49596 REAL_OPCODE: Y 49597 ATTRIBUTES: MASKOP_EVEX 49598 PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 49599 OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 49600 IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 49601 } 49602 49603 49604 # EMITTING VMOVAPD (VMOVAPD-256-3) 49605 { 49606 ICLASS: VMOVAPD 49607 CPL: 3 49608 CATEGORY: DATAXFER 49609 EXTENSION: AVX512EVEX 49610 ISA_SET: AVX512F_256 49611 EXCEPTIONS: AVX512-E1 49612 REAL_OPCODE: Y 49613 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49614 PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 49615 OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 49616 IFORM: VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 49617 } 49618 49619 49620 # EMITTING VMOVAPS (VMOVAPS-128-1) 49621 { 49622 ICLASS: VMOVAPS 49623 CPL: 3 49624 CATEGORY: DATAXFER 49625 EXTENSION: AVX512EVEX 49626 ISA_SET: AVX512F_128 49627 EXCEPTIONS: AVX512-E1 49628 REAL_OPCODE: Y 49629 ATTRIBUTES: MASKOP_EVEX 49630 PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 49631 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 49632 IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 49633 } 49634 49635 { 49636 ICLASS: VMOVAPS 49637 CPL: 3 49638 CATEGORY: DATAXFER 49639 EXTENSION: AVX512EVEX 49640 ISA_SET: AVX512F_128 49641 EXCEPTIONS: AVX512-E1 49642 REAL_OPCODE: Y 49643 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49644 PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 49645 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 49646 IFORM: VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 49647 } 49648 49649 49650 # EMITTING VMOVAPS (VMOVAPS-128-2) 49651 { 49652 ICLASS: VMOVAPS 49653 CPL: 3 49654 CATEGORY: DATAXFER 49655 EXTENSION: AVX512EVEX 49656 ISA_SET: AVX512F_128 49657 EXCEPTIONS: AVX512-E1 49658 REAL_OPCODE: Y 49659 ATTRIBUTES: MASKOP_EVEX 49660 PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 49661 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 49662 IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 49663 } 49664 49665 49666 # EMITTING VMOVAPS (VMOVAPS-128-3) 49667 { 49668 ICLASS: VMOVAPS 49669 CPL: 3 49670 CATEGORY: DATAXFER 49671 EXTENSION: AVX512EVEX 49672 ISA_SET: AVX512F_128 49673 EXCEPTIONS: AVX512-E1 49674 REAL_OPCODE: Y 49675 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49676 PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 49677 OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 49678 IFORM: VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 49679 } 49680 49681 49682 # EMITTING VMOVAPS (VMOVAPS-256-1) 49683 { 49684 ICLASS: VMOVAPS 49685 CPL: 3 49686 CATEGORY: DATAXFER 49687 EXTENSION: AVX512EVEX 49688 ISA_SET: AVX512F_256 49689 EXCEPTIONS: AVX512-E1 49690 REAL_OPCODE: Y 49691 ATTRIBUTES: MASKOP_EVEX 49692 PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 49693 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 49694 IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 49695 } 49696 49697 { 49698 ICLASS: VMOVAPS 49699 CPL: 3 49700 CATEGORY: DATAXFER 49701 EXTENSION: AVX512EVEX 49702 ISA_SET: AVX512F_256 49703 EXCEPTIONS: AVX512-E1 49704 REAL_OPCODE: Y 49705 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49706 PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 49707 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 49708 IFORM: VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 49709 } 49710 49711 49712 # EMITTING VMOVAPS (VMOVAPS-256-2) 49713 { 49714 ICLASS: VMOVAPS 49715 CPL: 3 49716 CATEGORY: DATAXFER 49717 EXTENSION: AVX512EVEX 49718 ISA_SET: AVX512F_256 49719 EXCEPTIONS: AVX512-E1 49720 REAL_OPCODE: Y 49721 ATTRIBUTES: MASKOP_EVEX 49722 PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 49723 OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 49724 IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 49725 } 49726 49727 49728 # EMITTING VMOVAPS (VMOVAPS-256-3) 49729 { 49730 ICLASS: VMOVAPS 49731 CPL: 3 49732 CATEGORY: DATAXFER 49733 EXTENSION: AVX512EVEX 49734 ISA_SET: AVX512F_256 49735 EXCEPTIONS: AVX512-E1 49736 REAL_OPCODE: Y 49737 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49738 PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 49739 OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 49740 IFORM: VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 49741 } 49742 49743 49744 # EMITTING VMOVDDUP (VMOVDDUP-128-1) 49745 { 49746 ICLASS: VMOVDDUP 49747 CPL: 3 49748 CATEGORY: DATAXFER 49749 EXTENSION: AVX512EVEX 49750 ISA_SET: AVX512F_128 49751 EXCEPTIONS: AVX512-E5NF 49752 REAL_OPCODE: Y 49753 ATTRIBUTES: MASKOP_EVEX 49754 PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 49755 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 49756 IFORM: VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 49757 } 49758 49759 { 49760 ICLASS: VMOVDDUP 49761 CPL: 3 49762 CATEGORY: DATAXFER 49763 EXTENSION: AVX512EVEX 49764 ISA_SET: AVX512F_128 49765 EXCEPTIONS: AVX512-E5NF 49766 REAL_OPCODE: Y 49767 ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP 49768 PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() 49769 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 49770 IFORM: VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 49771 } 49772 49773 49774 # EMITTING VMOVDDUP (VMOVDDUP-256-1) 49775 { 49776 ICLASS: VMOVDDUP 49777 CPL: 3 49778 CATEGORY: DATAXFER 49779 EXTENSION: AVX512EVEX 49780 ISA_SET: AVX512F_256 49781 EXCEPTIONS: AVX512-E5NF 49782 REAL_OPCODE: Y 49783 ATTRIBUTES: MASKOP_EVEX 49784 PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 49785 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 49786 IFORM: VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 49787 } 49788 49789 { 49790 ICLASS: VMOVDDUP 49791 CPL: 3 49792 CATEGORY: DATAXFER 49793 EXTENSION: AVX512EVEX 49794 ISA_SET: AVX512F_256 49795 EXCEPTIONS: AVX512-E5NF 49796 REAL_OPCODE: Y 49797 ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP 49798 PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() 49799 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 49800 IFORM: VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 49801 } 49802 49803 49804 # EMITTING VMOVDQA32 (VMOVDQA32-128-1) 49805 { 49806 ICLASS: VMOVDQA32 49807 CPL: 3 49808 CATEGORY: DATAXFER 49809 EXTENSION: AVX512EVEX 49810 ISA_SET: AVX512F_128 49811 EXCEPTIONS: AVX512-E1 49812 REAL_OPCODE: Y 49813 ATTRIBUTES: MASKOP_EVEX 49814 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 49815 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 49816 IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 49817 } 49818 49819 { 49820 ICLASS: VMOVDQA32 49821 CPL: 3 49822 CATEGORY: DATAXFER 49823 EXTENSION: AVX512EVEX 49824 ISA_SET: AVX512F_128 49825 EXCEPTIONS: AVX512-E1 49826 REAL_OPCODE: Y 49827 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49828 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 49829 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 49830 IFORM: VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 49831 } 49832 49833 49834 # EMITTING VMOVDQA32 (VMOVDQA32-128-2) 49835 { 49836 ICLASS: VMOVDQA32 49837 CPL: 3 49838 CATEGORY: DATAXFER 49839 EXTENSION: AVX512EVEX 49840 ISA_SET: AVX512F_128 49841 EXCEPTIONS: AVX512-E1 49842 REAL_OPCODE: Y 49843 ATTRIBUTES: MASKOP_EVEX 49844 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 49845 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 49846 IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 49847 } 49848 49849 49850 # EMITTING VMOVDQA32 (VMOVDQA32-128-3) 49851 { 49852 ICLASS: VMOVDQA32 49853 CPL: 3 49854 CATEGORY: DATAXFER 49855 EXTENSION: AVX512EVEX 49856 ISA_SET: AVX512F_128 49857 EXCEPTIONS: AVX512-E1 49858 REAL_OPCODE: Y 49859 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49860 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 49861 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 49862 IFORM: VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 49863 } 49864 49865 49866 # EMITTING VMOVDQA32 (VMOVDQA32-256-1) 49867 { 49868 ICLASS: VMOVDQA32 49869 CPL: 3 49870 CATEGORY: DATAXFER 49871 EXTENSION: AVX512EVEX 49872 ISA_SET: AVX512F_256 49873 EXCEPTIONS: AVX512-E1 49874 REAL_OPCODE: Y 49875 ATTRIBUTES: MASKOP_EVEX 49876 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 49877 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 49878 IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 49879 } 49880 49881 { 49882 ICLASS: VMOVDQA32 49883 CPL: 3 49884 CATEGORY: DATAXFER 49885 EXTENSION: AVX512EVEX 49886 ISA_SET: AVX512F_256 49887 EXCEPTIONS: AVX512-E1 49888 REAL_OPCODE: Y 49889 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49890 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 49891 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 49892 IFORM: VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 49893 } 49894 49895 49896 # EMITTING VMOVDQA32 (VMOVDQA32-256-2) 49897 { 49898 ICLASS: VMOVDQA32 49899 CPL: 3 49900 CATEGORY: DATAXFER 49901 EXTENSION: AVX512EVEX 49902 ISA_SET: AVX512F_256 49903 EXCEPTIONS: AVX512-E1 49904 REAL_OPCODE: Y 49905 ATTRIBUTES: MASKOP_EVEX 49906 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 49907 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 49908 IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 49909 } 49910 49911 49912 # EMITTING VMOVDQA32 (VMOVDQA32-256-3) 49913 { 49914 ICLASS: VMOVDQA32 49915 CPL: 3 49916 CATEGORY: DATAXFER 49917 EXTENSION: AVX512EVEX 49918 ISA_SET: AVX512F_256 49919 EXCEPTIONS: AVX512-E1 49920 REAL_OPCODE: Y 49921 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49922 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 49923 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 49924 IFORM: VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 49925 } 49926 49927 49928 # EMITTING VMOVDQA64 (VMOVDQA64-128-1) 49929 { 49930 ICLASS: VMOVDQA64 49931 CPL: 3 49932 CATEGORY: DATAXFER 49933 EXTENSION: AVX512EVEX 49934 ISA_SET: AVX512F_128 49935 EXCEPTIONS: AVX512-E1 49936 REAL_OPCODE: Y 49937 ATTRIBUTES: MASKOP_EVEX 49938 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 49939 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 49940 IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 49941 } 49942 49943 { 49944 ICLASS: VMOVDQA64 49945 CPL: 3 49946 CATEGORY: DATAXFER 49947 EXTENSION: AVX512EVEX 49948 ISA_SET: AVX512F_128 49949 EXCEPTIONS: AVX512-E1 49950 REAL_OPCODE: Y 49951 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49952 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 49953 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 49954 IFORM: VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 49955 } 49956 49957 49958 # EMITTING VMOVDQA64 (VMOVDQA64-128-2) 49959 { 49960 ICLASS: VMOVDQA64 49961 CPL: 3 49962 CATEGORY: DATAXFER 49963 EXTENSION: AVX512EVEX 49964 ISA_SET: AVX512F_128 49965 EXCEPTIONS: AVX512-E1 49966 REAL_OPCODE: Y 49967 ATTRIBUTES: MASKOP_EVEX 49968 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 49969 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 49970 IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 49971 } 49972 49973 49974 # EMITTING VMOVDQA64 (VMOVDQA64-128-3) 49975 { 49976 ICLASS: VMOVDQA64 49977 CPL: 3 49978 CATEGORY: DATAXFER 49979 EXTENSION: AVX512EVEX 49980 ISA_SET: AVX512F_128 49981 EXCEPTIONS: AVX512-E1 49982 REAL_OPCODE: Y 49983 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49984 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 49985 OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 49986 IFORM: VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 49987 } 49988 49989 49990 # EMITTING VMOVDQA64 (VMOVDQA64-256-1) 49991 { 49992 ICLASS: VMOVDQA64 49993 CPL: 3 49994 CATEGORY: DATAXFER 49995 EXTENSION: AVX512EVEX 49996 ISA_SET: AVX512F_256 49997 EXCEPTIONS: AVX512-E1 49998 REAL_OPCODE: Y 49999 ATTRIBUTES: MASKOP_EVEX 50000 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 50001 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 50002 IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 50003 } 50004 50005 { 50006 ICLASS: VMOVDQA64 50007 CPL: 3 50008 CATEGORY: DATAXFER 50009 EXTENSION: AVX512EVEX 50010 ISA_SET: AVX512F_256 50011 EXCEPTIONS: AVX512-E1 50012 REAL_OPCODE: Y 50013 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50014 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 50015 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 50016 IFORM: VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 50017 } 50018 50019 50020 # EMITTING VMOVDQA64 (VMOVDQA64-256-2) 50021 { 50022 ICLASS: VMOVDQA64 50023 CPL: 3 50024 CATEGORY: DATAXFER 50025 EXTENSION: AVX512EVEX 50026 ISA_SET: AVX512F_256 50027 EXCEPTIONS: AVX512-E1 50028 REAL_OPCODE: Y 50029 ATTRIBUTES: MASKOP_EVEX 50030 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 50031 OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 50032 IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 50033 } 50034 50035 50036 # EMITTING VMOVDQA64 (VMOVDQA64-256-3) 50037 { 50038 ICLASS: VMOVDQA64 50039 CPL: 3 50040 CATEGORY: DATAXFER 50041 EXTENSION: AVX512EVEX 50042 ISA_SET: AVX512F_256 50043 EXCEPTIONS: AVX512-E1 50044 REAL_OPCODE: Y 50045 ATTRIBUTES: REQUIRES_ALIGNMENT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50046 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 50047 OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 50048 IFORM: VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 50049 } 50050 50051 50052 # EMITTING VMOVDQU16 (VMOVDQU16-128-1) 50053 { 50054 ICLASS: VMOVDQU16 50055 CPL: 3 50056 CATEGORY: DATAXFER 50057 EXTENSION: AVX512EVEX 50058 ISA_SET: AVX512BW_128 50059 EXCEPTIONS: AVX512-E4 50060 REAL_OPCODE: Y 50061 ATTRIBUTES: MASKOP_EVEX 50062 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 50063 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 50064 IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 50065 } 50066 50067 { 50068 ICLASS: VMOVDQU16 50069 CPL: 3 50070 CATEGORY: DATAXFER 50071 EXTENSION: AVX512EVEX 50072 ISA_SET: AVX512BW_128 50073 EXCEPTIONS: AVX512-E4 50074 REAL_OPCODE: Y 50075 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50076 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 50077 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 50078 IFORM: VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 50079 } 50080 50081 50082 # EMITTING VMOVDQU16 (VMOVDQU16-128-2) 50083 { 50084 ICLASS: VMOVDQU16 50085 CPL: 3 50086 CATEGORY: DATAXFER 50087 EXTENSION: AVX512EVEX 50088 ISA_SET: AVX512BW_128 50089 EXCEPTIONS: AVX512-E4 50090 REAL_OPCODE: Y 50091 ATTRIBUTES: MASKOP_EVEX 50092 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 50093 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 50094 IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 50095 } 50096 50097 50098 # EMITTING VMOVDQU16 (VMOVDQU16-128-3) 50099 { 50100 ICLASS: VMOVDQU16 50101 CPL: 3 50102 CATEGORY: DATAXFER 50103 EXTENSION: AVX512EVEX 50104 ISA_SET: AVX512BW_128 50105 EXCEPTIONS: AVX512-E4 50106 REAL_OPCODE: Y 50107 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50108 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 50109 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 50110 IFORM: VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 50111 } 50112 50113 50114 # EMITTING VMOVDQU16 (VMOVDQU16-256-1) 50115 { 50116 ICLASS: VMOVDQU16 50117 CPL: 3 50118 CATEGORY: DATAXFER 50119 EXTENSION: AVX512EVEX 50120 ISA_SET: AVX512BW_256 50121 EXCEPTIONS: AVX512-E4 50122 REAL_OPCODE: Y 50123 ATTRIBUTES: MASKOP_EVEX 50124 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 50125 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 50126 IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 50127 } 50128 50129 { 50130 ICLASS: VMOVDQU16 50131 CPL: 3 50132 CATEGORY: DATAXFER 50133 EXTENSION: AVX512EVEX 50134 ISA_SET: AVX512BW_256 50135 EXCEPTIONS: AVX512-E4 50136 REAL_OPCODE: Y 50137 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50138 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 50139 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 50140 IFORM: VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 50141 } 50142 50143 50144 # EMITTING VMOVDQU16 (VMOVDQU16-256-2) 50145 { 50146 ICLASS: VMOVDQU16 50147 CPL: 3 50148 CATEGORY: DATAXFER 50149 EXTENSION: AVX512EVEX 50150 ISA_SET: AVX512BW_256 50151 EXCEPTIONS: AVX512-E4 50152 REAL_OPCODE: Y 50153 ATTRIBUTES: MASKOP_EVEX 50154 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 50155 OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 50156 IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 50157 } 50158 50159 50160 # EMITTING VMOVDQU16 (VMOVDQU16-256-3) 50161 { 50162 ICLASS: VMOVDQU16 50163 CPL: 3 50164 CATEGORY: DATAXFER 50165 EXTENSION: AVX512EVEX 50166 ISA_SET: AVX512BW_256 50167 EXCEPTIONS: AVX512-E4 50168 REAL_OPCODE: Y 50169 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50170 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 50171 OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 50172 IFORM: VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 50173 } 50174 50175 50176 # EMITTING VMOVDQU16 (VMOVDQU16-512-1) 50177 { 50178 ICLASS: VMOVDQU16 50179 CPL: 3 50180 CATEGORY: DATAXFER 50181 EXTENSION: AVX512EVEX 50182 ISA_SET: AVX512BW_512 50183 EXCEPTIONS: AVX512-E4 50184 REAL_OPCODE: Y 50185 ATTRIBUTES: MASKOP_EVEX 50186 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 50187 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 50188 IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 50189 } 50190 50191 { 50192 ICLASS: VMOVDQU16 50193 CPL: 3 50194 CATEGORY: DATAXFER 50195 EXTENSION: AVX512EVEX 50196 ISA_SET: AVX512BW_512 50197 EXCEPTIONS: AVX512-E4 50198 REAL_OPCODE: Y 50199 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50200 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 50201 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 50202 IFORM: VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 50203 } 50204 50205 50206 # EMITTING VMOVDQU16 (VMOVDQU16-512-2) 50207 { 50208 ICLASS: VMOVDQU16 50209 CPL: 3 50210 CATEGORY: DATAXFER 50211 EXTENSION: AVX512EVEX 50212 ISA_SET: AVX512BW_512 50213 EXCEPTIONS: AVX512-E4 50214 REAL_OPCODE: Y 50215 ATTRIBUTES: MASKOP_EVEX 50216 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 50217 OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 50218 IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 50219 } 50220 50221 50222 # EMITTING VMOVDQU16 (VMOVDQU16-512-3) 50223 { 50224 ICLASS: VMOVDQU16 50225 CPL: 3 50226 CATEGORY: DATAXFER 50227 EXTENSION: AVX512EVEX 50228 ISA_SET: AVX512BW_512 50229 EXCEPTIONS: AVX512-E4 50230 REAL_OPCODE: Y 50231 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50232 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 50233 OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 50234 IFORM: VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 50235 } 50236 50237 50238 # EMITTING VMOVDQU32 (VMOVDQU32-128-1) 50239 { 50240 ICLASS: VMOVDQU32 50241 CPL: 3 50242 CATEGORY: DATAXFER 50243 EXTENSION: AVX512EVEX 50244 ISA_SET: AVX512F_128 50245 EXCEPTIONS: AVX512-E4 50246 REAL_OPCODE: Y 50247 ATTRIBUTES: MASKOP_EVEX 50248 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 50249 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 50250 IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 50251 } 50252 50253 { 50254 ICLASS: VMOVDQU32 50255 CPL: 3 50256 CATEGORY: DATAXFER 50257 EXTENSION: AVX512EVEX 50258 ISA_SET: AVX512F_128 50259 EXCEPTIONS: AVX512-E4 50260 REAL_OPCODE: Y 50261 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50262 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 50263 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 50264 IFORM: VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 50265 } 50266 50267 50268 # EMITTING VMOVDQU32 (VMOVDQU32-128-2) 50269 { 50270 ICLASS: VMOVDQU32 50271 CPL: 3 50272 CATEGORY: DATAXFER 50273 EXTENSION: AVX512EVEX 50274 ISA_SET: AVX512F_128 50275 EXCEPTIONS: AVX512-E4 50276 REAL_OPCODE: Y 50277 ATTRIBUTES: MASKOP_EVEX 50278 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 50279 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 50280 IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 50281 } 50282 50283 50284 # EMITTING VMOVDQU32 (VMOVDQU32-128-3) 50285 { 50286 ICLASS: VMOVDQU32 50287 CPL: 3 50288 CATEGORY: DATAXFER 50289 EXTENSION: AVX512EVEX 50290 ISA_SET: AVX512F_128 50291 EXCEPTIONS: AVX512-E4 50292 REAL_OPCODE: Y 50293 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50294 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 50295 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 50296 IFORM: VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 50297 } 50298 50299 50300 # EMITTING VMOVDQU32 (VMOVDQU32-256-1) 50301 { 50302 ICLASS: VMOVDQU32 50303 CPL: 3 50304 CATEGORY: DATAXFER 50305 EXTENSION: AVX512EVEX 50306 ISA_SET: AVX512F_256 50307 EXCEPTIONS: AVX512-E4 50308 REAL_OPCODE: Y 50309 ATTRIBUTES: MASKOP_EVEX 50310 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 50311 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 50312 IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 50313 } 50314 50315 { 50316 ICLASS: VMOVDQU32 50317 CPL: 3 50318 CATEGORY: DATAXFER 50319 EXTENSION: AVX512EVEX 50320 ISA_SET: AVX512F_256 50321 EXCEPTIONS: AVX512-E4 50322 REAL_OPCODE: Y 50323 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50324 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 50325 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 50326 IFORM: VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 50327 } 50328 50329 50330 # EMITTING VMOVDQU32 (VMOVDQU32-256-2) 50331 { 50332 ICLASS: VMOVDQU32 50333 CPL: 3 50334 CATEGORY: DATAXFER 50335 EXTENSION: AVX512EVEX 50336 ISA_SET: AVX512F_256 50337 EXCEPTIONS: AVX512-E4 50338 REAL_OPCODE: Y 50339 ATTRIBUTES: MASKOP_EVEX 50340 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 50341 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 50342 IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 50343 } 50344 50345 50346 # EMITTING VMOVDQU32 (VMOVDQU32-256-3) 50347 { 50348 ICLASS: VMOVDQU32 50349 CPL: 3 50350 CATEGORY: DATAXFER 50351 EXTENSION: AVX512EVEX 50352 ISA_SET: AVX512F_256 50353 EXCEPTIONS: AVX512-E4 50354 REAL_OPCODE: Y 50355 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50356 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 50357 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 50358 IFORM: VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 50359 } 50360 50361 50362 # EMITTING VMOVDQU64 (VMOVDQU64-128-1) 50363 { 50364 ICLASS: VMOVDQU64 50365 CPL: 3 50366 CATEGORY: DATAXFER 50367 EXTENSION: AVX512EVEX 50368 ISA_SET: AVX512F_128 50369 EXCEPTIONS: AVX512-E4 50370 REAL_OPCODE: Y 50371 ATTRIBUTES: MASKOP_EVEX 50372 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 50373 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 50374 IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 50375 } 50376 50377 { 50378 ICLASS: VMOVDQU64 50379 CPL: 3 50380 CATEGORY: DATAXFER 50381 EXTENSION: AVX512EVEX 50382 ISA_SET: AVX512F_128 50383 EXCEPTIONS: AVX512-E4 50384 REAL_OPCODE: Y 50385 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50386 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 50387 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 50388 IFORM: VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 50389 } 50390 50391 50392 # EMITTING VMOVDQU64 (VMOVDQU64-128-2) 50393 { 50394 ICLASS: VMOVDQU64 50395 CPL: 3 50396 CATEGORY: DATAXFER 50397 EXTENSION: AVX512EVEX 50398 ISA_SET: AVX512F_128 50399 EXCEPTIONS: AVX512-E4 50400 REAL_OPCODE: Y 50401 ATTRIBUTES: MASKOP_EVEX 50402 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 50403 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 50404 IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 50405 } 50406 50407 50408 # EMITTING VMOVDQU64 (VMOVDQU64-128-3) 50409 { 50410 ICLASS: VMOVDQU64 50411 CPL: 3 50412 CATEGORY: DATAXFER 50413 EXTENSION: AVX512EVEX 50414 ISA_SET: AVX512F_128 50415 EXCEPTIONS: AVX512-E4 50416 REAL_OPCODE: Y 50417 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50418 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 50419 OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 50420 IFORM: VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 50421 } 50422 50423 50424 # EMITTING VMOVDQU64 (VMOVDQU64-256-1) 50425 { 50426 ICLASS: VMOVDQU64 50427 CPL: 3 50428 CATEGORY: DATAXFER 50429 EXTENSION: AVX512EVEX 50430 ISA_SET: AVX512F_256 50431 EXCEPTIONS: AVX512-E4 50432 REAL_OPCODE: Y 50433 ATTRIBUTES: MASKOP_EVEX 50434 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 50435 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 50436 IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 50437 } 50438 50439 { 50440 ICLASS: VMOVDQU64 50441 CPL: 3 50442 CATEGORY: DATAXFER 50443 EXTENSION: AVX512EVEX 50444 ISA_SET: AVX512F_256 50445 EXCEPTIONS: AVX512-E4 50446 REAL_OPCODE: Y 50447 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50448 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 50449 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 50450 IFORM: VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 50451 } 50452 50453 50454 # EMITTING VMOVDQU64 (VMOVDQU64-256-2) 50455 { 50456 ICLASS: VMOVDQU64 50457 CPL: 3 50458 CATEGORY: DATAXFER 50459 EXTENSION: AVX512EVEX 50460 ISA_SET: AVX512F_256 50461 EXCEPTIONS: AVX512-E4 50462 REAL_OPCODE: Y 50463 ATTRIBUTES: MASKOP_EVEX 50464 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 50465 OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 50466 IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 50467 } 50468 50469 50470 # EMITTING VMOVDQU64 (VMOVDQU64-256-3) 50471 { 50472 ICLASS: VMOVDQU64 50473 CPL: 3 50474 CATEGORY: DATAXFER 50475 EXTENSION: AVX512EVEX 50476 ISA_SET: AVX512F_256 50477 EXCEPTIONS: AVX512-E4 50478 REAL_OPCODE: Y 50479 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50480 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 50481 OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 50482 IFORM: VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 50483 } 50484 50485 50486 # EMITTING VMOVDQU8 (VMOVDQU8-128-1) 50487 { 50488 ICLASS: VMOVDQU8 50489 CPL: 3 50490 CATEGORY: DATAXFER 50491 EXTENSION: AVX512EVEX 50492 ISA_SET: AVX512BW_128 50493 EXCEPTIONS: AVX512-E4 50494 REAL_OPCODE: Y 50495 ATTRIBUTES: MASKOP_EVEX 50496 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 50497 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 50498 IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 50499 } 50500 50501 { 50502 ICLASS: VMOVDQU8 50503 CPL: 3 50504 CATEGORY: DATAXFER 50505 EXTENSION: AVX512EVEX 50506 ISA_SET: AVX512BW_128 50507 EXCEPTIONS: AVX512-E4 50508 REAL_OPCODE: Y 50509 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50510 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 50511 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 50512 IFORM: VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 50513 } 50514 50515 50516 # EMITTING VMOVDQU8 (VMOVDQU8-128-2) 50517 { 50518 ICLASS: VMOVDQU8 50519 CPL: 3 50520 CATEGORY: DATAXFER 50521 EXTENSION: AVX512EVEX 50522 ISA_SET: AVX512BW_128 50523 EXCEPTIONS: AVX512-E4 50524 REAL_OPCODE: Y 50525 ATTRIBUTES: MASKOP_EVEX 50526 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 50527 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 50528 IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 50529 } 50530 50531 50532 # EMITTING VMOVDQU8 (VMOVDQU8-128-3) 50533 { 50534 ICLASS: VMOVDQU8 50535 CPL: 3 50536 CATEGORY: DATAXFER 50537 EXTENSION: AVX512EVEX 50538 ISA_SET: AVX512BW_128 50539 EXCEPTIONS: AVX512-E4 50540 REAL_OPCODE: Y 50541 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50542 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 50543 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 50544 IFORM: VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 50545 } 50546 50547 50548 # EMITTING VMOVDQU8 (VMOVDQU8-256-1) 50549 { 50550 ICLASS: VMOVDQU8 50551 CPL: 3 50552 CATEGORY: DATAXFER 50553 EXTENSION: AVX512EVEX 50554 ISA_SET: AVX512BW_256 50555 EXCEPTIONS: AVX512-E4 50556 REAL_OPCODE: Y 50557 ATTRIBUTES: MASKOP_EVEX 50558 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 50559 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 50560 IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 50561 } 50562 50563 { 50564 ICLASS: VMOVDQU8 50565 CPL: 3 50566 CATEGORY: DATAXFER 50567 EXTENSION: AVX512EVEX 50568 ISA_SET: AVX512BW_256 50569 EXCEPTIONS: AVX512-E4 50570 REAL_OPCODE: Y 50571 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50572 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 50573 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 50574 IFORM: VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 50575 } 50576 50577 50578 # EMITTING VMOVDQU8 (VMOVDQU8-256-2) 50579 { 50580 ICLASS: VMOVDQU8 50581 CPL: 3 50582 CATEGORY: DATAXFER 50583 EXTENSION: AVX512EVEX 50584 ISA_SET: AVX512BW_256 50585 EXCEPTIONS: AVX512-E4 50586 REAL_OPCODE: Y 50587 ATTRIBUTES: MASKOP_EVEX 50588 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 50589 OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 50590 IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 50591 } 50592 50593 50594 # EMITTING VMOVDQU8 (VMOVDQU8-256-3) 50595 { 50596 ICLASS: VMOVDQU8 50597 CPL: 3 50598 CATEGORY: DATAXFER 50599 EXTENSION: AVX512EVEX 50600 ISA_SET: AVX512BW_256 50601 EXCEPTIONS: AVX512-E4 50602 REAL_OPCODE: Y 50603 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50604 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 50605 OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 50606 IFORM: VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 50607 } 50608 50609 50610 # EMITTING VMOVDQU8 (VMOVDQU8-512-1) 50611 { 50612 ICLASS: VMOVDQU8 50613 CPL: 3 50614 CATEGORY: DATAXFER 50615 EXTENSION: AVX512EVEX 50616 ISA_SET: AVX512BW_512 50617 EXCEPTIONS: AVX512-E4 50618 REAL_OPCODE: Y 50619 ATTRIBUTES: MASKOP_EVEX 50620 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 50621 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 50622 IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 50623 } 50624 50625 { 50626 ICLASS: VMOVDQU8 50627 CPL: 3 50628 CATEGORY: DATAXFER 50629 EXTENSION: AVX512EVEX 50630 ISA_SET: AVX512BW_512 50631 EXCEPTIONS: AVX512-E4 50632 REAL_OPCODE: Y 50633 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50634 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 50635 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 50636 IFORM: VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 50637 } 50638 50639 50640 # EMITTING VMOVDQU8 (VMOVDQU8-512-2) 50641 { 50642 ICLASS: VMOVDQU8 50643 CPL: 3 50644 CATEGORY: DATAXFER 50645 EXTENSION: AVX512EVEX 50646 ISA_SET: AVX512BW_512 50647 EXCEPTIONS: AVX512-E4 50648 REAL_OPCODE: Y 50649 ATTRIBUTES: MASKOP_EVEX 50650 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 50651 OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 50652 IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 50653 } 50654 50655 50656 # EMITTING VMOVDQU8 (VMOVDQU8-512-3) 50657 { 50658 ICLASS: VMOVDQU8 50659 CPL: 3 50660 CATEGORY: DATAXFER 50661 EXTENSION: AVX512EVEX 50662 ISA_SET: AVX512BW_512 50663 EXCEPTIONS: AVX512-E4 50664 REAL_OPCODE: Y 50665 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50666 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 50667 OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 50668 IFORM: VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 50669 } 50670 50671 50672 # EMITTING VMOVNTDQ (VMOVNTDQ-128-1) 50673 { 50674 ICLASS: VMOVNTDQ 50675 CPL: 3 50676 CATEGORY: DATAXFER 50677 EXTENSION: AVX512EVEX 50678 ISA_SET: AVX512F_128 50679 EXCEPTIONS: AVX512-E1NF 50680 REAL_OPCODE: Y 50681 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 50682 PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 50683 OPERANDS: MEM0:w:dq:u32 REG0=XMM_R3():r:dq:u32 50684 IFORM: VMOVNTDQ_MEMu32_XMMu32_AVX512 50685 } 50686 50687 50688 # EMITTING VMOVNTDQ (VMOVNTDQ-256-1) 50689 { 50690 ICLASS: VMOVNTDQ 50691 CPL: 3 50692 CATEGORY: DATAXFER 50693 EXTENSION: AVX512EVEX 50694 ISA_SET: AVX512F_256 50695 EXCEPTIONS: AVX512-E1NF 50696 REAL_OPCODE: Y 50697 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 50698 PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 50699 OPERANDS: MEM0:w:qq:u32 REG0=YMM_R3():r:qq:u32 50700 IFORM: VMOVNTDQ_MEMu32_YMMu32_AVX512 50701 } 50702 50703 50704 # EMITTING VMOVNTDQA (VMOVNTDQA-128-1) 50705 { 50706 ICLASS: VMOVNTDQA 50707 CPL: 3 50708 CATEGORY: DATAXFER 50709 EXTENSION: AVX512EVEX 50710 ISA_SET: AVX512F_128 50711 EXCEPTIONS: AVX512-E1NF 50712 REAL_OPCODE: Y 50713 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 50714 PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 50715 OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:dq:u32 50716 IFORM: VMOVNTDQA_XMMu32_MEMu32_AVX512 50717 } 50718 50719 50720 # EMITTING VMOVNTDQA (VMOVNTDQA-256-1) 50721 { 50722 ICLASS: VMOVNTDQA 50723 CPL: 3 50724 CATEGORY: DATAXFER 50725 EXTENSION: AVX512EVEX 50726 ISA_SET: AVX512F_256 50727 EXCEPTIONS: AVX512-E1NF 50728 REAL_OPCODE: Y 50729 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 50730 PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 50731 OPERANDS: REG0=YMM_R3():w:qq:u32 MEM0:r:qq:u32 50732 IFORM: VMOVNTDQA_YMMu32_MEMu32_AVX512 50733 } 50734 50735 50736 # EMITTING VMOVNTPD (VMOVNTPD-128-1) 50737 { 50738 ICLASS: VMOVNTPD 50739 CPL: 3 50740 CATEGORY: DATAXFER 50741 EXTENSION: AVX512EVEX 50742 ISA_SET: AVX512F_128 50743 EXCEPTIONS: AVX512-E1NF 50744 REAL_OPCODE: Y 50745 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 50746 PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() 50747 OPERANDS: MEM0:w:dq:f64 REG0=XMM_R3():r:dq:f64 50748 IFORM: VMOVNTPD_MEMf64_XMMf64_AVX512 50749 } 50750 50751 50752 # EMITTING VMOVNTPD (VMOVNTPD-256-1) 50753 { 50754 ICLASS: VMOVNTPD 50755 CPL: 3 50756 CATEGORY: DATAXFER 50757 EXTENSION: AVX512EVEX 50758 ISA_SET: AVX512F_256 50759 EXCEPTIONS: AVX512-E1NF 50760 REAL_OPCODE: Y 50761 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 50762 PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() 50763 OPERANDS: MEM0:w:qq:f64 REG0=YMM_R3():r:qq:f64 50764 IFORM: VMOVNTPD_MEMf64_YMMf64_AVX512 50765 } 50766 50767 50768 # EMITTING VMOVNTPS (VMOVNTPS-128-1) 50769 { 50770 ICLASS: VMOVNTPS 50771 CPL: 3 50772 CATEGORY: DATAXFER 50773 EXTENSION: AVX512EVEX 50774 ISA_SET: AVX512F_128 50775 EXCEPTIONS: AVX512-E1NF 50776 REAL_OPCODE: Y 50777 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 50778 PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 50779 OPERANDS: MEM0:w:dq:f32 REG0=XMM_R3():r:dq:f32 50780 IFORM: VMOVNTPS_MEMf32_XMMf32_AVX512 50781 } 50782 50783 50784 # EMITTING VMOVNTPS (VMOVNTPS-256-1) 50785 { 50786 ICLASS: VMOVNTPS 50787 CPL: 3 50788 CATEGORY: DATAXFER 50789 EXTENSION: AVX512EVEX 50790 ISA_SET: AVX512F_256 50791 EXCEPTIONS: AVX512-E1NF 50792 REAL_OPCODE: Y 50793 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 50794 PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 50795 OPERANDS: MEM0:w:qq:f32 REG0=YMM_R3():r:qq:f32 50796 IFORM: VMOVNTPS_MEMf32_YMMf32_AVX512 50797 } 50798 50799 50800 # EMITTING VMOVSHDUP (VMOVSHDUP-128-1) 50801 { 50802 ICLASS: VMOVSHDUP 50803 CPL: 3 50804 CATEGORY: DATAXFER 50805 EXTENSION: AVX512EVEX 50806 ISA_SET: AVX512F_128 50807 EXCEPTIONS: AVX512-E4NF 50808 REAL_OPCODE: Y 50809 ATTRIBUTES: MASKOP_EVEX 50810 PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 50811 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 50812 IFORM: VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 50813 } 50814 50815 { 50816 ICLASS: VMOVSHDUP 50817 CPL: 3 50818 CATEGORY: DATAXFER 50819 EXTENSION: AVX512EVEX 50820 ISA_SET: AVX512F_128 50821 EXCEPTIONS: AVX512-E4NF 50822 REAL_OPCODE: Y 50823 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50824 PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 50825 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 50826 IFORM: VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 50827 } 50828 50829 50830 # EMITTING VMOVSHDUP (VMOVSHDUP-256-1) 50831 { 50832 ICLASS: VMOVSHDUP 50833 CPL: 3 50834 CATEGORY: DATAXFER 50835 EXTENSION: AVX512EVEX 50836 ISA_SET: AVX512F_256 50837 EXCEPTIONS: AVX512-E4NF 50838 REAL_OPCODE: Y 50839 ATTRIBUTES: MASKOP_EVEX 50840 PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 50841 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 50842 IFORM: VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 50843 } 50844 50845 { 50846 ICLASS: VMOVSHDUP 50847 CPL: 3 50848 CATEGORY: DATAXFER 50849 EXTENSION: AVX512EVEX 50850 ISA_SET: AVX512F_256 50851 EXCEPTIONS: AVX512-E4NF 50852 REAL_OPCODE: Y 50853 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50854 PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 50855 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 50856 IFORM: VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 50857 } 50858 50859 50860 # EMITTING VMOVSLDUP (VMOVSLDUP-128-1) 50861 { 50862 ICLASS: VMOVSLDUP 50863 CPL: 3 50864 CATEGORY: DATAXFER 50865 EXTENSION: AVX512EVEX 50866 ISA_SET: AVX512F_128 50867 EXCEPTIONS: AVX512-E4NF 50868 REAL_OPCODE: Y 50869 ATTRIBUTES: MASKOP_EVEX 50870 PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 50871 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 50872 IFORM: VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 50873 } 50874 50875 { 50876 ICLASS: VMOVSLDUP 50877 CPL: 3 50878 CATEGORY: DATAXFER 50879 EXTENSION: AVX512EVEX 50880 ISA_SET: AVX512F_128 50881 EXCEPTIONS: AVX512-E4NF 50882 REAL_OPCODE: Y 50883 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50884 PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 50885 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 50886 IFORM: VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 50887 } 50888 50889 50890 # EMITTING VMOVSLDUP (VMOVSLDUP-256-1) 50891 { 50892 ICLASS: VMOVSLDUP 50893 CPL: 3 50894 CATEGORY: DATAXFER 50895 EXTENSION: AVX512EVEX 50896 ISA_SET: AVX512F_256 50897 EXCEPTIONS: AVX512-E4NF 50898 REAL_OPCODE: Y 50899 ATTRIBUTES: MASKOP_EVEX 50900 PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 50901 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 50902 IFORM: VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 50903 } 50904 50905 { 50906 ICLASS: VMOVSLDUP 50907 CPL: 3 50908 CATEGORY: DATAXFER 50909 EXTENSION: AVX512EVEX 50910 ISA_SET: AVX512F_256 50911 EXCEPTIONS: AVX512-E4NF 50912 REAL_OPCODE: Y 50913 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50914 PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 50915 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 50916 IFORM: VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 50917 } 50918 50919 50920 # EMITTING VMOVUPD (VMOVUPD-128-1) 50921 { 50922 ICLASS: VMOVUPD 50923 CPL: 3 50924 CATEGORY: DATAXFER 50925 EXTENSION: AVX512EVEX 50926 ISA_SET: AVX512F_128 50927 EXCEPTIONS: AVX512-E4 50928 REAL_OPCODE: Y 50929 ATTRIBUTES: MASKOP_EVEX 50930 PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 50931 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 50932 IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 50933 } 50934 50935 { 50936 ICLASS: VMOVUPD 50937 CPL: 3 50938 CATEGORY: DATAXFER 50939 EXTENSION: AVX512EVEX 50940 ISA_SET: AVX512F_128 50941 EXCEPTIONS: AVX512-E4 50942 REAL_OPCODE: Y 50943 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50944 PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 50945 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 50946 IFORM: VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 50947 } 50948 50949 50950 # EMITTING VMOVUPD (VMOVUPD-128-2) 50951 { 50952 ICLASS: VMOVUPD 50953 CPL: 3 50954 CATEGORY: DATAXFER 50955 EXTENSION: AVX512EVEX 50956 ISA_SET: AVX512F_128 50957 EXCEPTIONS: AVX512-E4 50958 REAL_OPCODE: Y 50959 ATTRIBUTES: MASKOP_EVEX 50960 PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 50961 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 50962 IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 50963 } 50964 50965 50966 # EMITTING VMOVUPD (VMOVUPD-128-3) 50967 { 50968 ICLASS: VMOVUPD 50969 CPL: 3 50970 CATEGORY: DATAXFER 50971 EXTENSION: AVX512EVEX 50972 ISA_SET: AVX512F_128 50973 EXCEPTIONS: AVX512-E4 50974 REAL_OPCODE: Y 50975 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50976 PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 50977 OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 50978 IFORM: VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 50979 } 50980 50981 50982 # EMITTING VMOVUPD (VMOVUPD-256-1) 50983 { 50984 ICLASS: VMOVUPD 50985 CPL: 3 50986 CATEGORY: DATAXFER 50987 EXTENSION: AVX512EVEX 50988 ISA_SET: AVX512F_256 50989 EXCEPTIONS: AVX512-E4 50990 REAL_OPCODE: Y 50991 ATTRIBUTES: MASKOP_EVEX 50992 PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 50993 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 50994 IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 50995 } 50996 50997 { 50998 ICLASS: VMOVUPD 50999 CPL: 3 51000 CATEGORY: DATAXFER 51001 EXTENSION: AVX512EVEX 51002 ISA_SET: AVX512F_256 51003 EXCEPTIONS: AVX512-E4 51004 REAL_OPCODE: Y 51005 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51006 PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 51007 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 51008 IFORM: VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 51009 } 51010 51011 51012 # EMITTING VMOVUPD (VMOVUPD-256-2) 51013 { 51014 ICLASS: VMOVUPD 51015 CPL: 3 51016 CATEGORY: DATAXFER 51017 EXTENSION: AVX512EVEX 51018 ISA_SET: AVX512F_256 51019 EXCEPTIONS: AVX512-E4 51020 REAL_OPCODE: Y 51021 ATTRIBUTES: MASKOP_EVEX 51022 PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 51023 OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 51024 IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 51025 } 51026 51027 51028 # EMITTING VMOVUPD (VMOVUPD-256-3) 51029 { 51030 ICLASS: VMOVUPD 51031 CPL: 3 51032 CATEGORY: DATAXFER 51033 EXTENSION: AVX512EVEX 51034 ISA_SET: AVX512F_256 51035 EXCEPTIONS: AVX512-E4 51036 REAL_OPCODE: Y 51037 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51038 PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 51039 OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 51040 IFORM: VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 51041 } 51042 51043 51044 # EMITTING VMOVUPS (VMOVUPS-128-1) 51045 { 51046 ICLASS: VMOVUPS 51047 CPL: 3 51048 CATEGORY: DATAXFER 51049 EXTENSION: AVX512EVEX 51050 ISA_SET: AVX512F_128 51051 EXCEPTIONS: AVX512-E4 51052 REAL_OPCODE: Y 51053 ATTRIBUTES: MASKOP_EVEX 51054 PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 51055 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 51056 IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 51057 } 51058 51059 { 51060 ICLASS: VMOVUPS 51061 CPL: 3 51062 CATEGORY: DATAXFER 51063 EXTENSION: AVX512EVEX 51064 ISA_SET: AVX512F_128 51065 EXCEPTIONS: AVX512-E4 51066 REAL_OPCODE: Y 51067 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51068 PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 51069 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 51070 IFORM: VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 51071 } 51072 51073 51074 # EMITTING VMOVUPS (VMOVUPS-128-2) 51075 { 51076 ICLASS: VMOVUPS 51077 CPL: 3 51078 CATEGORY: DATAXFER 51079 EXTENSION: AVX512EVEX 51080 ISA_SET: AVX512F_128 51081 EXCEPTIONS: AVX512-E4 51082 REAL_OPCODE: Y 51083 ATTRIBUTES: MASKOP_EVEX 51084 PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 51085 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 51086 IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 51087 } 51088 51089 51090 # EMITTING VMOVUPS (VMOVUPS-128-3) 51091 { 51092 ICLASS: VMOVUPS 51093 CPL: 3 51094 CATEGORY: DATAXFER 51095 EXTENSION: AVX512EVEX 51096 ISA_SET: AVX512F_128 51097 EXCEPTIONS: AVX512-E4 51098 REAL_OPCODE: Y 51099 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51100 PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 51101 OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 51102 IFORM: VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 51103 } 51104 51105 51106 # EMITTING VMOVUPS (VMOVUPS-256-1) 51107 { 51108 ICLASS: VMOVUPS 51109 CPL: 3 51110 CATEGORY: DATAXFER 51111 EXTENSION: AVX512EVEX 51112 ISA_SET: AVX512F_256 51113 EXCEPTIONS: AVX512-E4 51114 REAL_OPCODE: Y 51115 ATTRIBUTES: MASKOP_EVEX 51116 PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 51117 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 51118 IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 51119 } 51120 51121 { 51122 ICLASS: VMOVUPS 51123 CPL: 3 51124 CATEGORY: DATAXFER 51125 EXTENSION: AVX512EVEX 51126 ISA_SET: AVX512F_256 51127 EXCEPTIONS: AVX512-E4 51128 REAL_OPCODE: Y 51129 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51130 PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 51131 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 51132 IFORM: VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 51133 } 51134 51135 51136 # EMITTING VMOVUPS (VMOVUPS-256-2) 51137 { 51138 ICLASS: VMOVUPS 51139 CPL: 3 51140 CATEGORY: DATAXFER 51141 EXTENSION: AVX512EVEX 51142 ISA_SET: AVX512F_256 51143 EXCEPTIONS: AVX512-E4 51144 REAL_OPCODE: Y 51145 ATTRIBUTES: MASKOP_EVEX 51146 PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 51147 OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 51148 IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 51149 } 51150 51151 51152 # EMITTING VMOVUPS (VMOVUPS-256-3) 51153 { 51154 ICLASS: VMOVUPS 51155 CPL: 3 51156 CATEGORY: DATAXFER 51157 EXTENSION: AVX512EVEX 51158 ISA_SET: AVX512F_256 51159 EXCEPTIONS: AVX512-E4 51160 REAL_OPCODE: Y 51161 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51162 PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 51163 OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 51164 IFORM: VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 51165 } 51166 51167 51168 # EMITTING VMULPD (VMULPD-128-1) 51169 { 51170 ICLASS: VMULPD 51171 CPL: 3 51172 CATEGORY: AVX512 51173 EXTENSION: AVX512EVEX 51174 ISA_SET: AVX512F_128 51175 EXCEPTIONS: AVX512-E2 51176 REAL_OPCODE: Y 51177 ATTRIBUTES: MXCSR MASKOP_EVEX 51178 PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 51179 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 51180 IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 51181 } 51182 51183 { 51184 ICLASS: VMULPD 51185 CPL: 3 51186 CATEGORY: AVX512 51187 EXTENSION: AVX512EVEX 51188 ISA_SET: AVX512F_128 51189 EXCEPTIONS: AVX512-E2 51190 REAL_OPCODE: Y 51191 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51192 PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 51193 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 51194 IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 51195 } 51196 51197 51198 # EMITTING VMULPD (VMULPD-256-1) 51199 { 51200 ICLASS: VMULPD 51201 CPL: 3 51202 CATEGORY: AVX512 51203 EXTENSION: AVX512EVEX 51204 ISA_SET: AVX512F_256 51205 EXCEPTIONS: AVX512-E2 51206 REAL_OPCODE: Y 51207 ATTRIBUTES: MXCSR MASKOP_EVEX 51208 PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 51209 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 51210 IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 51211 } 51212 51213 { 51214 ICLASS: VMULPD 51215 CPL: 3 51216 CATEGORY: AVX512 51217 EXTENSION: AVX512EVEX 51218 ISA_SET: AVX512F_256 51219 EXCEPTIONS: AVX512-E2 51220 REAL_OPCODE: Y 51221 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51222 PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 51223 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 51224 IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 51225 } 51226 51227 51228 # EMITTING VMULPS (VMULPS-128-1) 51229 { 51230 ICLASS: VMULPS 51231 CPL: 3 51232 CATEGORY: AVX512 51233 EXTENSION: AVX512EVEX 51234 ISA_SET: AVX512F_128 51235 EXCEPTIONS: AVX512-E2 51236 REAL_OPCODE: Y 51237 ATTRIBUTES: MXCSR MASKOP_EVEX 51238 PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 51239 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 51240 IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 51241 } 51242 51243 { 51244 ICLASS: VMULPS 51245 CPL: 3 51246 CATEGORY: AVX512 51247 EXTENSION: AVX512EVEX 51248 ISA_SET: AVX512F_128 51249 EXCEPTIONS: AVX512-E2 51250 REAL_OPCODE: Y 51251 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51252 PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 51253 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 51254 IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 51255 } 51256 51257 51258 # EMITTING VMULPS (VMULPS-256-1) 51259 { 51260 ICLASS: VMULPS 51261 CPL: 3 51262 CATEGORY: AVX512 51263 EXTENSION: AVX512EVEX 51264 ISA_SET: AVX512F_256 51265 EXCEPTIONS: AVX512-E2 51266 REAL_OPCODE: Y 51267 ATTRIBUTES: MXCSR MASKOP_EVEX 51268 PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 51269 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 51270 IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 51271 } 51272 51273 { 51274 ICLASS: VMULPS 51275 CPL: 3 51276 CATEGORY: AVX512 51277 EXTENSION: AVX512EVEX 51278 ISA_SET: AVX512F_256 51279 EXCEPTIONS: AVX512-E2 51280 REAL_OPCODE: Y 51281 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51282 PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 51283 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 51284 IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 51285 } 51286 51287 51288 # EMITTING VORPD (VORPD-128-1) 51289 { 51290 ICLASS: VORPD 51291 CPL: 3 51292 CATEGORY: LOGICAL_FP 51293 EXTENSION: AVX512EVEX 51294 ISA_SET: AVX512DQ_128 51295 EXCEPTIONS: AVX512-E4 51296 REAL_OPCODE: Y 51297 ATTRIBUTES: MASKOP_EVEX 51298 PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 51299 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 51300 IFORM: VORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 51301 } 51302 51303 { 51304 ICLASS: VORPD 51305 CPL: 3 51306 CATEGORY: LOGICAL_FP 51307 EXTENSION: AVX512EVEX 51308 ISA_SET: AVX512DQ_128 51309 EXCEPTIONS: AVX512-E4 51310 REAL_OPCODE: Y 51311 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51312 PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 51313 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 51314 IFORM: VORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 51315 } 51316 51317 51318 # EMITTING VORPD (VORPD-256-1) 51319 { 51320 ICLASS: VORPD 51321 CPL: 3 51322 CATEGORY: LOGICAL_FP 51323 EXTENSION: AVX512EVEX 51324 ISA_SET: AVX512DQ_256 51325 EXCEPTIONS: AVX512-E4 51326 REAL_OPCODE: Y 51327 ATTRIBUTES: MASKOP_EVEX 51328 PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 51329 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 51330 IFORM: VORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 51331 } 51332 51333 { 51334 ICLASS: VORPD 51335 CPL: 3 51336 CATEGORY: LOGICAL_FP 51337 EXTENSION: AVX512EVEX 51338 ISA_SET: AVX512DQ_256 51339 EXCEPTIONS: AVX512-E4 51340 REAL_OPCODE: Y 51341 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51342 PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 51343 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 51344 IFORM: VORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 51345 } 51346 51347 51348 # EMITTING VORPD (VORPD-512-1) 51349 { 51350 ICLASS: VORPD 51351 CPL: 3 51352 CATEGORY: LOGICAL_FP 51353 EXTENSION: AVX512EVEX 51354 ISA_SET: AVX512DQ_512 51355 EXCEPTIONS: AVX512-E4 51356 REAL_OPCODE: Y 51357 ATTRIBUTES: MASKOP_EVEX 51358 PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 51359 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 51360 IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 51361 } 51362 51363 { 51364 ICLASS: VORPD 51365 CPL: 3 51366 CATEGORY: LOGICAL_FP 51367 EXTENSION: AVX512EVEX 51368 ISA_SET: AVX512DQ_512 51369 EXCEPTIONS: AVX512-E4 51370 REAL_OPCODE: Y 51371 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51372 PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 51373 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 51374 IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 51375 } 51376 51377 51378 # EMITTING VORPS (VORPS-128-1) 51379 { 51380 ICLASS: VORPS 51381 CPL: 3 51382 CATEGORY: LOGICAL_FP 51383 EXTENSION: AVX512EVEX 51384 ISA_SET: AVX512DQ_128 51385 EXCEPTIONS: AVX512-E4 51386 REAL_OPCODE: Y 51387 ATTRIBUTES: MASKOP_EVEX 51388 PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 51389 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 51390 IFORM: VORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 51391 } 51392 51393 { 51394 ICLASS: VORPS 51395 CPL: 3 51396 CATEGORY: LOGICAL_FP 51397 EXTENSION: AVX512EVEX 51398 ISA_SET: AVX512DQ_128 51399 EXCEPTIONS: AVX512-E4 51400 REAL_OPCODE: Y 51401 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51402 PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 51403 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 51404 IFORM: VORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 51405 } 51406 51407 51408 # EMITTING VORPS (VORPS-256-1) 51409 { 51410 ICLASS: VORPS 51411 CPL: 3 51412 CATEGORY: LOGICAL_FP 51413 EXTENSION: AVX512EVEX 51414 ISA_SET: AVX512DQ_256 51415 EXCEPTIONS: AVX512-E4 51416 REAL_OPCODE: Y 51417 ATTRIBUTES: MASKOP_EVEX 51418 PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 51419 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 51420 IFORM: VORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 51421 } 51422 51423 { 51424 ICLASS: VORPS 51425 CPL: 3 51426 CATEGORY: LOGICAL_FP 51427 EXTENSION: AVX512EVEX 51428 ISA_SET: AVX512DQ_256 51429 EXCEPTIONS: AVX512-E4 51430 REAL_OPCODE: Y 51431 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51432 PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 51433 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 51434 IFORM: VORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 51435 } 51436 51437 51438 # EMITTING VORPS (VORPS-512-1) 51439 { 51440 ICLASS: VORPS 51441 CPL: 3 51442 CATEGORY: LOGICAL_FP 51443 EXTENSION: AVX512EVEX 51444 ISA_SET: AVX512DQ_512 51445 EXCEPTIONS: AVX512-E4 51446 REAL_OPCODE: Y 51447 ATTRIBUTES: MASKOP_EVEX 51448 PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 51449 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 51450 IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 51451 } 51452 51453 { 51454 ICLASS: VORPS 51455 CPL: 3 51456 CATEGORY: LOGICAL_FP 51457 EXTENSION: AVX512EVEX 51458 ISA_SET: AVX512DQ_512 51459 EXCEPTIONS: AVX512-E4 51460 REAL_OPCODE: Y 51461 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51462 PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 51463 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 51464 IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 51465 } 51466 51467 51468 # EMITTING VPABSB (VPABSB-128-1) 51469 { 51470 ICLASS: VPABSB 51471 CPL: 3 51472 CATEGORY: AVX512 51473 EXTENSION: AVX512EVEX 51474 ISA_SET: AVX512BW_128 51475 EXCEPTIONS: AVX512-E4 51476 REAL_OPCODE: Y 51477 ATTRIBUTES: MASKOP_EVEX 51478 PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 51479 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 51480 IFORM: VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 51481 } 51482 51483 { 51484 ICLASS: VPABSB 51485 CPL: 3 51486 CATEGORY: AVX512 51487 EXTENSION: AVX512EVEX 51488 ISA_SET: AVX512BW_128 51489 EXCEPTIONS: AVX512-E4 51490 REAL_OPCODE: Y 51491 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51492 PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 51493 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 51494 IFORM: VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 51495 } 51496 51497 51498 # EMITTING VPABSB (VPABSB-256-1) 51499 { 51500 ICLASS: VPABSB 51501 CPL: 3 51502 CATEGORY: AVX512 51503 EXTENSION: AVX512EVEX 51504 ISA_SET: AVX512BW_256 51505 EXCEPTIONS: AVX512-E4 51506 REAL_OPCODE: Y 51507 ATTRIBUTES: MASKOP_EVEX 51508 PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 51509 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 51510 IFORM: VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 51511 } 51512 51513 { 51514 ICLASS: VPABSB 51515 CPL: 3 51516 CATEGORY: AVX512 51517 EXTENSION: AVX512EVEX 51518 ISA_SET: AVX512BW_256 51519 EXCEPTIONS: AVX512-E4 51520 REAL_OPCODE: Y 51521 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51522 PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 51523 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 51524 IFORM: VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 51525 } 51526 51527 51528 # EMITTING VPABSB (VPABSB-512-1) 51529 { 51530 ICLASS: VPABSB 51531 CPL: 3 51532 CATEGORY: AVX512 51533 EXTENSION: AVX512EVEX 51534 ISA_SET: AVX512BW_512 51535 EXCEPTIONS: AVX512-E4 51536 REAL_OPCODE: Y 51537 ATTRIBUTES: MASKOP_EVEX 51538 PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 51539 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi8 51540 IFORM: VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 51541 } 51542 51543 { 51544 ICLASS: VPABSB 51545 CPL: 3 51546 CATEGORY: AVX512 51547 EXTENSION: AVX512EVEX 51548 ISA_SET: AVX512BW_512 51549 EXCEPTIONS: AVX512-E4 51550 REAL_OPCODE: Y 51551 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51552 PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 51553 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i8 51554 IFORM: VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 51555 } 51556 51557 51558 # EMITTING VPABSD (VPABSD-128-1) 51559 { 51560 ICLASS: VPABSD 51561 CPL: 3 51562 CATEGORY: AVX512 51563 EXTENSION: AVX512EVEX 51564 ISA_SET: AVX512F_128 51565 EXCEPTIONS: AVX512-E4 51566 REAL_OPCODE: Y 51567 ATTRIBUTES: MASKOP_EVEX 51568 PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 51569 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 51570 IFORM: VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 51571 } 51572 51573 { 51574 ICLASS: VPABSD 51575 CPL: 3 51576 CATEGORY: AVX512 51577 EXTENSION: AVX512EVEX 51578 ISA_SET: AVX512F_128 51579 EXCEPTIONS: AVX512-E4 51580 REAL_OPCODE: Y 51581 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51582 PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 51583 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 51584 IFORM: VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 51585 } 51586 51587 51588 # EMITTING VPABSD (VPABSD-256-1) 51589 { 51590 ICLASS: VPABSD 51591 CPL: 3 51592 CATEGORY: AVX512 51593 EXTENSION: AVX512EVEX 51594 ISA_SET: AVX512F_256 51595 EXCEPTIONS: AVX512-E4 51596 REAL_OPCODE: Y 51597 ATTRIBUTES: MASKOP_EVEX 51598 PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 51599 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 51600 IFORM: VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 51601 } 51602 51603 { 51604 ICLASS: VPABSD 51605 CPL: 3 51606 CATEGORY: AVX512 51607 EXTENSION: AVX512EVEX 51608 ISA_SET: AVX512F_256 51609 EXCEPTIONS: AVX512-E4 51610 REAL_OPCODE: Y 51611 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51612 PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 51613 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 51614 IFORM: VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 51615 } 51616 51617 51618 # EMITTING VPABSQ (VPABSQ-128-1) 51619 { 51620 ICLASS: VPABSQ 51621 CPL: 3 51622 CATEGORY: AVX512 51623 EXTENSION: AVX512EVEX 51624 ISA_SET: AVX512F_128 51625 EXCEPTIONS: AVX512-E4 51626 REAL_OPCODE: Y 51627 ATTRIBUTES: MASKOP_EVEX 51628 PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 51629 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64 51630 IFORM: VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 51631 } 51632 51633 { 51634 ICLASS: VPABSQ 51635 CPL: 3 51636 CATEGORY: AVX512 51637 EXTENSION: AVX512EVEX 51638 ISA_SET: AVX512F_128 51639 EXCEPTIONS: AVX512-E4 51640 REAL_OPCODE: Y 51641 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51642 PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 51643 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR 51644 IFORM: VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 51645 } 51646 51647 51648 # EMITTING VPABSQ (VPABSQ-256-1) 51649 { 51650 ICLASS: VPABSQ 51651 CPL: 3 51652 CATEGORY: AVX512 51653 EXTENSION: AVX512EVEX 51654 ISA_SET: AVX512F_256 51655 EXCEPTIONS: AVX512-E4 51656 REAL_OPCODE: Y 51657 ATTRIBUTES: MASKOP_EVEX 51658 PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 51659 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64 51660 IFORM: VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 51661 } 51662 51663 { 51664 ICLASS: VPABSQ 51665 CPL: 3 51666 CATEGORY: AVX512 51667 EXTENSION: AVX512EVEX 51668 ISA_SET: AVX512F_256 51669 EXCEPTIONS: AVX512-E4 51670 REAL_OPCODE: Y 51671 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51672 PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 51673 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR 51674 IFORM: VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 51675 } 51676 51677 51678 # EMITTING VPABSW (VPABSW-128-1) 51679 { 51680 ICLASS: VPABSW 51681 CPL: 3 51682 CATEGORY: AVX512 51683 EXTENSION: AVX512EVEX 51684 ISA_SET: AVX512BW_128 51685 EXCEPTIONS: AVX512-E4 51686 REAL_OPCODE: Y 51687 ATTRIBUTES: MASKOP_EVEX 51688 PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 51689 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 51690 IFORM: VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 51691 } 51692 51693 { 51694 ICLASS: VPABSW 51695 CPL: 3 51696 CATEGORY: AVX512 51697 EXTENSION: AVX512EVEX 51698 ISA_SET: AVX512BW_128 51699 EXCEPTIONS: AVX512-E4 51700 REAL_OPCODE: Y 51701 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51702 PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 51703 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 51704 IFORM: VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 51705 } 51706 51707 51708 # EMITTING VPABSW (VPABSW-256-1) 51709 { 51710 ICLASS: VPABSW 51711 CPL: 3 51712 CATEGORY: AVX512 51713 EXTENSION: AVX512EVEX 51714 ISA_SET: AVX512BW_256 51715 EXCEPTIONS: AVX512-E4 51716 REAL_OPCODE: Y 51717 ATTRIBUTES: MASKOP_EVEX 51718 PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 51719 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 51720 IFORM: VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 51721 } 51722 51723 { 51724 ICLASS: VPABSW 51725 CPL: 3 51726 CATEGORY: AVX512 51727 EXTENSION: AVX512EVEX 51728 ISA_SET: AVX512BW_256 51729 EXCEPTIONS: AVX512-E4 51730 REAL_OPCODE: Y 51731 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51732 PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 51733 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 51734 IFORM: VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 51735 } 51736 51737 51738 # EMITTING VPABSW (VPABSW-512-1) 51739 { 51740 ICLASS: VPABSW 51741 CPL: 3 51742 CATEGORY: AVX512 51743 EXTENSION: AVX512EVEX 51744 ISA_SET: AVX512BW_512 51745 EXCEPTIONS: AVX512-E4 51746 REAL_OPCODE: Y 51747 ATTRIBUTES: MASKOP_EVEX 51748 PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 51749 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 51750 IFORM: VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 51751 } 51752 51753 { 51754 ICLASS: VPABSW 51755 CPL: 3 51756 CATEGORY: AVX512 51757 EXTENSION: AVX512EVEX 51758 ISA_SET: AVX512BW_512 51759 EXCEPTIONS: AVX512-E4 51760 REAL_OPCODE: Y 51761 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 51762 PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 51763 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i16 51764 IFORM: VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 51765 } 51766 51767 51768 # EMITTING VPACKSSDW (VPACKSSDW-128-1) 51769 { 51770 ICLASS: VPACKSSDW 51771 CPL: 3 51772 CATEGORY: AVX512 51773 EXTENSION: AVX512EVEX 51774 ISA_SET: AVX512BW_128 51775 EXCEPTIONS: AVX512-E4NF 51776 REAL_OPCODE: Y 51777 ATTRIBUTES: MASKOP_EVEX 51778 PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 51779 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 51780 IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 51781 } 51782 51783 { 51784 ICLASS: VPACKSSDW 51785 CPL: 3 51786 CATEGORY: AVX512 51787 EXTENSION: AVX512EVEX 51788 ISA_SET: AVX512BW_128 51789 EXCEPTIONS: AVX512-E4NF 51790 REAL_OPCODE: Y 51791 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51792 PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 51793 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 51794 IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 51795 } 51796 51797 51798 # EMITTING VPACKSSDW (VPACKSSDW-256-1) 51799 { 51800 ICLASS: VPACKSSDW 51801 CPL: 3 51802 CATEGORY: AVX512 51803 EXTENSION: AVX512EVEX 51804 ISA_SET: AVX512BW_256 51805 EXCEPTIONS: AVX512-E4NF 51806 REAL_OPCODE: Y 51807 ATTRIBUTES: MASKOP_EVEX 51808 PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 51809 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 51810 IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 51811 } 51812 51813 { 51814 ICLASS: VPACKSSDW 51815 CPL: 3 51816 CATEGORY: AVX512 51817 EXTENSION: AVX512EVEX 51818 ISA_SET: AVX512BW_256 51819 EXCEPTIONS: AVX512-E4NF 51820 REAL_OPCODE: Y 51821 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51822 PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 51823 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 51824 IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 51825 } 51826 51827 51828 # EMITTING VPACKSSDW (VPACKSSDW-512-1) 51829 { 51830 ICLASS: VPACKSSDW 51831 CPL: 3 51832 CATEGORY: AVX512 51833 EXTENSION: AVX512EVEX 51834 ISA_SET: AVX512BW_512 51835 EXCEPTIONS: AVX512-E4NF 51836 REAL_OPCODE: Y 51837 ATTRIBUTES: MASKOP_EVEX 51838 PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 51839 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 51840 IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 51841 } 51842 51843 { 51844 ICLASS: VPACKSSDW 51845 CPL: 3 51846 CATEGORY: AVX512 51847 EXTENSION: AVX512EVEX 51848 ISA_SET: AVX512BW_512 51849 EXCEPTIONS: AVX512-E4NF 51850 REAL_OPCODE: Y 51851 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51852 PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 51853 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR 51854 IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 51855 } 51856 51857 51858 # EMITTING VPACKSSWB (VPACKSSWB-128-1) 51859 { 51860 ICLASS: VPACKSSWB 51861 CPL: 3 51862 CATEGORY: AVX512 51863 EXTENSION: AVX512EVEX 51864 ISA_SET: AVX512BW_128 51865 EXCEPTIONS: AVX512-E4NF 51866 REAL_OPCODE: Y 51867 ATTRIBUTES: MASKOP_EVEX 51868 PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 51869 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 51870 IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 51871 } 51872 51873 { 51874 ICLASS: VPACKSSWB 51875 CPL: 3 51876 CATEGORY: AVX512 51877 EXTENSION: AVX512EVEX 51878 ISA_SET: AVX512BW_128 51879 EXCEPTIONS: AVX512-E4NF 51880 REAL_OPCODE: Y 51881 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 51882 PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 51883 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 51884 IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 51885 } 51886 51887 51888 # EMITTING VPACKSSWB (VPACKSSWB-256-1) 51889 { 51890 ICLASS: VPACKSSWB 51891 CPL: 3 51892 CATEGORY: AVX512 51893 EXTENSION: AVX512EVEX 51894 ISA_SET: AVX512BW_256 51895 EXCEPTIONS: AVX512-E4NF 51896 REAL_OPCODE: Y 51897 ATTRIBUTES: MASKOP_EVEX 51898 PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 51899 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 51900 IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 51901 } 51902 51903 { 51904 ICLASS: VPACKSSWB 51905 CPL: 3 51906 CATEGORY: AVX512 51907 EXTENSION: AVX512EVEX 51908 ISA_SET: AVX512BW_256 51909 EXCEPTIONS: AVX512-E4NF 51910 REAL_OPCODE: Y 51911 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 51912 PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 51913 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 51914 IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 51915 } 51916 51917 51918 # EMITTING VPACKSSWB (VPACKSSWB-512-1) 51919 { 51920 ICLASS: VPACKSSWB 51921 CPL: 3 51922 CATEGORY: AVX512 51923 EXTENSION: AVX512EVEX 51924 ISA_SET: AVX512BW_512 51925 EXCEPTIONS: AVX512-E4NF 51926 REAL_OPCODE: Y 51927 ATTRIBUTES: MASKOP_EVEX 51928 PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 51929 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 51930 IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 51931 } 51932 51933 { 51934 ICLASS: VPACKSSWB 51935 CPL: 3 51936 CATEGORY: AVX512 51937 EXTENSION: AVX512EVEX 51938 ISA_SET: AVX512BW_512 51939 EXCEPTIONS: AVX512-E4NF 51940 REAL_OPCODE: Y 51941 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 51942 PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 51943 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 51944 IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 51945 } 51946 51947 51948 # EMITTING VPACKUSDW (VPACKUSDW-128-1) 51949 { 51950 ICLASS: VPACKUSDW 51951 CPL: 3 51952 CATEGORY: AVX512 51953 EXTENSION: AVX512EVEX 51954 ISA_SET: AVX512BW_128 51955 EXCEPTIONS: AVX512-E4NF 51956 REAL_OPCODE: Y 51957 ATTRIBUTES: MASKOP_EVEX 51958 PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 51959 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 51960 IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 51961 } 51962 51963 { 51964 ICLASS: VPACKUSDW 51965 CPL: 3 51966 CATEGORY: AVX512 51967 EXTENSION: AVX512EVEX 51968 ISA_SET: AVX512BW_128 51969 EXCEPTIONS: AVX512-E4NF 51970 REAL_OPCODE: Y 51971 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 51972 PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 51973 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 51974 IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 51975 } 51976 51977 51978 # EMITTING VPACKUSDW (VPACKUSDW-256-1) 51979 { 51980 ICLASS: VPACKUSDW 51981 CPL: 3 51982 CATEGORY: AVX512 51983 EXTENSION: AVX512EVEX 51984 ISA_SET: AVX512BW_256 51985 EXCEPTIONS: AVX512-E4NF 51986 REAL_OPCODE: Y 51987 ATTRIBUTES: MASKOP_EVEX 51988 PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 51989 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 51990 IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 51991 } 51992 51993 { 51994 ICLASS: VPACKUSDW 51995 CPL: 3 51996 CATEGORY: AVX512 51997 EXTENSION: AVX512EVEX 51998 ISA_SET: AVX512BW_256 51999 EXCEPTIONS: AVX512-E4NF 52000 REAL_OPCODE: Y 52001 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52002 PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 52003 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 52004 IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 52005 } 52006 52007 52008 # EMITTING VPACKUSDW (VPACKUSDW-512-1) 52009 { 52010 ICLASS: VPACKUSDW 52011 CPL: 3 52012 CATEGORY: AVX512 52013 EXTENSION: AVX512EVEX 52014 ISA_SET: AVX512BW_512 52015 EXCEPTIONS: AVX512-E4NF 52016 REAL_OPCODE: Y 52017 ATTRIBUTES: MASKOP_EVEX 52018 PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 52019 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 52020 IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 52021 } 52022 52023 { 52024 ICLASS: VPACKUSDW 52025 CPL: 3 52026 CATEGORY: AVX512 52027 EXTENSION: AVX512EVEX 52028 ISA_SET: AVX512BW_512 52029 EXCEPTIONS: AVX512-E4NF 52030 REAL_OPCODE: Y 52031 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52032 PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 52033 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 52034 IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 52035 } 52036 52037 52038 # EMITTING VPACKUSWB (VPACKUSWB-128-1) 52039 { 52040 ICLASS: VPACKUSWB 52041 CPL: 3 52042 CATEGORY: AVX512 52043 EXTENSION: AVX512EVEX 52044 ISA_SET: AVX512BW_128 52045 EXCEPTIONS: AVX512-E4NF 52046 REAL_OPCODE: Y 52047 ATTRIBUTES: MASKOP_EVEX 52048 PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 52049 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 52050 IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 52051 } 52052 52053 { 52054 ICLASS: VPACKUSWB 52055 CPL: 3 52056 CATEGORY: AVX512 52057 EXTENSION: AVX512EVEX 52058 ISA_SET: AVX512BW_128 52059 EXCEPTIONS: AVX512-E4NF 52060 REAL_OPCODE: Y 52061 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 52062 PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 52063 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 52064 IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 52065 } 52066 52067 52068 # EMITTING VPACKUSWB (VPACKUSWB-256-1) 52069 { 52070 ICLASS: VPACKUSWB 52071 CPL: 3 52072 CATEGORY: AVX512 52073 EXTENSION: AVX512EVEX 52074 ISA_SET: AVX512BW_256 52075 EXCEPTIONS: AVX512-E4NF 52076 REAL_OPCODE: Y 52077 ATTRIBUTES: MASKOP_EVEX 52078 PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 52079 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 52080 IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 52081 } 52082 52083 { 52084 ICLASS: VPACKUSWB 52085 CPL: 3 52086 CATEGORY: AVX512 52087 EXTENSION: AVX512EVEX 52088 ISA_SET: AVX512BW_256 52089 EXCEPTIONS: AVX512-E4NF 52090 REAL_OPCODE: Y 52091 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 52092 PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 52093 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 52094 IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 52095 } 52096 52097 52098 # EMITTING VPACKUSWB (VPACKUSWB-512-1) 52099 { 52100 ICLASS: VPACKUSWB 52101 CPL: 3 52102 CATEGORY: AVX512 52103 EXTENSION: AVX512EVEX 52104 ISA_SET: AVX512BW_512 52105 EXCEPTIONS: AVX512-E4NF 52106 REAL_OPCODE: Y 52107 ATTRIBUTES: MASKOP_EVEX 52108 PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 52109 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 52110 IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 52111 } 52112 52113 { 52114 ICLASS: VPACKUSWB 52115 CPL: 3 52116 CATEGORY: AVX512 52117 EXTENSION: AVX512EVEX 52118 ISA_SET: AVX512BW_512 52119 EXCEPTIONS: AVX512-E4NF 52120 REAL_OPCODE: Y 52121 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 52122 PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 52123 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 52124 IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 52125 } 52126 52127 52128 # EMITTING VPADDB (VPADDB-128-1) 52129 { 52130 ICLASS: VPADDB 52131 CPL: 3 52132 CATEGORY: AVX512 52133 EXTENSION: AVX512EVEX 52134 ISA_SET: AVX512BW_128 52135 EXCEPTIONS: AVX512-E4 52136 REAL_OPCODE: Y 52137 ATTRIBUTES: MASKOP_EVEX 52138 PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 52139 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 52140 IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 52141 } 52142 52143 { 52144 ICLASS: VPADDB 52145 CPL: 3 52146 CATEGORY: AVX512 52147 EXTENSION: AVX512EVEX 52148 ISA_SET: AVX512BW_128 52149 EXCEPTIONS: AVX512-E4 52150 REAL_OPCODE: Y 52151 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52152 PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 52153 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 52154 IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 52155 } 52156 52157 52158 # EMITTING VPADDB (VPADDB-256-1) 52159 { 52160 ICLASS: VPADDB 52161 CPL: 3 52162 CATEGORY: AVX512 52163 EXTENSION: AVX512EVEX 52164 ISA_SET: AVX512BW_256 52165 EXCEPTIONS: AVX512-E4 52166 REAL_OPCODE: Y 52167 ATTRIBUTES: MASKOP_EVEX 52168 PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 52169 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 52170 IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 52171 } 52172 52173 { 52174 ICLASS: VPADDB 52175 CPL: 3 52176 CATEGORY: AVX512 52177 EXTENSION: AVX512EVEX 52178 ISA_SET: AVX512BW_256 52179 EXCEPTIONS: AVX512-E4 52180 REAL_OPCODE: Y 52181 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52182 PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 52183 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 52184 IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 52185 } 52186 52187 52188 # EMITTING VPADDB (VPADDB-512-1) 52189 { 52190 ICLASS: VPADDB 52191 CPL: 3 52192 CATEGORY: AVX512 52193 EXTENSION: AVX512EVEX 52194 ISA_SET: AVX512BW_512 52195 EXCEPTIONS: AVX512-E4 52196 REAL_OPCODE: Y 52197 ATTRIBUTES: MASKOP_EVEX 52198 PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 52199 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 52200 IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 52201 } 52202 52203 { 52204 ICLASS: VPADDB 52205 CPL: 3 52206 CATEGORY: AVX512 52207 EXTENSION: AVX512EVEX 52208 ISA_SET: AVX512BW_512 52209 EXCEPTIONS: AVX512-E4 52210 REAL_OPCODE: Y 52211 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52212 PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 52213 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 52214 IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 52215 } 52216 52217 52218 # EMITTING VPADDD (VPADDD-128-1) 52219 { 52220 ICLASS: VPADDD 52221 CPL: 3 52222 CATEGORY: AVX512 52223 EXTENSION: AVX512EVEX 52224 ISA_SET: AVX512F_128 52225 EXCEPTIONS: AVX512-E4 52226 REAL_OPCODE: Y 52227 ATTRIBUTES: MASKOP_EVEX 52228 PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 52229 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 52230 IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 52231 } 52232 52233 { 52234 ICLASS: VPADDD 52235 CPL: 3 52236 CATEGORY: AVX512 52237 EXTENSION: AVX512EVEX 52238 ISA_SET: AVX512F_128 52239 EXCEPTIONS: AVX512-E4 52240 REAL_OPCODE: Y 52241 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52242 PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 52243 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 52244 IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 52245 } 52246 52247 52248 # EMITTING VPADDD (VPADDD-256-1) 52249 { 52250 ICLASS: VPADDD 52251 CPL: 3 52252 CATEGORY: AVX512 52253 EXTENSION: AVX512EVEX 52254 ISA_SET: AVX512F_256 52255 EXCEPTIONS: AVX512-E4 52256 REAL_OPCODE: Y 52257 ATTRIBUTES: MASKOP_EVEX 52258 PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 52259 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 52260 IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 52261 } 52262 52263 { 52264 ICLASS: VPADDD 52265 CPL: 3 52266 CATEGORY: AVX512 52267 EXTENSION: AVX512EVEX 52268 ISA_SET: AVX512F_256 52269 EXCEPTIONS: AVX512-E4 52270 REAL_OPCODE: Y 52271 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52272 PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 52273 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 52274 IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 52275 } 52276 52277 52278 # EMITTING VPADDQ (VPADDQ-128-1) 52279 { 52280 ICLASS: VPADDQ 52281 CPL: 3 52282 CATEGORY: AVX512 52283 EXTENSION: AVX512EVEX 52284 ISA_SET: AVX512F_128 52285 EXCEPTIONS: AVX512-E4 52286 REAL_OPCODE: Y 52287 ATTRIBUTES: MASKOP_EVEX 52288 PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 52289 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 52290 IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 52291 } 52292 52293 { 52294 ICLASS: VPADDQ 52295 CPL: 3 52296 CATEGORY: AVX512 52297 EXTENSION: AVX512EVEX 52298 ISA_SET: AVX512F_128 52299 EXCEPTIONS: AVX512-E4 52300 REAL_OPCODE: Y 52301 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52302 PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 52303 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 52304 IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 52305 } 52306 52307 52308 # EMITTING VPADDQ (VPADDQ-256-1) 52309 { 52310 ICLASS: VPADDQ 52311 CPL: 3 52312 CATEGORY: AVX512 52313 EXTENSION: AVX512EVEX 52314 ISA_SET: AVX512F_256 52315 EXCEPTIONS: AVX512-E4 52316 REAL_OPCODE: Y 52317 ATTRIBUTES: MASKOP_EVEX 52318 PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 52319 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 52320 IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 52321 } 52322 52323 { 52324 ICLASS: VPADDQ 52325 CPL: 3 52326 CATEGORY: AVX512 52327 EXTENSION: AVX512EVEX 52328 ISA_SET: AVX512F_256 52329 EXCEPTIONS: AVX512-E4 52330 REAL_OPCODE: Y 52331 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52332 PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 52333 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 52334 IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 52335 } 52336 52337 52338 # EMITTING VPADDSB (VPADDSB-128-1) 52339 { 52340 ICLASS: VPADDSB 52341 CPL: 3 52342 CATEGORY: AVX512 52343 EXTENSION: AVX512EVEX 52344 ISA_SET: AVX512BW_128 52345 EXCEPTIONS: AVX512-E4 52346 REAL_OPCODE: Y 52347 ATTRIBUTES: MASKOP_EVEX 52348 PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 52349 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 52350 IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 52351 } 52352 52353 { 52354 ICLASS: VPADDSB 52355 CPL: 3 52356 CATEGORY: AVX512 52357 EXTENSION: AVX512EVEX 52358 ISA_SET: AVX512BW_128 52359 EXCEPTIONS: AVX512-E4 52360 REAL_OPCODE: Y 52361 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52362 PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 52363 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 52364 IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 52365 } 52366 52367 52368 # EMITTING VPADDSB (VPADDSB-256-1) 52369 { 52370 ICLASS: VPADDSB 52371 CPL: 3 52372 CATEGORY: AVX512 52373 EXTENSION: AVX512EVEX 52374 ISA_SET: AVX512BW_256 52375 EXCEPTIONS: AVX512-E4 52376 REAL_OPCODE: Y 52377 ATTRIBUTES: MASKOP_EVEX 52378 PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 52379 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 52380 IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 52381 } 52382 52383 { 52384 ICLASS: VPADDSB 52385 CPL: 3 52386 CATEGORY: AVX512 52387 EXTENSION: AVX512EVEX 52388 ISA_SET: AVX512BW_256 52389 EXCEPTIONS: AVX512-E4 52390 REAL_OPCODE: Y 52391 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52392 PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 52393 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 52394 IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 52395 } 52396 52397 52398 # EMITTING VPADDSB (VPADDSB-512-1) 52399 { 52400 ICLASS: VPADDSB 52401 CPL: 3 52402 CATEGORY: AVX512 52403 EXTENSION: AVX512EVEX 52404 ISA_SET: AVX512BW_512 52405 EXCEPTIONS: AVX512-E4 52406 REAL_OPCODE: Y 52407 ATTRIBUTES: MASKOP_EVEX 52408 PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 52409 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 52410 IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 52411 } 52412 52413 { 52414 ICLASS: VPADDSB 52415 CPL: 3 52416 CATEGORY: AVX512 52417 EXTENSION: AVX512EVEX 52418 ISA_SET: AVX512BW_512 52419 EXCEPTIONS: AVX512-E4 52420 REAL_OPCODE: Y 52421 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52422 PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 52423 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 52424 IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 52425 } 52426 52427 52428 # EMITTING VPADDSW (VPADDSW-128-1) 52429 { 52430 ICLASS: VPADDSW 52431 CPL: 3 52432 CATEGORY: AVX512 52433 EXTENSION: AVX512EVEX 52434 ISA_SET: AVX512BW_128 52435 EXCEPTIONS: AVX512-E4 52436 REAL_OPCODE: Y 52437 ATTRIBUTES: MASKOP_EVEX 52438 PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 52439 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 52440 IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 52441 } 52442 52443 { 52444 ICLASS: VPADDSW 52445 CPL: 3 52446 CATEGORY: AVX512 52447 EXTENSION: AVX512EVEX 52448 ISA_SET: AVX512BW_128 52449 EXCEPTIONS: AVX512-E4 52450 REAL_OPCODE: Y 52451 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52452 PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 52453 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 52454 IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 52455 } 52456 52457 52458 # EMITTING VPADDSW (VPADDSW-256-1) 52459 { 52460 ICLASS: VPADDSW 52461 CPL: 3 52462 CATEGORY: AVX512 52463 EXTENSION: AVX512EVEX 52464 ISA_SET: AVX512BW_256 52465 EXCEPTIONS: AVX512-E4 52466 REAL_OPCODE: Y 52467 ATTRIBUTES: MASKOP_EVEX 52468 PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 52469 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 52470 IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 52471 } 52472 52473 { 52474 ICLASS: VPADDSW 52475 CPL: 3 52476 CATEGORY: AVX512 52477 EXTENSION: AVX512EVEX 52478 ISA_SET: AVX512BW_256 52479 EXCEPTIONS: AVX512-E4 52480 REAL_OPCODE: Y 52481 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52482 PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 52483 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 52484 IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 52485 } 52486 52487 52488 # EMITTING VPADDSW (VPADDSW-512-1) 52489 { 52490 ICLASS: VPADDSW 52491 CPL: 3 52492 CATEGORY: AVX512 52493 EXTENSION: AVX512EVEX 52494 ISA_SET: AVX512BW_512 52495 EXCEPTIONS: AVX512-E4 52496 REAL_OPCODE: Y 52497 ATTRIBUTES: MASKOP_EVEX 52498 PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 52499 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 52500 IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 52501 } 52502 52503 { 52504 ICLASS: VPADDSW 52505 CPL: 3 52506 CATEGORY: AVX512 52507 EXTENSION: AVX512EVEX 52508 ISA_SET: AVX512BW_512 52509 EXCEPTIONS: AVX512-E4 52510 REAL_OPCODE: Y 52511 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52512 PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 52513 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 52514 IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 52515 } 52516 52517 52518 # EMITTING VPADDUSB (VPADDUSB-128-1) 52519 { 52520 ICLASS: VPADDUSB 52521 CPL: 3 52522 CATEGORY: AVX512 52523 EXTENSION: AVX512EVEX 52524 ISA_SET: AVX512BW_128 52525 EXCEPTIONS: AVX512-E4 52526 REAL_OPCODE: Y 52527 ATTRIBUTES: MASKOP_EVEX 52528 PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 52529 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 52530 IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 52531 } 52532 52533 { 52534 ICLASS: VPADDUSB 52535 CPL: 3 52536 CATEGORY: AVX512 52537 EXTENSION: AVX512EVEX 52538 ISA_SET: AVX512BW_128 52539 EXCEPTIONS: AVX512-E4 52540 REAL_OPCODE: Y 52541 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52542 PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 52543 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 52544 IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 52545 } 52546 52547 52548 # EMITTING VPADDUSB (VPADDUSB-256-1) 52549 { 52550 ICLASS: VPADDUSB 52551 CPL: 3 52552 CATEGORY: AVX512 52553 EXTENSION: AVX512EVEX 52554 ISA_SET: AVX512BW_256 52555 EXCEPTIONS: AVX512-E4 52556 REAL_OPCODE: Y 52557 ATTRIBUTES: MASKOP_EVEX 52558 PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 52559 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 52560 IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 52561 } 52562 52563 { 52564 ICLASS: VPADDUSB 52565 CPL: 3 52566 CATEGORY: AVX512 52567 EXTENSION: AVX512EVEX 52568 ISA_SET: AVX512BW_256 52569 EXCEPTIONS: AVX512-E4 52570 REAL_OPCODE: Y 52571 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52572 PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 52573 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 52574 IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 52575 } 52576 52577 52578 # EMITTING VPADDUSB (VPADDUSB-512-1) 52579 { 52580 ICLASS: VPADDUSB 52581 CPL: 3 52582 CATEGORY: AVX512 52583 EXTENSION: AVX512EVEX 52584 ISA_SET: AVX512BW_512 52585 EXCEPTIONS: AVX512-E4 52586 REAL_OPCODE: Y 52587 ATTRIBUTES: MASKOP_EVEX 52588 PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 52589 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 52590 IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 52591 } 52592 52593 { 52594 ICLASS: VPADDUSB 52595 CPL: 3 52596 CATEGORY: AVX512 52597 EXTENSION: AVX512EVEX 52598 ISA_SET: AVX512BW_512 52599 EXCEPTIONS: AVX512-E4 52600 REAL_OPCODE: Y 52601 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52602 PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 52603 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 52604 IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 52605 } 52606 52607 52608 # EMITTING VPADDUSW (VPADDUSW-128-1) 52609 { 52610 ICLASS: VPADDUSW 52611 CPL: 3 52612 CATEGORY: AVX512 52613 EXTENSION: AVX512EVEX 52614 ISA_SET: AVX512BW_128 52615 EXCEPTIONS: AVX512-E4 52616 REAL_OPCODE: Y 52617 ATTRIBUTES: MASKOP_EVEX 52618 PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 52619 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 52620 IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 52621 } 52622 52623 { 52624 ICLASS: VPADDUSW 52625 CPL: 3 52626 CATEGORY: AVX512 52627 EXTENSION: AVX512EVEX 52628 ISA_SET: AVX512BW_128 52629 EXCEPTIONS: AVX512-E4 52630 REAL_OPCODE: Y 52631 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52632 PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 52633 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 52634 IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 52635 } 52636 52637 52638 # EMITTING VPADDUSW (VPADDUSW-256-1) 52639 { 52640 ICLASS: VPADDUSW 52641 CPL: 3 52642 CATEGORY: AVX512 52643 EXTENSION: AVX512EVEX 52644 ISA_SET: AVX512BW_256 52645 EXCEPTIONS: AVX512-E4 52646 REAL_OPCODE: Y 52647 ATTRIBUTES: MASKOP_EVEX 52648 PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 52649 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 52650 IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 52651 } 52652 52653 { 52654 ICLASS: VPADDUSW 52655 CPL: 3 52656 CATEGORY: AVX512 52657 EXTENSION: AVX512EVEX 52658 ISA_SET: AVX512BW_256 52659 EXCEPTIONS: AVX512-E4 52660 REAL_OPCODE: Y 52661 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52662 PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 52663 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 52664 IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 52665 } 52666 52667 52668 # EMITTING VPADDUSW (VPADDUSW-512-1) 52669 { 52670 ICLASS: VPADDUSW 52671 CPL: 3 52672 CATEGORY: AVX512 52673 EXTENSION: AVX512EVEX 52674 ISA_SET: AVX512BW_512 52675 EXCEPTIONS: AVX512-E4 52676 REAL_OPCODE: Y 52677 ATTRIBUTES: MASKOP_EVEX 52678 PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 52679 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 52680 IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 52681 } 52682 52683 { 52684 ICLASS: VPADDUSW 52685 CPL: 3 52686 CATEGORY: AVX512 52687 EXTENSION: AVX512EVEX 52688 ISA_SET: AVX512BW_512 52689 EXCEPTIONS: AVX512-E4 52690 REAL_OPCODE: Y 52691 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52692 PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 52693 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 52694 IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 52695 } 52696 52697 52698 # EMITTING VPADDW (VPADDW-128-1) 52699 { 52700 ICLASS: VPADDW 52701 CPL: 3 52702 CATEGORY: AVX512 52703 EXTENSION: AVX512EVEX 52704 ISA_SET: AVX512BW_128 52705 EXCEPTIONS: AVX512-E4 52706 REAL_OPCODE: Y 52707 ATTRIBUTES: MASKOP_EVEX 52708 PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 52709 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 52710 IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 52711 } 52712 52713 { 52714 ICLASS: VPADDW 52715 CPL: 3 52716 CATEGORY: AVX512 52717 EXTENSION: AVX512EVEX 52718 ISA_SET: AVX512BW_128 52719 EXCEPTIONS: AVX512-E4 52720 REAL_OPCODE: Y 52721 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52722 PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 52723 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 52724 IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 52725 } 52726 52727 52728 # EMITTING VPADDW (VPADDW-256-1) 52729 { 52730 ICLASS: VPADDW 52731 CPL: 3 52732 CATEGORY: AVX512 52733 EXTENSION: AVX512EVEX 52734 ISA_SET: AVX512BW_256 52735 EXCEPTIONS: AVX512-E4 52736 REAL_OPCODE: Y 52737 ATTRIBUTES: MASKOP_EVEX 52738 PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 52739 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 52740 IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 52741 } 52742 52743 { 52744 ICLASS: VPADDW 52745 CPL: 3 52746 CATEGORY: AVX512 52747 EXTENSION: AVX512EVEX 52748 ISA_SET: AVX512BW_256 52749 EXCEPTIONS: AVX512-E4 52750 REAL_OPCODE: Y 52751 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52752 PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 52753 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 52754 IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 52755 } 52756 52757 52758 # EMITTING VPADDW (VPADDW-512-1) 52759 { 52760 ICLASS: VPADDW 52761 CPL: 3 52762 CATEGORY: AVX512 52763 EXTENSION: AVX512EVEX 52764 ISA_SET: AVX512BW_512 52765 EXCEPTIONS: AVX512-E4 52766 REAL_OPCODE: Y 52767 ATTRIBUTES: MASKOP_EVEX 52768 PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 52769 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 52770 IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 52771 } 52772 52773 { 52774 ICLASS: VPADDW 52775 CPL: 3 52776 CATEGORY: AVX512 52777 EXTENSION: AVX512EVEX 52778 ISA_SET: AVX512BW_512 52779 EXCEPTIONS: AVX512-E4 52780 REAL_OPCODE: Y 52781 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 52782 PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 52783 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 52784 IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 52785 } 52786 52787 52788 # EMITTING VPALIGNR (VPALIGNR-128-1) 52789 { 52790 ICLASS: VPALIGNR 52791 CPL: 3 52792 CATEGORY: AVX512 52793 EXTENSION: AVX512EVEX 52794 ISA_SET: AVX512BW_128 52795 EXCEPTIONS: AVX512-E4NF 52796 REAL_OPCODE: Y 52797 ATTRIBUTES: MASKOP_EVEX 52798 PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8() 52799 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b 52800 IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 52801 } 52802 52803 { 52804 ICLASS: VPALIGNR 52805 CPL: 3 52806 CATEGORY: AVX512 52807 EXTENSION: AVX512EVEX 52808 ISA_SET: AVX512BW_128 52809 EXCEPTIONS: AVX512-E4NF 52810 REAL_OPCODE: Y 52811 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 52812 PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() 52813 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b 52814 IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 52815 } 52816 52817 52818 # EMITTING VPALIGNR (VPALIGNR-256-1) 52819 { 52820 ICLASS: VPALIGNR 52821 CPL: 3 52822 CATEGORY: AVX512 52823 EXTENSION: AVX512EVEX 52824 ISA_SET: AVX512BW_256 52825 EXCEPTIONS: AVX512-E4NF 52826 REAL_OPCODE: Y 52827 ATTRIBUTES: MASKOP_EVEX 52828 PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8() 52829 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b 52830 IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 52831 } 52832 52833 { 52834 ICLASS: VPALIGNR 52835 CPL: 3 52836 CATEGORY: AVX512 52837 EXTENSION: AVX512EVEX 52838 ISA_SET: AVX512BW_256 52839 EXCEPTIONS: AVX512-E4NF 52840 REAL_OPCODE: Y 52841 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 52842 PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() 52843 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b 52844 IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 52845 } 52846 52847 52848 # EMITTING VPALIGNR (VPALIGNR-512-1) 52849 { 52850 ICLASS: VPALIGNR 52851 CPL: 3 52852 CATEGORY: AVX512 52853 EXTENSION: AVX512EVEX 52854 ISA_SET: AVX512BW_512 52855 EXCEPTIONS: AVX512-E4NF 52856 REAL_OPCODE: Y 52857 ATTRIBUTES: MASKOP_EVEX 52858 PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8() 52859 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b 52860 IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 52861 } 52862 52863 { 52864 ICLASS: VPALIGNR 52865 CPL: 3 52866 CATEGORY: AVX512 52867 EXTENSION: AVX512EVEX 52868 ISA_SET: AVX512BW_512 52869 EXCEPTIONS: AVX512-E4NF 52870 REAL_OPCODE: Y 52871 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 52872 PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() 52873 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b 52874 IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 52875 } 52876 52877 52878 # EMITTING VPANDD (VPANDD-128-1) 52879 { 52880 ICLASS: VPANDD 52881 CPL: 3 52882 CATEGORY: LOGICAL 52883 EXTENSION: AVX512EVEX 52884 ISA_SET: AVX512F_128 52885 EXCEPTIONS: AVX512-E4 52886 REAL_OPCODE: Y 52887 ATTRIBUTES: MASKOP_EVEX 52888 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 52889 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 52890 IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 52891 } 52892 52893 { 52894 ICLASS: VPANDD 52895 CPL: 3 52896 CATEGORY: LOGICAL 52897 EXTENSION: AVX512EVEX 52898 ISA_SET: AVX512F_128 52899 EXCEPTIONS: AVX512-E4 52900 REAL_OPCODE: Y 52901 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52902 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 52903 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 52904 IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 52905 } 52906 52907 52908 # EMITTING VPANDD (VPANDD-256-1) 52909 { 52910 ICLASS: VPANDD 52911 CPL: 3 52912 CATEGORY: LOGICAL 52913 EXTENSION: AVX512EVEX 52914 ISA_SET: AVX512F_256 52915 EXCEPTIONS: AVX512-E4 52916 REAL_OPCODE: Y 52917 ATTRIBUTES: MASKOP_EVEX 52918 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 52919 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 52920 IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 52921 } 52922 52923 { 52924 ICLASS: VPANDD 52925 CPL: 3 52926 CATEGORY: LOGICAL 52927 EXTENSION: AVX512EVEX 52928 ISA_SET: AVX512F_256 52929 EXCEPTIONS: AVX512-E4 52930 REAL_OPCODE: Y 52931 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52932 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 52933 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 52934 IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 52935 } 52936 52937 52938 # EMITTING VPANDND (VPANDND-128-1) 52939 { 52940 ICLASS: VPANDND 52941 CPL: 3 52942 CATEGORY: LOGICAL 52943 EXTENSION: AVX512EVEX 52944 ISA_SET: AVX512F_128 52945 EXCEPTIONS: AVX512-E4 52946 REAL_OPCODE: Y 52947 ATTRIBUTES: MASKOP_EVEX 52948 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 52949 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 52950 IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 52951 } 52952 52953 { 52954 ICLASS: VPANDND 52955 CPL: 3 52956 CATEGORY: LOGICAL 52957 EXTENSION: AVX512EVEX 52958 ISA_SET: AVX512F_128 52959 EXCEPTIONS: AVX512-E4 52960 REAL_OPCODE: Y 52961 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52962 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 52963 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 52964 IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 52965 } 52966 52967 52968 # EMITTING VPANDND (VPANDND-256-1) 52969 { 52970 ICLASS: VPANDND 52971 CPL: 3 52972 CATEGORY: LOGICAL 52973 EXTENSION: AVX512EVEX 52974 ISA_SET: AVX512F_256 52975 EXCEPTIONS: AVX512-E4 52976 REAL_OPCODE: Y 52977 ATTRIBUTES: MASKOP_EVEX 52978 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 52979 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 52980 IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 52981 } 52982 52983 { 52984 ICLASS: VPANDND 52985 CPL: 3 52986 CATEGORY: LOGICAL 52987 EXTENSION: AVX512EVEX 52988 ISA_SET: AVX512F_256 52989 EXCEPTIONS: AVX512-E4 52990 REAL_OPCODE: Y 52991 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52992 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 52993 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 52994 IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 52995 } 52996 52997 52998 # EMITTING VPANDNQ (VPANDNQ-128-1) 52999 { 53000 ICLASS: VPANDNQ 53001 CPL: 3 53002 CATEGORY: LOGICAL 53003 EXTENSION: AVX512EVEX 53004 ISA_SET: AVX512F_128 53005 EXCEPTIONS: AVX512-E4 53006 REAL_OPCODE: Y 53007 ATTRIBUTES: MASKOP_EVEX 53008 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 53009 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 53010 IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 53011 } 53012 53013 { 53014 ICLASS: VPANDNQ 53015 CPL: 3 53016 CATEGORY: LOGICAL 53017 EXTENSION: AVX512EVEX 53018 ISA_SET: AVX512F_128 53019 EXCEPTIONS: AVX512-E4 53020 REAL_OPCODE: Y 53021 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 53022 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 53023 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 53024 IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 53025 } 53026 53027 53028 # EMITTING VPANDNQ (VPANDNQ-256-1) 53029 { 53030 ICLASS: VPANDNQ 53031 CPL: 3 53032 CATEGORY: LOGICAL 53033 EXTENSION: AVX512EVEX 53034 ISA_SET: AVX512F_256 53035 EXCEPTIONS: AVX512-E4 53036 REAL_OPCODE: Y 53037 ATTRIBUTES: MASKOP_EVEX 53038 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 53039 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 53040 IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 53041 } 53042 53043 { 53044 ICLASS: VPANDNQ 53045 CPL: 3 53046 CATEGORY: LOGICAL 53047 EXTENSION: AVX512EVEX 53048 ISA_SET: AVX512F_256 53049 EXCEPTIONS: AVX512-E4 53050 REAL_OPCODE: Y 53051 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 53052 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 53053 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 53054 IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 53055 } 53056 53057 53058 # EMITTING VPANDQ (VPANDQ-128-1) 53059 { 53060 ICLASS: VPANDQ 53061 CPL: 3 53062 CATEGORY: LOGICAL 53063 EXTENSION: AVX512EVEX 53064 ISA_SET: AVX512F_128 53065 EXCEPTIONS: AVX512-E4 53066 REAL_OPCODE: Y 53067 ATTRIBUTES: MASKOP_EVEX 53068 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 53069 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 53070 IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 53071 } 53072 53073 { 53074 ICLASS: VPANDQ 53075 CPL: 3 53076 CATEGORY: LOGICAL 53077 EXTENSION: AVX512EVEX 53078 ISA_SET: AVX512F_128 53079 EXCEPTIONS: AVX512-E4 53080 REAL_OPCODE: Y 53081 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 53082 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 53083 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 53084 IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 53085 } 53086 53087 53088 # EMITTING VPANDQ (VPANDQ-256-1) 53089 { 53090 ICLASS: VPANDQ 53091 CPL: 3 53092 CATEGORY: LOGICAL 53093 EXTENSION: AVX512EVEX 53094 ISA_SET: AVX512F_256 53095 EXCEPTIONS: AVX512-E4 53096 REAL_OPCODE: Y 53097 ATTRIBUTES: MASKOP_EVEX 53098 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 53099 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 53100 IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 53101 } 53102 53103 { 53104 ICLASS: VPANDQ 53105 CPL: 3 53106 CATEGORY: LOGICAL 53107 EXTENSION: AVX512EVEX 53108 ISA_SET: AVX512F_256 53109 EXCEPTIONS: AVX512-E4 53110 REAL_OPCODE: Y 53111 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 53112 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 53113 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 53114 IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 53115 } 53116 53117 53118 # EMITTING VPAVGB (VPAVGB-128-1) 53119 { 53120 ICLASS: VPAVGB 53121 CPL: 3 53122 CATEGORY: AVX512 53123 EXTENSION: AVX512EVEX 53124 ISA_SET: AVX512BW_128 53125 EXCEPTIONS: AVX512-E4 53126 REAL_OPCODE: Y 53127 ATTRIBUTES: MASKOP_EVEX 53128 PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 53129 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 53130 IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 53131 } 53132 53133 { 53134 ICLASS: VPAVGB 53135 CPL: 3 53136 CATEGORY: AVX512 53137 EXTENSION: AVX512EVEX 53138 ISA_SET: AVX512BW_128 53139 EXCEPTIONS: AVX512-E4 53140 REAL_OPCODE: Y 53141 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 53142 PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 53143 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 53144 IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 53145 } 53146 53147 53148 # EMITTING VPAVGB (VPAVGB-256-1) 53149 { 53150 ICLASS: VPAVGB 53151 CPL: 3 53152 CATEGORY: AVX512 53153 EXTENSION: AVX512EVEX 53154 ISA_SET: AVX512BW_256 53155 EXCEPTIONS: AVX512-E4 53156 REAL_OPCODE: Y 53157 ATTRIBUTES: MASKOP_EVEX 53158 PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 53159 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 53160 IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 53161 } 53162 53163 { 53164 ICLASS: VPAVGB 53165 CPL: 3 53166 CATEGORY: AVX512 53167 EXTENSION: AVX512EVEX 53168 ISA_SET: AVX512BW_256 53169 EXCEPTIONS: AVX512-E4 53170 REAL_OPCODE: Y 53171 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 53172 PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 53173 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 53174 IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 53175 } 53176 53177 53178 # EMITTING VPAVGB (VPAVGB-512-1) 53179 { 53180 ICLASS: VPAVGB 53181 CPL: 3 53182 CATEGORY: AVX512 53183 EXTENSION: AVX512EVEX 53184 ISA_SET: AVX512BW_512 53185 EXCEPTIONS: AVX512-E4 53186 REAL_OPCODE: Y 53187 ATTRIBUTES: MASKOP_EVEX 53188 PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 53189 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 53190 IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 53191 } 53192 53193 { 53194 ICLASS: VPAVGB 53195 CPL: 3 53196 CATEGORY: AVX512 53197 EXTENSION: AVX512EVEX 53198 ISA_SET: AVX512BW_512 53199 EXCEPTIONS: AVX512-E4 53200 REAL_OPCODE: Y 53201 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 53202 PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 53203 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 53204 IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 53205 } 53206 53207 53208 # EMITTING VPAVGW (VPAVGW-128-1) 53209 { 53210 ICLASS: VPAVGW 53211 CPL: 3 53212 CATEGORY: AVX512 53213 EXTENSION: AVX512EVEX 53214 ISA_SET: AVX512BW_128 53215 EXCEPTIONS: AVX512-E4 53216 REAL_OPCODE: Y 53217 ATTRIBUTES: MASKOP_EVEX 53218 PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 53219 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 53220 IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 53221 } 53222 53223 { 53224 ICLASS: VPAVGW 53225 CPL: 3 53226 CATEGORY: AVX512 53227 EXTENSION: AVX512EVEX 53228 ISA_SET: AVX512BW_128 53229 EXCEPTIONS: AVX512-E4 53230 REAL_OPCODE: Y 53231 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 53232 PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 53233 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 53234 IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 53235 } 53236 53237 53238 # EMITTING VPAVGW (VPAVGW-256-1) 53239 { 53240 ICLASS: VPAVGW 53241 CPL: 3 53242 CATEGORY: AVX512 53243 EXTENSION: AVX512EVEX 53244 ISA_SET: AVX512BW_256 53245 EXCEPTIONS: AVX512-E4 53246 REAL_OPCODE: Y 53247 ATTRIBUTES: MASKOP_EVEX 53248 PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 53249 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 53250 IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 53251 } 53252 53253 { 53254 ICLASS: VPAVGW 53255 CPL: 3 53256 CATEGORY: AVX512 53257 EXTENSION: AVX512EVEX 53258 ISA_SET: AVX512BW_256 53259 EXCEPTIONS: AVX512-E4 53260 REAL_OPCODE: Y 53261 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 53262 PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 53263 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 53264 IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 53265 } 53266 53267 53268 # EMITTING VPAVGW (VPAVGW-512-1) 53269 { 53270 ICLASS: VPAVGW 53271 CPL: 3 53272 CATEGORY: AVX512 53273 EXTENSION: AVX512EVEX 53274 ISA_SET: AVX512BW_512 53275 EXCEPTIONS: AVX512-E4 53276 REAL_OPCODE: Y 53277 ATTRIBUTES: MASKOP_EVEX 53278 PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 53279 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 53280 IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 53281 } 53282 53283 { 53284 ICLASS: VPAVGW 53285 CPL: 3 53286 CATEGORY: AVX512 53287 EXTENSION: AVX512EVEX 53288 ISA_SET: AVX512BW_512 53289 EXCEPTIONS: AVX512-E4 53290 REAL_OPCODE: Y 53291 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 53292 PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 53293 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 53294 IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 53295 } 53296 53297 53298 # EMITTING VPBLENDMB (VPBLENDMB-128-1) 53299 { 53300 ICLASS: VPBLENDMB 53301 CPL: 3 53302 CATEGORY: BLEND 53303 EXTENSION: AVX512EVEX 53304 ISA_SET: AVX512BW_128 53305 EXCEPTIONS: AVX512-E4 53306 REAL_OPCODE: Y 53307 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 53308 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 53309 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 53310 IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 53311 } 53312 53313 { 53314 ICLASS: VPBLENDMB 53315 CPL: 3 53316 CATEGORY: BLEND 53317 EXTENSION: AVX512EVEX 53318 ISA_SET: AVX512BW_128 53319 EXCEPTIONS: AVX512-E4 53320 REAL_OPCODE: Y 53321 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM 53322 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() 53323 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 53324 IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 53325 } 53326 53327 53328 # EMITTING VPBLENDMB (VPBLENDMB-256-1) 53329 { 53330 ICLASS: VPBLENDMB 53331 CPL: 3 53332 CATEGORY: BLEND 53333 EXTENSION: AVX512EVEX 53334 ISA_SET: AVX512BW_256 53335 EXCEPTIONS: AVX512-E4 53336 REAL_OPCODE: Y 53337 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 53338 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 53339 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 53340 IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 53341 } 53342 53343 { 53344 ICLASS: VPBLENDMB 53345 CPL: 3 53346 CATEGORY: BLEND 53347 EXTENSION: AVX512EVEX 53348 ISA_SET: AVX512BW_256 53349 EXCEPTIONS: AVX512-E4 53350 REAL_OPCODE: Y 53351 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM 53352 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() 53353 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 53354 IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 53355 } 53356 53357 53358 # EMITTING VPBLENDMB (VPBLENDMB-512-1) 53359 { 53360 ICLASS: VPBLENDMB 53361 CPL: 3 53362 CATEGORY: BLEND 53363 EXTENSION: AVX512EVEX 53364 ISA_SET: AVX512BW_512 53365 EXCEPTIONS: AVX512-E4 53366 REAL_OPCODE: Y 53367 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 53368 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 53369 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 53370 IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 53371 } 53372 53373 { 53374 ICLASS: VPBLENDMB 53375 CPL: 3 53376 CATEGORY: BLEND 53377 EXTENSION: AVX512EVEX 53378 ISA_SET: AVX512BW_512 53379 EXCEPTIONS: AVX512-E4 53380 REAL_OPCODE: Y 53381 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM 53382 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() 53383 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 53384 IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 53385 } 53386 53387 53388 # EMITTING VPBLENDMD (VPBLENDMD-128-1) 53389 { 53390 ICLASS: VPBLENDMD 53391 CPL: 3 53392 CATEGORY: BLEND 53393 EXTENSION: AVX512EVEX 53394 ISA_SET: AVX512F_128 53395 EXCEPTIONS: AVX512-E4 53396 REAL_OPCODE: Y 53397 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 53398 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 53399 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 53400 IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 53401 } 53402 53403 { 53404 ICLASS: VPBLENDMD 53405 CPL: 3 53406 CATEGORY: BLEND 53407 EXTENSION: AVX512EVEX 53408 ISA_SET: AVX512F_128 53409 EXCEPTIONS: AVX512-E4 53410 REAL_OPCODE: Y 53411 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 53412 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 53413 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 53414 IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 53415 } 53416 53417 53418 # EMITTING VPBLENDMD (VPBLENDMD-256-1) 53419 { 53420 ICLASS: VPBLENDMD 53421 CPL: 3 53422 CATEGORY: BLEND 53423 EXTENSION: AVX512EVEX 53424 ISA_SET: AVX512F_256 53425 EXCEPTIONS: AVX512-E4 53426 REAL_OPCODE: Y 53427 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 53428 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 53429 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 53430 IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 53431 } 53432 53433 { 53434 ICLASS: VPBLENDMD 53435 CPL: 3 53436 CATEGORY: BLEND 53437 EXTENSION: AVX512EVEX 53438 ISA_SET: AVX512F_256 53439 EXCEPTIONS: AVX512-E4 53440 REAL_OPCODE: Y 53441 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 53442 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 53443 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 53444 IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 53445 } 53446 53447 53448 # EMITTING VPBLENDMQ (VPBLENDMQ-128-1) 53449 { 53450 ICLASS: VPBLENDMQ 53451 CPL: 3 53452 CATEGORY: BLEND 53453 EXTENSION: AVX512EVEX 53454 ISA_SET: AVX512F_128 53455 EXCEPTIONS: AVX512-E4 53456 REAL_OPCODE: Y 53457 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 53458 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 53459 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 53460 IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 53461 } 53462 53463 { 53464 ICLASS: VPBLENDMQ 53465 CPL: 3 53466 CATEGORY: BLEND 53467 EXTENSION: AVX512EVEX 53468 ISA_SET: AVX512F_128 53469 EXCEPTIONS: AVX512-E4 53470 REAL_OPCODE: Y 53471 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 53472 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 53473 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 53474 IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 53475 } 53476 53477 53478 # EMITTING VPBLENDMQ (VPBLENDMQ-256-1) 53479 { 53480 ICLASS: VPBLENDMQ 53481 CPL: 3 53482 CATEGORY: BLEND 53483 EXTENSION: AVX512EVEX 53484 ISA_SET: AVX512F_256 53485 EXCEPTIONS: AVX512-E4 53486 REAL_OPCODE: Y 53487 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 53488 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 53489 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 53490 IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 53491 } 53492 53493 { 53494 ICLASS: VPBLENDMQ 53495 CPL: 3 53496 CATEGORY: BLEND 53497 EXTENSION: AVX512EVEX 53498 ISA_SET: AVX512F_256 53499 EXCEPTIONS: AVX512-E4 53500 REAL_OPCODE: Y 53501 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULL BROADCAST_ENABLED 53502 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 53503 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 53504 IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 53505 } 53506 53507 53508 # EMITTING VPBLENDMW (VPBLENDMW-128-1) 53509 { 53510 ICLASS: VPBLENDMW 53511 CPL: 3 53512 CATEGORY: BLEND 53513 EXTENSION: AVX512EVEX 53514 ISA_SET: AVX512BW_128 53515 EXCEPTIONS: AVX512-E4 53516 REAL_OPCODE: Y 53517 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 53518 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 53519 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 53520 IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 53521 } 53522 53523 { 53524 ICLASS: VPBLENDMW 53525 CPL: 3 53526 CATEGORY: BLEND 53527 EXTENSION: AVX512EVEX 53528 ISA_SET: AVX512BW_128 53529 EXCEPTIONS: AVX512-E4 53530 REAL_OPCODE: Y 53531 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM 53532 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 53533 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 53534 IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 53535 } 53536 53537 53538 # EMITTING VPBLENDMW (VPBLENDMW-256-1) 53539 { 53540 ICLASS: VPBLENDMW 53541 CPL: 3 53542 CATEGORY: BLEND 53543 EXTENSION: AVX512EVEX 53544 ISA_SET: AVX512BW_256 53545 EXCEPTIONS: AVX512-E4 53546 REAL_OPCODE: Y 53547 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 53548 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 53549 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 53550 IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 53551 } 53552 53553 { 53554 ICLASS: VPBLENDMW 53555 CPL: 3 53556 CATEGORY: BLEND 53557 EXTENSION: AVX512EVEX 53558 ISA_SET: AVX512BW_256 53559 EXCEPTIONS: AVX512-E4 53560 REAL_OPCODE: Y 53561 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM 53562 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 53563 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 53564 IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 53565 } 53566 53567 53568 # EMITTING VPBLENDMW (VPBLENDMW-512-1) 53569 { 53570 ICLASS: VPBLENDMW 53571 CPL: 3 53572 CATEGORY: BLEND 53573 EXTENSION: AVX512EVEX 53574 ISA_SET: AVX512BW_512 53575 EXCEPTIONS: AVX512-E4 53576 REAL_OPCODE: Y 53577 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 53578 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 53579 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 53580 IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 53581 } 53582 53583 { 53584 ICLASS: VPBLENDMW 53585 CPL: 3 53586 CATEGORY: BLEND 53587 EXTENSION: AVX512EVEX 53588 ISA_SET: AVX512BW_512 53589 EXCEPTIONS: AVX512-E4 53590 REAL_OPCODE: Y 53591 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MASK_AS_CONTROL DISP8_FULLMEM 53592 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 53593 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 53594 IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 53595 } 53596 53597 53598 # EMITTING VPBROADCASTB (VPBROADCASTB-128-1) 53599 { 53600 ICLASS: VPBROADCASTB 53601 CPL: 3 53602 CATEGORY: BROADCAST 53603 EXTENSION: AVX512EVEX 53604 ISA_SET: AVX512BW_128 53605 EXCEPTIONS: AVX512-E6 53606 REAL_OPCODE: Y 53607 ATTRIBUTES: MASKOP_EVEX 53608 PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 53609 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO16_8 53610 IFORM: VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 53611 } 53612 53613 { 53614 ICLASS: VPBROADCASTB 53615 CPL: 3 53616 CATEGORY: BROADCAST 53617 EXTENSION: AVX512EVEX 53618 ISA_SET: AVX512BW_128 53619 EXCEPTIONS: AVX512-E6 53620 REAL_OPCODE: Y 53621 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE 53622 PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() 53623 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 53624 IFORM: VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 53625 } 53626 53627 53628 # EMITTING VPBROADCASTB (VPBROADCASTB-128-2) 53629 { 53630 ICLASS: VPBROADCASTB 53631 CPL: 3 53632 CATEGORY: BROADCAST 53633 EXTENSION: AVX512EVEX 53634 ISA_SET: AVX512BW_128 53635 EXCEPTIONS: AVX512-E7NM 53636 REAL_OPCODE: Y 53637 ATTRIBUTES: MASKOP_EVEX 53638 PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 53639 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO16_8 53640 IFORM: VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 53641 } 53642 53643 53644 # EMITTING VPBROADCASTB (VPBROADCASTB-256-1) 53645 { 53646 ICLASS: VPBROADCASTB 53647 CPL: 3 53648 CATEGORY: BROADCAST 53649 EXTENSION: AVX512EVEX 53650 ISA_SET: AVX512BW_256 53651 EXCEPTIONS: AVX512-E6 53652 REAL_OPCODE: Y 53653 ATTRIBUTES: MASKOP_EVEX 53654 PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 53655 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO32_8 53656 IFORM: VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 53657 } 53658 53659 { 53660 ICLASS: VPBROADCASTB 53661 CPL: 3 53662 CATEGORY: BROADCAST 53663 EXTENSION: AVX512EVEX 53664 ISA_SET: AVX512BW_256 53665 EXCEPTIONS: AVX512-E6 53666 REAL_OPCODE: Y 53667 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE 53668 PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() 53669 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 53670 IFORM: VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 53671 } 53672 53673 53674 # EMITTING VPBROADCASTB (VPBROADCASTB-256-2) 53675 { 53676 ICLASS: VPBROADCASTB 53677 CPL: 3 53678 CATEGORY: BROADCAST 53679 EXTENSION: AVX512EVEX 53680 ISA_SET: AVX512BW_256 53681 EXCEPTIONS: AVX512-E7NM 53682 REAL_OPCODE: Y 53683 ATTRIBUTES: MASKOP_EVEX 53684 PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 53685 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO32_8 53686 IFORM: VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 53687 } 53688 53689 53690 # EMITTING VPBROADCASTB (VPBROADCASTB-512-1) 53691 { 53692 ICLASS: VPBROADCASTB 53693 CPL: 3 53694 CATEGORY: BROADCAST 53695 EXTENSION: AVX512EVEX 53696 ISA_SET: AVX512BW_512 53697 EXCEPTIONS: AVX512-E6 53698 REAL_OPCODE: Y 53699 ATTRIBUTES: MASKOP_EVEX 53700 PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 53701 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO64_8 53702 IFORM: VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 53703 } 53704 53705 { 53706 ICLASS: VPBROADCASTB 53707 CPL: 3 53708 CATEGORY: BROADCAST 53709 EXTENSION: AVX512EVEX 53710 ISA_SET: AVX512BW_512 53711 EXCEPTIONS: AVX512-E6 53712 REAL_OPCODE: Y 53713 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE 53714 PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() 53715 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO64_8 53716 IFORM: VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 53717 } 53718 53719 53720 # EMITTING VPBROADCASTB (VPBROADCASTB-512-2) 53721 { 53722 ICLASS: VPBROADCASTB 53723 CPL: 3 53724 CATEGORY: BROADCAST 53725 EXTENSION: AVX512EVEX 53726 ISA_SET: AVX512BW_512 53727 EXCEPTIONS: AVX512-E7NM 53728 REAL_OPCODE: Y 53729 ATTRIBUTES: MASKOP_EVEX 53730 PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 53731 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO64_8 53732 IFORM: VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 53733 } 53734 53735 53736 # EMITTING VPBROADCASTD (VPBROADCASTD-128-1) 53737 { 53738 ICLASS: VPBROADCASTD 53739 CPL: 3 53740 CATEGORY: BROADCAST 53741 EXTENSION: AVX512EVEX 53742 ISA_SET: AVX512F_128 53743 EXCEPTIONS: AVX512-E6 53744 REAL_OPCODE: Y 53745 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 53746 PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 53747 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 53748 IFORM: VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 53749 } 53750 53751 53752 # EMITTING VPBROADCASTD (VPBROADCASTD-128-2) 53753 { 53754 ICLASS: VPBROADCASTD 53755 CPL: 3 53756 CATEGORY: BROADCAST 53757 EXTENSION: AVX512EVEX 53758 ISA_SET: AVX512F_128 53759 EXCEPTIONS: AVX512-E6 53760 REAL_OPCODE: Y 53761 ATTRIBUTES: MASKOP_EVEX 53762 PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 53763 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO4_32 53764 IFORM: VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 53765 } 53766 53767 53768 # EMITTING VPBROADCASTD (VPBROADCASTD-128-3) 53769 { 53770 ICLASS: VPBROADCASTD 53771 CPL: 3 53772 CATEGORY: BROADCAST 53773 EXTENSION: AVX512EVEX 53774 ISA_SET: AVX512F_128 53775 EXCEPTIONS: AVX512-E7NM 53776 REAL_OPCODE: Y 53777 ATTRIBUTES: MASKOP_EVEX 53778 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 53779 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 53780 IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 53781 } 53782 53783 53784 # EMITTING VPBROADCASTD (VPBROADCASTD-256-1) 53785 { 53786 ICLASS: VPBROADCASTD 53787 CPL: 3 53788 CATEGORY: BROADCAST 53789 EXTENSION: AVX512EVEX 53790 ISA_SET: AVX512F_256 53791 EXCEPTIONS: AVX512-E6 53792 REAL_OPCODE: Y 53793 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 53794 PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 53795 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 53796 IFORM: VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 53797 } 53798 53799 53800 # EMITTING VPBROADCASTD (VPBROADCASTD-256-2) 53801 { 53802 ICLASS: VPBROADCASTD 53803 CPL: 3 53804 CATEGORY: BROADCAST 53805 EXTENSION: AVX512EVEX 53806 ISA_SET: AVX512F_256 53807 EXCEPTIONS: AVX512-E6 53808 REAL_OPCODE: Y 53809 ATTRIBUTES: MASKOP_EVEX 53810 PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 53811 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO8_32 53812 IFORM: VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 53813 } 53814 53815 53816 # EMITTING VPBROADCASTD (VPBROADCASTD-256-3) 53817 { 53818 ICLASS: VPBROADCASTD 53819 CPL: 3 53820 CATEGORY: BROADCAST 53821 EXTENSION: AVX512EVEX 53822 ISA_SET: AVX512F_256 53823 EXCEPTIONS: AVX512-E7NM 53824 REAL_OPCODE: Y 53825 ATTRIBUTES: MASKOP_EVEX 53826 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 53827 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 53828 IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 53829 } 53830 53831 53832 # EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-128-1) 53833 { 53834 ICLASS: VPBROADCASTMB2Q 53835 CPL: 3 53836 CATEGORY: BROADCAST 53837 EXTENSION: AVX512EVEX 53838 ISA_SET: AVX512CD_128 53839 EXCEPTIONS: AVX512-E6NF 53840 REAL_OPCODE: Y 53841 PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 53842 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO2_8 53843 IFORM: VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 53844 } 53845 53846 53847 # EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-256-1) 53848 { 53849 ICLASS: VPBROADCASTMB2Q 53850 CPL: 3 53851 CATEGORY: BROADCAST 53852 EXTENSION: AVX512EVEX 53853 ISA_SET: AVX512CD_256 53854 EXCEPTIONS: AVX512-E6NF 53855 REAL_OPCODE: Y 53856 PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 53857 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO4_8 53858 IFORM: VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 53859 } 53860 53861 53862 # EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-128-1) 53863 { 53864 ICLASS: VPBROADCASTMW2D 53865 CPL: 3 53866 CATEGORY: BROADCAST 53867 EXTENSION: AVX512EVEX 53868 ISA_SET: AVX512CD_128 53869 EXCEPTIONS: AVX512-E6NF 53870 REAL_OPCODE: Y 53871 PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 53872 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO4_16 53873 IFORM: VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 53874 } 53875 53876 53877 # EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-256-1) 53878 { 53879 ICLASS: VPBROADCASTMW2D 53880 CPL: 3 53881 CATEGORY: BROADCAST 53882 EXTENSION: AVX512EVEX 53883 ISA_SET: AVX512CD_256 53884 EXCEPTIONS: AVX512-E6NF 53885 REAL_OPCODE: Y 53886 PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 53887 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO8_16 53888 IFORM: VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 53889 } 53890 53891 53892 # EMITTING VPBROADCASTQ (VPBROADCASTQ-128-1) 53893 { 53894 ICLASS: VPBROADCASTQ 53895 CPL: 3 53896 CATEGORY: BROADCAST 53897 EXTENSION: AVX512EVEX 53898 ISA_SET: AVX512F_128 53899 EXCEPTIONS: AVX512-E6 53900 REAL_OPCODE: Y 53901 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 53902 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() 53903 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 53904 IFORM: VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 53905 } 53906 53907 53908 # EMITTING VPBROADCASTQ (VPBROADCASTQ-128-2) 53909 { 53910 ICLASS: VPBROADCASTQ 53911 CPL: 3 53912 CATEGORY: BROADCAST 53913 EXTENSION: AVX512EVEX 53914 ISA_SET: AVX512F_128 53915 EXCEPTIONS: AVX512-E6 53916 REAL_OPCODE: Y 53917 ATTRIBUTES: MASKOP_EVEX 53918 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 53919 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO2_64 53920 IFORM: VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 53921 } 53922 53923 53924 # EMITTING VPBROADCASTQ (VPBROADCASTQ-128-3) 53925 { 53926 ICLASS: VPBROADCASTQ 53927 CPL: 3 53928 CATEGORY: BROADCAST 53929 EXTENSION: AVX512EVEX 53930 ISA_SET: AVX512F_128 53931 EXCEPTIONS: AVX512-E7NM 53932 REAL_OPCODE: Y 53933 ATTRIBUTES: MASKOP_EVEX 53934 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR 53935 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO2_64 53936 IFORM: VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 53937 } 53938 53939 53940 # EMITTING VPBROADCASTQ (VPBROADCASTQ-256-1) 53941 { 53942 ICLASS: VPBROADCASTQ 53943 CPL: 3 53944 CATEGORY: BROADCAST 53945 EXTENSION: AVX512EVEX 53946 ISA_SET: AVX512F_256 53947 EXCEPTIONS: AVX512-E6 53948 REAL_OPCODE: Y 53949 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 53950 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() 53951 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 53952 IFORM: VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 53953 } 53954 53955 53956 # EMITTING VPBROADCASTQ (VPBROADCASTQ-256-2) 53957 { 53958 ICLASS: VPBROADCASTQ 53959 CPL: 3 53960 CATEGORY: BROADCAST 53961 EXTENSION: AVX512EVEX 53962 ISA_SET: AVX512F_256 53963 EXCEPTIONS: AVX512-E6 53964 REAL_OPCODE: Y 53965 ATTRIBUTES: MASKOP_EVEX 53966 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 53967 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO4_64 53968 IFORM: VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 53969 } 53970 53971 53972 # EMITTING VPBROADCASTQ (VPBROADCASTQ-256-3) 53973 { 53974 ICLASS: VPBROADCASTQ 53975 CPL: 3 53976 CATEGORY: BROADCAST 53977 EXTENSION: AVX512EVEX 53978 ISA_SET: AVX512F_256 53979 EXCEPTIONS: AVX512-E7NM 53980 REAL_OPCODE: Y 53981 ATTRIBUTES: MASKOP_EVEX 53982 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR 53983 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO4_64 53984 IFORM: VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 53985 } 53986 53987 53988 # EMITTING VPBROADCASTW (VPBROADCASTW-128-1) 53989 { 53990 ICLASS: VPBROADCASTW 53991 CPL: 3 53992 CATEGORY: BROADCAST 53993 EXTENSION: AVX512EVEX 53994 ISA_SET: AVX512BW_128 53995 EXCEPTIONS: AVX512-E6 53996 REAL_OPCODE: Y 53997 ATTRIBUTES: MASKOP_EVEX 53998 PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 53999 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO8_16 54000 IFORM: VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 54001 } 54002 54003 { 54004 ICLASS: VPBROADCASTW 54005 CPL: 3 54006 CATEGORY: BROADCAST 54007 EXTENSION: AVX512EVEX 54008 ISA_SET: AVX512BW_128 54009 EXCEPTIONS: AVX512-E6 54010 REAL_OPCODE: Y 54011 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD 54012 PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() 54013 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO8_16 54014 IFORM: VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 54015 } 54016 54017 54018 # EMITTING VPBROADCASTW (VPBROADCASTW-128-2) 54019 { 54020 ICLASS: VPBROADCASTW 54021 CPL: 3 54022 CATEGORY: BROADCAST 54023 EXTENSION: AVX512EVEX 54024 ISA_SET: AVX512BW_128 54025 EXCEPTIONS: AVX512-E7NM 54026 REAL_OPCODE: Y 54027 ATTRIBUTES: MASKOP_EVEX 54028 PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 54029 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO8_16 54030 IFORM: VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 54031 } 54032 54033 54034 # EMITTING VPBROADCASTW (VPBROADCASTW-256-1) 54035 { 54036 ICLASS: VPBROADCASTW 54037 CPL: 3 54038 CATEGORY: BROADCAST 54039 EXTENSION: AVX512EVEX 54040 ISA_SET: AVX512BW_256 54041 EXCEPTIONS: AVX512-E6 54042 REAL_OPCODE: Y 54043 ATTRIBUTES: MASKOP_EVEX 54044 PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 54045 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO16_16 54046 IFORM: VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 54047 } 54048 54049 { 54050 ICLASS: VPBROADCASTW 54051 CPL: 3 54052 CATEGORY: BROADCAST 54053 EXTENSION: AVX512EVEX 54054 ISA_SET: AVX512BW_256 54055 EXCEPTIONS: AVX512-E6 54056 REAL_OPCODE: Y 54057 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD 54058 PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() 54059 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO16_16 54060 IFORM: VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 54061 } 54062 54063 54064 # EMITTING VPBROADCASTW (VPBROADCASTW-256-2) 54065 { 54066 ICLASS: VPBROADCASTW 54067 CPL: 3 54068 CATEGORY: BROADCAST 54069 EXTENSION: AVX512EVEX 54070 ISA_SET: AVX512BW_256 54071 EXCEPTIONS: AVX512-E7NM 54072 REAL_OPCODE: Y 54073 ATTRIBUTES: MASKOP_EVEX 54074 PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 54075 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO16_16 54076 IFORM: VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 54077 } 54078 54079 54080 # EMITTING VPBROADCASTW (VPBROADCASTW-512-1) 54081 { 54082 ICLASS: VPBROADCASTW 54083 CPL: 3 54084 CATEGORY: BROADCAST 54085 EXTENSION: AVX512EVEX 54086 ISA_SET: AVX512BW_512 54087 EXCEPTIONS: AVX512-E6 54088 REAL_OPCODE: Y 54089 ATTRIBUTES: MASKOP_EVEX 54090 PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 54091 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO32_16 54092 IFORM: VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 54093 } 54094 54095 { 54096 ICLASS: VPBROADCASTW 54097 CPL: 3 54098 CATEGORY: BROADCAST 54099 EXTENSION: AVX512EVEX 54100 ISA_SET: AVX512BW_512 54101 EXCEPTIONS: AVX512-E6 54102 REAL_OPCODE: Y 54103 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD 54104 PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() 54105 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO32_16 54106 IFORM: VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 54107 } 54108 54109 54110 # EMITTING VPBROADCASTW (VPBROADCASTW-512-2) 54111 { 54112 ICLASS: VPBROADCASTW 54113 CPL: 3 54114 CATEGORY: BROADCAST 54115 EXTENSION: AVX512EVEX 54116 ISA_SET: AVX512BW_512 54117 EXCEPTIONS: AVX512-E7NM 54118 REAL_OPCODE: Y 54119 ATTRIBUTES: MASKOP_EVEX 54120 PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 54121 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO32_16 54122 IFORM: VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 54123 } 54124 54125 54126 # EMITTING VPCMPB (VPCMPB-128-1) 54127 { 54128 ICLASS: VPCMPB 54129 CPL: 3 54130 CATEGORY: AVX512 54131 EXTENSION: AVX512EVEX 54132 ISA_SET: AVX512BW_128 54133 EXCEPTIONS: AVX512-E4 54134 REAL_OPCODE: Y 54135 ATTRIBUTES: MASKOP_EVEX 54136 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() 54137 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 IMM0:r:b 54138 IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 54139 } 54140 54141 { 54142 ICLASS: VPCMPB 54143 CPL: 3 54144 CATEGORY: AVX512 54145 EXTENSION: AVX512EVEX 54146 ISA_SET: AVX512BW_128 54147 EXCEPTIONS: AVX512-E4 54148 REAL_OPCODE: Y 54149 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54150 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 54151 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b 54152 IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 54153 } 54154 54155 54156 # EMITTING VPCMPB (VPCMPB-256-1) 54157 { 54158 ICLASS: VPCMPB 54159 CPL: 3 54160 CATEGORY: AVX512 54161 EXTENSION: AVX512EVEX 54162 ISA_SET: AVX512BW_256 54163 EXCEPTIONS: AVX512-E4 54164 REAL_OPCODE: Y 54165 ATTRIBUTES: MASKOP_EVEX 54166 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() 54167 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 IMM0:r:b 54168 IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 54169 } 54170 54171 { 54172 ICLASS: VPCMPB 54173 CPL: 3 54174 CATEGORY: AVX512 54175 EXTENSION: AVX512EVEX 54176 ISA_SET: AVX512BW_256 54177 EXCEPTIONS: AVX512-E4 54178 REAL_OPCODE: Y 54179 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54180 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 54181 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 IMM0:r:b 54182 IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 54183 } 54184 54185 54186 # EMITTING VPCMPB (VPCMPB-512-1) 54187 { 54188 ICLASS: VPCMPB 54189 CPL: 3 54190 CATEGORY: AVX512 54191 EXTENSION: AVX512EVEX 54192 ISA_SET: AVX512BW_512 54193 EXCEPTIONS: AVX512-E4 54194 REAL_OPCODE: Y 54195 ATTRIBUTES: MASKOP_EVEX 54196 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() 54197 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 IMM0:r:b 54198 IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 54199 } 54200 54201 { 54202 ICLASS: VPCMPB 54203 CPL: 3 54204 CATEGORY: AVX512 54205 EXTENSION: AVX512EVEX 54206 ISA_SET: AVX512BW_512 54207 EXCEPTIONS: AVX512-E4 54208 REAL_OPCODE: Y 54209 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54210 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 54211 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 IMM0:r:b 54212 IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 54213 } 54214 54215 54216 # EMITTING VPCMPD (VPCMPD-128-1) 54217 { 54218 ICLASS: VPCMPD 54219 CPL: 3 54220 CATEGORY: AVX512 54221 EXTENSION: AVX512EVEX 54222 ISA_SET: AVX512F_128 54223 EXCEPTIONS: AVX512-E4 54224 REAL_OPCODE: Y 54225 ATTRIBUTES: MASKOP_EVEX 54226 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() 54227 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 IMM0:r:b 54228 IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 54229 } 54230 54231 { 54232 ICLASS: VPCMPD 54233 CPL: 3 54234 CATEGORY: AVX512 54235 EXTENSION: AVX512EVEX 54236 ISA_SET: AVX512F_128 54237 EXCEPTIONS: AVX512-E4 54238 REAL_OPCODE: Y 54239 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54240 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 54241 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b 54242 IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 54243 } 54244 54245 54246 # EMITTING VPCMPD (VPCMPD-256-1) 54247 { 54248 ICLASS: VPCMPD 54249 CPL: 3 54250 CATEGORY: AVX512 54251 EXTENSION: AVX512EVEX 54252 ISA_SET: AVX512F_256 54253 EXCEPTIONS: AVX512-E4 54254 REAL_OPCODE: Y 54255 ATTRIBUTES: MASKOP_EVEX 54256 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() 54257 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 IMM0:r:b 54258 IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 54259 } 54260 54261 { 54262 ICLASS: VPCMPD 54263 CPL: 3 54264 CATEGORY: AVX512 54265 EXTENSION: AVX512EVEX 54266 ISA_SET: AVX512F_256 54267 EXCEPTIONS: AVX512-E4 54268 REAL_OPCODE: Y 54269 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54270 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 54271 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b 54272 IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 54273 } 54274 54275 54276 # EMITTING VPCMPEQB (VPCMPEQB-128-1) 54277 { 54278 ICLASS: VPCMPEQB 54279 CPL: 3 54280 CATEGORY: AVX512 54281 EXTENSION: AVX512EVEX 54282 ISA_SET: AVX512BW_128 54283 EXCEPTIONS: AVX512-E4 54284 REAL_OPCODE: Y 54285 ATTRIBUTES: MASKOP_EVEX 54286 PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 54287 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 54288 IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 54289 } 54290 54291 { 54292 ICLASS: VPCMPEQB 54293 CPL: 3 54294 CATEGORY: AVX512 54295 EXTENSION: AVX512EVEX 54296 ISA_SET: AVX512BW_128 54297 EXCEPTIONS: AVX512-E4 54298 REAL_OPCODE: Y 54299 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54300 PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 54301 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 54302 IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 54303 } 54304 54305 54306 # EMITTING VPCMPEQB (VPCMPEQB-256-1) 54307 { 54308 ICLASS: VPCMPEQB 54309 CPL: 3 54310 CATEGORY: AVX512 54311 EXTENSION: AVX512EVEX 54312 ISA_SET: AVX512BW_256 54313 EXCEPTIONS: AVX512-E4 54314 REAL_OPCODE: Y 54315 ATTRIBUTES: MASKOP_EVEX 54316 PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 54317 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 54318 IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 54319 } 54320 54321 { 54322 ICLASS: VPCMPEQB 54323 CPL: 3 54324 CATEGORY: AVX512 54325 EXTENSION: AVX512EVEX 54326 ISA_SET: AVX512BW_256 54327 EXCEPTIONS: AVX512-E4 54328 REAL_OPCODE: Y 54329 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54330 PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 54331 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 54332 IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 54333 } 54334 54335 54336 # EMITTING VPCMPEQB (VPCMPEQB-512-1) 54337 { 54338 ICLASS: VPCMPEQB 54339 CPL: 3 54340 CATEGORY: AVX512 54341 EXTENSION: AVX512EVEX 54342 ISA_SET: AVX512BW_512 54343 EXCEPTIONS: AVX512-E4 54344 REAL_OPCODE: Y 54345 ATTRIBUTES: MASKOP_EVEX 54346 PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 54347 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 54348 IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 54349 } 54350 54351 { 54352 ICLASS: VPCMPEQB 54353 CPL: 3 54354 CATEGORY: AVX512 54355 EXTENSION: AVX512EVEX 54356 ISA_SET: AVX512BW_512 54357 EXCEPTIONS: AVX512-E4 54358 REAL_OPCODE: Y 54359 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54360 PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 54361 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 54362 IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 54363 } 54364 54365 54366 # EMITTING VPCMPEQD (VPCMPEQD-128-1) 54367 { 54368 ICLASS: VPCMPEQD 54369 CPL: 3 54370 CATEGORY: AVX512 54371 EXTENSION: AVX512EVEX 54372 ISA_SET: AVX512F_128 54373 EXCEPTIONS: AVX512-E4 54374 REAL_OPCODE: Y 54375 ATTRIBUTES: MASKOP_EVEX 54376 PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 54377 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 54378 IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 54379 } 54380 54381 { 54382 ICLASS: VPCMPEQD 54383 CPL: 3 54384 CATEGORY: AVX512 54385 EXTENSION: AVX512EVEX 54386 ISA_SET: AVX512F_128 54387 EXCEPTIONS: AVX512-E4 54388 REAL_OPCODE: Y 54389 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54390 PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 54391 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 54392 IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 54393 } 54394 54395 54396 # EMITTING VPCMPEQD (VPCMPEQD-256-1) 54397 { 54398 ICLASS: VPCMPEQD 54399 CPL: 3 54400 CATEGORY: AVX512 54401 EXTENSION: AVX512EVEX 54402 ISA_SET: AVX512F_256 54403 EXCEPTIONS: AVX512-E4 54404 REAL_OPCODE: Y 54405 ATTRIBUTES: MASKOP_EVEX 54406 PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 54407 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 54408 IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 54409 } 54410 54411 { 54412 ICLASS: VPCMPEQD 54413 CPL: 3 54414 CATEGORY: AVX512 54415 EXTENSION: AVX512EVEX 54416 ISA_SET: AVX512F_256 54417 EXCEPTIONS: AVX512-E4 54418 REAL_OPCODE: Y 54419 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54420 PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 54421 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 54422 IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 54423 } 54424 54425 54426 # EMITTING VPCMPEQQ (VPCMPEQQ-128-1) 54427 { 54428 ICLASS: VPCMPEQQ 54429 CPL: 3 54430 CATEGORY: AVX512 54431 EXTENSION: AVX512EVEX 54432 ISA_SET: AVX512F_128 54433 EXCEPTIONS: AVX512-E4 54434 REAL_OPCODE: Y 54435 ATTRIBUTES: MASKOP_EVEX 54436 PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 54437 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 54438 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 54439 } 54440 54441 { 54442 ICLASS: VPCMPEQQ 54443 CPL: 3 54444 CATEGORY: AVX512 54445 EXTENSION: AVX512EVEX 54446 ISA_SET: AVX512F_128 54447 EXCEPTIONS: AVX512-E4 54448 REAL_OPCODE: Y 54449 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54450 PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 54451 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 54452 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 54453 } 54454 54455 54456 # EMITTING VPCMPEQQ (VPCMPEQQ-256-1) 54457 { 54458 ICLASS: VPCMPEQQ 54459 CPL: 3 54460 CATEGORY: AVX512 54461 EXTENSION: AVX512EVEX 54462 ISA_SET: AVX512F_256 54463 EXCEPTIONS: AVX512-E4 54464 REAL_OPCODE: Y 54465 ATTRIBUTES: MASKOP_EVEX 54466 PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 54467 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 54468 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 54469 } 54470 54471 { 54472 ICLASS: VPCMPEQQ 54473 CPL: 3 54474 CATEGORY: AVX512 54475 EXTENSION: AVX512EVEX 54476 ISA_SET: AVX512F_256 54477 EXCEPTIONS: AVX512-E4 54478 REAL_OPCODE: Y 54479 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54480 PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 54481 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 54482 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 54483 } 54484 54485 54486 # EMITTING VPCMPEQW (VPCMPEQW-128-1) 54487 { 54488 ICLASS: VPCMPEQW 54489 CPL: 3 54490 CATEGORY: AVX512 54491 EXTENSION: AVX512EVEX 54492 ISA_SET: AVX512BW_128 54493 EXCEPTIONS: AVX512-E4 54494 REAL_OPCODE: Y 54495 ATTRIBUTES: MASKOP_EVEX 54496 PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 54497 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 54498 IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 54499 } 54500 54501 { 54502 ICLASS: VPCMPEQW 54503 CPL: 3 54504 CATEGORY: AVX512 54505 EXTENSION: AVX512EVEX 54506 ISA_SET: AVX512BW_128 54507 EXCEPTIONS: AVX512-E4 54508 REAL_OPCODE: Y 54509 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54510 PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 54511 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 54512 IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 54513 } 54514 54515 54516 # EMITTING VPCMPEQW (VPCMPEQW-256-1) 54517 { 54518 ICLASS: VPCMPEQW 54519 CPL: 3 54520 CATEGORY: AVX512 54521 EXTENSION: AVX512EVEX 54522 ISA_SET: AVX512BW_256 54523 EXCEPTIONS: AVX512-E4 54524 REAL_OPCODE: Y 54525 ATTRIBUTES: MASKOP_EVEX 54526 PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 54527 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 54528 IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 54529 } 54530 54531 { 54532 ICLASS: VPCMPEQW 54533 CPL: 3 54534 CATEGORY: AVX512 54535 EXTENSION: AVX512EVEX 54536 ISA_SET: AVX512BW_256 54537 EXCEPTIONS: AVX512-E4 54538 REAL_OPCODE: Y 54539 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54540 PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 54541 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 54542 IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 54543 } 54544 54545 54546 # EMITTING VPCMPEQW (VPCMPEQW-512-1) 54547 { 54548 ICLASS: VPCMPEQW 54549 CPL: 3 54550 CATEGORY: AVX512 54551 EXTENSION: AVX512EVEX 54552 ISA_SET: AVX512BW_512 54553 EXCEPTIONS: AVX512-E4 54554 REAL_OPCODE: Y 54555 ATTRIBUTES: MASKOP_EVEX 54556 PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 54557 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 54558 IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 54559 } 54560 54561 { 54562 ICLASS: VPCMPEQW 54563 CPL: 3 54564 CATEGORY: AVX512 54565 EXTENSION: AVX512EVEX 54566 ISA_SET: AVX512BW_512 54567 EXCEPTIONS: AVX512-E4 54568 REAL_OPCODE: Y 54569 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54570 PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 54571 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 54572 IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 54573 } 54574 54575 54576 # EMITTING VPCMPGTB (VPCMPGTB-128-1) 54577 { 54578 ICLASS: VPCMPGTB 54579 CPL: 3 54580 CATEGORY: AVX512 54581 EXTENSION: AVX512EVEX 54582 ISA_SET: AVX512BW_128 54583 EXCEPTIONS: AVX512-E4 54584 REAL_OPCODE: Y 54585 ATTRIBUTES: MASKOP_EVEX 54586 PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 54587 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 54588 IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 54589 } 54590 54591 { 54592 ICLASS: VPCMPGTB 54593 CPL: 3 54594 CATEGORY: AVX512 54595 EXTENSION: AVX512EVEX 54596 ISA_SET: AVX512BW_128 54597 EXCEPTIONS: AVX512-E4 54598 REAL_OPCODE: Y 54599 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54600 PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 54601 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 54602 IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 54603 } 54604 54605 54606 # EMITTING VPCMPGTB (VPCMPGTB-256-1) 54607 { 54608 ICLASS: VPCMPGTB 54609 CPL: 3 54610 CATEGORY: AVX512 54611 EXTENSION: AVX512EVEX 54612 ISA_SET: AVX512BW_256 54613 EXCEPTIONS: AVX512-E4 54614 REAL_OPCODE: Y 54615 ATTRIBUTES: MASKOP_EVEX 54616 PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 54617 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 54618 IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 54619 } 54620 54621 { 54622 ICLASS: VPCMPGTB 54623 CPL: 3 54624 CATEGORY: AVX512 54625 EXTENSION: AVX512EVEX 54626 ISA_SET: AVX512BW_256 54627 EXCEPTIONS: AVX512-E4 54628 REAL_OPCODE: Y 54629 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54630 PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 54631 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 54632 IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 54633 } 54634 54635 54636 # EMITTING VPCMPGTB (VPCMPGTB-512-1) 54637 { 54638 ICLASS: VPCMPGTB 54639 CPL: 3 54640 CATEGORY: AVX512 54641 EXTENSION: AVX512EVEX 54642 ISA_SET: AVX512BW_512 54643 EXCEPTIONS: AVX512-E4 54644 REAL_OPCODE: Y 54645 ATTRIBUTES: MASKOP_EVEX 54646 PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 54647 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 54648 IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 54649 } 54650 54651 { 54652 ICLASS: VPCMPGTB 54653 CPL: 3 54654 CATEGORY: AVX512 54655 EXTENSION: AVX512EVEX 54656 ISA_SET: AVX512BW_512 54657 EXCEPTIONS: AVX512-E4 54658 REAL_OPCODE: Y 54659 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54660 PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 54661 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 54662 IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 54663 } 54664 54665 54666 # EMITTING VPCMPGTD (VPCMPGTD-128-1) 54667 { 54668 ICLASS: VPCMPGTD 54669 CPL: 3 54670 CATEGORY: AVX512 54671 EXTENSION: AVX512EVEX 54672 ISA_SET: AVX512F_128 54673 EXCEPTIONS: AVX512-E4 54674 REAL_OPCODE: Y 54675 ATTRIBUTES: MASKOP_EVEX 54676 PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 54677 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 54678 IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 54679 } 54680 54681 { 54682 ICLASS: VPCMPGTD 54683 CPL: 3 54684 CATEGORY: AVX512 54685 EXTENSION: AVX512EVEX 54686 ISA_SET: AVX512F_128 54687 EXCEPTIONS: AVX512-E4 54688 REAL_OPCODE: Y 54689 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54690 PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 54691 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 54692 IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 54693 } 54694 54695 54696 # EMITTING VPCMPGTD (VPCMPGTD-256-1) 54697 { 54698 ICLASS: VPCMPGTD 54699 CPL: 3 54700 CATEGORY: AVX512 54701 EXTENSION: AVX512EVEX 54702 ISA_SET: AVX512F_256 54703 EXCEPTIONS: AVX512-E4 54704 REAL_OPCODE: Y 54705 ATTRIBUTES: MASKOP_EVEX 54706 PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 54707 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 54708 IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 54709 } 54710 54711 { 54712 ICLASS: VPCMPGTD 54713 CPL: 3 54714 CATEGORY: AVX512 54715 EXTENSION: AVX512EVEX 54716 ISA_SET: AVX512F_256 54717 EXCEPTIONS: AVX512-E4 54718 REAL_OPCODE: Y 54719 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54720 PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 54721 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 54722 IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 54723 } 54724 54725 54726 # EMITTING VPCMPGTQ (VPCMPGTQ-128-1) 54727 { 54728 ICLASS: VPCMPGTQ 54729 CPL: 3 54730 CATEGORY: AVX512 54731 EXTENSION: AVX512EVEX 54732 ISA_SET: AVX512F_128 54733 EXCEPTIONS: AVX512-E4 54734 REAL_OPCODE: Y 54735 ATTRIBUTES: MASKOP_EVEX 54736 PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 54737 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 54738 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 54739 } 54740 54741 { 54742 ICLASS: VPCMPGTQ 54743 CPL: 3 54744 CATEGORY: AVX512 54745 EXTENSION: AVX512EVEX 54746 ISA_SET: AVX512F_128 54747 EXCEPTIONS: AVX512-E4 54748 REAL_OPCODE: Y 54749 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54750 PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 54751 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 54752 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 54753 } 54754 54755 54756 # EMITTING VPCMPGTQ (VPCMPGTQ-256-1) 54757 { 54758 ICLASS: VPCMPGTQ 54759 CPL: 3 54760 CATEGORY: AVX512 54761 EXTENSION: AVX512EVEX 54762 ISA_SET: AVX512F_256 54763 EXCEPTIONS: AVX512-E4 54764 REAL_OPCODE: Y 54765 ATTRIBUTES: MASKOP_EVEX 54766 PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 54767 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 54768 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 54769 } 54770 54771 { 54772 ICLASS: VPCMPGTQ 54773 CPL: 3 54774 CATEGORY: AVX512 54775 EXTENSION: AVX512EVEX 54776 ISA_SET: AVX512F_256 54777 EXCEPTIONS: AVX512-E4 54778 REAL_OPCODE: Y 54779 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54780 PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 54781 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 54782 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 54783 } 54784 54785 54786 # EMITTING VPCMPGTW (VPCMPGTW-128-1) 54787 { 54788 ICLASS: VPCMPGTW 54789 CPL: 3 54790 CATEGORY: AVX512 54791 EXTENSION: AVX512EVEX 54792 ISA_SET: AVX512BW_128 54793 EXCEPTIONS: AVX512-E4 54794 REAL_OPCODE: Y 54795 ATTRIBUTES: MASKOP_EVEX 54796 PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 54797 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 54798 IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 54799 } 54800 54801 { 54802 ICLASS: VPCMPGTW 54803 CPL: 3 54804 CATEGORY: AVX512 54805 EXTENSION: AVX512EVEX 54806 ISA_SET: AVX512BW_128 54807 EXCEPTIONS: AVX512-E4 54808 REAL_OPCODE: Y 54809 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54810 PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 54811 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 54812 IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 54813 } 54814 54815 54816 # EMITTING VPCMPGTW (VPCMPGTW-256-1) 54817 { 54818 ICLASS: VPCMPGTW 54819 CPL: 3 54820 CATEGORY: AVX512 54821 EXTENSION: AVX512EVEX 54822 ISA_SET: AVX512BW_256 54823 EXCEPTIONS: AVX512-E4 54824 REAL_OPCODE: Y 54825 ATTRIBUTES: MASKOP_EVEX 54826 PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 54827 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 54828 IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 54829 } 54830 54831 { 54832 ICLASS: VPCMPGTW 54833 CPL: 3 54834 CATEGORY: AVX512 54835 EXTENSION: AVX512EVEX 54836 ISA_SET: AVX512BW_256 54837 EXCEPTIONS: AVX512-E4 54838 REAL_OPCODE: Y 54839 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54840 PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 54841 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 54842 IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 54843 } 54844 54845 54846 # EMITTING VPCMPGTW (VPCMPGTW-512-1) 54847 { 54848 ICLASS: VPCMPGTW 54849 CPL: 3 54850 CATEGORY: AVX512 54851 EXTENSION: AVX512EVEX 54852 ISA_SET: AVX512BW_512 54853 EXCEPTIONS: AVX512-E4 54854 REAL_OPCODE: Y 54855 ATTRIBUTES: MASKOP_EVEX 54856 PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 54857 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 54858 IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 54859 } 54860 54861 { 54862 ICLASS: VPCMPGTW 54863 CPL: 3 54864 CATEGORY: AVX512 54865 EXTENSION: AVX512EVEX 54866 ISA_SET: AVX512BW_512 54867 EXCEPTIONS: AVX512-E4 54868 REAL_OPCODE: Y 54869 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54870 PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 54871 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 54872 IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 54873 } 54874 54875 54876 # EMITTING VPCMPQ (VPCMPQ-128-1) 54877 { 54878 ICLASS: VPCMPQ 54879 CPL: 3 54880 CATEGORY: AVX512 54881 EXTENSION: AVX512EVEX 54882 ISA_SET: AVX512F_128 54883 EXCEPTIONS: AVX512-E4 54884 REAL_OPCODE: Y 54885 ATTRIBUTES: MASKOP_EVEX 54886 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() 54887 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 IMM0:r:b 54888 IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 54889 } 54890 54891 { 54892 ICLASS: VPCMPQ 54893 CPL: 3 54894 CATEGORY: AVX512 54895 EXTENSION: AVX512EVEX 54896 ISA_SET: AVX512F_128 54897 EXCEPTIONS: AVX512-E4 54898 REAL_OPCODE: Y 54899 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54900 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 54901 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b 54902 IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 54903 } 54904 54905 54906 # EMITTING VPCMPQ (VPCMPQ-256-1) 54907 { 54908 ICLASS: VPCMPQ 54909 CPL: 3 54910 CATEGORY: AVX512 54911 EXTENSION: AVX512EVEX 54912 ISA_SET: AVX512F_256 54913 EXCEPTIONS: AVX512-E4 54914 REAL_OPCODE: Y 54915 ATTRIBUTES: MASKOP_EVEX 54916 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() 54917 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 IMM0:r:b 54918 IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 54919 } 54920 54921 { 54922 ICLASS: VPCMPQ 54923 CPL: 3 54924 CATEGORY: AVX512 54925 EXTENSION: AVX512EVEX 54926 ISA_SET: AVX512F_256 54927 EXCEPTIONS: AVX512-E4 54928 REAL_OPCODE: Y 54929 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54930 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 54931 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b 54932 IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 54933 } 54934 54935 54936 # EMITTING VPCMPUB (VPCMPUB-128-1) 54937 { 54938 ICLASS: VPCMPUB 54939 CPL: 3 54940 CATEGORY: AVX512 54941 EXTENSION: AVX512EVEX 54942 ISA_SET: AVX512BW_128 54943 EXCEPTIONS: AVX512-E4 54944 REAL_OPCODE: Y 54945 ATTRIBUTES: MASKOP_EVEX 54946 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() 54947 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b 54948 IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 54949 } 54950 54951 { 54952 ICLASS: VPCMPUB 54953 CPL: 3 54954 CATEGORY: AVX512 54955 EXTENSION: AVX512EVEX 54956 ISA_SET: AVX512BW_128 54957 EXCEPTIONS: AVX512-E4 54958 REAL_OPCODE: Y 54959 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54960 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 54961 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b 54962 IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 54963 } 54964 54965 54966 # EMITTING VPCMPUB (VPCMPUB-256-1) 54967 { 54968 ICLASS: VPCMPUB 54969 CPL: 3 54970 CATEGORY: AVX512 54971 EXTENSION: AVX512EVEX 54972 ISA_SET: AVX512BW_256 54973 EXCEPTIONS: AVX512-E4 54974 REAL_OPCODE: Y 54975 ATTRIBUTES: MASKOP_EVEX 54976 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() 54977 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b 54978 IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 54979 } 54980 54981 { 54982 ICLASS: VPCMPUB 54983 CPL: 3 54984 CATEGORY: AVX512 54985 EXTENSION: AVX512EVEX 54986 ISA_SET: AVX512BW_256 54987 EXCEPTIONS: AVX512-E4 54988 REAL_OPCODE: Y 54989 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54990 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 54991 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b 54992 IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 54993 } 54994 54995 54996 # EMITTING VPCMPUB (VPCMPUB-512-1) 54997 { 54998 ICLASS: VPCMPUB 54999 CPL: 3 55000 CATEGORY: AVX512 55001 EXTENSION: AVX512EVEX 55002 ISA_SET: AVX512BW_512 55003 EXCEPTIONS: AVX512-E4 55004 REAL_OPCODE: Y 55005 ATTRIBUTES: MASKOP_EVEX 55006 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() 55007 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b 55008 IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 55009 } 55010 55011 { 55012 ICLASS: VPCMPUB 55013 CPL: 3 55014 CATEGORY: AVX512 55015 EXTENSION: AVX512EVEX 55016 ISA_SET: AVX512BW_512 55017 EXCEPTIONS: AVX512-E4 55018 REAL_OPCODE: Y 55019 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55020 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 55021 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b 55022 IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 55023 } 55024 55025 55026 # EMITTING VPCMPUD (VPCMPUD-128-1) 55027 { 55028 ICLASS: VPCMPUD 55029 CPL: 3 55030 CATEGORY: AVX512 55031 EXTENSION: AVX512EVEX 55032 ISA_SET: AVX512F_128 55033 EXCEPTIONS: AVX512-E4 55034 REAL_OPCODE: Y 55035 ATTRIBUTES: MASKOP_EVEX 55036 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() 55037 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 55038 IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 55039 } 55040 55041 { 55042 ICLASS: VPCMPUD 55043 CPL: 3 55044 CATEGORY: AVX512 55045 EXTENSION: AVX512EVEX 55046 ISA_SET: AVX512F_128 55047 EXCEPTIONS: AVX512-E4 55048 REAL_OPCODE: Y 55049 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55050 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 55051 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 55052 IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 55053 } 55054 55055 55056 # EMITTING VPCMPUD (VPCMPUD-256-1) 55057 { 55058 ICLASS: VPCMPUD 55059 CPL: 3 55060 CATEGORY: AVX512 55061 EXTENSION: AVX512EVEX 55062 ISA_SET: AVX512F_256 55063 EXCEPTIONS: AVX512-E4 55064 REAL_OPCODE: Y 55065 ATTRIBUTES: MASKOP_EVEX 55066 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() 55067 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 55068 IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 55069 } 55070 55071 { 55072 ICLASS: VPCMPUD 55073 CPL: 3 55074 CATEGORY: AVX512 55075 EXTENSION: AVX512EVEX 55076 ISA_SET: AVX512F_256 55077 EXCEPTIONS: AVX512-E4 55078 REAL_OPCODE: Y 55079 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55080 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 55081 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 55082 IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 55083 } 55084 55085 55086 # EMITTING VPCMPUQ (VPCMPUQ-128-1) 55087 { 55088 ICLASS: VPCMPUQ 55089 CPL: 3 55090 CATEGORY: AVX512 55091 EXTENSION: AVX512EVEX 55092 ISA_SET: AVX512F_128 55093 EXCEPTIONS: AVX512-E4 55094 REAL_OPCODE: Y 55095 ATTRIBUTES: MASKOP_EVEX 55096 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() 55097 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 55098 IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 55099 } 55100 55101 { 55102 ICLASS: VPCMPUQ 55103 CPL: 3 55104 CATEGORY: AVX512 55105 EXTENSION: AVX512EVEX 55106 ISA_SET: AVX512F_128 55107 EXCEPTIONS: AVX512-E4 55108 REAL_OPCODE: Y 55109 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55110 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 55111 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 55112 IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 55113 } 55114 55115 55116 # EMITTING VPCMPUQ (VPCMPUQ-256-1) 55117 { 55118 ICLASS: VPCMPUQ 55119 CPL: 3 55120 CATEGORY: AVX512 55121 EXTENSION: AVX512EVEX 55122 ISA_SET: AVX512F_256 55123 EXCEPTIONS: AVX512-E4 55124 REAL_OPCODE: Y 55125 ATTRIBUTES: MASKOP_EVEX 55126 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() 55127 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 55128 IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 55129 } 55130 55131 { 55132 ICLASS: VPCMPUQ 55133 CPL: 3 55134 CATEGORY: AVX512 55135 EXTENSION: AVX512EVEX 55136 ISA_SET: AVX512F_256 55137 EXCEPTIONS: AVX512-E4 55138 REAL_OPCODE: Y 55139 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55140 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 55141 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 55142 IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 55143 } 55144 55145 55146 # EMITTING VPCMPUW (VPCMPUW-128-1) 55147 { 55148 ICLASS: VPCMPUW 55149 CPL: 3 55150 CATEGORY: AVX512 55151 EXTENSION: AVX512EVEX 55152 ISA_SET: AVX512BW_128 55153 EXCEPTIONS: AVX512-E4 55154 REAL_OPCODE: Y 55155 ATTRIBUTES: MASKOP_EVEX 55156 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() 55157 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b 55158 IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 55159 } 55160 55161 { 55162 ICLASS: VPCMPUW 55163 CPL: 3 55164 CATEGORY: AVX512 55165 EXTENSION: AVX512EVEX 55166 ISA_SET: AVX512BW_128 55167 EXCEPTIONS: AVX512-E4 55168 REAL_OPCODE: Y 55169 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55170 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 55171 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b 55172 IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 55173 } 55174 55175 55176 # EMITTING VPCMPUW (VPCMPUW-256-1) 55177 { 55178 ICLASS: VPCMPUW 55179 CPL: 3 55180 CATEGORY: AVX512 55181 EXTENSION: AVX512EVEX 55182 ISA_SET: AVX512BW_256 55183 EXCEPTIONS: AVX512-E4 55184 REAL_OPCODE: Y 55185 ATTRIBUTES: MASKOP_EVEX 55186 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() 55187 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b 55188 IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 55189 } 55190 55191 { 55192 ICLASS: VPCMPUW 55193 CPL: 3 55194 CATEGORY: AVX512 55195 EXTENSION: AVX512EVEX 55196 ISA_SET: AVX512BW_256 55197 EXCEPTIONS: AVX512-E4 55198 REAL_OPCODE: Y 55199 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55200 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 55201 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b 55202 IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 55203 } 55204 55205 55206 # EMITTING VPCMPUW (VPCMPUW-512-1) 55207 { 55208 ICLASS: VPCMPUW 55209 CPL: 3 55210 CATEGORY: AVX512 55211 EXTENSION: AVX512EVEX 55212 ISA_SET: AVX512BW_512 55213 EXCEPTIONS: AVX512-E4 55214 REAL_OPCODE: Y 55215 ATTRIBUTES: MASKOP_EVEX 55216 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() 55217 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b 55218 IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 55219 } 55220 55221 { 55222 ICLASS: VPCMPUW 55223 CPL: 3 55224 CATEGORY: AVX512 55225 EXTENSION: AVX512EVEX 55226 ISA_SET: AVX512BW_512 55227 EXCEPTIONS: AVX512-E4 55228 REAL_OPCODE: Y 55229 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55230 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 55231 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b 55232 IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 55233 } 55234 55235 55236 # EMITTING VPCMPW (VPCMPW-128-1) 55237 { 55238 ICLASS: VPCMPW 55239 CPL: 3 55240 CATEGORY: AVX512 55241 EXTENSION: AVX512EVEX 55242 ISA_SET: AVX512BW_128 55243 EXCEPTIONS: AVX512-E4 55244 REAL_OPCODE: Y 55245 ATTRIBUTES: MASKOP_EVEX 55246 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() 55247 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 IMM0:r:b 55248 IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 55249 } 55250 55251 { 55252 ICLASS: VPCMPW 55253 CPL: 3 55254 CATEGORY: AVX512 55255 EXTENSION: AVX512EVEX 55256 ISA_SET: AVX512BW_128 55257 EXCEPTIONS: AVX512-E4 55258 REAL_OPCODE: Y 55259 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55260 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 55261 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b 55262 IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 55263 } 55264 55265 55266 # EMITTING VPCMPW (VPCMPW-256-1) 55267 { 55268 ICLASS: VPCMPW 55269 CPL: 3 55270 CATEGORY: AVX512 55271 EXTENSION: AVX512EVEX 55272 ISA_SET: AVX512BW_256 55273 EXCEPTIONS: AVX512-E4 55274 REAL_OPCODE: Y 55275 ATTRIBUTES: MASKOP_EVEX 55276 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() 55277 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 IMM0:r:b 55278 IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 55279 } 55280 55281 { 55282 ICLASS: VPCMPW 55283 CPL: 3 55284 CATEGORY: AVX512 55285 EXTENSION: AVX512EVEX 55286 ISA_SET: AVX512BW_256 55287 EXCEPTIONS: AVX512-E4 55288 REAL_OPCODE: Y 55289 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55290 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 55291 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 IMM0:r:b 55292 IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 55293 } 55294 55295 55296 # EMITTING VPCMPW (VPCMPW-512-1) 55297 { 55298 ICLASS: VPCMPW 55299 CPL: 3 55300 CATEGORY: AVX512 55301 EXTENSION: AVX512EVEX 55302 ISA_SET: AVX512BW_512 55303 EXCEPTIONS: AVX512-E4 55304 REAL_OPCODE: Y 55305 ATTRIBUTES: MASKOP_EVEX 55306 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() 55307 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 IMM0:r:b 55308 IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 55309 } 55310 55311 { 55312 ICLASS: VPCMPW 55313 CPL: 3 55314 CATEGORY: AVX512 55315 EXTENSION: AVX512EVEX 55316 ISA_SET: AVX512BW_512 55317 EXCEPTIONS: AVX512-E4 55318 REAL_OPCODE: Y 55319 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55320 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 55321 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 IMM0:r:b 55322 IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 55323 } 55324 55325 55326 # EMITTING VPCOMPRESSD (VPCOMPRESSD-128-1) 55327 { 55328 ICLASS: VPCOMPRESSD 55329 CPL: 3 55330 CATEGORY: COMPRESS 55331 EXTENSION: AVX512EVEX 55332 ISA_SET: AVX512F_128 55333 EXCEPTIONS: AVX512-E4 55334 REAL_OPCODE: Y 55335 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 55336 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 55337 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 55338 IFORM: VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 55339 } 55340 55341 55342 # EMITTING VPCOMPRESSD (VPCOMPRESSD-128-2) 55343 { 55344 ICLASS: VPCOMPRESSD 55345 CPL: 3 55346 CATEGORY: COMPRESS 55347 EXTENSION: AVX512EVEX 55348 ISA_SET: AVX512F_128 55349 EXCEPTIONS: AVX512-E4 55350 REAL_OPCODE: Y 55351 ATTRIBUTES: MASKOP_EVEX 55352 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 55353 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 55354 IFORM: VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 55355 } 55356 55357 55358 # EMITTING VPCOMPRESSD (VPCOMPRESSD-256-1) 55359 { 55360 ICLASS: VPCOMPRESSD 55361 CPL: 3 55362 CATEGORY: COMPRESS 55363 EXTENSION: AVX512EVEX 55364 ISA_SET: AVX512F_256 55365 EXCEPTIONS: AVX512-E4 55366 REAL_OPCODE: Y 55367 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 55368 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 55369 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 55370 IFORM: VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 55371 } 55372 55373 55374 # EMITTING VPCOMPRESSD (VPCOMPRESSD-256-2) 55375 { 55376 ICLASS: VPCOMPRESSD 55377 CPL: 3 55378 CATEGORY: COMPRESS 55379 EXTENSION: AVX512EVEX 55380 ISA_SET: AVX512F_256 55381 EXCEPTIONS: AVX512-E4 55382 REAL_OPCODE: Y 55383 ATTRIBUTES: MASKOP_EVEX 55384 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 55385 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 55386 IFORM: VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 55387 } 55388 55389 55390 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-1) 55391 { 55392 ICLASS: VPCOMPRESSQ 55393 CPL: 3 55394 CATEGORY: COMPRESS 55395 EXTENSION: AVX512EVEX 55396 ISA_SET: AVX512F_128 55397 EXCEPTIONS: AVX512-E4 55398 REAL_OPCODE: Y 55399 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 55400 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 55401 OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 55402 IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 55403 } 55404 55405 55406 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-2) 55407 { 55408 ICLASS: VPCOMPRESSQ 55409 CPL: 3 55410 CATEGORY: COMPRESS 55411 EXTENSION: AVX512EVEX 55412 ISA_SET: AVX512F_128 55413 EXCEPTIONS: AVX512-E4 55414 REAL_OPCODE: Y 55415 ATTRIBUTES: MASKOP_EVEX 55416 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 55417 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 55418 IFORM: VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 55419 } 55420 55421 55422 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-1) 55423 { 55424 ICLASS: VPCOMPRESSQ 55425 CPL: 3 55426 CATEGORY: COMPRESS 55427 EXTENSION: AVX512EVEX 55428 ISA_SET: AVX512F_256 55429 EXCEPTIONS: AVX512-E4 55430 REAL_OPCODE: Y 55431 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 55432 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 55433 OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 55434 IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 55435 } 55436 55437 55438 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-2) 55439 { 55440 ICLASS: VPCOMPRESSQ 55441 CPL: 3 55442 CATEGORY: COMPRESS 55443 EXTENSION: AVX512EVEX 55444 ISA_SET: AVX512F_256 55445 EXCEPTIONS: AVX512-E4 55446 REAL_OPCODE: Y 55447 ATTRIBUTES: MASKOP_EVEX 55448 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 55449 OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 55450 IFORM: VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 55451 } 55452 55453 55454 # EMITTING VPCONFLICTD (VPCONFLICTD-128-1) 55455 { 55456 ICLASS: VPCONFLICTD 55457 CPL: 3 55458 CATEGORY: CONFLICT 55459 EXTENSION: AVX512EVEX 55460 ISA_SET: AVX512CD_128 55461 EXCEPTIONS: AVX512-E4 55462 REAL_OPCODE: Y 55463 ATTRIBUTES: MASKOP_EVEX 55464 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 55465 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 55466 IFORM: VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 55467 } 55468 55469 { 55470 ICLASS: VPCONFLICTD 55471 CPL: 3 55472 CATEGORY: CONFLICT 55473 EXTENSION: AVX512EVEX 55474 ISA_SET: AVX512CD_128 55475 EXCEPTIONS: AVX512-E4 55476 REAL_OPCODE: Y 55477 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55478 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 55479 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 55480 IFORM: VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 55481 } 55482 55483 55484 # EMITTING VPCONFLICTD (VPCONFLICTD-256-1) 55485 { 55486 ICLASS: VPCONFLICTD 55487 CPL: 3 55488 CATEGORY: CONFLICT 55489 EXTENSION: AVX512EVEX 55490 ISA_SET: AVX512CD_256 55491 EXCEPTIONS: AVX512-E4 55492 REAL_OPCODE: Y 55493 ATTRIBUTES: MASKOP_EVEX 55494 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 55495 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 55496 IFORM: VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 55497 } 55498 55499 { 55500 ICLASS: VPCONFLICTD 55501 CPL: 3 55502 CATEGORY: CONFLICT 55503 EXTENSION: AVX512EVEX 55504 ISA_SET: AVX512CD_256 55505 EXCEPTIONS: AVX512-E4 55506 REAL_OPCODE: Y 55507 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55508 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 55509 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 55510 IFORM: VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 55511 } 55512 55513 55514 # EMITTING VPCONFLICTQ (VPCONFLICTQ-128-1) 55515 { 55516 ICLASS: VPCONFLICTQ 55517 CPL: 3 55518 CATEGORY: CONFLICT 55519 EXTENSION: AVX512EVEX 55520 ISA_SET: AVX512CD_128 55521 EXCEPTIONS: AVX512-E4 55522 REAL_OPCODE: Y 55523 ATTRIBUTES: MASKOP_EVEX 55524 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 55525 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 55526 IFORM: VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 55527 } 55528 55529 { 55530 ICLASS: VPCONFLICTQ 55531 CPL: 3 55532 CATEGORY: CONFLICT 55533 EXTENSION: AVX512EVEX 55534 ISA_SET: AVX512CD_128 55535 EXCEPTIONS: AVX512-E4 55536 REAL_OPCODE: Y 55537 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55538 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 55539 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 55540 IFORM: VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 55541 } 55542 55543 55544 # EMITTING VPCONFLICTQ (VPCONFLICTQ-256-1) 55545 { 55546 ICLASS: VPCONFLICTQ 55547 CPL: 3 55548 CATEGORY: CONFLICT 55549 EXTENSION: AVX512EVEX 55550 ISA_SET: AVX512CD_256 55551 EXCEPTIONS: AVX512-E4 55552 REAL_OPCODE: Y 55553 ATTRIBUTES: MASKOP_EVEX 55554 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 55555 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 55556 IFORM: VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 55557 } 55558 55559 { 55560 ICLASS: VPCONFLICTQ 55561 CPL: 3 55562 CATEGORY: CONFLICT 55563 EXTENSION: AVX512EVEX 55564 ISA_SET: AVX512CD_256 55565 EXCEPTIONS: AVX512-E4 55566 REAL_OPCODE: Y 55567 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55568 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 55569 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 55570 IFORM: VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 55571 } 55572 55573 55574 # EMITTING VPERMD (VPERMD-256-1) 55575 { 55576 ICLASS: VPERMD 55577 CPL: 3 55578 CATEGORY: AVX512 55579 EXTENSION: AVX512EVEX 55580 ISA_SET: AVX512F_256 55581 EXCEPTIONS: AVX512-E4NF 55582 REAL_OPCODE: Y 55583 ATTRIBUTES: MASKOP_EVEX 55584 PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 55585 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 55586 IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 55587 } 55588 55589 { 55590 ICLASS: VPERMD 55591 CPL: 3 55592 CATEGORY: AVX512 55593 EXTENSION: AVX512EVEX 55594 ISA_SET: AVX512F_256 55595 EXCEPTIONS: AVX512-E4NF 55596 REAL_OPCODE: Y 55597 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55598 PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 55599 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 55600 IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 55601 } 55602 55603 55604 # EMITTING VPERMI2D (VPERMI2D-128-1) 55605 { 55606 ICLASS: VPERMI2D 55607 CPL: 3 55608 CATEGORY: AVX512 55609 EXTENSION: AVX512EVEX 55610 ISA_SET: AVX512F_128 55611 EXCEPTIONS: AVX512-E4NF 55612 REAL_OPCODE: Y 55613 ATTRIBUTES: MASKOP_EVEX 55614 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 55615 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 55616 IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 55617 } 55618 55619 { 55620 ICLASS: VPERMI2D 55621 CPL: 3 55622 CATEGORY: AVX512 55623 EXTENSION: AVX512EVEX 55624 ISA_SET: AVX512F_128 55625 EXCEPTIONS: AVX512-E4NF 55626 REAL_OPCODE: Y 55627 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55628 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 55629 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 55630 IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 55631 } 55632 55633 55634 # EMITTING VPERMI2D (VPERMI2D-256-1) 55635 { 55636 ICLASS: VPERMI2D 55637 CPL: 3 55638 CATEGORY: AVX512 55639 EXTENSION: AVX512EVEX 55640 ISA_SET: AVX512F_256 55641 EXCEPTIONS: AVX512-E4NF 55642 REAL_OPCODE: Y 55643 ATTRIBUTES: MASKOP_EVEX 55644 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 55645 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 55646 IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 55647 } 55648 55649 { 55650 ICLASS: VPERMI2D 55651 CPL: 3 55652 CATEGORY: AVX512 55653 EXTENSION: AVX512EVEX 55654 ISA_SET: AVX512F_256 55655 EXCEPTIONS: AVX512-E4NF 55656 REAL_OPCODE: Y 55657 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55658 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 55659 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 55660 IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 55661 } 55662 55663 55664 # EMITTING VPERMI2PD (VPERMI2PD-128-1) 55665 { 55666 ICLASS: VPERMI2PD 55667 CPL: 3 55668 CATEGORY: AVX512 55669 EXTENSION: AVX512EVEX 55670 ISA_SET: AVX512F_128 55671 EXCEPTIONS: AVX512-E4NF 55672 REAL_OPCODE: Y 55673 ATTRIBUTES: MASKOP_EVEX 55674 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 55675 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 55676 IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 55677 } 55678 55679 { 55680 ICLASS: VPERMI2PD 55681 CPL: 3 55682 CATEGORY: AVX512 55683 EXTENSION: AVX512EVEX 55684 ISA_SET: AVX512F_128 55685 EXCEPTIONS: AVX512-E4NF 55686 REAL_OPCODE: Y 55687 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55688 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 55689 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 55690 IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 55691 } 55692 55693 55694 # EMITTING VPERMI2PD (VPERMI2PD-256-1) 55695 { 55696 ICLASS: VPERMI2PD 55697 CPL: 3 55698 CATEGORY: AVX512 55699 EXTENSION: AVX512EVEX 55700 ISA_SET: AVX512F_256 55701 EXCEPTIONS: AVX512-E4NF 55702 REAL_OPCODE: Y 55703 ATTRIBUTES: MASKOP_EVEX 55704 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 55705 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 55706 IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 55707 } 55708 55709 { 55710 ICLASS: VPERMI2PD 55711 CPL: 3 55712 CATEGORY: AVX512 55713 EXTENSION: AVX512EVEX 55714 ISA_SET: AVX512F_256 55715 EXCEPTIONS: AVX512-E4NF 55716 REAL_OPCODE: Y 55717 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55718 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 55719 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 55720 IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 55721 } 55722 55723 55724 # EMITTING VPERMI2PS (VPERMI2PS-128-1) 55725 { 55726 ICLASS: VPERMI2PS 55727 CPL: 3 55728 CATEGORY: AVX512 55729 EXTENSION: AVX512EVEX 55730 ISA_SET: AVX512F_128 55731 EXCEPTIONS: AVX512-E4NF 55732 REAL_OPCODE: Y 55733 ATTRIBUTES: MASKOP_EVEX 55734 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 55735 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 55736 IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 55737 } 55738 55739 { 55740 ICLASS: VPERMI2PS 55741 CPL: 3 55742 CATEGORY: AVX512 55743 EXTENSION: AVX512EVEX 55744 ISA_SET: AVX512F_128 55745 EXCEPTIONS: AVX512-E4NF 55746 REAL_OPCODE: Y 55747 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55748 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 55749 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 55750 IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 55751 } 55752 55753 55754 # EMITTING VPERMI2PS (VPERMI2PS-256-1) 55755 { 55756 ICLASS: VPERMI2PS 55757 CPL: 3 55758 CATEGORY: AVX512 55759 EXTENSION: AVX512EVEX 55760 ISA_SET: AVX512F_256 55761 EXCEPTIONS: AVX512-E4NF 55762 REAL_OPCODE: Y 55763 ATTRIBUTES: MASKOP_EVEX 55764 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 55765 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 55766 IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 55767 } 55768 55769 { 55770 ICLASS: VPERMI2PS 55771 CPL: 3 55772 CATEGORY: AVX512 55773 EXTENSION: AVX512EVEX 55774 ISA_SET: AVX512F_256 55775 EXCEPTIONS: AVX512-E4NF 55776 REAL_OPCODE: Y 55777 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55778 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 55779 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 55780 IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 55781 } 55782 55783 55784 # EMITTING VPERMI2Q (VPERMI2Q-128-1) 55785 { 55786 ICLASS: VPERMI2Q 55787 CPL: 3 55788 CATEGORY: AVX512 55789 EXTENSION: AVX512EVEX 55790 ISA_SET: AVX512F_128 55791 EXCEPTIONS: AVX512-E4NF 55792 REAL_OPCODE: Y 55793 ATTRIBUTES: MASKOP_EVEX 55794 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 55795 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 55796 IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 55797 } 55798 55799 { 55800 ICLASS: VPERMI2Q 55801 CPL: 3 55802 CATEGORY: AVX512 55803 EXTENSION: AVX512EVEX 55804 ISA_SET: AVX512F_128 55805 EXCEPTIONS: AVX512-E4NF 55806 REAL_OPCODE: Y 55807 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55808 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 55809 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 55810 IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 55811 } 55812 55813 55814 # EMITTING VPERMI2Q (VPERMI2Q-256-1) 55815 { 55816 ICLASS: VPERMI2Q 55817 CPL: 3 55818 CATEGORY: AVX512 55819 EXTENSION: AVX512EVEX 55820 ISA_SET: AVX512F_256 55821 EXCEPTIONS: AVX512-E4NF 55822 REAL_OPCODE: Y 55823 ATTRIBUTES: MASKOP_EVEX 55824 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 55825 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 55826 IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 55827 } 55828 55829 { 55830 ICLASS: VPERMI2Q 55831 CPL: 3 55832 CATEGORY: AVX512 55833 EXTENSION: AVX512EVEX 55834 ISA_SET: AVX512F_256 55835 EXCEPTIONS: AVX512-E4NF 55836 REAL_OPCODE: Y 55837 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55838 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 55839 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 55840 IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 55841 } 55842 55843 55844 # EMITTING VPERMI2W (VPERMI2W-128-1) 55845 { 55846 ICLASS: VPERMI2W 55847 CPL: 3 55848 CATEGORY: AVX512 55849 EXTENSION: AVX512EVEX 55850 ISA_SET: AVX512BW_128 55851 EXCEPTIONS: AVX512-E4NF 55852 REAL_OPCODE: Y 55853 ATTRIBUTES: MASKOP_EVEX 55854 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 55855 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 55856 IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 55857 } 55858 55859 { 55860 ICLASS: VPERMI2W 55861 CPL: 3 55862 CATEGORY: AVX512 55863 EXTENSION: AVX512EVEX 55864 ISA_SET: AVX512BW_128 55865 EXCEPTIONS: AVX512-E4NF 55866 REAL_OPCODE: Y 55867 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 55868 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 55869 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 55870 IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 55871 } 55872 55873 55874 # EMITTING VPERMI2W (VPERMI2W-256-1) 55875 { 55876 ICLASS: VPERMI2W 55877 CPL: 3 55878 CATEGORY: AVX512 55879 EXTENSION: AVX512EVEX 55880 ISA_SET: AVX512BW_256 55881 EXCEPTIONS: AVX512-E4NF 55882 REAL_OPCODE: Y 55883 ATTRIBUTES: MASKOP_EVEX 55884 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 55885 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 55886 IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 55887 } 55888 55889 { 55890 ICLASS: VPERMI2W 55891 CPL: 3 55892 CATEGORY: AVX512 55893 EXTENSION: AVX512EVEX 55894 ISA_SET: AVX512BW_256 55895 EXCEPTIONS: AVX512-E4NF 55896 REAL_OPCODE: Y 55897 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 55898 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 55899 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 55900 IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 55901 } 55902 55903 55904 # EMITTING VPERMI2W (VPERMI2W-512-1) 55905 { 55906 ICLASS: VPERMI2W 55907 CPL: 3 55908 CATEGORY: AVX512 55909 EXTENSION: AVX512EVEX 55910 ISA_SET: AVX512BW_512 55911 EXCEPTIONS: AVX512-E4NF 55912 REAL_OPCODE: Y 55913 ATTRIBUTES: MASKOP_EVEX 55914 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 55915 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 55916 IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 55917 } 55918 55919 { 55920 ICLASS: VPERMI2W 55921 CPL: 3 55922 CATEGORY: AVX512 55923 EXTENSION: AVX512EVEX 55924 ISA_SET: AVX512BW_512 55925 EXCEPTIONS: AVX512-E4NF 55926 REAL_OPCODE: Y 55927 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 55928 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 55929 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 55930 IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 55931 } 55932 55933 55934 # EMITTING VPERMILPD (VPERMILPD-128-1) 55935 { 55936 ICLASS: VPERMILPD 55937 CPL: 3 55938 CATEGORY: AVX512 55939 EXTENSION: AVX512EVEX 55940 ISA_SET: AVX512F_128 55941 EXCEPTIONS: AVX512-E4NF 55942 REAL_OPCODE: Y 55943 ATTRIBUTES: MASKOP_EVEX 55944 PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() 55945 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b 55946 IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 55947 } 55948 55949 { 55950 ICLASS: VPERMILPD 55951 CPL: 3 55952 CATEGORY: AVX512 55953 EXTENSION: AVX512EVEX 55954 ISA_SET: AVX512F_128 55955 EXCEPTIONS: AVX512-E4NF 55956 REAL_OPCODE: Y 55957 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55958 PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 55959 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 55960 IFORM: VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 55961 } 55962 55963 55964 # EMITTING VPERMILPD (VPERMILPD-128-2) 55965 { 55966 ICLASS: VPERMILPD 55967 CPL: 3 55968 CATEGORY: AVX512 55969 EXTENSION: AVX512EVEX 55970 ISA_SET: AVX512F_128 55971 EXCEPTIONS: AVX512-E4NF 55972 REAL_OPCODE: Y 55973 ATTRIBUTES: MASKOP_EVEX 55974 PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 55975 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 55976 IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 55977 } 55978 55979 { 55980 ICLASS: VPERMILPD 55981 CPL: 3 55982 CATEGORY: AVX512 55983 EXTENSION: AVX512EVEX 55984 ISA_SET: AVX512F_128 55985 EXCEPTIONS: AVX512-E4NF 55986 REAL_OPCODE: Y 55987 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55988 PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 55989 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 55990 IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 55991 } 55992 55993 55994 # EMITTING VPERMILPD (VPERMILPD-256-1) 55995 { 55996 ICLASS: VPERMILPD 55997 CPL: 3 55998 CATEGORY: AVX512 55999 EXTENSION: AVX512EVEX 56000 ISA_SET: AVX512F_256 56001 EXCEPTIONS: AVX512-E4NF 56002 REAL_OPCODE: Y 56003 ATTRIBUTES: MASKOP_EVEX 56004 PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 56005 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b 56006 IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 56007 } 56008 56009 { 56010 ICLASS: VPERMILPD 56011 CPL: 3 56012 CATEGORY: AVX512 56013 EXTENSION: AVX512EVEX 56014 ISA_SET: AVX512F_256 56015 EXCEPTIONS: AVX512-E4NF 56016 REAL_OPCODE: Y 56017 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56018 PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 56019 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 56020 IFORM: VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 56021 } 56022 56023 56024 # EMITTING VPERMILPD (VPERMILPD-256-2) 56025 { 56026 ICLASS: VPERMILPD 56027 CPL: 3 56028 CATEGORY: AVX512 56029 EXTENSION: AVX512EVEX 56030 ISA_SET: AVX512F_256 56031 EXCEPTIONS: AVX512-E4NF 56032 REAL_OPCODE: Y 56033 ATTRIBUTES: MASKOP_EVEX 56034 PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 56035 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 56036 IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 56037 } 56038 56039 { 56040 ICLASS: VPERMILPD 56041 CPL: 3 56042 CATEGORY: AVX512 56043 EXTENSION: AVX512EVEX 56044 ISA_SET: AVX512F_256 56045 EXCEPTIONS: AVX512-E4NF 56046 REAL_OPCODE: Y 56047 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56048 PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 56049 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 56050 IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 56051 } 56052 56053 56054 # EMITTING VPERMILPS (VPERMILPS-128-1) 56055 { 56056 ICLASS: VPERMILPS 56057 CPL: 3 56058 CATEGORY: AVX512 56059 EXTENSION: AVX512EVEX 56060 ISA_SET: AVX512F_128 56061 EXCEPTIONS: AVX512-E4NF 56062 REAL_OPCODE: Y 56063 ATTRIBUTES: MASKOP_EVEX 56064 PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 56065 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b 56066 IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 56067 } 56068 56069 { 56070 ICLASS: VPERMILPS 56071 CPL: 3 56072 CATEGORY: AVX512 56073 EXTENSION: AVX512EVEX 56074 ISA_SET: AVX512F_128 56075 EXCEPTIONS: AVX512-E4NF 56076 REAL_OPCODE: Y 56077 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56078 PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 56079 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 56080 IFORM: VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 56081 } 56082 56083 56084 # EMITTING VPERMILPS (VPERMILPS-128-2) 56085 { 56086 ICLASS: VPERMILPS 56087 CPL: 3 56088 CATEGORY: AVX512 56089 EXTENSION: AVX512EVEX 56090 ISA_SET: AVX512F_128 56091 EXCEPTIONS: AVX512-E4NF 56092 REAL_OPCODE: Y 56093 ATTRIBUTES: MASKOP_EVEX 56094 PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 56095 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 56096 IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 56097 } 56098 56099 { 56100 ICLASS: VPERMILPS 56101 CPL: 3 56102 CATEGORY: AVX512 56103 EXTENSION: AVX512EVEX 56104 ISA_SET: AVX512F_128 56105 EXCEPTIONS: AVX512-E4NF 56106 REAL_OPCODE: Y 56107 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56108 PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 56109 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 56110 IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 56111 } 56112 56113 56114 # EMITTING VPERMILPS (VPERMILPS-256-1) 56115 { 56116 ICLASS: VPERMILPS 56117 CPL: 3 56118 CATEGORY: AVX512 56119 EXTENSION: AVX512EVEX 56120 ISA_SET: AVX512F_256 56121 EXCEPTIONS: AVX512-E4NF 56122 REAL_OPCODE: Y 56123 ATTRIBUTES: MASKOP_EVEX 56124 PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 56125 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b 56126 IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 56127 } 56128 56129 { 56130 ICLASS: VPERMILPS 56131 CPL: 3 56132 CATEGORY: AVX512 56133 EXTENSION: AVX512EVEX 56134 ISA_SET: AVX512F_256 56135 EXCEPTIONS: AVX512-E4NF 56136 REAL_OPCODE: Y 56137 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56138 PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 56139 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 56140 IFORM: VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 56141 } 56142 56143 56144 # EMITTING VPERMILPS (VPERMILPS-256-2) 56145 { 56146 ICLASS: VPERMILPS 56147 CPL: 3 56148 CATEGORY: AVX512 56149 EXTENSION: AVX512EVEX 56150 ISA_SET: AVX512F_256 56151 EXCEPTIONS: AVX512-E4NF 56152 REAL_OPCODE: Y 56153 ATTRIBUTES: MASKOP_EVEX 56154 PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 56155 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 56156 IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 56157 } 56158 56159 { 56160 ICLASS: VPERMILPS 56161 CPL: 3 56162 CATEGORY: AVX512 56163 EXTENSION: AVX512EVEX 56164 ISA_SET: AVX512F_256 56165 EXCEPTIONS: AVX512-E4NF 56166 REAL_OPCODE: Y 56167 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56168 PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 56169 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 56170 IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 56171 } 56172 56173 56174 # EMITTING VPERMPD (VPERMPD-256-1) 56175 { 56176 ICLASS: VPERMPD 56177 CPL: 3 56178 CATEGORY: AVX512 56179 EXTENSION: AVX512EVEX 56180 ISA_SET: AVX512F_256 56181 EXCEPTIONS: AVX512-E4NF 56182 REAL_OPCODE: Y 56183 ATTRIBUTES: MASKOP_EVEX 56184 PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 56185 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b 56186 IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 56187 } 56188 56189 { 56190 ICLASS: VPERMPD 56191 CPL: 3 56192 CATEGORY: AVX512 56193 EXTENSION: AVX512EVEX 56194 ISA_SET: AVX512F_256 56195 EXCEPTIONS: AVX512-E4NF 56196 REAL_OPCODE: Y 56197 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56198 PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 56199 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 56200 IFORM: VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 56201 } 56202 56203 56204 # EMITTING VPERMPD (VPERMPD-256-2) 56205 { 56206 ICLASS: VPERMPD 56207 CPL: 3 56208 CATEGORY: AVX512 56209 EXTENSION: AVX512EVEX 56210 ISA_SET: AVX512F_256 56211 EXCEPTIONS: AVX512-E4NF 56212 REAL_OPCODE: Y 56213 ATTRIBUTES: MASKOP_EVEX 56214 PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 56215 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 56216 IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 56217 } 56218 56219 { 56220 ICLASS: VPERMPD 56221 CPL: 3 56222 CATEGORY: AVX512 56223 EXTENSION: AVX512EVEX 56224 ISA_SET: AVX512F_256 56225 EXCEPTIONS: AVX512-E4NF 56226 REAL_OPCODE: Y 56227 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56228 PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 56229 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 56230 IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 56231 } 56232 56233 56234 # EMITTING VPERMPS (VPERMPS-256-1) 56235 { 56236 ICLASS: VPERMPS 56237 CPL: 3 56238 CATEGORY: AVX512 56239 EXTENSION: AVX512EVEX 56240 ISA_SET: AVX512F_256 56241 EXCEPTIONS: AVX512-E4NF 56242 REAL_OPCODE: Y 56243 ATTRIBUTES: MASKOP_EVEX 56244 PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 56245 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 56246 IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 56247 } 56248 56249 { 56250 ICLASS: VPERMPS 56251 CPL: 3 56252 CATEGORY: AVX512 56253 EXTENSION: AVX512EVEX 56254 ISA_SET: AVX512F_256 56255 EXCEPTIONS: AVX512-E4NF 56256 REAL_OPCODE: Y 56257 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56258 PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 56259 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 56260 IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 56261 } 56262 56263 56264 # EMITTING VPERMQ (VPERMQ-256-1) 56265 { 56266 ICLASS: VPERMQ 56267 CPL: 3 56268 CATEGORY: AVX512 56269 EXTENSION: AVX512EVEX 56270 ISA_SET: AVX512F_256 56271 EXCEPTIONS: AVX512-E4NF 56272 REAL_OPCODE: Y 56273 ATTRIBUTES: MASKOP_EVEX 56274 PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 56275 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 56276 IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 56277 } 56278 56279 { 56280 ICLASS: VPERMQ 56281 CPL: 3 56282 CATEGORY: AVX512 56283 EXTENSION: AVX512EVEX 56284 ISA_SET: AVX512F_256 56285 EXCEPTIONS: AVX512-E4NF 56286 REAL_OPCODE: Y 56287 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56288 PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 56289 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 56290 IFORM: VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 56291 } 56292 56293 56294 # EMITTING VPERMQ (VPERMQ-256-2) 56295 { 56296 ICLASS: VPERMQ 56297 CPL: 3 56298 CATEGORY: AVX512 56299 EXTENSION: AVX512EVEX 56300 ISA_SET: AVX512F_256 56301 EXCEPTIONS: AVX512-E4NF 56302 REAL_OPCODE: Y 56303 ATTRIBUTES: MASKOP_EVEX 56304 PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 56305 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 56306 IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 56307 } 56308 56309 { 56310 ICLASS: VPERMQ 56311 CPL: 3 56312 CATEGORY: AVX512 56313 EXTENSION: AVX512EVEX 56314 ISA_SET: AVX512F_256 56315 EXCEPTIONS: AVX512-E4NF 56316 REAL_OPCODE: Y 56317 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56318 PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 56319 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 56320 IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 56321 } 56322 56323 56324 # EMITTING VPERMT2D (VPERMT2D-128-1) 56325 { 56326 ICLASS: VPERMT2D 56327 CPL: 3 56328 CATEGORY: AVX512 56329 EXTENSION: AVX512EVEX 56330 ISA_SET: AVX512F_128 56331 EXCEPTIONS: AVX512-E4NF 56332 REAL_OPCODE: Y 56333 ATTRIBUTES: MASKOP_EVEX 56334 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 56335 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 56336 IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 56337 } 56338 56339 { 56340 ICLASS: VPERMT2D 56341 CPL: 3 56342 CATEGORY: AVX512 56343 EXTENSION: AVX512EVEX 56344 ISA_SET: AVX512F_128 56345 EXCEPTIONS: AVX512-E4NF 56346 REAL_OPCODE: Y 56347 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56348 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 56349 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 56350 IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 56351 } 56352 56353 56354 # EMITTING VPERMT2D (VPERMT2D-256-1) 56355 { 56356 ICLASS: VPERMT2D 56357 CPL: 3 56358 CATEGORY: AVX512 56359 EXTENSION: AVX512EVEX 56360 ISA_SET: AVX512F_256 56361 EXCEPTIONS: AVX512-E4NF 56362 REAL_OPCODE: Y 56363 ATTRIBUTES: MASKOP_EVEX 56364 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 56365 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 56366 IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 56367 } 56368 56369 { 56370 ICLASS: VPERMT2D 56371 CPL: 3 56372 CATEGORY: AVX512 56373 EXTENSION: AVX512EVEX 56374 ISA_SET: AVX512F_256 56375 EXCEPTIONS: AVX512-E4NF 56376 REAL_OPCODE: Y 56377 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56378 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 56379 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 56380 IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 56381 } 56382 56383 56384 # EMITTING VPERMT2PD (VPERMT2PD-128-1) 56385 { 56386 ICLASS: VPERMT2PD 56387 CPL: 3 56388 CATEGORY: AVX512 56389 EXTENSION: AVX512EVEX 56390 ISA_SET: AVX512F_128 56391 EXCEPTIONS: AVX512-E4NF 56392 REAL_OPCODE: Y 56393 ATTRIBUTES: MASKOP_EVEX 56394 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 56395 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 56396 IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 56397 } 56398 56399 { 56400 ICLASS: VPERMT2PD 56401 CPL: 3 56402 CATEGORY: AVX512 56403 EXTENSION: AVX512EVEX 56404 ISA_SET: AVX512F_128 56405 EXCEPTIONS: AVX512-E4NF 56406 REAL_OPCODE: Y 56407 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56408 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 56409 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 56410 IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 56411 } 56412 56413 56414 # EMITTING VPERMT2PD (VPERMT2PD-256-1) 56415 { 56416 ICLASS: VPERMT2PD 56417 CPL: 3 56418 CATEGORY: AVX512 56419 EXTENSION: AVX512EVEX 56420 ISA_SET: AVX512F_256 56421 EXCEPTIONS: AVX512-E4NF 56422 REAL_OPCODE: Y 56423 ATTRIBUTES: MASKOP_EVEX 56424 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 56425 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 56426 IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 56427 } 56428 56429 { 56430 ICLASS: VPERMT2PD 56431 CPL: 3 56432 CATEGORY: AVX512 56433 EXTENSION: AVX512EVEX 56434 ISA_SET: AVX512F_256 56435 EXCEPTIONS: AVX512-E4NF 56436 REAL_OPCODE: Y 56437 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56438 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 56439 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 56440 IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 56441 } 56442 56443 56444 # EMITTING VPERMT2PS (VPERMT2PS-128-1) 56445 { 56446 ICLASS: VPERMT2PS 56447 CPL: 3 56448 CATEGORY: AVX512 56449 EXTENSION: AVX512EVEX 56450 ISA_SET: AVX512F_128 56451 EXCEPTIONS: AVX512-E4NF 56452 REAL_OPCODE: Y 56453 ATTRIBUTES: MASKOP_EVEX 56454 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 56455 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 56456 IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 56457 } 56458 56459 { 56460 ICLASS: VPERMT2PS 56461 CPL: 3 56462 CATEGORY: AVX512 56463 EXTENSION: AVX512EVEX 56464 ISA_SET: AVX512F_128 56465 EXCEPTIONS: AVX512-E4NF 56466 REAL_OPCODE: Y 56467 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56468 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 56469 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 56470 IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 56471 } 56472 56473 56474 # EMITTING VPERMT2PS (VPERMT2PS-256-1) 56475 { 56476 ICLASS: VPERMT2PS 56477 CPL: 3 56478 CATEGORY: AVX512 56479 EXTENSION: AVX512EVEX 56480 ISA_SET: AVX512F_256 56481 EXCEPTIONS: AVX512-E4NF 56482 REAL_OPCODE: Y 56483 ATTRIBUTES: MASKOP_EVEX 56484 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 56485 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 56486 IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 56487 } 56488 56489 { 56490 ICLASS: VPERMT2PS 56491 CPL: 3 56492 CATEGORY: AVX512 56493 EXTENSION: AVX512EVEX 56494 ISA_SET: AVX512F_256 56495 EXCEPTIONS: AVX512-E4NF 56496 REAL_OPCODE: Y 56497 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56498 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 56499 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 56500 IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 56501 } 56502 56503 56504 # EMITTING VPERMT2Q (VPERMT2Q-128-1) 56505 { 56506 ICLASS: VPERMT2Q 56507 CPL: 3 56508 CATEGORY: AVX512 56509 EXTENSION: AVX512EVEX 56510 ISA_SET: AVX512F_128 56511 EXCEPTIONS: AVX512-E4NF 56512 REAL_OPCODE: Y 56513 ATTRIBUTES: MASKOP_EVEX 56514 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 56515 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 56516 IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 56517 } 56518 56519 { 56520 ICLASS: VPERMT2Q 56521 CPL: 3 56522 CATEGORY: AVX512 56523 EXTENSION: AVX512EVEX 56524 ISA_SET: AVX512F_128 56525 EXCEPTIONS: AVX512-E4NF 56526 REAL_OPCODE: Y 56527 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56528 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 56529 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 56530 IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 56531 } 56532 56533 56534 # EMITTING VPERMT2Q (VPERMT2Q-256-1) 56535 { 56536 ICLASS: VPERMT2Q 56537 CPL: 3 56538 CATEGORY: AVX512 56539 EXTENSION: AVX512EVEX 56540 ISA_SET: AVX512F_256 56541 EXCEPTIONS: AVX512-E4NF 56542 REAL_OPCODE: Y 56543 ATTRIBUTES: MASKOP_EVEX 56544 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 56545 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 56546 IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 56547 } 56548 56549 { 56550 ICLASS: VPERMT2Q 56551 CPL: 3 56552 CATEGORY: AVX512 56553 EXTENSION: AVX512EVEX 56554 ISA_SET: AVX512F_256 56555 EXCEPTIONS: AVX512-E4NF 56556 REAL_OPCODE: Y 56557 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56558 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 56559 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 56560 IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 56561 } 56562 56563 56564 # EMITTING VPERMT2W (VPERMT2W-128-1) 56565 { 56566 ICLASS: VPERMT2W 56567 CPL: 3 56568 CATEGORY: AVX512 56569 EXTENSION: AVX512EVEX 56570 ISA_SET: AVX512BW_128 56571 EXCEPTIONS: AVX512-E4NF 56572 REAL_OPCODE: Y 56573 ATTRIBUTES: MASKOP_EVEX 56574 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 56575 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 56576 IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 56577 } 56578 56579 { 56580 ICLASS: VPERMT2W 56581 CPL: 3 56582 CATEGORY: AVX512 56583 EXTENSION: AVX512EVEX 56584 ISA_SET: AVX512BW_128 56585 EXCEPTIONS: AVX512-E4NF 56586 REAL_OPCODE: Y 56587 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 56588 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 56589 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 56590 IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 56591 } 56592 56593 56594 # EMITTING VPERMT2W (VPERMT2W-256-1) 56595 { 56596 ICLASS: VPERMT2W 56597 CPL: 3 56598 CATEGORY: AVX512 56599 EXTENSION: AVX512EVEX 56600 ISA_SET: AVX512BW_256 56601 EXCEPTIONS: AVX512-E4NF 56602 REAL_OPCODE: Y 56603 ATTRIBUTES: MASKOP_EVEX 56604 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 56605 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 56606 IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 56607 } 56608 56609 { 56610 ICLASS: VPERMT2W 56611 CPL: 3 56612 CATEGORY: AVX512 56613 EXTENSION: AVX512EVEX 56614 ISA_SET: AVX512BW_256 56615 EXCEPTIONS: AVX512-E4NF 56616 REAL_OPCODE: Y 56617 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 56618 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 56619 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 56620 IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 56621 } 56622 56623 56624 # EMITTING VPERMT2W (VPERMT2W-512-1) 56625 { 56626 ICLASS: VPERMT2W 56627 CPL: 3 56628 CATEGORY: AVX512 56629 EXTENSION: AVX512EVEX 56630 ISA_SET: AVX512BW_512 56631 EXCEPTIONS: AVX512-E4NF 56632 REAL_OPCODE: Y 56633 ATTRIBUTES: MASKOP_EVEX 56634 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 56635 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 56636 IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 56637 } 56638 56639 { 56640 ICLASS: VPERMT2W 56641 CPL: 3 56642 CATEGORY: AVX512 56643 EXTENSION: AVX512EVEX 56644 ISA_SET: AVX512BW_512 56645 EXCEPTIONS: AVX512-E4NF 56646 REAL_OPCODE: Y 56647 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 56648 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 56649 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 56650 IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 56651 } 56652 56653 56654 # EMITTING VPERMW (VPERMW-128-1) 56655 { 56656 ICLASS: VPERMW 56657 CPL: 3 56658 CATEGORY: AVX512 56659 EXTENSION: AVX512EVEX 56660 ISA_SET: AVX512BW_128 56661 EXCEPTIONS: AVX512-E4NF 56662 REAL_OPCODE: Y 56663 ATTRIBUTES: MASKOP_EVEX 56664 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 56665 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 56666 IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 56667 } 56668 56669 { 56670 ICLASS: VPERMW 56671 CPL: 3 56672 CATEGORY: AVX512 56673 EXTENSION: AVX512EVEX 56674 ISA_SET: AVX512BW_128 56675 EXCEPTIONS: AVX512-E4NF 56676 REAL_OPCODE: Y 56677 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 56678 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 56679 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 56680 IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 56681 } 56682 56683 56684 # EMITTING VPERMW (VPERMW-256-1) 56685 { 56686 ICLASS: VPERMW 56687 CPL: 3 56688 CATEGORY: AVX512 56689 EXTENSION: AVX512EVEX 56690 ISA_SET: AVX512BW_256 56691 EXCEPTIONS: AVX512-E4NF 56692 REAL_OPCODE: Y 56693 ATTRIBUTES: MASKOP_EVEX 56694 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 56695 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 56696 IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 56697 } 56698 56699 { 56700 ICLASS: VPERMW 56701 CPL: 3 56702 CATEGORY: AVX512 56703 EXTENSION: AVX512EVEX 56704 ISA_SET: AVX512BW_256 56705 EXCEPTIONS: AVX512-E4NF 56706 REAL_OPCODE: Y 56707 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 56708 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 56709 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 56710 IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 56711 } 56712 56713 56714 # EMITTING VPERMW (VPERMW-512-1) 56715 { 56716 ICLASS: VPERMW 56717 CPL: 3 56718 CATEGORY: AVX512 56719 EXTENSION: AVX512EVEX 56720 ISA_SET: AVX512BW_512 56721 EXCEPTIONS: AVX512-E4NF 56722 REAL_OPCODE: Y 56723 ATTRIBUTES: MASKOP_EVEX 56724 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 56725 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 56726 IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 56727 } 56728 56729 { 56730 ICLASS: VPERMW 56731 CPL: 3 56732 CATEGORY: AVX512 56733 EXTENSION: AVX512EVEX 56734 ISA_SET: AVX512BW_512 56735 EXCEPTIONS: AVX512-E4NF 56736 REAL_OPCODE: Y 56737 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 56738 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 56739 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 56740 IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 56741 } 56742 56743 56744 # EMITTING VPEXPANDD (VPEXPANDD-128-1) 56745 { 56746 ICLASS: VPEXPANDD 56747 CPL: 3 56748 CATEGORY: EXPAND 56749 EXTENSION: AVX512EVEX 56750 ISA_SET: AVX512F_128 56751 EXCEPTIONS: AVX512-E4 56752 REAL_OPCODE: Y 56753 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 56754 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 56755 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 56756 IFORM: VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 56757 } 56758 56759 56760 # EMITTING VPEXPANDD (VPEXPANDD-128-2) 56761 { 56762 ICLASS: VPEXPANDD 56763 CPL: 3 56764 CATEGORY: EXPAND 56765 EXTENSION: AVX512EVEX 56766 ISA_SET: AVX512F_128 56767 EXCEPTIONS: AVX512-E4 56768 REAL_OPCODE: Y 56769 ATTRIBUTES: MASKOP_EVEX 56770 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 56771 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 56772 IFORM: VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 56773 } 56774 56775 56776 # EMITTING VPEXPANDD (VPEXPANDD-256-1) 56777 { 56778 ICLASS: VPEXPANDD 56779 CPL: 3 56780 CATEGORY: EXPAND 56781 EXTENSION: AVX512EVEX 56782 ISA_SET: AVX512F_256 56783 EXCEPTIONS: AVX512-E4 56784 REAL_OPCODE: Y 56785 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 56786 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 56787 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 56788 IFORM: VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 56789 } 56790 56791 56792 # EMITTING VPEXPANDD (VPEXPANDD-256-2) 56793 { 56794 ICLASS: VPEXPANDD 56795 CPL: 3 56796 CATEGORY: EXPAND 56797 EXTENSION: AVX512EVEX 56798 ISA_SET: AVX512F_256 56799 EXCEPTIONS: AVX512-E4 56800 REAL_OPCODE: Y 56801 ATTRIBUTES: MASKOP_EVEX 56802 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 56803 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 56804 IFORM: VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 56805 } 56806 56807 56808 # EMITTING VPEXPANDQ (VPEXPANDQ-128-1) 56809 { 56810 ICLASS: VPEXPANDQ 56811 CPL: 3 56812 CATEGORY: EXPAND 56813 EXTENSION: AVX512EVEX 56814 ISA_SET: AVX512F_128 56815 EXCEPTIONS: AVX512-E4 56816 REAL_OPCODE: Y 56817 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 56818 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 56819 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 56820 IFORM: VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 56821 } 56822 56823 56824 # EMITTING VPEXPANDQ (VPEXPANDQ-128-2) 56825 { 56826 ICLASS: VPEXPANDQ 56827 CPL: 3 56828 CATEGORY: EXPAND 56829 EXTENSION: AVX512EVEX 56830 ISA_SET: AVX512F_128 56831 EXCEPTIONS: AVX512-E4 56832 REAL_OPCODE: Y 56833 ATTRIBUTES: MASKOP_EVEX 56834 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 56835 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 56836 IFORM: VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 56837 } 56838 56839 56840 # EMITTING VPEXPANDQ (VPEXPANDQ-256-1) 56841 { 56842 ICLASS: VPEXPANDQ 56843 CPL: 3 56844 CATEGORY: EXPAND 56845 EXTENSION: AVX512EVEX 56846 ISA_SET: AVX512F_256 56847 EXCEPTIONS: AVX512-E4 56848 REAL_OPCODE: Y 56849 ATTRIBUTES: MASK_VARIABLE_MEMOP MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT 56850 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 56851 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 56852 IFORM: VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 56853 } 56854 56855 56856 # EMITTING VPEXPANDQ (VPEXPANDQ-256-2) 56857 { 56858 ICLASS: VPEXPANDQ 56859 CPL: 3 56860 CATEGORY: EXPAND 56861 EXTENSION: AVX512EVEX 56862 ISA_SET: AVX512F_256 56863 EXCEPTIONS: AVX512-E4 56864 REAL_OPCODE: Y 56865 ATTRIBUTES: MASKOP_EVEX 56866 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 56867 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 56868 IFORM: VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 56869 } 56870 56871 56872 # EMITTING VPEXTRB (VPEXTRB-128-1) 56873 { 56874 ICLASS: VPEXTRB 56875 CPL: 3 56876 CATEGORY: AVX512 56877 EXTENSION: AVX512EVEX 56878 ISA_SET: AVX512BW_128N 56879 EXCEPTIONS: AVX512-E9NF 56880 REAL_OPCODE: Y 56881 PATTERN: EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() 56882 OPERANDS: REG0=GPR32_B():w:d:u8 REG1=XMM_R3():r:dq:u8 IMM0:r:b 56883 IFORM: VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 56884 } 56885 56886 { 56887 ICLASS: VPEXTRB 56888 CPL: 3 56889 CATEGORY: AVX512 56890 EXTENSION: AVX512EVEX 56891 ISA_SET: AVX512BW_128N 56892 EXCEPTIONS: AVX512-E9NF 56893 REAL_OPCODE: Y 56894 ATTRIBUTES: DISP8_GPR_WRITER_STORE_BYTE 56895 PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE() 56896 OPERANDS: MEM0:w:b:u8 REG0=XMM_R3():r:dq:u8 IMM0:r:b 56897 IFORM: VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 56898 } 56899 56900 56901 # EMITTING VPEXTRD (VPEXTRD-128-1) 56902 { 56903 ICLASS: VPEXTRD 56904 CPL: 3 56905 CATEGORY: AVX512 56906 EXTENSION: AVX512EVEX 56907 ISA_SET: AVX512DQ_128N 56908 EXCEPTIONS: AVX512-E9NF 56909 REAL_OPCODE: Y 56910 PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() 56911 OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b 56912 IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 56913 } 56914 56915 { 56916 ICLASS: VPEXTRD 56917 CPL: 3 56918 CATEGORY: AVX512 56919 EXTENSION: AVX512EVEX 56920 ISA_SET: AVX512DQ_128N 56921 EXCEPTIONS: AVX512-E9NF 56922 REAL_OPCODE: Y 56923 ATTRIBUTES: DISP8_GPR_WRITER_STORE 56924 PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() 56925 OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b 56926 IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 56927 } 56928 56929 56930 # EMITTING VPEXTRQ (VPEXTRQ-128-1) 56931 { 56932 ICLASS: VPEXTRQ 56933 CPL: 3 56934 CATEGORY: AVX512 56935 EXTENSION: AVX512EVEX 56936 ISA_SET: AVX512DQ_128N 56937 EXCEPTIONS: AVX512-E9NF 56938 REAL_OPCODE: Y 56939 PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() 56940 OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 IMM0:r:b 56941 IFORM: VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 56942 } 56943 56944 { 56945 ICLASS: VPEXTRQ 56946 CPL: 3 56947 CATEGORY: AVX512 56948 EXTENSION: AVX512EVEX 56949 ISA_SET: AVX512DQ_128N 56950 EXCEPTIONS: AVX512-E9NF 56951 REAL_OPCODE: Y 56952 ATTRIBUTES: DISP8_GPR_WRITER_STORE 56953 PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() 56954 OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IMM0:r:b 56955 IFORM: VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 56956 } 56957 56958 56959 # EMITTING VPEXTRW (VPEXTRW-128-1) 56960 { 56961 ICLASS: VPEXTRW 56962 CPL: 3 56963 CATEGORY: AVX512 56964 EXTENSION: AVX512EVEX 56965 ISA_SET: AVX512BW_128N 56966 EXCEPTIONS: AVX512-E9NF 56967 REAL_OPCODE: Y 56968 PATTERN: EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() 56969 OPERANDS: REG0=GPR32_B():w:d:u16 REG1=XMM_R3():r:dq:u16 IMM0:r:b 56970 IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 56971 } 56972 56973 { 56974 ICLASS: VPEXTRW 56975 CPL: 3 56976 CATEGORY: AVX512 56977 EXTENSION: AVX512EVEX 56978 ISA_SET: AVX512BW_128N 56979 EXCEPTIONS: AVX512-E9NF 56980 REAL_OPCODE: Y 56981 ATTRIBUTES: DISP8_GPR_WRITER_STORE_WORD 56982 PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD() 56983 OPERANDS: MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16 IMM0:r:b 56984 IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 56985 } 56986 56987 56988 # EMITTING VPEXTRW (VPEXTRW-128-2) 56989 { 56990 ICLASS: VPEXTRW 56991 CPL: 3 56992 CATEGORY: AVX512 56993 EXTENSION: AVX512EVEX 56994 ISA_SET: AVX512BW_128N 56995 EXCEPTIONS: AVX512-E9NF 56996 REAL_OPCODE: Y 56997 PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() 56998 OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b 56999 IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 57000 } 57001 57002 57003 # EMITTING VPGATHERDD (VPGATHERDD-128-1) 57004 { 57005 ICLASS: VPGATHERDD 57006 CPL: 3 57007 CATEGORY: GATHER 57008 EXTENSION: AVX512EVEX 57009 ISA_SET: AVX512F_128 57010 EXCEPTIONS: AVX512-E12 57011 REAL_OPCODE: Y 57012 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 57013 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 57014 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u32 57015 IFORM: VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 57016 } 57017 57018 57019 # EMITTING VPGATHERDD (VPGATHERDD-256-1) 57020 { 57021 ICLASS: VPGATHERDD 57022 CPL: 3 57023 CATEGORY: GATHER 57024 EXTENSION: AVX512EVEX 57025 ISA_SET: AVX512F_256 57026 EXCEPTIONS: AVX512-E12 57027 REAL_OPCODE: Y 57028 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 57029 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 57030 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u32 57031 IFORM: VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 57032 } 57033 57034 57035 # EMITTING VPGATHERDQ (VPGATHERDQ-128-1) 57036 { 57037 ICLASS: VPGATHERDQ 57038 CPL: 3 57039 CATEGORY: GATHER 57040 EXTENSION: AVX512EVEX 57041 ISA_SET: AVX512F_128 57042 EXCEPTIONS: AVX512-E12 57043 REAL_OPCODE: Y 57044 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 57045 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 57046 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u64 57047 IFORM: VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 57048 } 57049 57050 57051 # EMITTING VPGATHERDQ (VPGATHERDQ-256-1) 57052 { 57053 ICLASS: VPGATHERDQ 57054 CPL: 3 57055 CATEGORY: GATHER 57056 EXTENSION: AVX512EVEX 57057 ISA_SET: AVX512F_256 57058 EXCEPTIONS: AVX512-E12 57059 REAL_OPCODE: Y 57060 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 57061 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 57062 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u64 57063 IFORM: VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 57064 } 57065 57066 57067 # EMITTING VPGATHERQD (VPGATHERQD-128-1) 57068 { 57069 ICLASS: VPGATHERQD 57070 CPL: 3 57071 CATEGORY: GATHER 57072 EXTENSION: AVX512EVEX 57073 ISA_SET: AVX512F_128 57074 EXCEPTIONS: AVX512-E12 57075 REAL_OPCODE: Y 57076 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 57077 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 57078 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:q:u32 57079 IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 57080 } 57081 57082 57083 # EMITTING VPGATHERQD (VPGATHERQD-256-1) 57084 { 57085 ICLASS: VPGATHERQD 57086 CPL: 3 57087 CATEGORY: GATHER 57088 EXTENSION: AVX512EVEX 57089 ISA_SET: AVX512F_256 57090 EXCEPTIONS: AVX512-E12 57091 REAL_OPCODE: Y 57092 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 57093 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 57094 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u32 57095 IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 57096 } 57097 57098 57099 # EMITTING VPGATHERQQ (VPGATHERQQ-128-1) 57100 { 57101 ICLASS: VPGATHERQQ 57102 CPL: 3 57103 CATEGORY: GATHER 57104 EXTENSION: AVX512EVEX 57105 ISA_SET: AVX512F_128 57106 EXCEPTIONS: AVX512-E12 57107 REAL_OPCODE: Y 57108 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 57109 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 57110 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:dq:u64 57111 IFORM: VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 57112 } 57113 57114 57115 # EMITTING VPGATHERQQ (VPGATHERQQ-256-1) 57116 { 57117 ICLASS: VPGATHERQQ 57118 CPL: 3 57119 CATEGORY: GATHER 57120 EXTENSION: AVX512EVEX 57121 ISA_SET: AVX512F_256 57122 EXCEPTIONS: AVX512-E12 57123 REAL_OPCODE: Y 57124 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER MASKOP_EVEX DISP8_GSCAT 57125 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 57126 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:qq:u64 57127 IFORM: VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 57128 } 57129 57130 57131 # EMITTING VPINSRB (VPINSRB-128-1) 57132 { 57133 ICLASS: VPINSRB 57134 CPL: 3 57135 CATEGORY: AVX512 57136 EXTENSION: AVX512EVEX 57137 ISA_SET: AVX512BW_128N 57138 EXCEPTIONS: AVX512-E9NF 57139 REAL_OPCODE: Y 57140 PATTERN: EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() 57141 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b 57142 IFORM: VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 57143 } 57144 57145 { 57146 ICLASS: VPINSRB 57147 CPL: 3 57148 CATEGORY: AVX512 57149 EXTENSION: AVX512EVEX 57150 ISA_SET: AVX512BW_128N 57151 EXCEPTIONS: AVX512-E9NF 57152 REAL_OPCODE: Y 57153 ATTRIBUTES: DISP8_GPR_READER_BYTE 57154 PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE() 57155 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b 57156 IFORM: VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 57157 } 57158 57159 57160 # EMITTING VPINSRD (VPINSRD-128-1) 57161 { 57162 ICLASS: VPINSRD 57163 CPL: 3 57164 CATEGORY: AVX512 57165 EXTENSION: AVX512EVEX 57166 ISA_SET: AVX512DQ_128N 57167 EXCEPTIONS: AVX512-E9NF 57168 REAL_OPCODE: Y 57169 PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() 57170 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b 57171 IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 57172 } 57173 57174 { 57175 ICLASS: VPINSRD 57176 CPL: 3 57177 CATEGORY: AVX512 57178 EXTENSION: AVX512EVEX 57179 ISA_SET: AVX512DQ_128N 57180 EXCEPTIONS: AVX512-E9NF 57181 REAL_OPCODE: Y 57182 ATTRIBUTES: DISP8_GPR_READER 57183 PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() 57184 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b 57185 IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 57186 } 57187 57188 57189 # EMITTING VPINSRQ (VPINSRQ-128-1) 57190 { 57191 ICLASS: VPINSRQ 57192 CPL: 3 57193 CATEGORY: AVX512 57194 EXTENSION: AVX512EVEX 57195 ISA_SET: AVX512DQ_128N 57196 EXCEPTIONS: AVX512-E9NF 57197 REAL_OPCODE: Y 57198 PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() 57199 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b 57200 IFORM: VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 57201 } 57202 57203 { 57204 ICLASS: VPINSRQ 57205 CPL: 3 57206 CATEGORY: AVX512 57207 EXTENSION: AVX512EVEX 57208 ISA_SET: AVX512DQ_128N 57209 EXCEPTIONS: AVX512-E9NF 57210 REAL_OPCODE: Y 57211 ATTRIBUTES: DISP8_GPR_READER 57212 PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() 57213 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 MEM0:r:q:u64 IMM0:r:b 57214 IFORM: VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 57215 } 57216 57217 57218 # EMITTING VPINSRW (VPINSRW-128-1) 57219 { 57220 ICLASS: VPINSRW 57221 CPL: 3 57222 CATEGORY: AVX512 57223 EXTENSION: AVX512EVEX 57224 ISA_SET: AVX512BW_128N 57225 EXCEPTIONS: AVX512-E9NF 57226 REAL_OPCODE: Y 57227 PATTERN: EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() 57228 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b 57229 IFORM: VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 57230 } 57231 57232 { 57233 ICLASS: VPINSRW 57234 CPL: 3 57235 CATEGORY: AVX512 57236 EXTENSION: AVX512EVEX 57237 ISA_SET: AVX512BW_128N 57238 EXCEPTIONS: AVX512-E9NF 57239 REAL_OPCODE: Y 57240 ATTRIBUTES: DISP8_GPR_READER_WORD 57241 PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD() 57242 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b 57243 IFORM: VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 57244 } 57245 57246 57247 # EMITTING VPLZCNTD (VPLZCNTD-128-1) 57248 { 57249 ICLASS: VPLZCNTD 57250 CPL: 3 57251 CATEGORY: CONFLICT 57252 EXTENSION: AVX512EVEX 57253 ISA_SET: AVX512CD_128 57254 EXCEPTIONS: AVX512-E4 57255 REAL_OPCODE: Y 57256 ATTRIBUTES: MASKOP_EVEX 57257 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 57258 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 57259 IFORM: VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 57260 } 57261 57262 { 57263 ICLASS: VPLZCNTD 57264 CPL: 3 57265 CATEGORY: CONFLICT 57266 EXTENSION: AVX512EVEX 57267 ISA_SET: AVX512CD_128 57268 EXCEPTIONS: AVX512-E4 57269 REAL_OPCODE: Y 57270 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57271 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 57272 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 57273 IFORM: VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 57274 } 57275 57276 57277 # EMITTING VPLZCNTD (VPLZCNTD-256-1) 57278 { 57279 ICLASS: VPLZCNTD 57280 CPL: 3 57281 CATEGORY: CONFLICT 57282 EXTENSION: AVX512EVEX 57283 ISA_SET: AVX512CD_256 57284 EXCEPTIONS: AVX512-E4 57285 REAL_OPCODE: Y 57286 ATTRIBUTES: MASKOP_EVEX 57287 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 57288 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 57289 IFORM: VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 57290 } 57291 57292 { 57293 ICLASS: VPLZCNTD 57294 CPL: 3 57295 CATEGORY: CONFLICT 57296 EXTENSION: AVX512EVEX 57297 ISA_SET: AVX512CD_256 57298 EXCEPTIONS: AVX512-E4 57299 REAL_OPCODE: Y 57300 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57301 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 57302 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 57303 IFORM: VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 57304 } 57305 57306 57307 # EMITTING VPLZCNTQ (VPLZCNTQ-128-1) 57308 { 57309 ICLASS: VPLZCNTQ 57310 CPL: 3 57311 CATEGORY: CONFLICT 57312 EXTENSION: AVX512EVEX 57313 ISA_SET: AVX512CD_128 57314 EXCEPTIONS: AVX512-E4 57315 REAL_OPCODE: Y 57316 ATTRIBUTES: MASKOP_EVEX 57317 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 57318 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 57319 IFORM: VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 57320 } 57321 57322 { 57323 ICLASS: VPLZCNTQ 57324 CPL: 3 57325 CATEGORY: CONFLICT 57326 EXTENSION: AVX512EVEX 57327 ISA_SET: AVX512CD_128 57328 EXCEPTIONS: AVX512-E4 57329 REAL_OPCODE: Y 57330 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57331 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 57332 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 57333 IFORM: VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 57334 } 57335 57336 57337 # EMITTING VPLZCNTQ (VPLZCNTQ-256-1) 57338 { 57339 ICLASS: VPLZCNTQ 57340 CPL: 3 57341 CATEGORY: CONFLICT 57342 EXTENSION: AVX512EVEX 57343 ISA_SET: AVX512CD_256 57344 EXCEPTIONS: AVX512-E4 57345 REAL_OPCODE: Y 57346 ATTRIBUTES: MASKOP_EVEX 57347 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 57348 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 57349 IFORM: VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 57350 } 57351 57352 { 57353 ICLASS: VPLZCNTQ 57354 CPL: 3 57355 CATEGORY: CONFLICT 57356 EXTENSION: AVX512EVEX 57357 ISA_SET: AVX512CD_256 57358 EXCEPTIONS: AVX512-E4 57359 REAL_OPCODE: Y 57360 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57361 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 57362 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 57363 IFORM: VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 57364 } 57365 57366 57367 # EMITTING VPMADDUBSW (VPMADDUBSW-128-1) 57368 { 57369 ICLASS: VPMADDUBSW 57370 CPL: 3 57371 CATEGORY: AVX512 57372 EXTENSION: AVX512EVEX 57373 ISA_SET: AVX512BW_128 57374 EXCEPTIONS: AVX512-E4NF 57375 REAL_OPCODE: Y 57376 ATTRIBUTES: MASKOP_EVEX 57377 PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 57378 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 57379 IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 57380 } 57381 57382 { 57383 ICLASS: VPMADDUBSW 57384 CPL: 3 57385 CATEGORY: AVX512 57386 EXTENSION: AVX512EVEX 57387 ISA_SET: AVX512BW_128 57388 EXCEPTIONS: AVX512-E4NF 57389 REAL_OPCODE: Y 57390 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 57391 PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 57392 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 57393 IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 57394 } 57395 57396 57397 # EMITTING VPMADDUBSW (VPMADDUBSW-256-1) 57398 { 57399 ICLASS: VPMADDUBSW 57400 CPL: 3 57401 CATEGORY: AVX512 57402 EXTENSION: AVX512EVEX 57403 ISA_SET: AVX512BW_256 57404 EXCEPTIONS: AVX512-E4NF 57405 REAL_OPCODE: Y 57406 ATTRIBUTES: MASKOP_EVEX 57407 PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 57408 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 57409 IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 57410 } 57411 57412 { 57413 ICLASS: VPMADDUBSW 57414 CPL: 3 57415 CATEGORY: AVX512 57416 EXTENSION: AVX512EVEX 57417 ISA_SET: AVX512BW_256 57418 EXCEPTIONS: AVX512-E4NF 57419 REAL_OPCODE: Y 57420 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 57421 PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 57422 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 57423 IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 57424 } 57425 57426 57427 # EMITTING VPMADDUBSW (VPMADDUBSW-512-1) 57428 { 57429 ICLASS: VPMADDUBSW 57430 CPL: 3 57431 CATEGORY: AVX512 57432 EXTENSION: AVX512EVEX 57433 ISA_SET: AVX512BW_512 57434 EXCEPTIONS: AVX512-E4NF 57435 REAL_OPCODE: Y 57436 ATTRIBUTES: MASKOP_EVEX 57437 PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 57438 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 57439 IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 57440 } 57441 57442 { 57443 ICLASS: VPMADDUBSW 57444 CPL: 3 57445 CATEGORY: AVX512 57446 EXTENSION: AVX512EVEX 57447 ISA_SET: AVX512BW_512 57448 EXCEPTIONS: AVX512-E4NF 57449 REAL_OPCODE: Y 57450 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 57451 PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 57452 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 57453 IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 57454 } 57455 57456 57457 # EMITTING VPMADDWD (VPMADDWD-128-1) 57458 { 57459 ICLASS: VPMADDWD 57460 CPL: 3 57461 CATEGORY: AVX512 57462 EXTENSION: AVX512EVEX 57463 ISA_SET: AVX512BW_128 57464 EXCEPTIONS: AVX512-E4NF 57465 REAL_OPCODE: Y 57466 ATTRIBUTES: MASKOP_EVEX 57467 PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 57468 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 57469 IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 57470 } 57471 57472 { 57473 ICLASS: VPMADDWD 57474 CPL: 3 57475 CATEGORY: AVX512 57476 EXTENSION: AVX512EVEX 57477 ISA_SET: AVX512BW_128 57478 EXCEPTIONS: AVX512-E4NF 57479 REAL_OPCODE: Y 57480 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 57481 PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 57482 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 57483 IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 57484 } 57485 57486 57487 # EMITTING VPMADDWD (VPMADDWD-256-1) 57488 { 57489 ICLASS: VPMADDWD 57490 CPL: 3 57491 CATEGORY: AVX512 57492 EXTENSION: AVX512EVEX 57493 ISA_SET: AVX512BW_256 57494 EXCEPTIONS: AVX512-E4NF 57495 REAL_OPCODE: Y 57496 ATTRIBUTES: MASKOP_EVEX 57497 PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 57498 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 57499 IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 57500 } 57501 57502 { 57503 ICLASS: VPMADDWD 57504 CPL: 3 57505 CATEGORY: AVX512 57506 EXTENSION: AVX512EVEX 57507 ISA_SET: AVX512BW_256 57508 EXCEPTIONS: AVX512-E4NF 57509 REAL_OPCODE: Y 57510 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 57511 PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 57512 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 57513 IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 57514 } 57515 57516 57517 # EMITTING VPMADDWD (VPMADDWD-512-1) 57518 { 57519 ICLASS: VPMADDWD 57520 CPL: 3 57521 CATEGORY: AVX512 57522 EXTENSION: AVX512EVEX 57523 ISA_SET: AVX512BW_512 57524 EXCEPTIONS: AVX512-E4NF 57525 REAL_OPCODE: Y 57526 ATTRIBUTES: MASKOP_EVEX 57527 PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 57528 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 57529 IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 57530 } 57531 57532 { 57533 ICLASS: VPMADDWD 57534 CPL: 3 57535 CATEGORY: AVX512 57536 EXTENSION: AVX512EVEX 57537 ISA_SET: AVX512BW_512 57538 EXCEPTIONS: AVX512-E4NF 57539 REAL_OPCODE: Y 57540 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 57541 PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 57542 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 57543 IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 57544 } 57545 57546 57547 # EMITTING VPMAXSB (VPMAXSB-128-1) 57548 { 57549 ICLASS: VPMAXSB 57550 CPL: 3 57551 CATEGORY: AVX512 57552 EXTENSION: AVX512EVEX 57553 ISA_SET: AVX512BW_128 57554 EXCEPTIONS: AVX512-E4 57555 REAL_OPCODE: Y 57556 ATTRIBUTES: MASKOP_EVEX 57557 PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 57558 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 57559 IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 57560 } 57561 57562 { 57563 ICLASS: VPMAXSB 57564 CPL: 3 57565 CATEGORY: AVX512 57566 EXTENSION: AVX512EVEX 57567 ISA_SET: AVX512BW_128 57568 EXCEPTIONS: AVX512-E4 57569 REAL_OPCODE: Y 57570 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 57571 PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 57572 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 57573 IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 57574 } 57575 57576 57577 # EMITTING VPMAXSB (VPMAXSB-256-1) 57578 { 57579 ICLASS: VPMAXSB 57580 CPL: 3 57581 CATEGORY: AVX512 57582 EXTENSION: AVX512EVEX 57583 ISA_SET: AVX512BW_256 57584 EXCEPTIONS: AVX512-E4 57585 REAL_OPCODE: Y 57586 ATTRIBUTES: MASKOP_EVEX 57587 PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 57588 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 57589 IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 57590 } 57591 57592 { 57593 ICLASS: VPMAXSB 57594 CPL: 3 57595 CATEGORY: AVX512 57596 EXTENSION: AVX512EVEX 57597 ISA_SET: AVX512BW_256 57598 EXCEPTIONS: AVX512-E4 57599 REAL_OPCODE: Y 57600 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 57601 PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 57602 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 57603 IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 57604 } 57605 57606 57607 # EMITTING VPMAXSB (VPMAXSB-512-1) 57608 { 57609 ICLASS: VPMAXSB 57610 CPL: 3 57611 CATEGORY: AVX512 57612 EXTENSION: AVX512EVEX 57613 ISA_SET: AVX512BW_512 57614 EXCEPTIONS: AVX512-E4 57615 REAL_OPCODE: Y 57616 ATTRIBUTES: MASKOP_EVEX 57617 PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 57618 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 57619 IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 57620 } 57621 57622 { 57623 ICLASS: VPMAXSB 57624 CPL: 3 57625 CATEGORY: AVX512 57626 EXTENSION: AVX512EVEX 57627 ISA_SET: AVX512BW_512 57628 EXCEPTIONS: AVX512-E4 57629 REAL_OPCODE: Y 57630 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 57631 PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 57632 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 57633 IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 57634 } 57635 57636 57637 # EMITTING VPMAXSD (VPMAXSD-128-1) 57638 { 57639 ICLASS: VPMAXSD 57640 CPL: 3 57641 CATEGORY: AVX512 57642 EXTENSION: AVX512EVEX 57643 ISA_SET: AVX512F_128 57644 EXCEPTIONS: AVX512-E4 57645 REAL_OPCODE: Y 57646 ATTRIBUTES: MASKOP_EVEX 57647 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 57648 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 57649 IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 57650 } 57651 57652 { 57653 ICLASS: VPMAXSD 57654 CPL: 3 57655 CATEGORY: AVX512 57656 EXTENSION: AVX512EVEX 57657 ISA_SET: AVX512F_128 57658 EXCEPTIONS: AVX512-E4 57659 REAL_OPCODE: Y 57660 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57661 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 57662 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 57663 IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 57664 } 57665 57666 57667 # EMITTING VPMAXSD (VPMAXSD-256-1) 57668 { 57669 ICLASS: VPMAXSD 57670 CPL: 3 57671 CATEGORY: AVX512 57672 EXTENSION: AVX512EVEX 57673 ISA_SET: AVX512F_256 57674 EXCEPTIONS: AVX512-E4 57675 REAL_OPCODE: Y 57676 ATTRIBUTES: MASKOP_EVEX 57677 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 57678 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 57679 IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 57680 } 57681 57682 { 57683 ICLASS: VPMAXSD 57684 CPL: 3 57685 CATEGORY: AVX512 57686 EXTENSION: AVX512EVEX 57687 ISA_SET: AVX512F_256 57688 EXCEPTIONS: AVX512-E4 57689 REAL_OPCODE: Y 57690 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57691 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 57692 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 57693 IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 57694 } 57695 57696 57697 # EMITTING VPMAXSQ (VPMAXSQ-128-1) 57698 { 57699 ICLASS: VPMAXSQ 57700 CPL: 3 57701 CATEGORY: AVX512 57702 EXTENSION: AVX512EVEX 57703 ISA_SET: AVX512F_128 57704 EXCEPTIONS: AVX512-E4 57705 REAL_OPCODE: Y 57706 ATTRIBUTES: MASKOP_EVEX 57707 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 57708 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 57709 IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 57710 } 57711 57712 { 57713 ICLASS: VPMAXSQ 57714 CPL: 3 57715 CATEGORY: AVX512 57716 EXTENSION: AVX512EVEX 57717 ISA_SET: AVX512F_128 57718 EXCEPTIONS: AVX512-E4 57719 REAL_OPCODE: Y 57720 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57721 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 57722 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 57723 IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 57724 } 57725 57726 57727 # EMITTING VPMAXSQ (VPMAXSQ-256-1) 57728 { 57729 ICLASS: VPMAXSQ 57730 CPL: 3 57731 CATEGORY: AVX512 57732 EXTENSION: AVX512EVEX 57733 ISA_SET: AVX512F_256 57734 EXCEPTIONS: AVX512-E4 57735 REAL_OPCODE: Y 57736 ATTRIBUTES: MASKOP_EVEX 57737 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 57738 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 57739 IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 57740 } 57741 57742 { 57743 ICLASS: VPMAXSQ 57744 CPL: 3 57745 CATEGORY: AVX512 57746 EXTENSION: AVX512EVEX 57747 ISA_SET: AVX512F_256 57748 EXCEPTIONS: AVX512-E4 57749 REAL_OPCODE: Y 57750 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57751 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 57752 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 57753 IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 57754 } 57755 57756 57757 # EMITTING VPMAXSW (VPMAXSW-128-1) 57758 { 57759 ICLASS: VPMAXSW 57760 CPL: 3 57761 CATEGORY: AVX512 57762 EXTENSION: AVX512EVEX 57763 ISA_SET: AVX512BW_128 57764 EXCEPTIONS: AVX512-E4 57765 REAL_OPCODE: Y 57766 ATTRIBUTES: MASKOP_EVEX 57767 PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 57768 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 57769 IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 57770 } 57771 57772 { 57773 ICLASS: VPMAXSW 57774 CPL: 3 57775 CATEGORY: AVX512 57776 EXTENSION: AVX512EVEX 57777 ISA_SET: AVX512BW_128 57778 EXCEPTIONS: AVX512-E4 57779 REAL_OPCODE: Y 57780 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 57781 PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 57782 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 57783 IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 57784 } 57785 57786 57787 # EMITTING VPMAXSW (VPMAXSW-256-1) 57788 { 57789 ICLASS: VPMAXSW 57790 CPL: 3 57791 CATEGORY: AVX512 57792 EXTENSION: AVX512EVEX 57793 ISA_SET: AVX512BW_256 57794 EXCEPTIONS: AVX512-E4 57795 REAL_OPCODE: Y 57796 ATTRIBUTES: MASKOP_EVEX 57797 PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 57798 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 57799 IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 57800 } 57801 57802 { 57803 ICLASS: VPMAXSW 57804 CPL: 3 57805 CATEGORY: AVX512 57806 EXTENSION: AVX512EVEX 57807 ISA_SET: AVX512BW_256 57808 EXCEPTIONS: AVX512-E4 57809 REAL_OPCODE: Y 57810 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 57811 PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 57812 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 57813 IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 57814 } 57815 57816 57817 # EMITTING VPMAXSW (VPMAXSW-512-1) 57818 { 57819 ICLASS: VPMAXSW 57820 CPL: 3 57821 CATEGORY: AVX512 57822 EXTENSION: AVX512EVEX 57823 ISA_SET: AVX512BW_512 57824 EXCEPTIONS: AVX512-E4 57825 REAL_OPCODE: Y 57826 ATTRIBUTES: MASKOP_EVEX 57827 PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 57828 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 57829 IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 57830 } 57831 57832 { 57833 ICLASS: VPMAXSW 57834 CPL: 3 57835 CATEGORY: AVX512 57836 EXTENSION: AVX512EVEX 57837 ISA_SET: AVX512BW_512 57838 EXCEPTIONS: AVX512-E4 57839 REAL_OPCODE: Y 57840 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 57841 PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 57842 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 57843 IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 57844 } 57845 57846 57847 # EMITTING VPMAXUB (VPMAXUB-128-1) 57848 { 57849 ICLASS: VPMAXUB 57850 CPL: 3 57851 CATEGORY: AVX512 57852 EXTENSION: AVX512EVEX 57853 ISA_SET: AVX512BW_128 57854 EXCEPTIONS: AVX512-E4 57855 REAL_OPCODE: Y 57856 ATTRIBUTES: MASKOP_EVEX 57857 PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 57858 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 57859 IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 57860 } 57861 57862 { 57863 ICLASS: VPMAXUB 57864 CPL: 3 57865 CATEGORY: AVX512 57866 EXTENSION: AVX512EVEX 57867 ISA_SET: AVX512BW_128 57868 EXCEPTIONS: AVX512-E4 57869 REAL_OPCODE: Y 57870 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 57871 PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 57872 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 57873 IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 57874 } 57875 57876 57877 # EMITTING VPMAXUB (VPMAXUB-256-1) 57878 { 57879 ICLASS: VPMAXUB 57880 CPL: 3 57881 CATEGORY: AVX512 57882 EXTENSION: AVX512EVEX 57883 ISA_SET: AVX512BW_256 57884 EXCEPTIONS: AVX512-E4 57885 REAL_OPCODE: Y 57886 ATTRIBUTES: MASKOP_EVEX 57887 PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 57888 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 57889 IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 57890 } 57891 57892 { 57893 ICLASS: VPMAXUB 57894 CPL: 3 57895 CATEGORY: AVX512 57896 EXTENSION: AVX512EVEX 57897 ISA_SET: AVX512BW_256 57898 EXCEPTIONS: AVX512-E4 57899 REAL_OPCODE: Y 57900 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 57901 PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 57902 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 57903 IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 57904 } 57905 57906 57907 # EMITTING VPMAXUB (VPMAXUB-512-1) 57908 { 57909 ICLASS: VPMAXUB 57910 CPL: 3 57911 CATEGORY: AVX512 57912 EXTENSION: AVX512EVEX 57913 ISA_SET: AVX512BW_512 57914 EXCEPTIONS: AVX512-E4 57915 REAL_OPCODE: Y 57916 ATTRIBUTES: MASKOP_EVEX 57917 PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 57918 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 57919 IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 57920 } 57921 57922 { 57923 ICLASS: VPMAXUB 57924 CPL: 3 57925 CATEGORY: AVX512 57926 EXTENSION: AVX512EVEX 57927 ISA_SET: AVX512BW_512 57928 EXCEPTIONS: AVX512-E4 57929 REAL_OPCODE: Y 57930 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 57931 PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 57932 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 57933 IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 57934 } 57935 57936 57937 # EMITTING VPMAXUD (VPMAXUD-128-1) 57938 { 57939 ICLASS: VPMAXUD 57940 CPL: 3 57941 CATEGORY: AVX512 57942 EXTENSION: AVX512EVEX 57943 ISA_SET: AVX512F_128 57944 EXCEPTIONS: AVX512-E4 57945 REAL_OPCODE: Y 57946 ATTRIBUTES: MASKOP_EVEX 57947 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 57948 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 57949 IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 57950 } 57951 57952 { 57953 ICLASS: VPMAXUD 57954 CPL: 3 57955 CATEGORY: AVX512 57956 EXTENSION: AVX512EVEX 57957 ISA_SET: AVX512F_128 57958 EXCEPTIONS: AVX512-E4 57959 REAL_OPCODE: Y 57960 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57961 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 57962 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 57963 IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 57964 } 57965 57966 57967 # EMITTING VPMAXUD (VPMAXUD-256-1) 57968 { 57969 ICLASS: VPMAXUD 57970 CPL: 3 57971 CATEGORY: AVX512 57972 EXTENSION: AVX512EVEX 57973 ISA_SET: AVX512F_256 57974 EXCEPTIONS: AVX512-E4 57975 REAL_OPCODE: Y 57976 ATTRIBUTES: MASKOP_EVEX 57977 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 57978 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 57979 IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 57980 } 57981 57982 { 57983 ICLASS: VPMAXUD 57984 CPL: 3 57985 CATEGORY: AVX512 57986 EXTENSION: AVX512EVEX 57987 ISA_SET: AVX512F_256 57988 EXCEPTIONS: AVX512-E4 57989 REAL_OPCODE: Y 57990 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57991 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 57992 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 57993 IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 57994 } 57995 57996 57997 # EMITTING VPMAXUQ (VPMAXUQ-128-1) 57998 { 57999 ICLASS: VPMAXUQ 58000 CPL: 3 58001 CATEGORY: AVX512 58002 EXTENSION: AVX512EVEX 58003 ISA_SET: AVX512F_128 58004 EXCEPTIONS: AVX512-E4 58005 REAL_OPCODE: Y 58006 ATTRIBUTES: MASKOP_EVEX 58007 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 58008 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 58009 IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 58010 } 58011 58012 { 58013 ICLASS: VPMAXUQ 58014 CPL: 3 58015 CATEGORY: AVX512 58016 EXTENSION: AVX512EVEX 58017 ISA_SET: AVX512F_128 58018 EXCEPTIONS: AVX512-E4 58019 REAL_OPCODE: Y 58020 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 58021 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 58022 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 58023 IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 58024 } 58025 58026 58027 # EMITTING VPMAXUQ (VPMAXUQ-256-1) 58028 { 58029 ICLASS: VPMAXUQ 58030 CPL: 3 58031 CATEGORY: AVX512 58032 EXTENSION: AVX512EVEX 58033 ISA_SET: AVX512F_256 58034 EXCEPTIONS: AVX512-E4 58035 REAL_OPCODE: Y 58036 ATTRIBUTES: MASKOP_EVEX 58037 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 58038 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 58039 IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 58040 } 58041 58042 { 58043 ICLASS: VPMAXUQ 58044 CPL: 3 58045 CATEGORY: AVX512 58046 EXTENSION: AVX512EVEX 58047 ISA_SET: AVX512F_256 58048 EXCEPTIONS: AVX512-E4 58049 REAL_OPCODE: Y 58050 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 58051 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 58052 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 58053 IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 58054 } 58055 58056 58057 # EMITTING VPMAXUW (VPMAXUW-128-1) 58058 { 58059 ICLASS: VPMAXUW 58060 CPL: 3 58061 CATEGORY: AVX512 58062 EXTENSION: AVX512EVEX 58063 ISA_SET: AVX512BW_128 58064 EXCEPTIONS: AVX512-E4 58065 REAL_OPCODE: Y 58066 ATTRIBUTES: MASKOP_EVEX 58067 PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 58068 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 58069 IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 58070 } 58071 58072 { 58073 ICLASS: VPMAXUW 58074 CPL: 3 58075 CATEGORY: AVX512 58076 EXTENSION: AVX512EVEX 58077 ISA_SET: AVX512BW_128 58078 EXCEPTIONS: AVX512-E4 58079 REAL_OPCODE: Y 58080 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58081 PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 58082 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 58083 IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 58084 } 58085 58086 58087 # EMITTING VPMAXUW (VPMAXUW-256-1) 58088 { 58089 ICLASS: VPMAXUW 58090 CPL: 3 58091 CATEGORY: AVX512 58092 EXTENSION: AVX512EVEX 58093 ISA_SET: AVX512BW_256 58094 EXCEPTIONS: AVX512-E4 58095 REAL_OPCODE: Y 58096 ATTRIBUTES: MASKOP_EVEX 58097 PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 58098 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 58099 IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 58100 } 58101 58102 { 58103 ICLASS: VPMAXUW 58104 CPL: 3 58105 CATEGORY: AVX512 58106 EXTENSION: AVX512EVEX 58107 ISA_SET: AVX512BW_256 58108 EXCEPTIONS: AVX512-E4 58109 REAL_OPCODE: Y 58110 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58111 PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 58112 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 58113 IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 58114 } 58115 58116 58117 # EMITTING VPMAXUW (VPMAXUW-512-1) 58118 { 58119 ICLASS: VPMAXUW 58120 CPL: 3 58121 CATEGORY: AVX512 58122 EXTENSION: AVX512EVEX 58123 ISA_SET: AVX512BW_512 58124 EXCEPTIONS: AVX512-E4 58125 REAL_OPCODE: Y 58126 ATTRIBUTES: MASKOP_EVEX 58127 PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 58128 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 58129 IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 58130 } 58131 58132 { 58133 ICLASS: VPMAXUW 58134 CPL: 3 58135 CATEGORY: AVX512 58136 EXTENSION: AVX512EVEX 58137 ISA_SET: AVX512BW_512 58138 EXCEPTIONS: AVX512-E4 58139 REAL_OPCODE: Y 58140 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58141 PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 58142 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 58143 IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 58144 } 58145 58146 58147 # EMITTING VPMINSB (VPMINSB-128-1) 58148 { 58149 ICLASS: VPMINSB 58150 CPL: 3 58151 CATEGORY: AVX512 58152 EXTENSION: AVX512EVEX 58153 ISA_SET: AVX512BW_128 58154 EXCEPTIONS: AVX512-E4 58155 REAL_OPCODE: Y 58156 ATTRIBUTES: MASKOP_EVEX 58157 PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 58158 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 58159 IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 58160 } 58161 58162 { 58163 ICLASS: VPMINSB 58164 CPL: 3 58165 CATEGORY: AVX512 58166 EXTENSION: AVX512EVEX 58167 ISA_SET: AVX512BW_128 58168 EXCEPTIONS: AVX512-E4 58169 REAL_OPCODE: Y 58170 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58171 PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 58172 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 58173 IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 58174 } 58175 58176 58177 # EMITTING VPMINSB (VPMINSB-256-1) 58178 { 58179 ICLASS: VPMINSB 58180 CPL: 3 58181 CATEGORY: AVX512 58182 EXTENSION: AVX512EVEX 58183 ISA_SET: AVX512BW_256 58184 EXCEPTIONS: AVX512-E4 58185 REAL_OPCODE: Y 58186 ATTRIBUTES: MASKOP_EVEX 58187 PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 58188 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 58189 IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 58190 } 58191 58192 { 58193 ICLASS: VPMINSB 58194 CPL: 3 58195 CATEGORY: AVX512 58196 EXTENSION: AVX512EVEX 58197 ISA_SET: AVX512BW_256 58198 EXCEPTIONS: AVX512-E4 58199 REAL_OPCODE: Y 58200 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58201 PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 58202 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 58203 IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 58204 } 58205 58206 58207 # EMITTING VPMINSB (VPMINSB-512-1) 58208 { 58209 ICLASS: VPMINSB 58210 CPL: 3 58211 CATEGORY: AVX512 58212 EXTENSION: AVX512EVEX 58213 ISA_SET: AVX512BW_512 58214 EXCEPTIONS: AVX512-E4 58215 REAL_OPCODE: Y 58216 ATTRIBUTES: MASKOP_EVEX 58217 PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 58218 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 58219 IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 58220 } 58221 58222 { 58223 ICLASS: VPMINSB 58224 CPL: 3 58225 CATEGORY: AVX512 58226 EXTENSION: AVX512EVEX 58227 ISA_SET: AVX512BW_512 58228 EXCEPTIONS: AVX512-E4 58229 REAL_OPCODE: Y 58230 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58231 PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 58232 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 58233 IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 58234 } 58235 58236 58237 # EMITTING VPMINSD (VPMINSD-128-1) 58238 { 58239 ICLASS: VPMINSD 58240 CPL: 3 58241 CATEGORY: AVX512 58242 EXTENSION: AVX512EVEX 58243 ISA_SET: AVX512F_128 58244 EXCEPTIONS: AVX512-E4 58245 REAL_OPCODE: Y 58246 ATTRIBUTES: MASKOP_EVEX 58247 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 58248 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 58249 IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 58250 } 58251 58252 { 58253 ICLASS: VPMINSD 58254 CPL: 3 58255 CATEGORY: AVX512 58256 EXTENSION: AVX512EVEX 58257 ISA_SET: AVX512F_128 58258 EXCEPTIONS: AVX512-E4 58259 REAL_OPCODE: Y 58260 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 58261 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 58262 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 58263 IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 58264 } 58265 58266 58267 # EMITTING VPMINSD (VPMINSD-256-1) 58268 { 58269 ICLASS: VPMINSD 58270 CPL: 3 58271 CATEGORY: AVX512 58272 EXTENSION: AVX512EVEX 58273 ISA_SET: AVX512F_256 58274 EXCEPTIONS: AVX512-E4 58275 REAL_OPCODE: Y 58276 ATTRIBUTES: MASKOP_EVEX 58277 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 58278 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 58279 IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 58280 } 58281 58282 { 58283 ICLASS: VPMINSD 58284 CPL: 3 58285 CATEGORY: AVX512 58286 EXTENSION: AVX512EVEX 58287 ISA_SET: AVX512F_256 58288 EXCEPTIONS: AVX512-E4 58289 REAL_OPCODE: Y 58290 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 58291 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 58292 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 58293 IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 58294 } 58295 58296 58297 # EMITTING VPMINSQ (VPMINSQ-128-1) 58298 { 58299 ICLASS: VPMINSQ 58300 CPL: 3 58301 CATEGORY: AVX512 58302 EXTENSION: AVX512EVEX 58303 ISA_SET: AVX512F_128 58304 EXCEPTIONS: AVX512-E4 58305 REAL_OPCODE: Y 58306 ATTRIBUTES: MASKOP_EVEX 58307 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 58308 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 58309 IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 58310 } 58311 58312 { 58313 ICLASS: VPMINSQ 58314 CPL: 3 58315 CATEGORY: AVX512 58316 EXTENSION: AVX512EVEX 58317 ISA_SET: AVX512F_128 58318 EXCEPTIONS: AVX512-E4 58319 REAL_OPCODE: Y 58320 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 58321 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 58322 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 58323 IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 58324 } 58325 58326 58327 # EMITTING VPMINSQ (VPMINSQ-256-1) 58328 { 58329 ICLASS: VPMINSQ 58330 CPL: 3 58331 CATEGORY: AVX512 58332 EXTENSION: AVX512EVEX 58333 ISA_SET: AVX512F_256 58334 EXCEPTIONS: AVX512-E4 58335 REAL_OPCODE: Y 58336 ATTRIBUTES: MASKOP_EVEX 58337 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 58338 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 58339 IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 58340 } 58341 58342 { 58343 ICLASS: VPMINSQ 58344 CPL: 3 58345 CATEGORY: AVX512 58346 EXTENSION: AVX512EVEX 58347 ISA_SET: AVX512F_256 58348 EXCEPTIONS: AVX512-E4 58349 REAL_OPCODE: Y 58350 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 58351 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 58352 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 58353 IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 58354 } 58355 58356 58357 # EMITTING VPMINSW (VPMINSW-128-1) 58358 { 58359 ICLASS: VPMINSW 58360 CPL: 3 58361 CATEGORY: AVX512 58362 EXTENSION: AVX512EVEX 58363 ISA_SET: AVX512BW_128 58364 EXCEPTIONS: AVX512-E4 58365 REAL_OPCODE: Y 58366 ATTRIBUTES: MASKOP_EVEX 58367 PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 58368 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 58369 IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 58370 } 58371 58372 { 58373 ICLASS: VPMINSW 58374 CPL: 3 58375 CATEGORY: AVX512 58376 EXTENSION: AVX512EVEX 58377 ISA_SET: AVX512BW_128 58378 EXCEPTIONS: AVX512-E4 58379 REAL_OPCODE: Y 58380 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58381 PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 58382 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 58383 IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 58384 } 58385 58386 58387 # EMITTING VPMINSW (VPMINSW-256-1) 58388 { 58389 ICLASS: VPMINSW 58390 CPL: 3 58391 CATEGORY: AVX512 58392 EXTENSION: AVX512EVEX 58393 ISA_SET: AVX512BW_256 58394 EXCEPTIONS: AVX512-E4 58395 REAL_OPCODE: Y 58396 ATTRIBUTES: MASKOP_EVEX 58397 PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 58398 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 58399 IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 58400 } 58401 58402 { 58403 ICLASS: VPMINSW 58404 CPL: 3 58405 CATEGORY: AVX512 58406 EXTENSION: AVX512EVEX 58407 ISA_SET: AVX512BW_256 58408 EXCEPTIONS: AVX512-E4 58409 REAL_OPCODE: Y 58410 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58411 PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 58412 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 58413 IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 58414 } 58415 58416 58417 # EMITTING VPMINSW (VPMINSW-512-1) 58418 { 58419 ICLASS: VPMINSW 58420 CPL: 3 58421 CATEGORY: AVX512 58422 EXTENSION: AVX512EVEX 58423 ISA_SET: AVX512BW_512 58424 EXCEPTIONS: AVX512-E4 58425 REAL_OPCODE: Y 58426 ATTRIBUTES: MASKOP_EVEX 58427 PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 58428 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 58429 IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 58430 } 58431 58432 { 58433 ICLASS: VPMINSW 58434 CPL: 3 58435 CATEGORY: AVX512 58436 EXTENSION: AVX512EVEX 58437 ISA_SET: AVX512BW_512 58438 EXCEPTIONS: AVX512-E4 58439 REAL_OPCODE: Y 58440 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58441 PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 58442 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 58443 IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 58444 } 58445 58446 58447 # EMITTING VPMINUB (VPMINUB-128-1) 58448 { 58449 ICLASS: VPMINUB 58450 CPL: 3 58451 CATEGORY: AVX512 58452 EXTENSION: AVX512EVEX 58453 ISA_SET: AVX512BW_128 58454 EXCEPTIONS: AVX512-E4 58455 REAL_OPCODE: Y 58456 ATTRIBUTES: MASKOP_EVEX 58457 PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 58458 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 58459 IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 58460 } 58461 58462 { 58463 ICLASS: VPMINUB 58464 CPL: 3 58465 CATEGORY: AVX512 58466 EXTENSION: AVX512EVEX 58467 ISA_SET: AVX512BW_128 58468 EXCEPTIONS: AVX512-E4 58469 REAL_OPCODE: Y 58470 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58471 PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 58472 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 58473 IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 58474 } 58475 58476 58477 # EMITTING VPMINUB (VPMINUB-256-1) 58478 { 58479 ICLASS: VPMINUB 58480 CPL: 3 58481 CATEGORY: AVX512 58482 EXTENSION: AVX512EVEX 58483 ISA_SET: AVX512BW_256 58484 EXCEPTIONS: AVX512-E4 58485 REAL_OPCODE: Y 58486 ATTRIBUTES: MASKOP_EVEX 58487 PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 58488 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 58489 IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 58490 } 58491 58492 { 58493 ICLASS: VPMINUB 58494 CPL: 3 58495 CATEGORY: AVX512 58496 EXTENSION: AVX512EVEX 58497 ISA_SET: AVX512BW_256 58498 EXCEPTIONS: AVX512-E4 58499 REAL_OPCODE: Y 58500 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58501 PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 58502 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 58503 IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 58504 } 58505 58506 58507 # EMITTING VPMINUB (VPMINUB-512-1) 58508 { 58509 ICLASS: VPMINUB 58510 CPL: 3 58511 CATEGORY: AVX512 58512 EXTENSION: AVX512EVEX 58513 ISA_SET: AVX512BW_512 58514 EXCEPTIONS: AVX512-E4 58515 REAL_OPCODE: Y 58516 ATTRIBUTES: MASKOP_EVEX 58517 PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 58518 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 58519 IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 58520 } 58521 58522 { 58523 ICLASS: VPMINUB 58524 CPL: 3 58525 CATEGORY: AVX512 58526 EXTENSION: AVX512EVEX 58527 ISA_SET: AVX512BW_512 58528 EXCEPTIONS: AVX512-E4 58529 REAL_OPCODE: Y 58530 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58531 PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 58532 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 58533 IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 58534 } 58535 58536 58537 # EMITTING VPMINUD (VPMINUD-128-1) 58538 { 58539 ICLASS: VPMINUD 58540 CPL: 3 58541 CATEGORY: AVX512 58542 EXTENSION: AVX512EVEX 58543 ISA_SET: AVX512F_128 58544 EXCEPTIONS: AVX512-E4 58545 REAL_OPCODE: Y 58546 ATTRIBUTES: MASKOP_EVEX 58547 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 58548 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 58549 IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 58550 } 58551 58552 { 58553 ICLASS: VPMINUD 58554 CPL: 3 58555 CATEGORY: AVX512 58556 EXTENSION: AVX512EVEX 58557 ISA_SET: AVX512F_128 58558 EXCEPTIONS: AVX512-E4 58559 REAL_OPCODE: Y 58560 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 58561 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 58562 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 58563 IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 58564 } 58565 58566 58567 # EMITTING VPMINUD (VPMINUD-256-1) 58568 { 58569 ICLASS: VPMINUD 58570 CPL: 3 58571 CATEGORY: AVX512 58572 EXTENSION: AVX512EVEX 58573 ISA_SET: AVX512F_256 58574 EXCEPTIONS: AVX512-E4 58575 REAL_OPCODE: Y 58576 ATTRIBUTES: MASKOP_EVEX 58577 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 58578 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 58579 IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 58580 } 58581 58582 { 58583 ICLASS: VPMINUD 58584 CPL: 3 58585 CATEGORY: AVX512 58586 EXTENSION: AVX512EVEX 58587 ISA_SET: AVX512F_256 58588 EXCEPTIONS: AVX512-E4 58589 REAL_OPCODE: Y 58590 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 58591 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 58592 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 58593 IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 58594 } 58595 58596 58597 # EMITTING VPMINUQ (VPMINUQ-128-1) 58598 { 58599 ICLASS: VPMINUQ 58600 CPL: 3 58601 CATEGORY: AVX512 58602 EXTENSION: AVX512EVEX 58603 ISA_SET: AVX512F_128 58604 EXCEPTIONS: AVX512-E4 58605 REAL_OPCODE: Y 58606 ATTRIBUTES: MASKOP_EVEX 58607 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 58608 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 58609 IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 58610 } 58611 58612 { 58613 ICLASS: VPMINUQ 58614 CPL: 3 58615 CATEGORY: AVX512 58616 EXTENSION: AVX512EVEX 58617 ISA_SET: AVX512F_128 58618 EXCEPTIONS: AVX512-E4 58619 REAL_OPCODE: Y 58620 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 58621 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 58622 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 58623 IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 58624 } 58625 58626 58627 # EMITTING VPMINUQ (VPMINUQ-256-1) 58628 { 58629 ICLASS: VPMINUQ 58630 CPL: 3 58631 CATEGORY: AVX512 58632 EXTENSION: AVX512EVEX 58633 ISA_SET: AVX512F_256 58634 EXCEPTIONS: AVX512-E4 58635 REAL_OPCODE: Y 58636 ATTRIBUTES: MASKOP_EVEX 58637 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 58638 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 58639 IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 58640 } 58641 58642 { 58643 ICLASS: VPMINUQ 58644 CPL: 3 58645 CATEGORY: AVX512 58646 EXTENSION: AVX512EVEX 58647 ISA_SET: AVX512F_256 58648 EXCEPTIONS: AVX512-E4 58649 REAL_OPCODE: Y 58650 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 58651 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 58652 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 58653 IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 58654 } 58655 58656 58657 # EMITTING VPMINUW (VPMINUW-128-1) 58658 { 58659 ICLASS: VPMINUW 58660 CPL: 3 58661 CATEGORY: AVX512 58662 EXTENSION: AVX512EVEX 58663 ISA_SET: AVX512BW_128 58664 EXCEPTIONS: AVX512-E4 58665 REAL_OPCODE: Y 58666 ATTRIBUTES: MASKOP_EVEX 58667 PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 58668 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 58669 IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 58670 } 58671 58672 { 58673 ICLASS: VPMINUW 58674 CPL: 3 58675 CATEGORY: AVX512 58676 EXTENSION: AVX512EVEX 58677 ISA_SET: AVX512BW_128 58678 EXCEPTIONS: AVX512-E4 58679 REAL_OPCODE: Y 58680 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58681 PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 58682 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 58683 IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 58684 } 58685 58686 58687 # EMITTING VPMINUW (VPMINUW-256-1) 58688 { 58689 ICLASS: VPMINUW 58690 CPL: 3 58691 CATEGORY: AVX512 58692 EXTENSION: AVX512EVEX 58693 ISA_SET: AVX512BW_256 58694 EXCEPTIONS: AVX512-E4 58695 REAL_OPCODE: Y 58696 ATTRIBUTES: MASKOP_EVEX 58697 PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 58698 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 58699 IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 58700 } 58701 58702 { 58703 ICLASS: VPMINUW 58704 CPL: 3 58705 CATEGORY: AVX512 58706 EXTENSION: AVX512EVEX 58707 ISA_SET: AVX512BW_256 58708 EXCEPTIONS: AVX512-E4 58709 REAL_OPCODE: Y 58710 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58711 PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 58712 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 58713 IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 58714 } 58715 58716 58717 # EMITTING VPMINUW (VPMINUW-512-1) 58718 { 58719 ICLASS: VPMINUW 58720 CPL: 3 58721 CATEGORY: AVX512 58722 EXTENSION: AVX512EVEX 58723 ISA_SET: AVX512BW_512 58724 EXCEPTIONS: AVX512-E4 58725 REAL_OPCODE: Y 58726 ATTRIBUTES: MASKOP_EVEX 58727 PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 58728 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 58729 IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 58730 } 58731 58732 { 58733 ICLASS: VPMINUW 58734 CPL: 3 58735 CATEGORY: AVX512 58736 EXTENSION: AVX512EVEX 58737 ISA_SET: AVX512BW_512 58738 EXCEPTIONS: AVX512-E4 58739 REAL_OPCODE: Y 58740 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 58741 PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 58742 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 58743 IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 58744 } 58745 58746 58747 # EMITTING VPMOVB2M (VPMOVB2M-128-1) 58748 { 58749 ICLASS: VPMOVB2M 58750 CPL: 3 58751 CATEGORY: DATAXFER 58752 EXTENSION: AVX512EVEX 58753 ISA_SET: AVX512BW_128 58754 EXCEPTIONS: AVX512-E7NM 58755 REAL_OPCODE: Y 58756 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 58757 OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u8 58758 IFORM: VPMOVB2M_MASKmskw_XMMu8_AVX512 58759 } 58760 58761 58762 # EMITTING VPMOVB2M (VPMOVB2M-256-1) 58763 { 58764 ICLASS: VPMOVB2M 58765 CPL: 3 58766 CATEGORY: DATAXFER 58767 EXTENSION: AVX512EVEX 58768 ISA_SET: AVX512BW_256 58769 EXCEPTIONS: AVX512-E7NM 58770 REAL_OPCODE: Y 58771 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 58772 OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u8 58773 IFORM: VPMOVB2M_MASKmskw_YMMu8_AVX512 58774 } 58775 58776 58777 # EMITTING VPMOVB2M (VPMOVB2M-512-1) 58778 { 58779 ICLASS: VPMOVB2M 58780 CPL: 3 58781 CATEGORY: DATAXFER 58782 EXTENSION: AVX512EVEX 58783 ISA_SET: AVX512BW_512 58784 EXCEPTIONS: AVX512-E7NM 58785 REAL_OPCODE: Y 58786 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 58787 OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu8 58788 IFORM: VPMOVB2M_MASKmskw_ZMMu8_AVX512 58789 } 58790 58791 58792 # EMITTING VPMOVD2M (VPMOVD2M-128-1) 58793 { 58794 ICLASS: VPMOVD2M 58795 CPL: 3 58796 CATEGORY: DATAXFER 58797 EXTENSION: AVX512EVEX 58798 ISA_SET: AVX512DQ_128 58799 EXCEPTIONS: AVX512-E7NM 58800 REAL_OPCODE: Y 58801 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 58802 OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u32 58803 IFORM: VPMOVD2M_MASKmskw_XMMu32_AVX512 58804 } 58805 58806 58807 # EMITTING VPMOVD2M (VPMOVD2M-256-1) 58808 { 58809 ICLASS: VPMOVD2M 58810 CPL: 3 58811 CATEGORY: DATAXFER 58812 EXTENSION: AVX512EVEX 58813 ISA_SET: AVX512DQ_256 58814 EXCEPTIONS: AVX512-E7NM 58815 REAL_OPCODE: Y 58816 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 58817 OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u32 58818 IFORM: VPMOVD2M_MASKmskw_YMMu32_AVX512 58819 } 58820 58821 58822 # EMITTING VPMOVD2M (VPMOVD2M-512-1) 58823 { 58824 ICLASS: VPMOVD2M 58825 CPL: 3 58826 CATEGORY: DATAXFER 58827 EXTENSION: AVX512EVEX 58828 ISA_SET: AVX512DQ_512 58829 EXCEPTIONS: AVX512-E7NM 58830 REAL_OPCODE: Y 58831 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 58832 OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu32 58833 IFORM: VPMOVD2M_MASKmskw_ZMMu32_AVX512 58834 } 58835 58836 58837 # EMITTING VPMOVDB (VPMOVDB-128-1) 58838 { 58839 ICLASS: VPMOVDB 58840 CPL: 3 58841 CATEGORY: DATAXFER 58842 EXTENSION: AVX512EVEX 58843 ISA_SET: AVX512F_128 58844 EXCEPTIONS: AVX512-E6NF 58845 REAL_OPCODE: Y 58846 ATTRIBUTES: MASKOP_EVEX 58847 PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 58848 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 58849 IFORM: VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 58850 } 58851 58852 58853 # EMITTING VPMOVDB (VPMOVDB-128-2) 58854 { 58855 ICLASS: VPMOVDB 58856 CPL: 3 58857 CATEGORY: DATAXFER 58858 EXTENSION: AVX512EVEX 58859 ISA_SET: AVX512F_128 58860 EXCEPTIONS: AVX512-E6NF 58861 REAL_OPCODE: Y 58862 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 58863 PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 58864 OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 58865 IFORM: VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 58866 } 58867 58868 58869 # EMITTING VPMOVDB (VPMOVDB-256-1) 58870 { 58871 ICLASS: VPMOVDB 58872 CPL: 3 58873 CATEGORY: DATAXFER 58874 EXTENSION: AVX512EVEX 58875 ISA_SET: AVX512F_256 58876 EXCEPTIONS: AVX512-E6NF 58877 REAL_OPCODE: Y 58878 ATTRIBUTES: MASKOP_EVEX 58879 PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 58880 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 58881 IFORM: VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 58882 } 58883 58884 58885 # EMITTING VPMOVDB (VPMOVDB-256-2) 58886 { 58887 ICLASS: VPMOVDB 58888 CPL: 3 58889 CATEGORY: DATAXFER 58890 EXTENSION: AVX512EVEX 58891 ISA_SET: AVX512F_256 58892 EXCEPTIONS: AVX512-E6NF 58893 REAL_OPCODE: Y 58894 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 58895 PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 58896 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 58897 IFORM: VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 58898 } 58899 58900 58901 # EMITTING VPMOVDW (VPMOVDW-128-1) 58902 { 58903 ICLASS: VPMOVDW 58904 CPL: 3 58905 CATEGORY: DATAXFER 58906 EXTENSION: AVX512EVEX 58907 ISA_SET: AVX512F_128 58908 EXCEPTIONS: AVX512-E6NF 58909 REAL_OPCODE: Y 58910 ATTRIBUTES: MASKOP_EVEX 58911 PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 58912 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 58913 IFORM: VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 58914 } 58915 58916 58917 # EMITTING VPMOVDW (VPMOVDW-128-2) 58918 { 58919 ICLASS: VPMOVDW 58920 CPL: 3 58921 CATEGORY: DATAXFER 58922 EXTENSION: AVX512EVEX 58923 ISA_SET: AVX512F_128 58924 EXCEPTIONS: AVX512-E6NF 58925 REAL_OPCODE: Y 58926 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 58927 PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 58928 OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 58929 IFORM: VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 58930 } 58931 58932 58933 # EMITTING VPMOVDW (VPMOVDW-256-1) 58934 { 58935 ICLASS: VPMOVDW 58936 CPL: 3 58937 CATEGORY: DATAXFER 58938 EXTENSION: AVX512EVEX 58939 ISA_SET: AVX512F_256 58940 EXCEPTIONS: AVX512-E6NF 58941 REAL_OPCODE: Y 58942 ATTRIBUTES: MASKOP_EVEX 58943 PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 58944 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 58945 IFORM: VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 58946 } 58947 58948 58949 # EMITTING VPMOVDW (VPMOVDW-256-2) 58950 { 58951 ICLASS: VPMOVDW 58952 CPL: 3 58953 CATEGORY: DATAXFER 58954 EXTENSION: AVX512EVEX 58955 ISA_SET: AVX512F_256 58956 EXCEPTIONS: AVX512-E6NF 58957 REAL_OPCODE: Y 58958 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 58959 PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 58960 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 58961 IFORM: VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 58962 } 58963 58964 58965 # EMITTING VPMOVM2B (VPMOVM2B-128-1) 58966 { 58967 ICLASS: VPMOVM2B 58968 CPL: 3 58969 CATEGORY: DATAXFER 58970 EXTENSION: AVX512EVEX 58971 ISA_SET: AVX512BW_128 58972 EXCEPTIONS: AVX512-E7NM 58973 REAL_OPCODE: Y 58974 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 58975 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK_B():r:mskw 58976 IFORM: VPMOVM2B_XMMu8_MASKmskw_AVX512 58977 } 58978 58979 58980 # EMITTING VPMOVM2B (VPMOVM2B-256-1) 58981 { 58982 ICLASS: VPMOVM2B 58983 CPL: 3 58984 CATEGORY: DATAXFER 58985 EXTENSION: AVX512EVEX 58986 ISA_SET: AVX512BW_256 58987 EXCEPTIONS: AVX512-E7NM 58988 REAL_OPCODE: Y 58989 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 58990 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK_B():r:mskw 58991 IFORM: VPMOVM2B_YMMu8_MASKmskw_AVX512 58992 } 58993 58994 58995 # EMITTING VPMOVM2B (VPMOVM2B-512-1) 58996 { 58997 ICLASS: VPMOVM2B 58998 CPL: 3 58999 CATEGORY: DATAXFER 59000 EXTENSION: AVX512EVEX 59001 ISA_SET: AVX512BW_512 59002 EXCEPTIONS: AVX512-E7NM 59003 REAL_OPCODE: Y 59004 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 59005 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK_B():r:mskw 59006 IFORM: VPMOVM2B_ZMMu8_MASKmskw_AVX512 59007 } 59008 59009 59010 # EMITTING VPMOVM2D (VPMOVM2D-128-1) 59011 { 59012 ICLASS: VPMOVM2D 59013 CPL: 3 59014 CATEGORY: DATAXFER 59015 EXTENSION: AVX512EVEX 59016 ISA_SET: AVX512DQ_128 59017 EXCEPTIONS: AVX512-E7NM 59018 REAL_OPCODE: Y 59019 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 59020 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw 59021 IFORM: VPMOVM2D_XMMu32_MASKmskw_AVX512 59022 } 59023 59024 59025 # EMITTING VPMOVM2D (VPMOVM2D-256-1) 59026 { 59027 ICLASS: VPMOVM2D 59028 CPL: 3 59029 CATEGORY: DATAXFER 59030 EXTENSION: AVX512EVEX 59031 ISA_SET: AVX512DQ_256 59032 EXCEPTIONS: AVX512-E7NM 59033 REAL_OPCODE: Y 59034 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 59035 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw 59036 IFORM: VPMOVM2D_YMMu32_MASKmskw_AVX512 59037 } 59038 59039 59040 # EMITTING VPMOVM2D (VPMOVM2D-512-1) 59041 { 59042 ICLASS: VPMOVM2D 59043 CPL: 3 59044 CATEGORY: DATAXFER 59045 EXTENSION: AVX512EVEX 59046 ISA_SET: AVX512DQ_512 59047 EXCEPTIONS: AVX512-E7NM 59048 REAL_OPCODE: Y 59049 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 59050 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw 59051 IFORM: VPMOVM2D_ZMMu32_MASKmskw_AVX512 59052 } 59053 59054 59055 # EMITTING VPMOVM2Q (VPMOVM2Q-128-1) 59056 { 59057 ICLASS: VPMOVM2Q 59058 CPL: 3 59059 CATEGORY: DATAXFER 59060 EXTENSION: AVX512EVEX 59061 ISA_SET: AVX512DQ_128 59062 EXCEPTIONS: AVX512-E7NM 59063 REAL_OPCODE: Y 59064 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 59065 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw 59066 IFORM: VPMOVM2Q_XMMu64_MASKmskw_AVX512 59067 } 59068 59069 59070 # EMITTING VPMOVM2Q (VPMOVM2Q-256-1) 59071 { 59072 ICLASS: VPMOVM2Q 59073 CPL: 3 59074 CATEGORY: DATAXFER 59075 EXTENSION: AVX512EVEX 59076 ISA_SET: AVX512DQ_256 59077 EXCEPTIONS: AVX512-E7NM 59078 REAL_OPCODE: Y 59079 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 59080 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw 59081 IFORM: VPMOVM2Q_YMMu64_MASKmskw_AVX512 59082 } 59083 59084 59085 # EMITTING VPMOVM2Q (VPMOVM2Q-512-1) 59086 { 59087 ICLASS: VPMOVM2Q 59088 CPL: 3 59089 CATEGORY: DATAXFER 59090 EXTENSION: AVX512EVEX 59091 ISA_SET: AVX512DQ_512 59092 EXCEPTIONS: AVX512-E7NM 59093 REAL_OPCODE: Y 59094 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 59095 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw 59096 IFORM: VPMOVM2Q_ZMMu64_MASKmskw_AVX512 59097 } 59098 59099 59100 # EMITTING VPMOVM2W (VPMOVM2W-128-1) 59101 { 59102 ICLASS: VPMOVM2W 59103 CPL: 3 59104 CATEGORY: DATAXFER 59105 EXTENSION: AVX512EVEX 59106 ISA_SET: AVX512BW_128 59107 EXCEPTIONS: AVX512-E7NM 59108 REAL_OPCODE: Y 59109 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 59110 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK_B():r:mskw 59111 IFORM: VPMOVM2W_XMMu16_MASKmskw_AVX512 59112 } 59113 59114 59115 # EMITTING VPMOVM2W (VPMOVM2W-256-1) 59116 { 59117 ICLASS: VPMOVM2W 59118 CPL: 3 59119 CATEGORY: DATAXFER 59120 EXTENSION: AVX512EVEX 59121 ISA_SET: AVX512BW_256 59122 EXCEPTIONS: AVX512-E7NM 59123 REAL_OPCODE: Y 59124 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 59125 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK_B():r:mskw 59126 IFORM: VPMOVM2W_YMMu16_MASKmskw_AVX512 59127 } 59128 59129 59130 # EMITTING VPMOVM2W (VPMOVM2W-512-1) 59131 { 59132 ICLASS: VPMOVM2W 59133 CPL: 3 59134 CATEGORY: DATAXFER 59135 EXTENSION: AVX512EVEX 59136 ISA_SET: AVX512BW_512 59137 EXCEPTIONS: AVX512-E7NM 59138 REAL_OPCODE: Y 59139 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 59140 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK_B():r:mskw 59141 IFORM: VPMOVM2W_ZMMu16_MASKmskw_AVX512 59142 } 59143 59144 59145 # EMITTING VPMOVQ2M (VPMOVQ2M-128-1) 59146 { 59147 ICLASS: VPMOVQ2M 59148 CPL: 3 59149 CATEGORY: DATAXFER 59150 EXTENSION: AVX512EVEX 59151 ISA_SET: AVX512DQ_128 59152 EXCEPTIONS: AVX512-E7NM 59153 REAL_OPCODE: Y 59154 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 59155 OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u64 59156 IFORM: VPMOVQ2M_MASKmskw_XMMu64_AVX512 59157 } 59158 59159 59160 # EMITTING VPMOVQ2M (VPMOVQ2M-256-1) 59161 { 59162 ICLASS: VPMOVQ2M 59163 CPL: 3 59164 CATEGORY: DATAXFER 59165 EXTENSION: AVX512EVEX 59166 ISA_SET: AVX512DQ_256 59167 EXCEPTIONS: AVX512-E7NM 59168 REAL_OPCODE: Y 59169 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 59170 OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u64 59171 IFORM: VPMOVQ2M_MASKmskw_YMMu64_AVX512 59172 } 59173 59174 59175 # EMITTING VPMOVQ2M (VPMOVQ2M-512-1) 59176 { 59177 ICLASS: VPMOVQ2M 59178 CPL: 3 59179 CATEGORY: DATAXFER 59180 EXTENSION: AVX512EVEX 59181 ISA_SET: AVX512DQ_512 59182 EXCEPTIONS: AVX512-E7NM 59183 REAL_OPCODE: Y 59184 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 59185 OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu64 59186 IFORM: VPMOVQ2M_MASKmskw_ZMMu64_AVX512 59187 } 59188 59189 59190 # EMITTING VPMOVQB (VPMOVQB-128-1) 59191 { 59192 ICLASS: VPMOVQB 59193 CPL: 3 59194 CATEGORY: DATAXFER 59195 EXTENSION: AVX512EVEX 59196 ISA_SET: AVX512F_128 59197 EXCEPTIONS: AVX512-E6NF 59198 REAL_OPCODE: Y 59199 ATTRIBUTES: MASKOP_EVEX 59200 PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 59201 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 59202 IFORM: VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 59203 } 59204 59205 59206 # EMITTING VPMOVQB (VPMOVQB-128-2) 59207 { 59208 ICLASS: VPMOVQB 59209 CPL: 3 59210 CATEGORY: DATAXFER 59211 EXTENSION: AVX512EVEX 59212 ISA_SET: AVX512F_128 59213 EXCEPTIONS: AVX512-E6NF 59214 REAL_OPCODE: Y 59215 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 59216 PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 59217 OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 59218 IFORM: VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 59219 } 59220 59221 59222 # EMITTING VPMOVQB (VPMOVQB-256-1) 59223 { 59224 ICLASS: VPMOVQB 59225 CPL: 3 59226 CATEGORY: DATAXFER 59227 EXTENSION: AVX512EVEX 59228 ISA_SET: AVX512F_256 59229 EXCEPTIONS: AVX512-E6NF 59230 REAL_OPCODE: Y 59231 ATTRIBUTES: MASKOP_EVEX 59232 PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 59233 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 59234 IFORM: VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 59235 } 59236 59237 59238 # EMITTING VPMOVQB (VPMOVQB-256-2) 59239 { 59240 ICLASS: VPMOVQB 59241 CPL: 3 59242 CATEGORY: DATAXFER 59243 EXTENSION: AVX512EVEX 59244 ISA_SET: AVX512F_256 59245 EXCEPTIONS: AVX512-E6NF 59246 REAL_OPCODE: Y 59247 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 59248 PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 59249 OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 59250 IFORM: VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 59251 } 59252 59253 59254 # EMITTING VPMOVQD (VPMOVQD-128-1) 59255 { 59256 ICLASS: VPMOVQD 59257 CPL: 3 59258 CATEGORY: DATAXFER 59259 EXTENSION: AVX512EVEX 59260 ISA_SET: AVX512F_128 59261 EXCEPTIONS: AVX512-E6NF 59262 REAL_OPCODE: Y 59263 ATTRIBUTES: MASKOP_EVEX 59264 PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 59265 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 59266 IFORM: VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 59267 } 59268 59269 59270 # EMITTING VPMOVQD (VPMOVQD-128-2) 59271 { 59272 ICLASS: VPMOVQD 59273 CPL: 3 59274 CATEGORY: DATAXFER 59275 EXTENSION: AVX512EVEX 59276 ISA_SET: AVX512F_128 59277 EXCEPTIONS: AVX512-E6NF 59278 REAL_OPCODE: Y 59279 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59280 PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 59281 OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 59282 IFORM: VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 59283 } 59284 59285 59286 # EMITTING VPMOVQD (VPMOVQD-256-1) 59287 { 59288 ICLASS: VPMOVQD 59289 CPL: 3 59290 CATEGORY: DATAXFER 59291 EXTENSION: AVX512EVEX 59292 ISA_SET: AVX512F_256 59293 EXCEPTIONS: AVX512-E6NF 59294 REAL_OPCODE: Y 59295 ATTRIBUTES: MASKOP_EVEX 59296 PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 59297 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 59298 IFORM: VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 59299 } 59300 59301 59302 # EMITTING VPMOVQD (VPMOVQD-256-2) 59303 { 59304 ICLASS: VPMOVQD 59305 CPL: 3 59306 CATEGORY: DATAXFER 59307 EXTENSION: AVX512EVEX 59308 ISA_SET: AVX512F_256 59309 EXCEPTIONS: AVX512-E6NF 59310 REAL_OPCODE: Y 59311 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59312 PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 59313 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 59314 IFORM: VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 59315 } 59316 59317 59318 # EMITTING VPMOVQW (VPMOVQW-128-1) 59319 { 59320 ICLASS: VPMOVQW 59321 CPL: 3 59322 CATEGORY: DATAXFER 59323 EXTENSION: AVX512EVEX 59324 ISA_SET: AVX512F_128 59325 EXCEPTIONS: AVX512-E6NF 59326 REAL_OPCODE: Y 59327 ATTRIBUTES: MASKOP_EVEX 59328 PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 59329 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 59330 IFORM: VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 59331 } 59332 59333 59334 # EMITTING VPMOVQW (VPMOVQW-128-2) 59335 { 59336 ICLASS: VPMOVQW 59337 CPL: 3 59338 CATEGORY: DATAXFER 59339 EXTENSION: AVX512EVEX 59340 ISA_SET: AVX512F_128 59341 EXCEPTIONS: AVX512-E6NF 59342 REAL_OPCODE: Y 59343 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 59344 PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 59345 OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 59346 IFORM: VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 59347 } 59348 59349 59350 # EMITTING VPMOVQW (VPMOVQW-256-1) 59351 { 59352 ICLASS: VPMOVQW 59353 CPL: 3 59354 CATEGORY: DATAXFER 59355 EXTENSION: AVX512EVEX 59356 ISA_SET: AVX512F_256 59357 EXCEPTIONS: AVX512-E6NF 59358 REAL_OPCODE: Y 59359 ATTRIBUTES: MASKOP_EVEX 59360 PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 59361 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 59362 IFORM: VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 59363 } 59364 59365 59366 # EMITTING VPMOVQW (VPMOVQW-256-2) 59367 { 59368 ICLASS: VPMOVQW 59369 CPL: 3 59370 CATEGORY: DATAXFER 59371 EXTENSION: AVX512EVEX 59372 ISA_SET: AVX512F_256 59373 EXCEPTIONS: AVX512-E6NF 59374 REAL_OPCODE: Y 59375 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 59376 PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 59377 OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 59378 IFORM: VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 59379 } 59380 59381 59382 # EMITTING VPMOVSDB (VPMOVSDB-128-1) 59383 { 59384 ICLASS: VPMOVSDB 59385 CPL: 3 59386 CATEGORY: DATAXFER 59387 EXTENSION: AVX512EVEX 59388 ISA_SET: AVX512F_128 59389 EXCEPTIONS: AVX512-E6NF 59390 REAL_OPCODE: Y 59391 ATTRIBUTES: MASKOP_EVEX 59392 PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 59393 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 59394 IFORM: VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 59395 } 59396 59397 59398 # EMITTING VPMOVSDB (VPMOVSDB-128-2) 59399 { 59400 ICLASS: VPMOVSDB 59401 CPL: 3 59402 CATEGORY: DATAXFER 59403 EXTENSION: AVX512EVEX 59404 ISA_SET: AVX512F_128 59405 EXCEPTIONS: AVX512-E6NF 59406 REAL_OPCODE: Y 59407 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 59408 PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 59409 OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 59410 IFORM: VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 59411 } 59412 59413 59414 # EMITTING VPMOVSDB (VPMOVSDB-256-1) 59415 { 59416 ICLASS: VPMOVSDB 59417 CPL: 3 59418 CATEGORY: DATAXFER 59419 EXTENSION: AVX512EVEX 59420 ISA_SET: AVX512F_256 59421 EXCEPTIONS: AVX512-E6NF 59422 REAL_OPCODE: Y 59423 ATTRIBUTES: MASKOP_EVEX 59424 PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 59425 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 59426 IFORM: VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 59427 } 59428 59429 59430 # EMITTING VPMOVSDB (VPMOVSDB-256-2) 59431 { 59432 ICLASS: VPMOVSDB 59433 CPL: 3 59434 CATEGORY: DATAXFER 59435 EXTENSION: AVX512EVEX 59436 ISA_SET: AVX512F_256 59437 EXCEPTIONS: AVX512-E6NF 59438 REAL_OPCODE: Y 59439 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 59440 PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 59441 OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 59442 IFORM: VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 59443 } 59444 59445 59446 # EMITTING VPMOVSDW (VPMOVSDW-128-1) 59447 { 59448 ICLASS: VPMOVSDW 59449 CPL: 3 59450 CATEGORY: DATAXFER 59451 EXTENSION: AVX512EVEX 59452 ISA_SET: AVX512F_128 59453 EXCEPTIONS: AVX512-E6NF 59454 REAL_OPCODE: Y 59455 ATTRIBUTES: MASKOP_EVEX 59456 PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 59457 OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 59458 IFORM: VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 59459 } 59460 59461 59462 # EMITTING VPMOVSDW (VPMOVSDW-128-2) 59463 { 59464 ICLASS: VPMOVSDW 59465 CPL: 3 59466 CATEGORY: DATAXFER 59467 EXTENSION: AVX512EVEX 59468 ISA_SET: AVX512F_128 59469 EXCEPTIONS: AVX512-E6NF 59470 REAL_OPCODE: Y 59471 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59472 PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 59473 OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 59474 IFORM: VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 59475 } 59476 59477 59478 # EMITTING VPMOVSDW (VPMOVSDW-256-1) 59479 { 59480 ICLASS: VPMOVSDW 59481 CPL: 3 59482 CATEGORY: DATAXFER 59483 EXTENSION: AVX512EVEX 59484 ISA_SET: AVX512F_256 59485 EXCEPTIONS: AVX512-E6NF 59486 REAL_OPCODE: Y 59487 ATTRIBUTES: MASKOP_EVEX 59488 PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 59489 OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 59490 IFORM: VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 59491 } 59492 59493 59494 # EMITTING VPMOVSDW (VPMOVSDW-256-2) 59495 { 59496 ICLASS: VPMOVSDW 59497 CPL: 3 59498 CATEGORY: DATAXFER 59499 EXTENSION: AVX512EVEX 59500 ISA_SET: AVX512F_256 59501 EXCEPTIONS: AVX512-E6NF 59502 REAL_OPCODE: Y 59503 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59504 PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 59505 OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 59506 IFORM: VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 59507 } 59508 59509 59510 # EMITTING VPMOVSQB (VPMOVSQB-128-1) 59511 { 59512 ICLASS: VPMOVSQB 59513 CPL: 3 59514 CATEGORY: DATAXFER 59515 EXTENSION: AVX512EVEX 59516 ISA_SET: AVX512F_128 59517 EXCEPTIONS: AVX512-E6NF 59518 REAL_OPCODE: Y 59519 ATTRIBUTES: MASKOP_EVEX 59520 PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 59521 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 59522 IFORM: VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 59523 } 59524 59525 59526 # EMITTING VPMOVSQB (VPMOVSQB-128-2) 59527 { 59528 ICLASS: VPMOVSQB 59529 CPL: 3 59530 CATEGORY: DATAXFER 59531 EXTENSION: AVX512EVEX 59532 ISA_SET: AVX512F_128 59533 EXCEPTIONS: AVX512-E6NF 59534 REAL_OPCODE: Y 59535 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 59536 PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 59537 OPERANDS: MEM0:w:wrd:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 59538 IFORM: VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 59539 } 59540 59541 59542 # EMITTING VPMOVSQB (VPMOVSQB-256-1) 59543 { 59544 ICLASS: VPMOVSQB 59545 CPL: 3 59546 CATEGORY: DATAXFER 59547 EXTENSION: AVX512EVEX 59548 ISA_SET: AVX512F_256 59549 EXCEPTIONS: AVX512-E6NF 59550 REAL_OPCODE: Y 59551 ATTRIBUTES: MASKOP_EVEX 59552 PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 59553 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 59554 IFORM: VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 59555 } 59556 59557 59558 # EMITTING VPMOVSQB (VPMOVSQB-256-2) 59559 { 59560 ICLASS: VPMOVSQB 59561 CPL: 3 59562 CATEGORY: DATAXFER 59563 EXTENSION: AVX512EVEX 59564 ISA_SET: AVX512F_256 59565 EXCEPTIONS: AVX512-E6NF 59566 REAL_OPCODE: Y 59567 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 59568 PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 59569 OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 59570 IFORM: VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 59571 } 59572 59573 59574 # EMITTING VPMOVSQD (VPMOVSQD-128-1) 59575 { 59576 ICLASS: VPMOVSQD 59577 CPL: 3 59578 CATEGORY: DATAXFER 59579 EXTENSION: AVX512EVEX 59580 ISA_SET: AVX512F_128 59581 EXCEPTIONS: AVX512-E6NF 59582 REAL_OPCODE: Y 59583 ATTRIBUTES: MASKOP_EVEX 59584 PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 59585 OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 59586 IFORM: VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 59587 } 59588 59589 59590 # EMITTING VPMOVSQD (VPMOVSQD-128-2) 59591 { 59592 ICLASS: VPMOVSQD 59593 CPL: 3 59594 CATEGORY: DATAXFER 59595 EXTENSION: AVX512EVEX 59596 ISA_SET: AVX512F_128 59597 EXCEPTIONS: AVX512-E6NF 59598 REAL_OPCODE: Y 59599 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59600 PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 59601 OPERANDS: MEM0:w:q:i32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 59602 IFORM: VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 59603 } 59604 59605 59606 # EMITTING VPMOVSQD (VPMOVSQD-256-1) 59607 { 59608 ICLASS: VPMOVSQD 59609 CPL: 3 59610 CATEGORY: DATAXFER 59611 EXTENSION: AVX512EVEX 59612 ISA_SET: AVX512F_256 59613 EXCEPTIONS: AVX512-E6NF 59614 REAL_OPCODE: Y 59615 ATTRIBUTES: MASKOP_EVEX 59616 PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 59617 OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 59618 IFORM: VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 59619 } 59620 59621 59622 # EMITTING VPMOVSQD (VPMOVSQD-256-2) 59623 { 59624 ICLASS: VPMOVSQD 59625 CPL: 3 59626 CATEGORY: DATAXFER 59627 EXTENSION: AVX512EVEX 59628 ISA_SET: AVX512F_256 59629 EXCEPTIONS: AVX512-E6NF 59630 REAL_OPCODE: Y 59631 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59632 PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 59633 OPERANDS: MEM0:w:dq:i32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 59634 IFORM: VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 59635 } 59636 59637 59638 # EMITTING VPMOVSQW (VPMOVSQW-128-1) 59639 { 59640 ICLASS: VPMOVSQW 59641 CPL: 3 59642 CATEGORY: DATAXFER 59643 EXTENSION: AVX512EVEX 59644 ISA_SET: AVX512F_128 59645 EXCEPTIONS: AVX512-E6NF 59646 REAL_OPCODE: Y 59647 ATTRIBUTES: MASKOP_EVEX 59648 PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 59649 OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 59650 IFORM: VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 59651 } 59652 59653 59654 # EMITTING VPMOVSQW (VPMOVSQW-128-2) 59655 { 59656 ICLASS: VPMOVSQW 59657 CPL: 3 59658 CATEGORY: DATAXFER 59659 EXTENSION: AVX512EVEX 59660 ISA_SET: AVX512F_128 59661 EXCEPTIONS: AVX512-E6NF 59662 REAL_OPCODE: Y 59663 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 59664 PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 59665 OPERANDS: MEM0:w:d:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 59666 IFORM: VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 59667 } 59668 59669 59670 # EMITTING VPMOVSQW (VPMOVSQW-256-1) 59671 { 59672 ICLASS: VPMOVSQW 59673 CPL: 3 59674 CATEGORY: DATAXFER 59675 EXTENSION: AVX512EVEX 59676 ISA_SET: AVX512F_256 59677 EXCEPTIONS: AVX512-E6NF 59678 REAL_OPCODE: Y 59679 ATTRIBUTES: MASKOP_EVEX 59680 PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 59681 OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 59682 IFORM: VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 59683 } 59684 59685 59686 # EMITTING VPMOVSQW (VPMOVSQW-256-2) 59687 { 59688 ICLASS: VPMOVSQW 59689 CPL: 3 59690 CATEGORY: DATAXFER 59691 EXTENSION: AVX512EVEX 59692 ISA_SET: AVX512F_256 59693 EXCEPTIONS: AVX512-E6NF 59694 REAL_OPCODE: Y 59695 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 59696 PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 59697 OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 59698 IFORM: VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 59699 } 59700 59701 59702 # EMITTING VPMOVSWB (VPMOVSWB-128-1) 59703 { 59704 ICLASS: VPMOVSWB 59705 CPL: 3 59706 CATEGORY: DATAXFER 59707 EXTENSION: AVX512EVEX 59708 ISA_SET: AVX512BW_128 59709 EXCEPTIONS: AVX512-E6NF 59710 REAL_OPCODE: Y 59711 ATTRIBUTES: MASKOP_EVEX 59712 PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 59713 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i16 59714 IFORM: VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 59715 } 59716 59717 59718 # EMITTING VPMOVSWB (VPMOVSWB-128-2) 59719 { 59720 ICLASS: VPMOVSWB 59721 CPL: 3 59722 CATEGORY: DATAXFER 59723 EXTENSION: AVX512EVEX 59724 ISA_SET: AVX512BW_128 59725 EXCEPTIONS: AVX512-E6NF 59726 REAL_OPCODE: Y 59727 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59728 PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 59729 OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i16 59730 IFORM: VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 59731 } 59732 59733 59734 # EMITTING VPMOVSWB (VPMOVSWB-256-1) 59735 { 59736 ICLASS: VPMOVSWB 59737 CPL: 3 59738 CATEGORY: DATAXFER 59739 EXTENSION: AVX512EVEX 59740 ISA_SET: AVX512BW_256 59741 EXCEPTIONS: AVX512-E6NF 59742 REAL_OPCODE: Y 59743 ATTRIBUTES: MASKOP_EVEX 59744 PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 59745 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i16 59746 IFORM: VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 59747 } 59748 59749 59750 # EMITTING VPMOVSWB (VPMOVSWB-256-2) 59751 { 59752 ICLASS: VPMOVSWB 59753 CPL: 3 59754 CATEGORY: DATAXFER 59755 EXTENSION: AVX512EVEX 59756 ISA_SET: AVX512BW_256 59757 EXCEPTIONS: AVX512-E6NF 59758 REAL_OPCODE: Y 59759 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59760 PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 59761 OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i16 59762 IFORM: VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 59763 } 59764 59765 59766 # EMITTING VPMOVSWB (VPMOVSWB-512-1) 59767 { 59768 ICLASS: VPMOVSWB 59769 CPL: 3 59770 CATEGORY: DATAXFER 59771 EXTENSION: AVX512EVEX 59772 ISA_SET: AVX512BW_512 59773 EXCEPTIONS: AVX512-E6NF 59774 REAL_OPCODE: Y 59775 ATTRIBUTES: MASKOP_EVEX 59776 PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 59777 OPERANDS: REG0=YMM_B3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi16 59778 IFORM: VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 59779 } 59780 59781 59782 # EMITTING VPMOVSWB (VPMOVSWB-512-2) 59783 { 59784 ICLASS: VPMOVSWB 59785 CPL: 3 59786 CATEGORY: DATAXFER 59787 EXTENSION: AVX512EVEX 59788 ISA_SET: AVX512BW_512 59789 EXCEPTIONS: AVX512-E6NF 59790 REAL_OPCODE: Y 59791 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59792 PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 59793 OPERANDS: MEM0:w:qq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi16 59794 IFORM: VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 59795 } 59796 59797 59798 # EMITTING VPMOVSXBD (VPMOVSXBD-128-1) 59799 { 59800 ICLASS: VPMOVSXBD 59801 CPL: 3 59802 CATEGORY: DATAXFER 59803 EXTENSION: AVX512EVEX 59804 ISA_SET: AVX512F_128 59805 EXCEPTIONS: AVX512-E5 59806 REAL_OPCODE: Y 59807 ATTRIBUTES: MASKOP_EVEX 59808 PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 59809 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 59810 IFORM: VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 59811 } 59812 59813 { 59814 ICLASS: VPMOVSXBD 59815 CPL: 3 59816 CATEGORY: DATAXFER 59817 EXTENSION: AVX512EVEX 59818 ISA_SET: AVX512F_128 59819 EXCEPTIONS: AVX512-E5 59820 REAL_OPCODE: Y 59821 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 59822 PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 59823 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 59824 IFORM: VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 59825 } 59826 59827 59828 # EMITTING VPMOVSXBD (VPMOVSXBD-256-1) 59829 { 59830 ICLASS: VPMOVSXBD 59831 CPL: 3 59832 CATEGORY: DATAXFER 59833 EXTENSION: AVX512EVEX 59834 ISA_SET: AVX512F_256 59835 EXCEPTIONS: AVX512-E5 59836 REAL_OPCODE: Y 59837 ATTRIBUTES: MASKOP_EVEX 59838 PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 59839 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 59840 IFORM: VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 59841 } 59842 59843 { 59844 ICLASS: VPMOVSXBD 59845 CPL: 3 59846 CATEGORY: DATAXFER 59847 EXTENSION: AVX512EVEX 59848 ISA_SET: AVX512F_256 59849 EXCEPTIONS: AVX512-E5 59850 REAL_OPCODE: Y 59851 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 59852 PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 59853 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 59854 IFORM: VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 59855 } 59856 59857 59858 # EMITTING VPMOVSXBQ (VPMOVSXBQ-128-1) 59859 { 59860 ICLASS: VPMOVSXBQ 59861 CPL: 3 59862 CATEGORY: DATAXFER 59863 EXTENSION: AVX512EVEX 59864 ISA_SET: AVX512F_128 59865 EXCEPTIONS: AVX512-E5 59866 REAL_OPCODE: Y 59867 ATTRIBUTES: MASKOP_EVEX 59868 PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 59869 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 59870 IFORM: VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 59871 } 59872 59873 { 59874 ICLASS: VPMOVSXBQ 59875 CPL: 3 59876 CATEGORY: DATAXFER 59877 EXTENSION: AVX512EVEX 59878 ISA_SET: AVX512F_128 59879 EXCEPTIONS: AVX512-E5 59880 REAL_OPCODE: Y 59881 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 59882 PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 59883 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 59884 IFORM: VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 59885 } 59886 59887 59888 # EMITTING VPMOVSXBQ (VPMOVSXBQ-256-1) 59889 { 59890 ICLASS: VPMOVSXBQ 59891 CPL: 3 59892 CATEGORY: DATAXFER 59893 EXTENSION: AVX512EVEX 59894 ISA_SET: AVX512F_256 59895 EXCEPTIONS: AVX512-E5 59896 REAL_OPCODE: Y 59897 ATTRIBUTES: MASKOP_EVEX 59898 PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 59899 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 59900 IFORM: VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 59901 } 59902 59903 { 59904 ICLASS: VPMOVSXBQ 59905 CPL: 3 59906 CATEGORY: DATAXFER 59907 EXTENSION: AVX512EVEX 59908 ISA_SET: AVX512F_256 59909 EXCEPTIONS: AVX512-E5 59910 REAL_OPCODE: Y 59911 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 59912 PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 59913 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 59914 IFORM: VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 59915 } 59916 59917 59918 # EMITTING VPMOVSXBW (VPMOVSXBW-128-1) 59919 { 59920 ICLASS: VPMOVSXBW 59921 CPL: 3 59922 CATEGORY: DATAXFER 59923 EXTENSION: AVX512EVEX 59924 ISA_SET: AVX512BW_128 59925 EXCEPTIONS: AVX512-E5 59926 REAL_OPCODE: Y 59927 ATTRIBUTES: MASKOP_EVEX 59928 PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 59929 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 59930 IFORM: VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 59931 } 59932 59933 { 59934 ICLASS: VPMOVSXBW 59935 CPL: 3 59936 CATEGORY: DATAXFER 59937 EXTENSION: AVX512EVEX 59938 ISA_SET: AVX512BW_128 59939 EXCEPTIONS: AVX512-E5 59940 REAL_OPCODE: Y 59941 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59942 PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 59943 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 59944 IFORM: VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 59945 } 59946 59947 59948 # EMITTING VPMOVSXBW (VPMOVSXBW-256-1) 59949 { 59950 ICLASS: VPMOVSXBW 59951 CPL: 3 59952 CATEGORY: DATAXFER 59953 EXTENSION: AVX512EVEX 59954 ISA_SET: AVX512BW_256 59955 EXCEPTIONS: AVX512-E5 59956 REAL_OPCODE: Y 59957 ATTRIBUTES: MASKOP_EVEX 59958 PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 59959 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 59960 IFORM: VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 59961 } 59962 59963 { 59964 ICLASS: VPMOVSXBW 59965 CPL: 3 59966 CATEGORY: DATAXFER 59967 EXTENSION: AVX512EVEX 59968 ISA_SET: AVX512BW_256 59969 EXCEPTIONS: AVX512-E5 59970 REAL_OPCODE: Y 59971 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 59972 PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 59973 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 59974 IFORM: VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 59975 } 59976 59977 59978 # EMITTING VPMOVSXBW (VPMOVSXBW-512-1) 59979 { 59980 ICLASS: VPMOVSXBW 59981 CPL: 3 59982 CATEGORY: DATAXFER 59983 EXTENSION: AVX512EVEX 59984 ISA_SET: AVX512BW_512 59985 EXCEPTIONS: AVX512-E5 59986 REAL_OPCODE: Y 59987 ATTRIBUTES: MASKOP_EVEX 59988 PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 59989 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 59990 IFORM: VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 59991 } 59992 59993 { 59994 ICLASS: VPMOVSXBW 59995 CPL: 3 59996 CATEGORY: DATAXFER 59997 EXTENSION: AVX512EVEX 59998 ISA_SET: AVX512BW_512 59999 EXCEPTIONS: AVX512-E5 60000 REAL_OPCODE: Y 60001 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60002 PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 60003 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 60004 IFORM: VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 60005 } 60006 60007 60008 # EMITTING VPMOVSXDQ (VPMOVSXDQ-128-1) 60009 { 60010 ICLASS: VPMOVSXDQ 60011 CPL: 3 60012 CATEGORY: DATAXFER 60013 EXTENSION: AVX512EVEX 60014 ISA_SET: AVX512F_128 60015 EXCEPTIONS: AVX512-E5 60016 REAL_OPCODE: Y 60017 ATTRIBUTES: MASKOP_EVEX 60018 PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 60019 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 60020 IFORM: VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 60021 } 60022 60023 { 60024 ICLASS: VPMOVSXDQ 60025 CPL: 3 60026 CATEGORY: DATAXFER 60027 EXTENSION: AVX512EVEX 60028 ISA_SET: AVX512F_128 60029 EXCEPTIONS: AVX512-E5 60030 REAL_OPCODE: Y 60031 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60032 PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 60033 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 60034 IFORM: VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 60035 } 60036 60037 60038 # EMITTING VPMOVSXDQ (VPMOVSXDQ-256-1) 60039 { 60040 ICLASS: VPMOVSXDQ 60041 CPL: 3 60042 CATEGORY: DATAXFER 60043 EXTENSION: AVX512EVEX 60044 ISA_SET: AVX512F_256 60045 EXCEPTIONS: AVX512-E5 60046 REAL_OPCODE: Y 60047 ATTRIBUTES: MASKOP_EVEX 60048 PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 60049 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 60050 IFORM: VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 60051 } 60052 60053 { 60054 ICLASS: VPMOVSXDQ 60055 CPL: 3 60056 CATEGORY: DATAXFER 60057 EXTENSION: AVX512EVEX 60058 ISA_SET: AVX512F_256 60059 EXCEPTIONS: AVX512-E5 60060 REAL_OPCODE: Y 60061 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60062 PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 60063 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 60064 IFORM: VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 60065 } 60066 60067 60068 # EMITTING VPMOVSXWD (VPMOVSXWD-128-1) 60069 { 60070 ICLASS: VPMOVSXWD 60071 CPL: 3 60072 CATEGORY: DATAXFER 60073 EXTENSION: AVX512EVEX 60074 ISA_SET: AVX512F_128 60075 EXCEPTIONS: AVX512-E5 60076 REAL_OPCODE: Y 60077 ATTRIBUTES: MASKOP_EVEX 60078 PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 60079 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 60080 IFORM: VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 60081 } 60082 60083 { 60084 ICLASS: VPMOVSXWD 60085 CPL: 3 60086 CATEGORY: DATAXFER 60087 EXTENSION: AVX512EVEX 60088 ISA_SET: AVX512F_128 60089 EXCEPTIONS: AVX512-E5 60090 REAL_OPCODE: Y 60091 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60092 PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 60093 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 60094 IFORM: VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 60095 } 60096 60097 60098 # EMITTING VPMOVSXWD (VPMOVSXWD-256-1) 60099 { 60100 ICLASS: VPMOVSXWD 60101 CPL: 3 60102 CATEGORY: DATAXFER 60103 EXTENSION: AVX512EVEX 60104 ISA_SET: AVX512F_256 60105 EXCEPTIONS: AVX512-E5 60106 REAL_OPCODE: Y 60107 ATTRIBUTES: MASKOP_EVEX 60108 PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 60109 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 60110 IFORM: VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 60111 } 60112 60113 { 60114 ICLASS: VPMOVSXWD 60115 CPL: 3 60116 CATEGORY: DATAXFER 60117 EXTENSION: AVX512EVEX 60118 ISA_SET: AVX512F_256 60119 EXCEPTIONS: AVX512-E5 60120 REAL_OPCODE: Y 60121 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60122 PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 60123 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 60124 IFORM: VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 60125 } 60126 60127 60128 # EMITTING VPMOVSXWQ (VPMOVSXWQ-128-1) 60129 { 60130 ICLASS: VPMOVSXWQ 60131 CPL: 3 60132 CATEGORY: DATAXFER 60133 EXTENSION: AVX512EVEX 60134 ISA_SET: AVX512F_128 60135 EXCEPTIONS: AVX512-E5 60136 REAL_OPCODE: Y 60137 ATTRIBUTES: MASKOP_EVEX 60138 PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 60139 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 60140 IFORM: VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 60141 } 60142 60143 { 60144 ICLASS: VPMOVSXWQ 60145 CPL: 3 60146 CATEGORY: DATAXFER 60147 EXTENSION: AVX512EVEX 60148 ISA_SET: AVX512F_128 60149 EXCEPTIONS: AVX512-E5 60150 REAL_OPCODE: Y 60151 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 60152 PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 60153 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 60154 IFORM: VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 60155 } 60156 60157 60158 # EMITTING VPMOVSXWQ (VPMOVSXWQ-256-1) 60159 { 60160 ICLASS: VPMOVSXWQ 60161 CPL: 3 60162 CATEGORY: DATAXFER 60163 EXTENSION: AVX512EVEX 60164 ISA_SET: AVX512F_256 60165 EXCEPTIONS: AVX512-E5 60166 REAL_OPCODE: Y 60167 ATTRIBUTES: MASKOP_EVEX 60168 PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 60169 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 60170 IFORM: VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 60171 } 60172 60173 { 60174 ICLASS: VPMOVSXWQ 60175 CPL: 3 60176 CATEGORY: DATAXFER 60177 EXTENSION: AVX512EVEX 60178 ISA_SET: AVX512F_256 60179 EXCEPTIONS: AVX512-E5 60180 REAL_OPCODE: Y 60181 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 60182 PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 60183 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 60184 IFORM: VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 60185 } 60186 60187 60188 # EMITTING VPMOVUSDB (VPMOVUSDB-128-1) 60189 { 60190 ICLASS: VPMOVUSDB 60191 CPL: 3 60192 CATEGORY: DATAXFER 60193 EXTENSION: AVX512EVEX 60194 ISA_SET: AVX512F_128 60195 EXCEPTIONS: AVX512-E6NF 60196 REAL_OPCODE: Y 60197 ATTRIBUTES: MASKOP_EVEX 60198 PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 60199 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 60200 IFORM: VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 60201 } 60202 60203 60204 # EMITTING VPMOVUSDB (VPMOVUSDB-128-2) 60205 { 60206 ICLASS: VPMOVUSDB 60207 CPL: 3 60208 CATEGORY: DATAXFER 60209 EXTENSION: AVX512EVEX 60210 ISA_SET: AVX512F_128 60211 EXCEPTIONS: AVX512-E6NF 60212 REAL_OPCODE: Y 60213 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 60214 PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 60215 OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 60216 IFORM: VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 60217 } 60218 60219 60220 # EMITTING VPMOVUSDB (VPMOVUSDB-256-1) 60221 { 60222 ICLASS: VPMOVUSDB 60223 CPL: 3 60224 CATEGORY: DATAXFER 60225 EXTENSION: AVX512EVEX 60226 ISA_SET: AVX512F_256 60227 EXCEPTIONS: AVX512-E6NF 60228 REAL_OPCODE: Y 60229 ATTRIBUTES: MASKOP_EVEX 60230 PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 60231 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 60232 IFORM: VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 60233 } 60234 60235 60236 # EMITTING VPMOVUSDB (VPMOVUSDB-256-2) 60237 { 60238 ICLASS: VPMOVUSDB 60239 CPL: 3 60240 CATEGORY: DATAXFER 60241 EXTENSION: AVX512EVEX 60242 ISA_SET: AVX512F_256 60243 EXCEPTIONS: AVX512-E6NF 60244 REAL_OPCODE: Y 60245 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 60246 PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 60247 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 60248 IFORM: VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 60249 } 60250 60251 60252 # EMITTING VPMOVUSDW (VPMOVUSDW-128-1) 60253 { 60254 ICLASS: VPMOVUSDW 60255 CPL: 3 60256 CATEGORY: DATAXFER 60257 EXTENSION: AVX512EVEX 60258 ISA_SET: AVX512F_128 60259 EXCEPTIONS: AVX512-E6NF 60260 REAL_OPCODE: Y 60261 ATTRIBUTES: MASKOP_EVEX 60262 PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 60263 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 60264 IFORM: VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 60265 } 60266 60267 60268 # EMITTING VPMOVUSDW (VPMOVUSDW-128-2) 60269 { 60270 ICLASS: VPMOVUSDW 60271 CPL: 3 60272 CATEGORY: DATAXFER 60273 EXTENSION: AVX512EVEX 60274 ISA_SET: AVX512F_128 60275 EXCEPTIONS: AVX512-E6NF 60276 REAL_OPCODE: Y 60277 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60278 PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 60279 OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 60280 IFORM: VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 60281 } 60282 60283 60284 # EMITTING VPMOVUSDW (VPMOVUSDW-256-1) 60285 { 60286 ICLASS: VPMOVUSDW 60287 CPL: 3 60288 CATEGORY: DATAXFER 60289 EXTENSION: AVX512EVEX 60290 ISA_SET: AVX512F_256 60291 EXCEPTIONS: AVX512-E6NF 60292 REAL_OPCODE: Y 60293 ATTRIBUTES: MASKOP_EVEX 60294 PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 60295 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 60296 IFORM: VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 60297 } 60298 60299 60300 # EMITTING VPMOVUSDW (VPMOVUSDW-256-2) 60301 { 60302 ICLASS: VPMOVUSDW 60303 CPL: 3 60304 CATEGORY: DATAXFER 60305 EXTENSION: AVX512EVEX 60306 ISA_SET: AVX512F_256 60307 EXCEPTIONS: AVX512-E6NF 60308 REAL_OPCODE: Y 60309 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60310 PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 60311 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 60312 IFORM: VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 60313 } 60314 60315 60316 # EMITTING VPMOVUSQB (VPMOVUSQB-128-1) 60317 { 60318 ICLASS: VPMOVUSQB 60319 CPL: 3 60320 CATEGORY: DATAXFER 60321 EXTENSION: AVX512EVEX 60322 ISA_SET: AVX512F_128 60323 EXCEPTIONS: AVX512-E6NF 60324 REAL_OPCODE: Y 60325 ATTRIBUTES: MASKOP_EVEX 60326 PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 60327 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 60328 IFORM: VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 60329 } 60330 60331 60332 # EMITTING VPMOVUSQB (VPMOVUSQB-128-2) 60333 { 60334 ICLASS: VPMOVUSQB 60335 CPL: 3 60336 CATEGORY: DATAXFER 60337 EXTENSION: AVX512EVEX 60338 ISA_SET: AVX512F_128 60339 EXCEPTIONS: AVX512-E6NF 60340 REAL_OPCODE: Y 60341 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 60342 PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 60343 OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 60344 IFORM: VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 60345 } 60346 60347 60348 # EMITTING VPMOVUSQB (VPMOVUSQB-256-1) 60349 { 60350 ICLASS: VPMOVUSQB 60351 CPL: 3 60352 CATEGORY: DATAXFER 60353 EXTENSION: AVX512EVEX 60354 ISA_SET: AVX512F_256 60355 EXCEPTIONS: AVX512-E6NF 60356 REAL_OPCODE: Y 60357 ATTRIBUTES: MASKOP_EVEX 60358 PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 60359 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 60360 IFORM: VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 60361 } 60362 60363 60364 # EMITTING VPMOVUSQB (VPMOVUSQB-256-2) 60365 { 60366 ICLASS: VPMOVUSQB 60367 CPL: 3 60368 CATEGORY: DATAXFER 60369 EXTENSION: AVX512EVEX 60370 ISA_SET: AVX512F_256 60371 EXCEPTIONS: AVX512-E6NF 60372 REAL_OPCODE: Y 60373 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 60374 PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 60375 OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 60376 IFORM: VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 60377 } 60378 60379 60380 # EMITTING VPMOVUSQD (VPMOVUSQD-128-1) 60381 { 60382 ICLASS: VPMOVUSQD 60383 CPL: 3 60384 CATEGORY: DATAXFER 60385 EXTENSION: AVX512EVEX 60386 ISA_SET: AVX512F_128 60387 EXCEPTIONS: AVX512-E6NF 60388 REAL_OPCODE: Y 60389 ATTRIBUTES: MASKOP_EVEX 60390 PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 60391 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 60392 IFORM: VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 60393 } 60394 60395 60396 # EMITTING VPMOVUSQD (VPMOVUSQD-128-2) 60397 { 60398 ICLASS: VPMOVUSQD 60399 CPL: 3 60400 CATEGORY: DATAXFER 60401 EXTENSION: AVX512EVEX 60402 ISA_SET: AVX512F_128 60403 EXCEPTIONS: AVX512-E6NF 60404 REAL_OPCODE: Y 60405 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60406 PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 60407 OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 60408 IFORM: VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 60409 } 60410 60411 60412 # EMITTING VPMOVUSQD (VPMOVUSQD-256-1) 60413 { 60414 ICLASS: VPMOVUSQD 60415 CPL: 3 60416 CATEGORY: DATAXFER 60417 EXTENSION: AVX512EVEX 60418 ISA_SET: AVX512F_256 60419 EXCEPTIONS: AVX512-E6NF 60420 REAL_OPCODE: Y 60421 ATTRIBUTES: MASKOP_EVEX 60422 PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 60423 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 60424 IFORM: VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 60425 } 60426 60427 60428 # EMITTING VPMOVUSQD (VPMOVUSQD-256-2) 60429 { 60430 ICLASS: VPMOVUSQD 60431 CPL: 3 60432 CATEGORY: DATAXFER 60433 EXTENSION: AVX512EVEX 60434 ISA_SET: AVX512F_256 60435 EXCEPTIONS: AVX512-E6NF 60436 REAL_OPCODE: Y 60437 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60438 PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 60439 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 60440 IFORM: VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 60441 } 60442 60443 60444 # EMITTING VPMOVUSQW (VPMOVUSQW-128-1) 60445 { 60446 ICLASS: VPMOVUSQW 60447 CPL: 3 60448 CATEGORY: DATAXFER 60449 EXTENSION: AVX512EVEX 60450 ISA_SET: AVX512F_128 60451 EXCEPTIONS: AVX512-E6NF 60452 REAL_OPCODE: Y 60453 ATTRIBUTES: MASKOP_EVEX 60454 PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 60455 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 60456 IFORM: VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 60457 } 60458 60459 60460 # EMITTING VPMOVUSQW (VPMOVUSQW-128-2) 60461 { 60462 ICLASS: VPMOVUSQW 60463 CPL: 3 60464 CATEGORY: DATAXFER 60465 EXTENSION: AVX512EVEX 60466 ISA_SET: AVX512F_128 60467 EXCEPTIONS: AVX512-E6NF 60468 REAL_OPCODE: Y 60469 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 60470 PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 60471 OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 60472 IFORM: VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 60473 } 60474 60475 60476 # EMITTING VPMOVUSQW (VPMOVUSQW-256-1) 60477 { 60478 ICLASS: VPMOVUSQW 60479 CPL: 3 60480 CATEGORY: DATAXFER 60481 EXTENSION: AVX512EVEX 60482 ISA_SET: AVX512F_256 60483 EXCEPTIONS: AVX512-E6NF 60484 REAL_OPCODE: Y 60485 ATTRIBUTES: MASKOP_EVEX 60486 PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 60487 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 60488 IFORM: VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 60489 } 60490 60491 60492 # EMITTING VPMOVUSQW (VPMOVUSQW-256-2) 60493 { 60494 ICLASS: VPMOVUSQW 60495 CPL: 3 60496 CATEGORY: DATAXFER 60497 EXTENSION: AVX512EVEX 60498 ISA_SET: AVX512F_256 60499 EXCEPTIONS: AVX512-E6NF 60500 REAL_OPCODE: Y 60501 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 60502 PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 60503 OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 60504 IFORM: VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 60505 } 60506 60507 60508 # EMITTING VPMOVUSWB (VPMOVUSWB-128-1) 60509 { 60510 ICLASS: VPMOVUSWB 60511 CPL: 3 60512 CATEGORY: DATAXFER 60513 EXTENSION: AVX512EVEX 60514 ISA_SET: AVX512BW_128 60515 EXCEPTIONS: AVX512-E6NF 60516 REAL_OPCODE: Y 60517 ATTRIBUTES: MASKOP_EVEX 60518 PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 60519 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 60520 IFORM: VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 60521 } 60522 60523 60524 # EMITTING VPMOVUSWB (VPMOVUSWB-128-2) 60525 { 60526 ICLASS: VPMOVUSWB 60527 CPL: 3 60528 CATEGORY: DATAXFER 60529 EXTENSION: AVX512EVEX 60530 ISA_SET: AVX512BW_128 60531 EXCEPTIONS: AVX512-E6NF 60532 REAL_OPCODE: Y 60533 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60534 PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 60535 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 60536 IFORM: VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 60537 } 60538 60539 60540 # EMITTING VPMOVUSWB (VPMOVUSWB-256-1) 60541 { 60542 ICLASS: VPMOVUSWB 60543 CPL: 3 60544 CATEGORY: DATAXFER 60545 EXTENSION: AVX512EVEX 60546 ISA_SET: AVX512BW_256 60547 EXCEPTIONS: AVX512-E6NF 60548 REAL_OPCODE: Y 60549 ATTRIBUTES: MASKOP_EVEX 60550 PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 60551 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 60552 IFORM: VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 60553 } 60554 60555 60556 # EMITTING VPMOVUSWB (VPMOVUSWB-256-2) 60557 { 60558 ICLASS: VPMOVUSWB 60559 CPL: 3 60560 CATEGORY: DATAXFER 60561 EXTENSION: AVX512EVEX 60562 ISA_SET: AVX512BW_256 60563 EXCEPTIONS: AVX512-E6NF 60564 REAL_OPCODE: Y 60565 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60566 PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 60567 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 60568 IFORM: VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 60569 } 60570 60571 60572 # EMITTING VPMOVUSWB (VPMOVUSWB-512-1) 60573 { 60574 ICLASS: VPMOVUSWB 60575 CPL: 3 60576 CATEGORY: DATAXFER 60577 EXTENSION: AVX512EVEX 60578 ISA_SET: AVX512BW_512 60579 EXCEPTIONS: AVX512-E6NF 60580 REAL_OPCODE: Y 60581 ATTRIBUTES: MASKOP_EVEX 60582 PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 60583 OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 60584 IFORM: VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 60585 } 60586 60587 60588 # EMITTING VPMOVUSWB (VPMOVUSWB-512-2) 60589 { 60590 ICLASS: VPMOVUSWB 60591 CPL: 3 60592 CATEGORY: DATAXFER 60593 EXTENSION: AVX512EVEX 60594 ISA_SET: AVX512BW_512 60595 EXCEPTIONS: AVX512-E6NF 60596 REAL_OPCODE: Y 60597 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60598 PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 60599 OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 60600 IFORM: VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 60601 } 60602 60603 60604 # EMITTING VPMOVW2M (VPMOVW2M-128-1) 60605 { 60606 ICLASS: VPMOVW2M 60607 CPL: 3 60608 CATEGORY: DATAXFER 60609 EXTENSION: AVX512EVEX 60610 ISA_SET: AVX512BW_128 60611 EXCEPTIONS: AVX512-E7NM 60612 REAL_OPCODE: Y 60613 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 60614 OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u16 60615 IFORM: VPMOVW2M_MASKmskw_XMMu16_AVX512 60616 } 60617 60618 60619 # EMITTING VPMOVW2M (VPMOVW2M-256-1) 60620 { 60621 ICLASS: VPMOVW2M 60622 CPL: 3 60623 CATEGORY: DATAXFER 60624 EXTENSION: AVX512EVEX 60625 ISA_SET: AVX512BW_256 60626 EXCEPTIONS: AVX512-E7NM 60627 REAL_OPCODE: Y 60628 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 60629 OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u16 60630 IFORM: VPMOVW2M_MASKmskw_YMMu16_AVX512 60631 } 60632 60633 60634 # EMITTING VPMOVW2M (VPMOVW2M-512-1) 60635 { 60636 ICLASS: VPMOVW2M 60637 CPL: 3 60638 CATEGORY: DATAXFER 60639 EXTENSION: AVX512EVEX 60640 ISA_SET: AVX512BW_512 60641 EXCEPTIONS: AVX512-E7NM 60642 REAL_OPCODE: Y 60643 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 60644 OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu16 60645 IFORM: VPMOVW2M_MASKmskw_ZMMu16_AVX512 60646 } 60647 60648 60649 # EMITTING VPMOVWB (VPMOVWB-128-1) 60650 { 60651 ICLASS: VPMOVWB 60652 CPL: 3 60653 CATEGORY: DATAXFER 60654 EXTENSION: AVX512EVEX 60655 ISA_SET: AVX512BW_128 60656 EXCEPTIONS: AVX512-E6NF 60657 REAL_OPCODE: Y 60658 ATTRIBUTES: MASKOP_EVEX 60659 PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 60660 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 60661 IFORM: VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 60662 } 60663 60664 60665 # EMITTING VPMOVWB (VPMOVWB-128-2) 60666 { 60667 ICLASS: VPMOVWB 60668 CPL: 3 60669 CATEGORY: DATAXFER 60670 EXTENSION: AVX512EVEX 60671 ISA_SET: AVX512BW_128 60672 EXCEPTIONS: AVX512-E6NF 60673 REAL_OPCODE: Y 60674 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60675 PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 60676 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 60677 IFORM: VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 60678 } 60679 60680 60681 # EMITTING VPMOVWB (VPMOVWB-256-1) 60682 { 60683 ICLASS: VPMOVWB 60684 CPL: 3 60685 CATEGORY: DATAXFER 60686 EXTENSION: AVX512EVEX 60687 ISA_SET: AVX512BW_256 60688 EXCEPTIONS: AVX512-E6NF 60689 REAL_OPCODE: Y 60690 ATTRIBUTES: MASKOP_EVEX 60691 PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 60692 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 60693 IFORM: VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 60694 } 60695 60696 60697 # EMITTING VPMOVWB (VPMOVWB-256-2) 60698 { 60699 ICLASS: VPMOVWB 60700 CPL: 3 60701 CATEGORY: DATAXFER 60702 EXTENSION: AVX512EVEX 60703 ISA_SET: AVX512BW_256 60704 EXCEPTIONS: AVX512-E6NF 60705 REAL_OPCODE: Y 60706 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60707 PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 60708 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 60709 IFORM: VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 60710 } 60711 60712 60713 # EMITTING VPMOVWB (VPMOVWB-512-1) 60714 { 60715 ICLASS: VPMOVWB 60716 CPL: 3 60717 CATEGORY: DATAXFER 60718 EXTENSION: AVX512EVEX 60719 ISA_SET: AVX512BW_512 60720 EXCEPTIONS: AVX512-E6NF 60721 REAL_OPCODE: Y 60722 ATTRIBUTES: MASKOP_EVEX 60723 PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 60724 OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 60725 IFORM: VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 60726 } 60727 60728 60729 # EMITTING VPMOVWB (VPMOVWB-512-2) 60730 { 60731 ICLASS: VPMOVWB 60732 CPL: 3 60733 CATEGORY: DATAXFER 60734 EXTENSION: AVX512EVEX 60735 ISA_SET: AVX512BW_512 60736 EXCEPTIONS: AVX512-E6NF 60737 REAL_OPCODE: Y 60738 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60739 PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 60740 OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 60741 IFORM: VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 60742 } 60743 60744 60745 # EMITTING VPMOVZXBD (VPMOVZXBD-128-1) 60746 { 60747 ICLASS: VPMOVZXBD 60748 CPL: 3 60749 CATEGORY: DATAXFER 60750 EXTENSION: AVX512EVEX 60751 ISA_SET: AVX512F_128 60752 EXCEPTIONS: AVX512-E5 60753 REAL_OPCODE: Y 60754 ATTRIBUTES: MASKOP_EVEX 60755 PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 60756 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 60757 IFORM: VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 60758 } 60759 60760 { 60761 ICLASS: VPMOVZXBD 60762 CPL: 3 60763 CATEGORY: DATAXFER 60764 EXTENSION: AVX512EVEX 60765 ISA_SET: AVX512F_128 60766 EXCEPTIONS: AVX512-E5 60767 REAL_OPCODE: Y 60768 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 60769 PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 60770 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 60771 IFORM: VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 60772 } 60773 60774 60775 # EMITTING VPMOVZXBD (VPMOVZXBD-256-1) 60776 { 60777 ICLASS: VPMOVZXBD 60778 CPL: 3 60779 CATEGORY: DATAXFER 60780 EXTENSION: AVX512EVEX 60781 ISA_SET: AVX512F_256 60782 EXCEPTIONS: AVX512-E5 60783 REAL_OPCODE: Y 60784 ATTRIBUTES: MASKOP_EVEX 60785 PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 60786 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 60787 IFORM: VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 60788 } 60789 60790 { 60791 ICLASS: VPMOVZXBD 60792 CPL: 3 60793 CATEGORY: DATAXFER 60794 EXTENSION: AVX512EVEX 60795 ISA_SET: AVX512F_256 60796 EXCEPTIONS: AVX512-E5 60797 REAL_OPCODE: Y 60798 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 60799 PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 60800 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 60801 IFORM: VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 60802 } 60803 60804 60805 # EMITTING VPMOVZXBQ (VPMOVZXBQ-128-1) 60806 { 60807 ICLASS: VPMOVZXBQ 60808 CPL: 3 60809 CATEGORY: DATAXFER 60810 EXTENSION: AVX512EVEX 60811 ISA_SET: AVX512F_128 60812 EXCEPTIONS: AVX512-E5 60813 REAL_OPCODE: Y 60814 ATTRIBUTES: MASKOP_EVEX 60815 PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 60816 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 60817 IFORM: VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 60818 } 60819 60820 { 60821 ICLASS: VPMOVZXBQ 60822 CPL: 3 60823 CATEGORY: DATAXFER 60824 EXTENSION: AVX512EVEX 60825 ISA_SET: AVX512F_128 60826 EXCEPTIONS: AVX512-E5 60827 REAL_OPCODE: Y 60828 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 60829 PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 60830 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 60831 IFORM: VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 60832 } 60833 60834 60835 # EMITTING VPMOVZXBQ (VPMOVZXBQ-256-1) 60836 { 60837 ICLASS: VPMOVZXBQ 60838 CPL: 3 60839 CATEGORY: DATAXFER 60840 EXTENSION: AVX512EVEX 60841 ISA_SET: AVX512F_256 60842 EXCEPTIONS: AVX512-E5 60843 REAL_OPCODE: Y 60844 ATTRIBUTES: MASKOP_EVEX 60845 PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 60846 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 60847 IFORM: VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 60848 } 60849 60850 { 60851 ICLASS: VPMOVZXBQ 60852 CPL: 3 60853 CATEGORY: DATAXFER 60854 EXTENSION: AVX512EVEX 60855 ISA_SET: AVX512F_256 60856 EXCEPTIONS: AVX512-E5 60857 REAL_OPCODE: Y 60858 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 60859 PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 60860 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 60861 IFORM: VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 60862 } 60863 60864 60865 # EMITTING VPMOVZXBW (VPMOVZXBW-128-1) 60866 { 60867 ICLASS: VPMOVZXBW 60868 CPL: 3 60869 CATEGORY: DATAXFER 60870 EXTENSION: AVX512EVEX 60871 ISA_SET: AVX512BW_128 60872 EXCEPTIONS: AVX512-E5 60873 REAL_OPCODE: Y 60874 ATTRIBUTES: MASKOP_EVEX 60875 PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 60876 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 60877 IFORM: VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 60878 } 60879 60880 { 60881 ICLASS: VPMOVZXBW 60882 CPL: 3 60883 CATEGORY: DATAXFER 60884 EXTENSION: AVX512EVEX 60885 ISA_SET: AVX512BW_128 60886 EXCEPTIONS: AVX512-E5 60887 REAL_OPCODE: Y 60888 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60889 PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 60890 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 60891 IFORM: VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 60892 } 60893 60894 60895 # EMITTING VPMOVZXBW (VPMOVZXBW-256-1) 60896 { 60897 ICLASS: VPMOVZXBW 60898 CPL: 3 60899 CATEGORY: DATAXFER 60900 EXTENSION: AVX512EVEX 60901 ISA_SET: AVX512BW_256 60902 EXCEPTIONS: AVX512-E5 60903 REAL_OPCODE: Y 60904 ATTRIBUTES: MASKOP_EVEX 60905 PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 60906 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 60907 IFORM: VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 60908 } 60909 60910 { 60911 ICLASS: VPMOVZXBW 60912 CPL: 3 60913 CATEGORY: DATAXFER 60914 EXTENSION: AVX512EVEX 60915 ISA_SET: AVX512BW_256 60916 EXCEPTIONS: AVX512-E5 60917 REAL_OPCODE: Y 60918 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60919 PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 60920 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 60921 IFORM: VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 60922 } 60923 60924 60925 # EMITTING VPMOVZXBW (VPMOVZXBW-512-1) 60926 { 60927 ICLASS: VPMOVZXBW 60928 CPL: 3 60929 CATEGORY: DATAXFER 60930 EXTENSION: AVX512EVEX 60931 ISA_SET: AVX512BW_512 60932 EXCEPTIONS: AVX512-E5 60933 REAL_OPCODE: Y 60934 ATTRIBUTES: MASKOP_EVEX 60935 PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 60936 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 60937 IFORM: VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 60938 } 60939 60940 { 60941 ICLASS: VPMOVZXBW 60942 CPL: 3 60943 CATEGORY: DATAXFER 60944 EXTENSION: AVX512EVEX 60945 ISA_SET: AVX512BW_512 60946 EXCEPTIONS: AVX512-E5 60947 REAL_OPCODE: Y 60948 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60949 PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 60950 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 60951 IFORM: VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 60952 } 60953 60954 60955 # EMITTING VPMOVZXDQ (VPMOVZXDQ-128-1) 60956 { 60957 ICLASS: VPMOVZXDQ 60958 CPL: 3 60959 CATEGORY: DATAXFER 60960 EXTENSION: AVX512EVEX 60961 ISA_SET: AVX512F_128 60962 EXCEPTIONS: AVX512-E5 60963 REAL_OPCODE: Y 60964 ATTRIBUTES: MASKOP_EVEX 60965 PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 60966 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 60967 IFORM: VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 60968 } 60969 60970 { 60971 ICLASS: VPMOVZXDQ 60972 CPL: 3 60973 CATEGORY: DATAXFER 60974 EXTENSION: AVX512EVEX 60975 ISA_SET: AVX512F_128 60976 EXCEPTIONS: AVX512-E5 60977 REAL_OPCODE: Y 60978 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 60979 PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 60980 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 60981 IFORM: VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 60982 } 60983 60984 60985 # EMITTING VPMOVZXDQ (VPMOVZXDQ-256-1) 60986 { 60987 ICLASS: VPMOVZXDQ 60988 CPL: 3 60989 CATEGORY: DATAXFER 60990 EXTENSION: AVX512EVEX 60991 ISA_SET: AVX512F_256 60992 EXCEPTIONS: AVX512-E5 60993 REAL_OPCODE: Y 60994 ATTRIBUTES: MASKOP_EVEX 60995 PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 60996 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 60997 IFORM: VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 60998 } 60999 61000 { 61001 ICLASS: VPMOVZXDQ 61002 CPL: 3 61003 CATEGORY: DATAXFER 61004 EXTENSION: AVX512EVEX 61005 ISA_SET: AVX512F_256 61006 EXCEPTIONS: AVX512-E5 61007 REAL_OPCODE: Y 61008 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 61009 PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 61010 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 61011 IFORM: VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 61012 } 61013 61014 61015 # EMITTING VPMOVZXWD (VPMOVZXWD-128-1) 61016 { 61017 ICLASS: VPMOVZXWD 61018 CPL: 3 61019 CATEGORY: DATAXFER 61020 EXTENSION: AVX512EVEX 61021 ISA_SET: AVX512F_128 61022 EXCEPTIONS: AVX512-E5 61023 REAL_OPCODE: Y 61024 ATTRIBUTES: MASKOP_EVEX 61025 PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 61026 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 61027 IFORM: VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 61028 } 61029 61030 { 61031 ICLASS: VPMOVZXWD 61032 CPL: 3 61033 CATEGORY: DATAXFER 61034 EXTENSION: AVX512EVEX 61035 ISA_SET: AVX512F_128 61036 EXCEPTIONS: AVX512-E5 61037 REAL_OPCODE: Y 61038 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 61039 PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 61040 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 61041 IFORM: VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 61042 } 61043 61044 61045 # EMITTING VPMOVZXWD (VPMOVZXWD-256-1) 61046 { 61047 ICLASS: VPMOVZXWD 61048 CPL: 3 61049 CATEGORY: DATAXFER 61050 EXTENSION: AVX512EVEX 61051 ISA_SET: AVX512F_256 61052 EXCEPTIONS: AVX512-E5 61053 REAL_OPCODE: Y 61054 ATTRIBUTES: MASKOP_EVEX 61055 PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 61056 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 61057 IFORM: VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 61058 } 61059 61060 { 61061 ICLASS: VPMOVZXWD 61062 CPL: 3 61063 CATEGORY: DATAXFER 61064 EXTENSION: AVX512EVEX 61065 ISA_SET: AVX512F_256 61066 EXCEPTIONS: AVX512-E5 61067 REAL_OPCODE: Y 61068 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 61069 PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 61070 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 61071 IFORM: VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 61072 } 61073 61074 61075 # EMITTING VPMOVZXWQ (VPMOVZXWQ-128-1) 61076 { 61077 ICLASS: VPMOVZXWQ 61078 CPL: 3 61079 CATEGORY: DATAXFER 61080 EXTENSION: AVX512EVEX 61081 ISA_SET: AVX512F_128 61082 EXCEPTIONS: AVX512-E5 61083 REAL_OPCODE: Y 61084 ATTRIBUTES: MASKOP_EVEX 61085 PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 61086 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 61087 IFORM: VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 61088 } 61089 61090 { 61091 ICLASS: VPMOVZXWQ 61092 CPL: 3 61093 CATEGORY: DATAXFER 61094 EXTENSION: AVX512EVEX 61095 ISA_SET: AVX512F_128 61096 EXCEPTIONS: AVX512-E5 61097 REAL_OPCODE: Y 61098 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 61099 PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 61100 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 61101 IFORM: VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 61102 } 61103 61104 61105 # EMITTING VPMOVZXWQ (VPMOVZXWQ-256-1) 61106 { 61107 ICLASS: VPMOVZXWQ 61108 CPL: 3 61109 CATEGORY: DATAXFER 61110 EXTENSION: AVX512EVEX 61111 ISA_SET: AVX512F_256 61112 EXCEPTIONS: AVX512-E5 61113 REAL_OPCODE: Y 61114 ATTRIBUTES: MASKOP_EVEX 61115 PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 61116 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 61117 IFORM: VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 61118 } 61119 61120 { 61121 ICLASS: VPMOVZXWQ 61122 CPL: 3 61123 CATEGORY: DATAXFER 61124 EXTENSION: AVX512EVEX 61125 ISA_SET: AVX512F_256 61126 EXCEPTIONS: AVX512-E5 61127 REAL_OPCODE: Y 61128 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 61129 PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 61130 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 61131 IFORM: VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 61132 } 61133 61134 61135 # EMITTING VPMULDQ (VPMULDQ-128-1) 61136 { 61137 ICLASS: VPMULDQ 61138 CPL: 3 61139 CATEGORY: AVX512 61140 EXTENSION: AVX512EVEX 61141 ISA_SET: AVX512F_128 61142 EXCEPTIONS: AVX512-E4 61143 REAL_OPCODE: Y 61144 ATTRIBUTES: MASKOP_EVEX 61145 PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 61146 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 61147 IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 61148 } 61149 61150 { 61151 ICLASS: VPMULDQ 61152 CPL: 3 61153 CATEGORY: AVX512 61154 EXTENSION: AVX512EVEX 61155 ISA_SET: AVX512F_128 61156 EXCEPTIONS: AVX512-E4 61157 REAL_OPCODE: Y 61158 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61159 PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 61160 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 61161 IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 61162 } 61163 61164 61165 # EMITTING VPMULDQ (VPMULDQ-256-1) 61166 { 61167 ICLASS: VPMULDQ 61168 CPL: 3 61169 CATEGORY: AVX512 61170 EXTENSION: AVX512EVEX 61171 ISA_SET: AVX512F_256 61172 EXCEPTIONS: AVX512-E4 61173 REAL_OPCODE: Y 61174 ATTRIBUTES: MASKOP_EVEX 61175 PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 61176 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 61177 IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 61178 } 61179 61180 { 61181 ICLASS: VPMULDQ 61182 CPL: 3 61183 CATEGORY: AVX512 61184 EXTENSION: AVX512EVEX 61185 ISA_SET: AVX512F_256 61186 EXCEPTIONS: AVX512-E4 61187 REAL_OPCODE: Y 61188 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61189 PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 61190 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 61191 IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 61192 } 61193 61194 61195 # EMITTING VPMULHRSW (VPMULHRSW-128-1) 61196 { 61197 ICLASS: VPMULHRSW 61198 CPL: 3 61199 CATEGORY: AVX512 61200 EXTENSION: AVX512EVEX 61201 ISA_SET: AVX512BW_128 61202 EXCEPTIONS: AVX512-E4 61203 REAL_OPCODE: Y 61204 ATTRIBUTES: MASKOP_EVEX 61205 PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 61206 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 61207 IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 61208 } 61209 61210 { 61211 ICLASS: VPMULHRSW 61212 CPL: 3 61213 CATEGORY: AVX512 61214 EXTENSION: AVX512EVEX 61215 ISA_SET: AVX512BW_128 61216 EXCEPTIONS: AVX512-E4 61217 REAL_OPCODE: Y 61218 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61219 PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 61220 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 61221 IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 61222 } 61223 61224 61225 # EMITTING VPMULHRSW (VPMULHRSW-256-1) 61226 { 61227 ICLASS: VPMULHRSW 61228 CPL: 3 61229 CATEGORY: AVX512 61230 EXTENSION: AVX512EVEX 61231 ISA_SET: AVX512BW_256 61232 EXCEPTIONS: AVX512-E4 61233 REAL_OPCODE: Y 61234 ATTRIBUTES: MASKOP_EVEX 61235 PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 61236 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 61237 IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 61238 } 61239 61240 { 61241 ICLASS: VPMULHRSW 61242 CPL: 3 61243 CATEGORY: AVX512 61244 EXTENSION: AVX512EVEX 61245 ISA_SET: AVX512BW_256 61246 EXCEPTIONS: AVX512-E4 61247 REAL_OPCODE: Y 61248 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61249 PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 61250 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 61251 IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 61252 } 61253 61254 61255 # EMITTING VPMULHRSW (VPMULHRSW-512-1) 61256 { 61257 ICLASS: VPMULHRSW 61258 CPL: 3 61259 CATEGORY: AVX512 61260 EXTENSION: AVX512EVEX 61261 ISA_SET: AVX512BW_512 61262 EXCEPTIONS: AVX512-E4 61263 REAL_OPCODE: Y 61264 ATTRIBUTES: MASKOP_EVEX 61265 PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 61266 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 61267 IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 61268 } 61269 61270 { 61271 ICLASS: VPMULHRSW 61272 CPL: 3 61273 CATEGORY: AVX512 61274 EXTENSION: AVX512EVEX 61275 ISA_SET: AVX512BW_512 61276 EXCEPTIONS: AVX512-E4 61277 REAL_OPCODE: Y 61278 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61279 PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 61280 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 61281 IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 61282 } 61283 61284 61285 # EMITTING VPMULHUW (VPMULHUW-128-1) 61286 { 61287 ICLASS: VPMULHUW 61288 CPL: 3 61289 CATEGORY: AVX512 61290 EXTENSION: AVX512EVEX 61291 ISA_SET: AVX512BW_128 61292 EXCEPTIONS: AVX512-E4 61293 REAL_OPCODE: Y 61294 ATTRIBUTES: MASKOP_EVEX 61295 PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 61296 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 61297 IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 61298 } 61299 61300 { 61301 ICLASS: VPMULHUW 61302 CPL: 3 61303 CATEGORY: AVX512 61304 EXTENSION: AVX512EVEX 61305 ISA_SET: AVX512BW_128 61306 EXCEPTIONS: AVX512-E4 61307 REAL_OPCODE: Y 61308 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61309 PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 61310 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 61311 IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 61312 } 61313 61314 61315 # EMITTING VPMULHUW (VPMULHUW-256-1) 61316 { 61317 ICLASS: VPMULHUW 61318 CPL: 3 61319 CATEGORY: AVX512 61320 EXTENSION: AVX512EVEX 61321 ISA_SET: AVX512BW_256 61322 EXCEPTIONS: AVX512-E4 61323 REAL_OPCODE: Y 61324 ATTRIBUTES: MASKOP_EVEX 61325 PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 61326 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 61327 IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 61328 } 61329 61330 { 61331 ICLASS: VPMULHUW 61332 CPL: 3 61333 CATEGORY: AVX512 61334 EXTENSION: AVX512EVEX 61335 ISA_SET: AVX512BW_256 61336 EXCEPTIONS: AVX512-E4 61337 REAL_OPCODE: Y 61338 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61339 PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 61340 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 61341 IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 61342 } 61343 61344 61345 # EMITTING VPMULHUW (VPMULHUW-512-1) 61346 { 61347 ICLASS: VPMULHUW 61348 CPL: 3 61349 CATEGORY: AVX512 61350 EXTENSION: AVX512EVEX 61351 ISA_SET: AVX512BW_512 61352 EXCEPTIONS: AVX512-E4 61353 REAL_OPCODE: Y 61354 ATTRIBUTES: MASKOP_EVEX 61355 PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 61356 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 61357 IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 61358 } 61359 61360 { 61361 ICLASS: VPMULHUW 61362 CPL: 3 61363 CATEGORY: AVX512 61364 EXTENSION: AVX512EVEX 61365 ISA_SET: AVX512BW_512 61366 EXCEPTIONS: AVX512-E4 61367 REAL_OPCODE: Y 61368 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61369 PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 61370 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 61371 IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 61372 } 61373 61374 61375 # EMITTING VPMULHW (VPMULHW-128-1) 61376 { 61377 ICLASS: VPMULHW 61378 CPL: 3 61379 CATEGORY: AVX512 61380 EXTENSION: AVX512EVEX 61381 ISA_SET: AVX512BW_128 61382 EXCEPTIONS: AVX512-E4 61383 REAL_OPCODE: Y 61384 ATTRIBUTES: MASKOP_EVEX 61385 PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 61386 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 61387 IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 61388 } 61389 61390 { 61391 ICLASS: VPMULHW 61392 CPL: 3 61393 CATEGORY: AVX512 61394 EXTENSION: AVX512EVEX 61395 ISA_SET: AVX512BW_128 61396 EXCEPTIONS: AVX512-E4 61397 REAL_OPCODE: Y 61398 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61399 PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 61400 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 61401 IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 61402 } 61403 61404 61405 # EMITTING VPMULHW (VPMULHW-256-1) 61406 { 61407 ICLASS: VPMULHW 61408 CPL: 3 61409 CATEGORY: AVX512 61410 EXTENSION: AVX512EVEX 61411 ISA_SET: AVX512BW_256 61412 EXCEPTIONS: AVX512-E4 61413 REAL_OPCODE: Y 61414 ATTRIBUTES: MASKOP_EVEX 61415 PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 61416 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 61417 IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 61418 } 61419 61420 { 61421 ICLASS: VPMULHW 61422 CPL: 3 61423 CATEGORY: AVX512 61424 EXTENSION: AVX512EVEX 61425 ISA_SET: AVX512BW_256 61426 EXCEPTIONS: AVX512-E4 61427 REAL_OPCODE: Y 61428 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61429 PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 61430 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 61431 IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 61432 } 61433 61434 61435 # EMITTING VPMULHW (VPMULHW-512-1) 61436 { 61437 ICLASS: VPMULHW 61438 CPL: 3 61439 CATEGORY: AVX512 61440 EXTENSION: AVX512EVEX 61441 ISA_SET: AVX512BW_512 61442 EXCEPTIONS: AVX512-E4 61443 REAL_OPCODE: Y 61444 ATTRIBUTES: MASKOP_EVEX 61445 PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 61446 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 61447 IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 61448 } 61449 61450 { 61451 ICLASS: VPMULHW 61452 CPL: 3 61453 CATEGORY: AVX512 61454 EXTENSION: AVX512EVEX 61455 ISA_SET: AVX512BW_512 61456 EXCEPTIONS: AVX512-E4 61457 REAL_OPCODE: Y 61458 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61459 PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 61460 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 61461 IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 61462 } 61463 61464 61465 # EMITTING VPMULLD (VPMULLD-128-1) 61466 { 61467 ICLASS: VPMULLD 61468 CPL: 3 61469 CATEGORY: AVX512 61470 EXTENSION: AVX512EVEX 61471 ISA_SET: AVX512F_128 61472 EXCEPTIONS: AVX512-E4 61473 REAL_OPCODE: Y 61474 ATTRIBUTES: MASKOP_EVEX 61475 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 61476 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 61477 IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 61478 } 61479 61480 { 61481 ICLASS: VPMULLD 61482 CPL: 3 61483 CATEGORY: AVX512 61484 EXTENSION: AVX512EVEX 61485 ISA_SET: AVX512F_128 61486 EXCEPTIONS: AVX512-E4 61487 REAL_OPCODE: Y 61488 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61489 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 61490 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 61491 IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 61492 } 61493 61494 61495 # EMITTING VPMULLD (VPMULLD-256-1) 61496 { 61497 ICLASS: VPMULLD 61498 CPL: 3 61499 CATEGORY: AVX512 61500 EXTENSION: AVX512EVEX 61501 ISA_SET: AVX512F_256 61502 EXCEPTIONS: AVX512-E4 61503 REAL_OPCODE: Y 61504 ATTRIBUTES: MASKOP_EVEX 61505 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 61506 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 61507 IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 61508 } 61509 61510 { 61511 ICLASS: VPMULLD 61512 CPL: 3 61513 CATEGORY: AVX512 61514 EXTENSION: AVX512EVEX 61515 ISA_SET: AVX512F_256 61516 EXCEPTIONS: AVX512-E4 61517 REAL_OPCODE: Y 61518 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61519 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 61520 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 61521 IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 61522 } 61523 61524 61525 # EMITTING VPMULLQ (VPMULLQ-128-1) 61526 { 61527 ICLASS: VPMULLQ 61528 CPL: 3 61529 CATEGORY: AVX512 61530 EXTENSION: AVX512EVEX 61531 ISA_SET: AVX512DQ_128 61532 EXCEPTIONS: AVX512-E4 61533 REAL_OPCODE: Y 61534 ATTRIBUTES: MASKOP_EVEX 61535 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 61536 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 61537 IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 61538 } 61539 61540 { 61541 ICLASS: VPMULLQ 61542 CPL: 3 61543 CATEGORY: AVX512 61544 EXTENSION: AVX512EVEX 61545 ISA_SET: AVX512DQ_128 61546 EXCEPTIONS: AVX512-E4 61547 REAL_OPCODE: Y 61548 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61549 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 61550 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 61551 IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 61552 } 61553 61554 61555 # EMITTING VPMULLQ (VPMULLQ-256-1) 61556 { 61557 ICLASS: VPMULLQ 61558 CPL: 3 61559 CATEGORY: AVX512 61560 EXTENSION: AVX512EVEX 61561 ISA_SET: AVX512DQ_256 61562 EXCEPTIONS: AVX512-E4 61563 REAL_OPCODE: Y 61564 ATTRIBUTES: MASKOP_EVEX 61565 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 61566 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 61567 IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 61568 } 61569 61570 { 61571 ICLASS: VPMULLQ 61572 CPL: 3 61573 CATEGORY: AVX512 61574 EXTENSION: AVX512EVEX 61575 ISA_SET: AVX512DQ_256 61576 EXCEPTIONS: AVX512-E4 61577 REAL_OPCODE: Y 61578 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61579 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 61580 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 61581 IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 61582 } 61583 61584 61585 # EMITTING VPMULLQ (VPMULLQ-512-1) 61586 { 61587 ICLASS: VPMULLQ 61588 CPL: 3 61589 CATEGORY: AVX512 61590 EXTENSION: AVX512EVEX 61591 ISA_SET: AVX512DQ_512 61592 EXCEPTIONS: AVX512-E4 61593 REAL_OPCODE: Y 61594 ATTRIBUTES: MASKOP_EVEX 61595 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 61596 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 61597 IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 61598 } 61599 61600 { 61601 ICLASS: VPMULLQ 61602 CPL: 3 61603 CATEGORY: AVX512 61604 EXTENSION: AVX512EVEX 61605 ISA_SET: AVX512DQ_512 61606 EXCEPTIONS: AVX512-E4 61607 REAL_OPCODE: Y 61608 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61609 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 61610 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 61611 IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 61612 } 61613 61614 61615 # EMITTING VPMULLW (VPMULLW-128-1) 61616 { 61617 ICLASS: VPMULLW 61618 CPL: 3 61619 CATEGORY: AVX512 61620 EXTENSION: AVX512EVEX 61621 ISA_SET: AVX512BW_128 61622 EXCEPTIONS: AVX512-E4 61623 REAL_OPCODE: Y 61624 ATTRIBUTES: MASKOP_EVEX 61625 PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 61626 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 61627 IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 61628 } 61629 61630 { 61631 ICLASS: VPMULLW 61632 CPL: 3 61633 CATEGORY: AVX512 61634 EXTENSION: AVX512EVEX 61635 ISA_SET: AVX512BW_128 61636 EXCEPTIONS: AVX512-E4 61637 REAL_OPCODE: Y 61638 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61639 PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 61640 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 61641 IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 61642 } 61643 61644 61645 # EMITTING VPMULLW (VPMULLW-256-1) 61646 { 61647 ICLASS: VPMULLW 61648 CPL: 3 61649 CATEGORY: AVX512 61650 EXTENSION: AVX512EVEX 61651 ISA_SET: AVX512BW_256 61652 EXCEPTIONS: AVX512-E4 61653 REAL_OPCODE: Y 61654 ATTRIBUTES: MASKOP_EVEX 61655 PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 61656 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 61657 IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 61658 } 61659 61660 { 61661 ICLASS: VPMULLW 61662 CPL: 3 61663 CATEGORY: AVX512 61664 EXTENSION: AVX512EVEX 61665 ISA_SET: AVX512BW_256 61666 EXCEPTIONS: AVX512-E4 61667 REAL_OPCODE: Y 61668 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61669 PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 61670 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 61671 IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 61672 } 61673 61674 61675 # EMITTING VPMULLW (VPMULLW-512-1) 61676 { 61677 ICLASS: VPMULLW 61678 CPL: 3 61679 CATEGORY: AVX512 61680 EXTENSION: AVX512EVEX 61681 ISA_SET: AVX512BW_512 61682 EXCEPTIONS: AVX512-E4 61683 REAL_OPCODE: Y 61684 ATTRIBUTES: MASKOP_EVEX 61685 PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 61686 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 61687 IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 61688 } 61689 61690 { 61691 ICLASS: VPMULLW 61692 CPL: 3 61693 CATEGORY: AVX512 61694 EXTENSION: AVX512EVEX 61695 ISA_SET: AVX512BW_512 61696 EXCEPTIONS: AVX512-E4 61697 REAL_OPCODE: Y 61698 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 61699 PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 61700 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 61701 IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 61702 } 61703 61704 61705 # EMITTING VPMULUDQ (VPMULUDQ-128-1) 61706 { 61707 ICLASS: VPMULUDQ 61708 CPL: 3 61709 CATEGORY: AVX512 61710 EXTENSION: AVX512EVEX 61711 ISA_SET: AVX512F_128 61712 EXCEPTIONS: AVX512-E4 61713 REAL_OPCODE: Y 61714 ATTRIBUTES: MASKOP_EVEX 61715 PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 61716 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 61717 IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 61718 } 61719 61720 { 61721 ICLASS: VPMULUDQ 61722 CPL: 3 61723 CATEGORY: AVX512 61724 EXTENSION: AVX512EVEX 61725 ISA_SET: AVX512F_128 61726 EXCEPTIONS: AVX512-E4 61727 REAL_OPCODE: Y 61728 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61729 PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 61730 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 61731 IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 61732 } 61733 61734 61735 # EMITTING VPMULUDQ (VPMULUDQ-256-1) 61736 { 61737 ICLASS: VPMULUDQ 61738 CPL: 3 61739 CATEGORY: AVX512 61740 EXTENSION: AVX512EVEX 61741 ISA_SET: AVX512F_256 61742 EXCEPTIONS: AVX512-E4 61743 REAL_OPCODE: Y 61744 ATTRIBUTES: MASKOP_EVEX 61745 PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 61746 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 61747 IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 61748 } 61749 61750 { 61751 ICLASS: VPMULUDQ 61752 CPL: 3 61753 CATEGORY: AVX512 61754 EXTENSION: AVX512EVEX 61755 ISA_SET: AVX512F_256 61756 EXCEPTIONS: AVX512-E4 61757 REAL_OPCODE: Y 61758 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61759 PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 61760 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 61761 IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 61762 } 61763 61764 61765 # EMITTING VPORD (VPORD-128-1) 61766 { 61767 ICLASS: VPORD 61768 CPL: 3 61769 CATEGORY: LOGICAL 61770 EXTENSION: AVX512EVEX 61771 ISA_SET: AVX512F_128 61772 EXCEPTIONS: AVX512-E4 61773 REAL_OPCODE: Y 61774 ATTRIBUTES: MASKOP_EVEX 61775 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 61776 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 61777 IFORM: VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 61778 } 61779 61780 { 61781 ICLASS: VPORD 61782 CPL: 3 61783 CATEGORY: LOGICAL 61784 EXTENSION: AVX512EVEX 61785 ISA_SET: AVX512F_128 61786 EXCEPTIONS: AVX512-E4 61787 REAL_OPCODE: Y 61788 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61789 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 61790 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 61791 IFORM: VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 61792 } 61793 61794 61795 # EMITTING VPORD (VPORD-256-1) 61796 { 61797 ICLASS: VPORD 61798 CPL: 3 61799 CATEGORY: LOGICAL 61800 EXTENSION: AVX512EVEX 61801 ISA_SET: AVX512F_256 61802 EXCEPTIONS: AVX512-E4 61803 REAL_OPCODE: Y 61804 ATTRIBUTES: MASKOP_EVEX 61805 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 61806 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 61807 IFORM: VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 61808 } 61809 61810 { 61811 ICLASS: VPORD 61812 CPL: 3 61813 CATEGORY: LOGICAL 61814 EXTENSION: AVX512EVEX 61815 ISA_SET: AVX512F_256 61816 EXCEPTIONS: AVX512-E4 61817 REAL_OPCODE: Y 61818 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61819 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 61820 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 61821 IFORM: VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 61822 } 61823 61824 61825 # EMITTING VPORQ (VPORQ-128-1) 61826 { 61827 ICLASS: VPORQ 61828 CPL: 3 61829 CATEGORY: LOGICAL 61830 EXTENSION: AVX512EVEX 61831 ISA_SET: AVX512F_128 61832 EXCEPTIONS: AVX512-E4 61833 REAL_OPCODE: Y 61834 ATTRIBUTES: MASKOP_EVEX 61835 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 61836 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 61837 IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 61838 } 61839 61840 { 61841 ICLASS: VPORQ 61842 CPL: 3 61843 CATEGORY: LOGICAL 61844 EXTENSION: AVX512EVEX 61845 ISA_SET: AVX512F_128 61846 EXCEPTIONS: AVX512-E4 61847 REAL_OPCODE: Y 61848 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61849 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 61850 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 61851 IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 61852 } 61853 61854 61855 # EMITTING VPORQ (VPORQ-256-1) 61856 { 61857 ICLASS: VPORQ 61858 CPL: 3 61859 CATEGORY: LOGICAL 61860 EXTENSION: AVX512EVEX 61861 ISA_SET: AVX512F_256 61862 EXCEPTIONS: AVX512-E4 61863 REAL_OPCODE: Y 61864 ATTRIBUTES: MASKOP_EVEX 61865 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 61866 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 61867 IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 61868 } 61869 61870 { 61871 ICLASS: VPORQ 61872 CPL: 3 61873 CATEGORY: LOGICAL 61874 EXTENSION: AVX512EVEX 61875 ISA_SET: AVX512F_256 61876 EXCEPTIONS: AVX512-E4 61877 REAL_OPCODE: Y 61878 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61879 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 61880 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 61881 IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 61882 } 61883 61884 61885 # EMITTING VPROLD (VPROLD-128-1) 61886 { 61887 ICLASS: VPROLD 61888 CPL: 3 61889 CATEGORY: AVX512 61890 EXTENSION: AVX512EVEX 61891 ISA_SET: AVX512F_128 61892 EXCEPTIONS: AVX512-E4 61893 REAL_OPCODE: Y 61894 ATTRIBUTES: MASKOP_EVEX 61895 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8() 61896 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 61897 IFORM: VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 61898 } 61899 61900 { 61901 ICLASS: VPROLD 61902 CPL: 3 61903 CATEGORY: AVX512 61904 EXTENSION: AVX512EVEX 61905 ISA_SET: AVX512F_128 61906 EXCEPTIONS: AVX512-E4 61907 REAL_OPCODE: Y 61908 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61909 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 61910 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 61911 IFORM: VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 61912 } 61913 61914 61915 # EMITTING VPROLD (VPROLD-256-1) 61916 { 61917 ICLASS: VPROLD 61918 CPL: 3 61919 CATEGORY: AVX512 61920 EXTENSION: AVX512EVEX 61921 ISA_SET: AVX512F_256 61922 EXCEPTIONS: AVX512-E4 61923 REAL_OPCODE: Y 61924 ATTRIBUTES: MASKOP_EVEX 61925 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8() 61926 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 61927 IFORM: VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 61928 } 61929 61930 { 61931 ICLASS: VPROLD 61932 CPL: 3 61933 CATEGORY: AVX512 61934 EXTENSION: AVX512EVEX 61935 ISA_SET: AVX512F_256 61936 EXCEPTIONS: AVX512-E4 61937 REAL_OPCODE: Y 61938 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61939 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 61940 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 61941 IFORM: VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 61942 } 61943 61944 61945 # EMITTING VPROLQ (VPROLQ-128-1) 61946 { 61947 ICLASS: VPROLQ 61948 CPL: 3 61949 CATEGORY: AVX512 61950 EXTENSION: AVX512EVEX 61951 ISA_SET: AVX512F_128 61952 EXCEPTIONS: AVX512-E4 61953 REAL_OPCODE: Y 61954 ATTRIBUTES: MASKOP_EVEX 61955 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8() 61956 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b 61957 IFORM: VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 61958 } 61959 61960 { 61961 ICLASS: VPROLQ 61962 CPL: 3 61963 CATEGORY: AVX512 61964 EXTENSION: AVX512EVEX 61965 ISA_SET: AVX512F_128 61966 EXCEPTIONS: AVX512-E4 61967 REAL_OPCODE: Y 61968 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61969 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 61970 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 61971 IFORM: VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 61972 } 61973 61974 61975 # EMITTING VPROLQ (VPROLQ-256-1) 61976 { 61977 ICLASS: VPROLQ 61978 CPL: 3 61979 CATEGORY: AVX512 61980 EXTENSION: AVX512EVEX 61981 ISA_SET: AVX512F_256 61982 EXCEPTIONS: AVX512-E4 61983 REAL_OPCODE: Y 61984 ATTRIBUTES: MASKOP_EVEX 61985 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8() 61986 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 61987 IFORM: VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 61988 } 61989 61990 { 61991 ICLASS: VPROLQ 61992 CPL: 3 61993 CATEGORY: AVX512 61994 EXTENSION: AVX512EVEX 61995 ISA_SET: AVX512F_256 61996 EXCEPTIONS: AVX512-E4 61997 REAL_OPCODE: Y 61998 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 61999 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 62000 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 62001 IFORM: VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 62002 } 62003 62004 62005 # EMITTING VPROLVD (VPROLVD-128-1) 62006 { 62007 ICLASS: VPROLVD 62008 CPL: 3 62009 CATEGORY: AVX512 62010 EXTENSION: AVX512EVEX 62011 ISA_SET: AVX512F_128 62012 EXCEPTIONS: AVX512-E4 62013 REAL_OPCODE: Y 62014 ATTRIBUTES: MASKOP_EVEX 62015 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 62016 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 62017 IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 62018 } 62019 62020 { 62021 ICLASS: VPROLVD 62022 CPL: 3 62023 CATEGORY: AVX512 62024 EXTENSION: AVX512EVEX 62025 ISA_SET: AVX512F_128 62026 EXCEPTIONS: AVX512-E4 62027 REAL_OPCODE: Y 62028 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62029 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 62030 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 62031 IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 62032 } 62033 62034 62035 # EMITTING VPROLVD (VPROLVD-256-1) 62036 { 62037 ICLASS: VPROLVD 62038 CPL: 3 62039 CATEGORY: AVX512 62040 EXTENSION: AVX512EVEX 62041 ISA_SET: AVX512F_256 62042 EXCEPTIONS: AVX512-E4 62043 REAL_OPCODE: Y 62044 ATTRIBUTES: MASKOP_EVEX 62045 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 62046 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 62047 IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 62048 } 62049 62050 { 62051 ICLASS: VPROLVD 62052 CPL: 3 62053 CATEGORY: AVX512 62054 EXTENSION: AVX512EVEX 62055 ISA_SET: AVX512F_256 62056 EXCEPTIONS: AVX512-E4 62057 REAL_OPCODE: Y 62058 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62059 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 62060 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 62061 IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 62062 } 62063 62064 62065 # EMITTING VPROLVQ (VPROLVQ-128-1) 62066 { 62067 ICLASS: VPROLVQ 62068 CPL: 3 62069 CATEGORY: AVX512 62070 EXTENSION: AVX512EVEX 62071 ISA_SET: AVX512F_128 62072 EXCEPTIONS: AVX512-E4 62073 REAL_OPCODE: Y 62074 ATTRIBUTES: MASKOP_EVEX 62075 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 62076 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 62077 IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 62078 } 62079 62080 { 62081 ICLASS: VPROLVQ 62082 CPL: 3 62083 CATEGORY: AVX512 62084 EXTENSION: AVX512EVEX 62085 ISA_SET: AVX512F_128 62086 EXCEPTIONS: AVX512-E4 62087 REAL_OPCODE: Y 62088 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62089 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 62090 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 62091 IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 62092 } 62093 62094 62095 # EMITTING VPROLVQ (VPROLVQ-256-1) 62096 { 62097 ICLASS: VPROLVQ 62098 CPL: 3 62099 CATEGORY: AVX512 62100 EXTENSION: AVX512EVEX 62101 ISA_SET: AVX512F_256 62102 EXCEPTIONS: AVX512-E4 62103 REAL_OPCODE: Y 62104 ATTRIBUTES: MASKOP_EVEX 62105 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 62106 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 62107 IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 62108 } 62109 62110 { 62111 ICLASS: VPROLVQ 62112 CPL: 3 62113 CATEGORY: AVX512 62114 EXTENSION: AVX512EVEX 62115 ISA_SET: AVX512F_256 62116 EXCEPTIONS: AVX512-E4 62117 REAL_OPCODE: Y 62118 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62119 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 62120 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 62121 IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 62122 } 62123 62124 62125 # EMITTING VPRORD (VPRORD-128-1) 62126 { 62127 ICLASS: VPRORD 62128 CPL: 3 62129 CATEGORY: AVX512 62130 EXTENSION: AVX512EVEX 62131 ISA_SET: AVX512F_128 62132 EXCEPTIONS: AVX512-E4 62133 REAL_OPCODE: Y 62134 ATTRIBUTES: MASKOP_EVEX 62135 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8() 62136 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 62137 IFORM: VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 62138 } 62139 62140 { 62141 ICLASS: VPRORD 62142 CPL: 3 62143 CATEGORY: AVX512 62144 EXTENSION: AVX512EVEX 62145 ISA_SET: AVX512F_128 62146 EXCEPTIONS: AVX512-E4 62147 REAL_OPCODE: Y 62148 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62149 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 62150 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 62151 IFORM: VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 62152 } 62153 62154 62155 # EMITTING VPRORD (VPRORD-256-1) 62156 { 62157 ICLASS: VPRORD 62158 CPL: 3 62159 CATEGORY: AVX512 62160 EXTENSION: AVX512EVEX 62161 ISA_SET: AVX512F_256 62162 EXCEPTIONS: AVX512-E4 62163 REAL_OPCODE: Y 62164 ATTRIBUTES: MASKOP_EVEX 62165 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8() 62166 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 62167 IFORM: VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 62168 } 62169 62170 { 62171 ICLASS: VPRORD 62172 CPL: 3 62173 CATEGORY: AVX512 62174 EXTENSION: AVX512EVEX 62175 ISA_SET: AVX512F_256 62176 EXCEPTIONS: AVX512-E4 62177 REAL_OPCODE: Y 62178 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62179 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 62180 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 62181 IFORM: VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 62182 } 62183 62184 62185 # EMITTING VPRORQ (VPRORQ-128-1) 62186 { 62187 ICLASS: VPRORQ 62188 CPL: 3 62189 CATEGORY: AVX512 62190 EXTENSION: AVX512EVEX 62191 ISA_SET: AVX512F_128 62192 EXCEPTIONS: AVX512-E4 62193 REAL_OPCODE: Y 62194 ATTRIBUTES: MASKOP_EVEX 62195 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8() 62196 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b 62197 IFORM: VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 62198 } 62199 62200 { 62201 ICLASS: VPRORQ 62202 CPL: 3 62203 CATEGORY: AVX512 62204 EXTENSION: AVX512EVEX 62205 ISA_SET: AVX512F_128 62206 EXCEPTIONS: AVX512-E4 62207 REAL_OPCODE: Y 62208 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62209 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 62210 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 62211 IFORM: VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 62212 } 62213 62214 62215 # EMITTING VPRORQ (VPRORQ-256-1) 62216 { 62217 ICLASS: VPRORQ 62218 CPL: 3 62219 CATEGORY: AVX512 62220 EXTENSION: AVX512EVEX 62221 ISA_SET: AVX512F_256 62222 EXCEPTIONS: AVX512-E4 62223 REAL_OPCODE: Y 62224 ATTRIBUTES: MASKOP_EVEX 62225 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8() 62226 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 62227 IFORM: VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 62228 } 62229 62230 { 62231 ICLASS: VPRORQ 62232 CPL: 3 62233 CATEGORY: AVX512 62234 EXTENSION: AVX512EVEX 62235 ISA_SET: AVX512F_256 62236 EXCEPTIONS: AVX512-E4 62237 REAL_OPCODE: Y 62238 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62239 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 62240 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 62241 IFORM: VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 62242 } 62243 62244 62245 # EMITTING VPRORVD (VPRORVD-128-1) 62246 { 62247 ICLASS: VPRORVD 62248 CPL: 3 62249 CATEGORY: AVX512 62250 EXTENSION: AVX512EVEX 62251 ISA_SET: AVX512F_128 62252 EXCEPTIONS: AVX512-E4 62253 REAL_OPCODE: Y 62254 ATTRIBUTES: MASKOP_EVEX 62255 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 62256 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 62257 IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 62258 } 62259 62260 { 62261 ICLASS: VPRORVD 62262 CPL: 3 62263 CATEGORY: AVX512 62264 EXTENSION: AVX512EVEX 62265 ISA_SET: AVX512F_128 62266 EXCEPTIONS: AVX512-E4 62267 REAL_OPCODE: Y 62268 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62269 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 62270 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 62271 IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 62272 } 62273 62274 62275 # EMITTING VPRORVD (VPRORVD-256-1) 62276 { 62277 ICLASS: VPRORVD 62278 CPL: 3 62279 CATEGORY: AVX512 62280 EXTENSION: AVX512EVEX 62281 ISA_SET: AVX512F_256 62282 EXCEPTIONS: AVX512-E4 62283 REAL_OPCODE: Y 62284 ATTRIBUTES: MASKOP_EVEX 62285 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 62286 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 62287 IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 62288 } 62289 62290 { 62291 ICLASS: VPRORVD 62292 CPL: 3 62293 CATEGORY: AVX512 62294 EXTENSION: AVX512EVEX 62295 ISA_SET: AVX512F_256 62296 EXCEPTIONS: AVX512-E4 62297 REAL_OPCODE: Y 62298 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62299 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 62300 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 62301 IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 62302 } 62303 62304 62305 # EMITTING VPRORVQ (VPRORVQ-128-1) 62306 { 62307 ICLASS: VPRORVQ 62308 CPL: 3 62309 CATEGORY: AVX512 62310 EXTENSION: AVX512EVEX 62311 ISA_SET: AVX512F_128 62312 EXCEPTIONS: AVX512-E4 62313 REAL_OPCODE: Y 62314 ATTRIBUTES: MASKOP_EVEX 62315 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 62316 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 62317 IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 62318 } 62319 62320 { 62321 ICLASS: VPRORVQ 62322 CPL: 3 62323 CATEGORY: AVX512 62324 EXTENSION: AVX512EVEX 62325 ISA_SET: AVX512F_128 62326 EXCEPTIONS: AVX512-E4 62327 REAL_OPCODE: Y 62328 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62329 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 62330 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 62331 IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 62332 } 62333 62334 62335 # EMITTING VPRORVQ (VPRORVQ-256-1) 62336 { 62337 ICLASS: VPRORVQ 62338 CPL: 3 62339 CATEGORY: AVX512 62340 EXTENSION: AVX512EVEX 62341 ISA_SET: AVX512F_256 62342 EXCEPTIONS: AVX512-E4 62343 REAL_OPCODE: Y 62344 ATTRIBUTES: MASKOP_EVEX 62345 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 62346 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 62347 IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 62348 } 62349 62350 { 62351 ICLASS: VPRORVQ 62352 CPL: 3 62353 CATEGORY: AVX512 62354 EXTENSION: AVX512EVEX 62355 ISA_SET: AVX512F_256 62356 EXCEPTIONS: AVX512-E4 62357 REAL_OPCODE: Y 62358 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62359 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 62360 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 62361 IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 62362 } 62363 62364 62365 # EMITTING VPSADBW (VPSADBW-128-1) 62366 { 62367 ICLASS: VPSADBW 62368 CPL: 3 62369 CATEGORY: AVX512 62370 EXTENSION: AVX512EVEX 62371 ISA_SET: AVX512BW_128 62372 EXCEPTIONS: AVX512-E4NF 62373 REAL_OPCODE: Y 62374 PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 62375 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 REG2=XMM_B3():r:dq:u8 62376 IFORM: VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 62377 } 62378 62379 { 62380 ICLASS: VPSADBW 62381 CPL: 3 62382 CATEGORY: AVX512 62383 EXTENSION: AVX512EVEX 62384 ISA_SET: AVX512BW_128 62385 EXCEPTIONS: AVX512-E4NF 62386 REAL_OPCODE: Y 62387 ATTRIBUTES: DISP8_FULLMEM 62388 PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() 62389 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 MEM0:r:dq:u8 62390 IFORM: VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 62391 } 62392 62393 62394 # EMITTING VPSADBW (VPSADBW-256-1) 62395 { 62396 ICLASS: VPSADBW 62397 CPL: 3 62398 CATEGORY: AVX512 62399 EXTENSION: AVX512EVEX 62400 ISA_SET: AVX512BW_256 62401 EXCEPTIONS: AVX512-E4NF 62402 REAL_OPCODE: Y 62403 PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 62404 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 REG2=YMM_B3():r:qq:u8 62405 IFORM: VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 62406 } 62407 62408 { 62409 ICLASS: VPSADBW 62410 CPL: 3 62411 CATEGORY: AVX512 62412 EXTENSION: AVX512EVEX 62413 ISA_SET: AVX512BW_256 62414 EXCEPTIONS: AVX512-E4NF 62415 REAL_OPCODE: Y 62416 ATTRIBUTES: DISP8_FULLMEM 62417 PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() 62418 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 MEM0:r:qq:u8 62419 IFORM: VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 62420 } 62421 62422 62423 # EMITTING VPSADBW (VPSADBW-512-1) 62424 { 62425 ICLASS: VPSADBW 62426 CPL: 3 62427 CATEGORY: AVX512 62428 EXTENSION: AVX512EVEX 62429 ISA_SET: AVX512BW_512 62430 EXCEPTIONS: AVX512-E4NF 62431 REAL_OPCODE: Y 62432 PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 62433 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 REG2=ZMM_B3():r:zu8 62434 IFORM: VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 62435 } 62436 62437 { 62438 ICLASS: VPSADBW 62439 CPL: 3 62440 CATEGORY: AVX512 62441 EXTENSION: AVX512EVEX 62442 ISA_SET: AVX512BW_512 62443 EXCEPTIONS: AVX512-E4NF 62444 REAL_OPCODE: Y 62445 ATTRIBUTES: DISP8_FULLMEM 62446 PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() 62447 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 MEM0:r:zd:u8 62448 IFORM: VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 62449 } 62450 62451 62452 # EMITTING VPSCATTERDD (VPSCATTERDD-128-1) 62453 { 62454 ICLASS: VPSCATTERDD 62455 CPL: 3 62456 CATEGORY: SCATTER 62457 EXTENSION: AVX512EVEX 62458 ISA_SET: AVX512F_128 62459 EXCEPTIONS: AVX512-E12 62460 REAL_OPCODE: Y 62461 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 62462 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 62463 OPERANDS: MEM0:w:dq:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 62464 IFORM: VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 62465 } 62466 62467 62468 # EMITTING VPSCATTERDD (VPSCATTERDD-256-1) 62469 { 62470 ICLASS: VPSCATTERDD 62471 CPL: 3 62472 CATEGORY: SCATTER 62473 EXTENSION: AVX512EVEX 62474 ISA_SET: AVX512F_256 62475 EXCEPTIONS: AVX512-E12 62476 REAL_OPCODE: Y 62477 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 62478 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 62479 OPERANDS: MEM0:w:qq:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 62480 IFORM: VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 62481 } 62482 62483 62484 # EMITTING VPSCATTERDQ (VPSCATTERDQ-128-1) 62485 { 62486 ICLASS: VPSCATTERDQ 62487 CPL: 3 62488 CATEGORY: SCATTER 62489 EXTENSION: AVX512EVEX 62490 ISA_SET: AVX512F_128 62491 EXCEPTIONS: AVX512-E12 62492 REAL_OPCODE: Y 62493 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 62494 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 62495 OPERANDS: MEM0:w:dq:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 62496 IFORM: VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 62497 } 62498 62499 62500 # EMITTING VPSCATTERDQ (VPSCATTERDQ-256-1) 62501 { 62502 ICLASS: VPSCATTERDQ 62503 CPL: 3 62504 CATEGORY: SCATTER 62505 EXTENSION: AVX512EVEX 62506 ISA_SET: AVX512F_256 62507 EXCEPTIONS: AVX512-E12 62508 REAL_OPCODE: Y 62509 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 62510 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 62511 OPERANDS: MEM0:w:qq:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 62512 IFORM: VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 62513 } 62514 62515 62516 # EMITTING VPSCATTERQD (VPSCATTERQD-128-1) 62517 { 62518 ICLASS: VPSCATTERQD 62519 CPL: 3 62520 CATEGORY: SCATTER 62521 EXTENSION: AVX512EVEX 62522 ISA_SET: AVX512F_128 62523 EXCEPTIONS: AVX512-E12 62524 REAL_OPCODE: Y 62525 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 62526 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 62527 OPERANDS: MEM0:w:q:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 62528 IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 62529 } 62530 62531 62532 # EMITTING VPSCATTERQD (VPSCATTERQD-256-1) 62533 { 62534 ICLASS: VPSCATTERQD 62535 CPL: 3 62536 CATEGORY: SCATTER 62537 EXTENSION: AVX512EVEX 62538 ISA_SET: AVX512F_256 62539 EXCEPTIONS: AVX512-E12 62540 REAL_OPCODE: Y 62541 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 62542 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 62543 OPERANDS: MEM0:w:dq:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 62544 IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 62545 } 62546 62547 62548 # EMITTING VPSCATTERQQ (VPSCATTERQQ-128-1) 62549 { 62550 ICLASS: VPSCATTERQQ 62551 CPL: 3 62552 CATEGORY: SCATTER 62553 EXTENSION: AVX512EVEX 62554 ISA_SET: AVX512F_128 62555 EXCEPTIONS: AVX512-E12 62556 REAL_OPCODE: Y 62557 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 62558 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 62559 OPERANDS: MEM0:w:dq:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 62560 IFORM: VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 62561 } 62562 62563 62564 # EMITTING VPSCATTERQQ (VPSCATTERQQ-256-1) 62565 { 62566 ICLASS: VPSCATTERQQ 62567 CPL: 3 62568 CATEGORY: SCATTER 62569 EXTENSION: AVX512EVEX 62570 ISA_SET: AVX512F_256 62571 EXCEPTIONS: AVX512-E12 62572 REAL_OPCODE: Y 62573 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 62574 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 62575 OPERANDS: MEM0:w:qq:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 62576 IFORM: VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 62577 } 62578 62579 62580 # EMITTING VPSHUFB (VPSHUFB-128-1) 62581 { 62582 ICLASS: VPSHUFB 62583 CPL: 3 62584 CATEGORY: AVX512 62585 EXTENSION: AVX512EVEX 62586 ISA_SET: AVX512BW_128 62587 EXCEPTIONS: AVX512-E4NF 62588 REAL_OPCODE: Y 62589 ATTRIBUTES: MASKOP_EVEX 62590 PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 62591 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 62592 IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 62593 } 62594 62595 { 62596 ICLASS: VPSHUFB 62597 CPL: 3 62598 CATEGORY: AVX512 62599 EXTENSION: AVX512EVEX 62600 ISA_SET: AVX512BW_128 62601 EXCEPTIONS: AVX512-E4NF 62602 REAL_OPCODE: Y 62603 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 62604 PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 62605 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 62606 IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 62607 } 62608 62609 62610 # EMITTING VPSHUFB (VPSHUFB-256-1) 62611 { 62612 ICLASS: VPSHUFB 62613 CPL: 3 62614 CATEGORY: AVX512 62615 EXTENSION: AVX512EVEX 62616 ISA_SET: AVX512BW_256 62617 EXCEPTIONS: AVX512-E4NF 62618 REAL_OPCODE: Y 62619 ATTRIBUTES: MASKOP_EVEX 62620 PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 62621 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 62622 IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 62623 } 62624 62625 { 62626 ICLASS: VPSHUFB 62627 CPL: 3 62628 CATEGORY: AVX512 62629 EXTENSION: AVX512EVEX 62630 ISA_SET: AVX512BW_256 62631 EXCEPTIONS: AVX512-E4NF 62632 REAL_OPCODE: Y 62633 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 62634 PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 62635 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 62636 IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 62637 } 62638 62639 62640 # EMITTING VPSHUFB (VPSHUFB-512-1) 62641 { 62642 ICLASS: VPSHUFB 62643 CPL: 3 62644 CATEGORY: AVX512 62645 EXTENSION: AVX512EVEX 62646 ISA_SET: AVX512BW_512 62647 EXCEPTIONS: AVX512-E4NF 62648 REAL_OPCODE: Y 62649 ATTRIBUTES: MASKOP_EVEX 62650 PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 62651 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 62652 IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 62653 } 62654 62655 { 62656 ICLASS: VPSHUFB 62657 CPL: 3 62658 CATEGORY: AVX512 62659 EXTENSION: AVX512EVEX 62660 ISA_SET: AVX512BW_512 62661 EXCEPTIONS: AVX512-E4NF 62662 REAL_OPCODE: Y 62663 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 62664 PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 62665 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 62666 IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 62667 } 62668 62669 62670 # EMITTING VPSHUFD (VPSHUFD-128-1) 62671 { 62672 ICLASS: VPSHUFD 62673 CPL: 3 62674 CATEGORY: AVX512 62675 EXTENSION: AVX512EVEX 62676 ISA_SET: AVX512F_128 62677 EXCEPTIONS: AVX512-E4NF 62678 REAL_OPCODE: Y 62679 ATTRIBUTES: MASKOP_EVEX 62680 PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 62681 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 62682 IFORM: VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 62683 } 62684 62685 { 62686 ICLASS: VPSHUFD 62687 CPL: 3 62688 CATEGORY: AVX512 62689 EXTENSION: AVX512EVEX 62690 ISA_SET: AVX512F_128 62691 EXCEPTIONS: AVX512-E4NF 62692 REAL_OPCODE: Y 62693 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62694 PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 62695 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 62696 IFORM: VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 62697 } 62698 62699 62700 # EMITTING VPSHUFD (VPSHUFD-256-1) 62701 { 62702 ICLASS: VPSHUFD 62703 CPL: 3 62704 CATEGORY: AVX512 62705 EXTENSION: AVX512EVEX 62706 ISA_SET: AVX512F_256 62707 EXCEPTIONS: AVX512-E4NF 62708 REAL_OPCODE: Y 62709 ATTRIBUTES: MASKOP_EVEX 62710 PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 62711 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 62712 IFORM: VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 62713 } 62714 62715 { 62716 ICLASS: VPSHUFD 62717 CPL: 3 62718 CATEGORY: AVX512 62719 EXTENSION: AVX512EVEX 62720 ISA_SET: AVX512F_256 62721 EXCEPTIONS: AVX512-E4NF 62722 REAL_OPCODE: Y 62723 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62724 PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 62725 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 62726 IFORM: VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 62727 } 62728 62729 62730 # EMITTING VPSHUFHW (VPSHUFHW-128-1) 62731 { 62732 ICLASS: VPSHUFHW 62733 CPL: 3 62734 CATEGORY: AVX512 62735 EXTENSION: AVX512EVEX 62736 ISA_SET: AVX512BW_128 62737 EXCEPTIONS: AVX512-E4NF 62738 REAL_OPCODE: Y 62739 ATTRIBUTES: MASKOP_EVEX 62740 PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() 62741 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b 62742 IFORM: VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 62743 } 62744 62745 { 62746 ICLASS: VPSHUFHW 62747 CPL: 3 62748 CATEGORY: AVX512 62749 EXTENSION: AVX512EVEX 62750 ISA_SET: AVX512BW_128 62751 EXCEPTIONS: AVX512-E4NF 62752 REAL_OPCODE: Y 62753 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 62754 PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 62755 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b 62756 IFORM: VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 62757 } 62758 62759 62760 # EMITTING VPSHUFHW (VPSHUFHW-256-1) 62761 { 62762 ICLASS: VPSHUFHW 62763 CPL: 3 62764 CATEGORY: AVX512 62765 EXTENSION: AVX512EVEX 62766 ISA_SET: AVX512BW_256 62767 EXCEPTIONS: AVX512-E4NF 62768 REAL_OPCODE: Y 62769 ATTRIBUTES: MASKOP_EVEX 62770 PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() 62771 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b 62772 IFORM: VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 62773 } 62774 62775 { 62776 ICLASS: VPSHUFHW 62777 CPL: 3 62778 CATEGORY: AVX512 62779 EXTENSION: AVX512EVEX 62780 ISA_SET: AVX512BW_256 62781 EXCEPTIONS: AVX512-E4NF 62782 REAL_OPCODE: Y 62783 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 62784 PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 62785 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b 62786 IFORM: VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 62787 } 62788 62789 62790 # EMITTING VPSHUFHW (VPSHUFHW-512-1) 62791 { 62792 ICLASS: VPSHUFHW 62793 CPL: 3 62794 CATEGORY: AVX512 62795 EXTENSION: AVX512EVEX 62796 ISA_SET: AVX512BW_512 62797 EXCEPTIONS: AVX512-E4NF 62798 REAL_OPCODE: Y 62799 ATTRIBUTES: MASKOP_EVEX 62800 PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() 62801 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b 62802 IFORM: VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 62803 } 62804 62805 { 62806 ICLASS: VPSHUFHW 62807 CPL: 3 62808 CATEGORY: AVX512 62809 EXTENSION: AVX512EVEX 62810 ISA_SET: AVX512BW_512 62811 EXCEPTIONS: AVX512-E4NF 62812 REAL_OPCODE: Y 62813 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 62814 PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 62815 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b 62816 IFORM: VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 62817 } 62818 62819 62820 # EMITTING VPSHUFLW (VPSHUFLW-128-1) 62821 { 62822 ICLASS: VPSHUFLW 62823 CPL: 3 62824 CATEGORY: AVX512 62825 EXTENSION: AVX512EVEX 62826 ISA_SET: AVX512BW_128 62827 EXCEPTIONS: AVX512-E4NF 62828 REAL_OPCODE: Y 62829 ATTRIBUTES: MASKOP_EVEX 62830 PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() 62831 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b 62832 IFORM: VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 62833 } 62834 62835 { 62836 ICLASS: VPSHUFLW 62837 CPL: 3 62838 CATEGORY: AVX512 62839 EXTENSION: AVX512EVEX 62840 ISA_SET: AVX512BW_128 62841 EXCEPTIONS: AVX512-E4NF 62842 REAL_OPCODE: Y 62843 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 62844 PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 62845 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b 62846 IFORM: VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 62847 } 62848 62849 62850 # EMITTING VPSHUFLW (VPSHUFLW-256-1) 62851 { 62852 ICLASS: VPSHUFLW 62853 CPL: 3 62854 CATEGORY: AVX512 62855 EXTENSION: AVX512EVEX 62856 ISA_SET: AVX512BW_256 62857 EXCEPTIONS: AVX512-E4NF 62858 REAL_OPCODE: Y 62859 ATTRIBUTES: MASKOP_EVEX 62860 PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() 62861 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b 62862 IFORM: VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 62863 } 62864 62865 { 62866 ICLASS: VPSHUFLW 62867 CPL: 3 62868 CATEGORY: AVX512 62869 EXTENSION: AVX512EVEX 62870 ISA_SET: AVX512BW_256 62871 EXCEPTIONS: AVX512-E4NF 62872 REAL_OPCODE: Y 62873 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 62874 PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 62875 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b 62876 IFORM: VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 62877 } 62878 62879 62880 # EMITTING VPSHUFLW (VPSHUFLW-512-1) 62881 { 62882 ICLASS: VPSHUFLW 62883 CPL: 3 62884 CATEGORY: AVX512 62885 EXTENSION: AVX512EVEX 62886 ISA_SET: AVX512BW_512 62887 EXCEPTIONS: AVX512-E4NF 62888 REAL_OPCODE: Y 62889 ATTRIBUTES: MASKOP_EVEX 62890 PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() 62891 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b 62892 IFORM: VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 62893 } 62894 62895 { 62896 ICLASS: VPSHUFLW 62897 CPL: 3 62898 CATEGORY: AVX512 62899 EXTENSION: AVX512EVEX 62900 ISA_SET: AVX512BW_512 62901 EXCEPTIONS: AVX512-E4NF 62902 REAL_OPCODE: Y 62903 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 62904 PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 62905 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b 62906 IFORM: VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 62907 } 62908 62909 62910 # EMITTING VPSLLD (VPSLLD-128-1) 62911 { 62912 ICLASS: VPSLLD 62913 CPL: 3 62914 CATEGORY: AVX512 62915 EXTENSION: AVX512EVEX 62916 ISA_SET: AVX512F_128 62917 EXCEPTIONS: AVX512-E4NF 62918 REAL_OPCODE: Y 62919 ATTRIBUTES: MASKOP_EVEX 62920 PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 62921 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 62922 IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 62923 } 62924 62925 { 62926 ICLASS: VPSLLD 62927 CPL: 3 62928 CATEGORY: AVX512 62929 EXTENSION: AVX512EVEX 62930 ISA_SET: AVX512F_128 62931 EXCEPTIONS: AVX512-E4NF 62932 REAL_OPCODE: Y 62933 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 62934 PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() 62935 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 62936 IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 62937 } 62938 62939 62940 # EMITTING VPSLLD (VPSLLD-128-3) 62941 { 62942 ICLASS: VPSLLD 62943 CPL: 3 62944 CATEGORY: AVX512 62945 EXTENSION: AVX512EVEX 62946 ISA_SET: AVX512F_128 62947 EXCEPTIONS: AVX512-E4 62948 REAL_OPCODE: Y 62949 ATTRIBUTES: MASKOP_EVEX 62950 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8() 62951 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 62952 IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 62953 } 62954 62955 { 62956 ICLASS: VPSLLD 62957 CPL: 3 62958 CATEGORY: AVX512 62959 EXTENSION: AVX512EVEX 62960 ISA_SET: AVX512F_128 62961 EXCEPTIONS: AVX512-E4 62962 REAL_OPCODE: Y 62963 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 62964 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 62965 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 62966 IFORM: VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 62967 } 62968 62969 62970 # EMITTING VPSLLD (VPSLLD-256-1) 62971 { 62972 ICLASS: VPSLLD 62973 CPL: 3 62974 CATEGORY: AVX512 62975 EXTENSION: AVX512EVEX 62976 ISA_SET: AVX512F_256 62977 EXCEPTIONS: AVX512-E4NF 62978 REAL_OPCODE: Y 62979 ATTRIBUTES: MASKOP_EVEX 62980 PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 62981 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 62982 IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 62983 } 62984 62985 { 62986 ICLASS: VPSLLD 62987 CPL: 3 62988 CATEGORY: AVX512 62989 EXTENSION: AVX512EVEX 62990 ISA_SET: AVX512F_256 62991 EXCEPTIONS: AVX512-E4NF 62992 REAL_OPCODE: Y 62993 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 62994 PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() 62995 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 62996 IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 62997 } 62998 62999 63000 # EMITTING VPSLLD (VPSLLD-256-3) 63001 { 63002 ICLASS: VPSLLD 63003 CPL: 3 63004 CATEGORY: AVX512 63005 EXTENSION: AVX512EVEX 63006 ISA_SET: AVX512F_256 63007 EXCEPTIONS: AVX512-E4 63008 REAL_OPCODE: Y 63009 ATTRIBUTES: MASKOP_EVEX 63010 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8() 63011 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 63012 IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 63013 } 63014 63015 { 63016 ICLASS: VPSLLD 63017 CPL: 3 63018 CATEGORY: AVX512 63019 EXTENSION: AVX512EVEX 63020 ISA_SET: AVX512F_256 63021 EXCEPTIONS: AVX512-E4 63022 REAL_OPCODE: Y 63023 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63024 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 63025 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 63026 IFORM: VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 63027 } 63028 63029 63030 # EMITTING VPSLLDQ (VPSLLDQ-128-2) 63031 { 63032 ICLASS: VPSLLDQ 63033 CPL: 3 63034 CATEGORY: AVX512 63035 EXTENSION: AVX512EVEX 63036 ISA_SET: AVX512BW_128 63037 EXCEPTIONS: AVX512-E4NF 63038 REAL_OPCODE: Y 63039 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() 63040 OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b 63041 IFORM: VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 63042 } 63043 63044 { 63045 ICLASS: VPSLLDQ 63046 CPL: 3 63047 CATEGORY: AVX512 63048 EXTENSION: AVX512EVEX 63049 ISA_SET: AVX512BW_128 63050 EXCEPTIONS: AVX512-E4NF 63051 REAL_OPCODE: Y 63052 ATTRIBUTES: DISP8_FULLMEM 63053 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 63054 OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b 63055 IFORM: VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 63056 } 63057 63058 63059 # EMITTING VPSLLDQ (VPSLLDQ-256-2) 63060 { 63061 ICLASS: VPSLLDQ 63062 CPL: 3 63063 CATEGORY: AVX512 63064 EXTENSION: AVX512EVEX 63065 ISA_SET: AVX512BW_256 63066 EXCEPTIONS: AVX512-E4NF 63067 REAL_OPCODE: Y 63068 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() 63069 OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b 63070 IFORM: VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 63071 } 63072 63073 { 63074 ICLASS: VPSLLDQ 63075 CPL: 3 63076 CATEGORY: AVX512 63077 EXTENSION: AVX512EVEX 63078 ISA_SET: AVX512BW_256 63079 EXCEPTIONS: AVX512-E4NF 63080 REAL_OPCODE: Y 63081 ATTRIBUTES: DISP8_FULLMEM 63082 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 63083 OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b 63084 IFORM: VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 63085 } 63086 63087 63088 # EMITTING VPSLLDQ (VPSLLDQ-512-1) 63089 { 63090 ICLASS: VPSLLDQ 63091 CPL: 3 63092 CATEGORY: AVX512 63093 EXTENSION: AVX512EVEX 63094 ISA_SET: AVX512BW_512 63095 EXCEPTIONS: AVX512-E4NF 63096 REAL_OPCODE: Y 63097 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() 63098 OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b 63099 IFORM: VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 63100 } 63101 63102 { 63103 ICLASS: VPSLLDQ 63104 CPL: 3 63105 CATEGORY: AVX512 63106 EXTENSION: AVX512EVEX 63107 ISA_SET: AVX512BW_512 63108 EXCEPTIONS: AVX512-E4NF 63109 REAL_OPCODE: Y 63110 ATTRIBUTES: DISP8_FULLMEM 63111 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 63112 OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b 63113 IFORM: VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 63114 } 63115 63116 63117 # EMITTING VPSLLQ (VPSLLQ-128-1) 63118 { 63119 ICLASS: VPSLLQ 63120 CPL: 3 63121 CATEGORY: AVX512 63122 EXTENSION: AVX512EVEX 63123 ISA_SET: AVX512F_128 63124 EXCEPTIONS: AVX512-E4NF 63125 REAL_OPCODE: Y 63126 ATTRIBUTES: MASKOP_EVEX 63127 PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 63128 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 63129 IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 63130 } 63131 63132 { 63133 ICLASS: VPSLLQ 63134 CPL: 3 63135 CATEGORY: AVX512 63136 EXTENSION: AVX512EVEX 63137 ISA_SET: AVX512F_128 63138 EXCEPTIONS: AVX512-E4NF 63139 REAL_OPCODE: Y 63140 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 63141 PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() 63142 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 63143 IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 63144 } 63145 63146 63147 # EMITTING VPSLLQ (VPSLLQ-128-3) 63148 { 63149 ICLASS: VPSLLQ 63150 CPL: 3 63151 CATEGORY: AVX512 63152 EXTENSION: AVX512EVEX 63153 ISA_SET: AVX512F_128 63154 EXCEPTIONS: AVX512-E4 63155 REAL_OPCODE: Y 63156 ATTRIBUTES: MASKOP_EVEX 63157 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8() 63158 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b 63159 IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 63160 } 63161 63162 { 63163 ICLASS: VPSLLQ 63164 CPL: 3 63165 CATEGORY: AVX512 63166 EXTENSION: AVX512EVEX 63167 ISA_SET: AVX512F_128 63168 EXCEPTIONS: AVX512-E4 63169 REAL_OPCODE: Y 63170 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63171 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 63172 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 63173 IFORM: VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 63174 } 63175 63176 63177 # EMITTING VPSLLQ (VPSLLQ-256-1) 63178 { 63179 ICLASS: VPSLLQ 63180 CPL: 3 63181 CATEGORY: AVX512 63182 EXTENSION: AVX512EVEX 63183 ISA_SET: AVX512F_256 63184 EXCEPTIONS: AVX512-E4NF 63185 REAL_OPCODE: Y 63186 ATTRIBUTES: MASKOP_EVEX 63187 PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 63188 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 63189 IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 63190 } 63191 63192 { 63193 ICLASS: VPSLLQ 63194 CPL: 3 63195 CATEGORY: AVX512 63196 EXTENSION: AVX512EVEX 63197 ISA_SET: AVX512F_256 63198 EXCEPTIONS: AVX512-E4NF 63199 REAL_OPCODE: Y 63200 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 63201 PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() 63202 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 63203 IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 63204 } 63205 63206 63207 # EMITTING VPSLLQ (VPSLLQ-256-3) 63208 { 63209 ICLASS: VPSLLQ 63210 CPL: 3 63211 CATEGORY: AVX512 63212 EXTENSION: AVX512EVEX 63213 ISA_SET: AVX512F_256 63214 EXCEPTIONS: AVX512-E4 63215 REAL_OPCODE: Y 63216 ATTRIBUTES: MASKOP_EVEX 63217 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8() 63218 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 63219 IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 63220 } 63221 63222 { 63223 ICLASS: VPSLLQ 63224 CPL: 3 63225 CATEGORY: AVX512 63226 EXTENSION: AVX512EVEX 63227 ISA_SET: AVX512F_256 63228 EXCEPTIONS: AVX512-E4 63229 REAL_OPCODE: Y 63230 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63231 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 63232 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 63233 IFORM: VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 63234 } 63235 63236 63237 # EMITTING VPSLLVD (VPSLLVD-128-1) 63238 { 63239 ICLASS: VPSLLVD 63240 CPL: 3 63241 CATEGORY: AVX512 63242 EXTENSION: AVX512EVEX 63243 ISA_SET: AVX512F_128 63244 EXCEPTIONS: AVX512-E4 63245 REAL_OPCODE: Y 63246 ATTRIBUTES: MASKOP_EVEX 63247 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 63248 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 63249 IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 63250 } 63251 63252 { 63253 ICLASS: VPSLLVD 63254 CPL: 3 63255 CATEGORY: AVX512 63256 EXTENSION: AVX512EVEX 63257 ISA_SET: AVX512F_128 63258 EXCEPTIONS: AVX512-E4 63259 REAL_OPCODE: Y 63260 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63261 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 63262 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 63263 IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 63264 } 63265 63266 63267 # EMITTING VPSLLVD (VPSLLVD-256-1) 63268 { 63269 ICLASS: VPSLLVD 63270 CPL: 3 63271 CATEGORY: AVX512 63272 EXTENSION: AVX512EVEX 63273 ISA_SET: AVX512F_256 63274 EXCEPTIONS: AVX512-E4 63275 REAL_OPCODE: Y 63276 ATTRIBUTES: MASKOP_EVEX 63277 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 63278 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 63279 IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 63280 } 63281 63282 { 63283 ICLASS: VPSLLVD 63284 CPL: 3 63285 CATEGORY: AVX512 63286 EXTENSION: AVX512EVEX 63287 ISA_SET: AVX512F_256 63288 EXCEPTIONS: AVX512-E4 63289 REAL_OPCODE: Y 63290 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63291 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 63292 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 63293 IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 63294 } 63295 63296 63297 # EMITTING VPSLLVQ (VPSLLVQ-128-1) 63298 { 63299 ICLASS: VPSLLVQ 63300 CPL: 3 63301 CATEGORY: AVX512 63302 EXTENSION: AVX512EVEX 63303 ISA_SET: AVX512F_128 63304 EXCEPTIONS: AVX512-E4 63305 REAL_OPCODE: Y 63306 ATTRIBUTES: MASKOP_EVEX 63307 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 63308 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 63309 IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 63310 } 63311 63312 { 63313 ICLASS: VPSLLVQ 63314 CPL: 3 63315 CATEGORY: AVX512 63316 EXTENSION: AVX512EVEX 63317 ISA_SET: AVX512F_128 63318 EXCEPTIONS: AVX512-E4 63319 REAL_OPCODE: Y 63320 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63321 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 63322 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 63323 IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 63324 } 63325 63326 63327 # EMITTING VPSLLVQ (VPSLLVQ-256-1) 63328 { 63329 ICLASS: VPSLLVQ 63330 CPL: 3 63331 CATEGORY: AVX512 63332 EXTENSION: AVX512EVEX 63333 ISA_SET: AVX512F_256 63334 EXCEPTIONS: AVX512-E4 63335 REAL_OPCODE: Y 63336 ATTRIBUTES: MASKOP_EVEX 63337 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 63338 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 63339 IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 63340 } 63341 63342 { 63343 ICLASS: VPSLLVQ 63344 CPL: 3 63345 CATEGORY: AVX512 63346 EXTENSION: AVX512EVEX 63347 ISA_SET: AVX512F_256 63348 EXCEPTIONS: AVX512-E4 63349 REAL_OPCODE: Y 63350 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63351 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 63352 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 63353 IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 63354 } 63355 63356 63357 # EMITTING VPSLLVW (VPSLLVW-128-1) 63358 { 63359 ICLASS: VPSLLVW 63360 CPL: 3 63361 CATEGORY: AVX512 63362 EXTENSION: AVX512EVEX 63363 ISA_SET: AVX512BW_128 63364 EXCEPTIONS: AVX512-E4 63365 REAL_OPCODE: Y 63366 ATTRIBUTES: MASKOP_EVEX 63367 PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 63368 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 63369 IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 63370 } 63371 63372 { 63373 ICLASS: VPSLLVW 63374 CPL: 3 63375 CATEGORY: AVX512 63376 EXTENSION: AVX512EVEX 63377 ISA_SET: AVX512BW_128 63378 EXCEPTIONS: AVX512-E4 63379 REAL_OPCODE: Y 63380 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 63381 PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 63382 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 63383 IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 63384 } 63385 63386 63387 # EMITTING VPSLLVW (VPSLLVW-256-1) 63388 { 63389 ICLASS: VPSLLVW 63390 CPL: 3 63391 CATEGORY: AVX512 63392 EXTENSION: AVX512EVEX 63393 ISA_SET: AVX512BW_256 63394 EXCEPTIONS: AVX512-E4 63395 REAL_OPCODE: Y 63396 ATTRIBUTES: MASKOP_EVEX 63397 PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 63398 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 63399 IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 63400 } 63401 63402 { 63403 ICLASS: VPSLLVW 63404 CPL: 3 63405 CATEGORY: AVX512 63406 EXTENSION: AVX512EVEX 63407 ISA_SET: AVX512BW_256 63408 EXCEPTIONS: AVX512-E4 63409 REAL_OPCODE: Y 63410 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 63411 PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 63412 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 63413 IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 63414 } 63415 63416 63417 # EMITTING VPSLLVW (VPSLLVW-512-1) 63418 { 63419 ICLASS: VPSLLVW 63420 CPL: 3 63421 CATEGORY: AVX512 63422 EXTENSION: AVX512EVEX 63423 ISA_SET: AVX512BW_512 63424 EXCEPTIONS: AVX512-E4 63425 REAL_OPCODE: Y 63426 ATTRIBUTES: MASKOP_EVEX 63427 PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 63428 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 63429 IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 63430 } 63431 63432 { 63433 ICLASS: VPSLLVW 63434 CPL: 3 63435 CATEGORY: AVX512 63436 EXTENSION: AVX512EVEX 63437 ISA_SET: AVX512BW_512 63438 EXCEPTIONS: AVX512-E4 63439 REAL_OPCODE: Y 63440 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 63441 PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 63442 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 63443 IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 63444 } 63445 63446 63447 # EMITTING VPSLLW (VPSLLW-128-1) 63448 { 63449 ICLASS: VPSLLW 63450 CPL: 3 63451 CATEGORY: AVX512 63452 EXTENSION: AVX512EVEX 63453 ISA_SET: AVX512BW_128 63454 EXCEPTIONS: AVX512-E4NF 63455 REAL_OPCODE: Y 63456 ATTRIBUTES: MASKOP_EVEX 63457 PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 63458 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 63459 IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 63460 } 63461 63462 { 63463 ICLASS: VPSLLW 63464 CPL: 3 63465 CATEGORY: AVX512 63466 EXTENSION: AVX512EVEX 63467 ISA_SET: AVX512BW_128 63468 EXCEPTIONS: AVX512-E4NF 63469 REAL_OPCODE: Y 63470 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 63471 PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() 63472 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 63473 IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 63474 } 63475 63476 63477 # EMITTING VPSLLW (VPSLLW-128-3) 63478 { 63479 ICLASS: VPSLLW 63480 CPL: 3 63481 CATEGORY: AVX512 63482 EXTENSION: AVX512EVEX 63483 ISA_SET: AVX512BW_128 63484 EXCEPTIONS: AVX512-E4 63485 REAL_OPCODE: Y 63486 ATTRIBUTES: MASKOP_EVEX 63487 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8() 63488 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b 63489 IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 63490 } 63491 63492 { 63493 ICLASS: VPSLLW 63494 CPL: 3 63495 CATEGORY: AVX512 63496 EXTENSION: AVX512EVEX 63497 ISA_SET: AVX512BW_128 63498 EXCEPTIONS: AVX512-E4 63499 REAL_OPCODE: Y 63500 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 63501 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 63502 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b 63503 IFORM: VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 63504 } 63505 63506 63507 # EMITTING VPSLLW (VPSLLW-256-1) 63508 { 63509 ICLASS: VPSLLW 63510 CPL: 3 63511 CATEGORY: AVX512 63512 EXTENSION: AVX512EVEX 63513 ISA_SET: AVX512BW_256 63514 EXCEPTIONS: AVX512-E4NF 63515 REAL_OPCODE: Y 63516 ATTRIBUTES: MASKOP_EVEX 63517 PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 63518 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 63519 IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 63520 } 63521 63522 { 63523 ICLASS: VPSLLW 63524 CPL: 3 63525 CATEGORY: AVX512 63526 EXTENSION: AVX512EVEX 63527 ISA_SET: AVX512BW_256 63528 EXCEPTIONS: AVX512-E4NF 63529 REAL_OPCODE: Y 63530 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 63531 PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() 63532 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 63533 IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 63534 } 63535 63536 63537 # EMITTING VPSLLW (VPSLLW-256-3) 63538 { 63539 ICLASS: VPSLLW 63540 CPL: 3 63541 CATEGORY: AVX512 63542 EXTENSION: AVX512EVEX 63543 ISA_SET: AVX512BW_256 63544 EXCEPTIONS: AVX512-E4 63545 REAL_OPCODE: Y 63546 ATTRIBUTES: MASKOP_EVEX 63547 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8() 63548 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b 63549 IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 63550 } 63551 63552 { 63553 ICLASS: VPSLLW 63554 CPL: 3 63555 CATEGORY: AVX512 63556 EXTENSION: AVX512EVEX 63557 ISA_SET: AVX512BW_256 63558 EXCEPTIONS: AVX512-E4 63559 REAL_OPCODE: Y 63560 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 63561 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 63562 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b 63563 IFORM: VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 63564 } 63565 63566 63567 # EMITTING VPSLLW (VPSLLW-512-1) 63568 { 63569 ICLASS: VPSLLW 63570 CPL: 3 63571 CATEGORY: AVX512 63572 EXTENSION: AVX512EVEX 63573 ISA_SET: AVX512BW_512 63574 EXCEPTIONS: AVX512-E4NF 63575 REAL_OPCODE: Y 63576 ATTRIBUTES: MASKOP_EVEX 63577 PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 63578 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 63579 IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 63580 } 63581 63582 { 63583 ICLASS: VPSLLW 63584 CPL: 3 63585 CATEGORY: AVX512 63586 EXTENSION: AVX512EVEX 63587 ISA_SET: AVX512BW_512 63588 EXCEPTIONS: AVX512-E4NF 63589 REAL_OPCODE: Y 63590 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 63591 PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() 63592 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 63593 IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 63594 } 63595 63596 63597 # EMITTING VPSLLW (VPSLLW-512-2) 63598 { 63599 ICLASS: VPSLLW 63600 CPL: 3 63601 CATEGORY: AVX512 63602 EXTENSION: AVX512EVEX 63603 ISA_SET: AVX512BW_512 63604 EXCEPTIONS: AVX512-E4 63605 REAL_OPCODE: Y 63606 ATTRIBUTES: MASKOP_EVEX 63607 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8() 63608 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b 63609 IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 63610 } 63611 63612 { 63613 ICLASS: VPSLLW 63614 CPL: 3 63615 CATEGORY: AVX512 63616 EXTENSION: AVX512EVEX 63617 ISA_SET: AVX512BW_512 63618 EXCEPTIONS: AVX512-E4 63619 REAL_OPCODE: Y 63620 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 63621 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 63622 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b 63623 IFORM: VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 63624 } 63625 63626 63627 # EMITTING VPSRAD (VPSRAD-128-1) 63628 { 63629 ICLASS: VPSRAD 63630 CPL: 3 63631 CATEGORY: AVX512 63632 EXTENSION: AVX512EVEX 63633 ISA_SET: AVX512F_128 63634 EXCEPTIONS: AVX512-E4NF 63635 REAL_OPCODE: Y 63636 ATTRIBUTES: MASKOP_EVEX 63637 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 63638 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 63639 IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 63640 } 63641 63642 { 63643 ICLASS: VPSRAD 63644 CPL: 3 63645 CATEGORY: AVX512 63646 EXTENSION: AVX512EVEX 63647 ISA_SET: AVX512F_128 63648 EXCEPTIONS: AVX512-E4NF 63649 REAL_OPCODE: Y 63650 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 63651 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() 63652 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 63653 IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 63654 } 63655 63656 63657 # EMITTING VPSRAD (VPSRAD-128-3) 63658 { 63659 ICLASS: VPSRAD 63660 CPL: 3 63661 CATEGORY: AVX512 63662 EXTENSION: AVX512EVEX 63663 ISA_SET: AVX512F_128 63664 EXCEPTIONS: AVX512-E4 63665 REAL_OPCODE: Y 63666 ATTRIBUTES: MASKOP_EVEX 63667 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8() 63668 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 63669 IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 63670 } 63671 63672 { 63673 ICLASS: VPSRAD 63674 CPL: 3 63675 CATEGORY: AVX512 63676 EXTENSION: AVX512EVEX 63677 ISA_SET: AVX512F_128 63678 EXCEPTIONS: AVX512-E4 63679 REAL_OPCODE: Y 63680 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63681 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 63682 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 63683 IFORM: VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 63684 } 63685 63686 63687 # EMITTING VPSRAD (VPSRAD-256-1) 63688 { 63689 ICLASS: VPSRAD 63690 CPL: 3 63691 CATEGORY: AVX512 63692 EXTENSION: AVX512EVEX 63693 ISA_SET: AVX512F_256 63694 EXCEPTIONS: AVX512-E4NF 63695 REAL_OPCODE: Y 63696 ATTRIBUTES: MASKOP_EVEX 63697 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 63698 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 63699 IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 63700 } 63701 63702 { 63703 ICLASS: VPSRAD 63704 CPL: 3 63705 CATEGORY: AVX512 63706 EXTENSION: AVX512EVEX 63707 ISA_SET: AVX512F_256 63708 EXCEPTIONS: AVX512-E4NF 63709 REAL_OPCODE: Y 63710 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 63711 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() 63712 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 63713 IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 63714 } 63715 63716 63717 # EMITTING VPSRAD (VPSRAD-256-3) 63718 { 63719 ICLASS: VPSRAD 63720 CPL: 3 63721 CATEGORY: AVX512 63722 EXTENSION: AVX512EVEX 63723 ISA_SET: AVX512F_256 63724 EXCEPTIONS: AVX512-E4 63725 REAL_OPCODE: Y 63726 ATTRIBUTES: MASKOP_EVEX 63727 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8() 63728 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 63729 IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 63730 } 63731 63732 { 63733 ICLASS: VPSRAD 63734 CPL: 3 63735 CATEGORY: AVX512 63736 EXTENSION: AVX512EVEX 63737 ISA_SET: AVX512F_256 63738 EXCEPTIONS: AVX512-E4 63739 REAL_OPCODE: Y 63740 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63741 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 63742 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 63743 IFORM: VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 63744 } 63745 63746 63747 # EMITTING VPSRAQ (VPSRAQ-128-1) 63748 { 63749 ICLASS: VPSRAQ 63750 CPL: 3 63751 CATEGORY: AVX512 63752 EXTENSION: AVX512EVEX 63753 ISA_SET: AVX512F_128 63754 EXCEPTIONS: AVX512-E4NF 63755 REAL_OPCODE: Y 63756 ATTRIBUTES: MASKOP_EVEX 63757 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 63758 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 63759 IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 63760 } 63761 63762 { 63763 ICLASS: VPSRAQ 63764 CPL: 3 63765 CATEGORY: AVX512 63766 EXTENSION: AVX512EVEX 63767 ISA_SET: AVX512F_128 63768 EXCEPTIONS: AVX512-E4NF 63769 REAL_OPCODE: Y 63770 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 63771 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() 63772 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 63773 IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 63774 } 63775 63776 63777 # EMITTING VPSRAQ (VPSRAQ-128-2) 63778 { 63779 ICLASS: VPSRAQ 63780 CPL: 3 63781 CATEGORY: AVX512 63782 EXTENSION: AVX512EVEX 63783 ISA_SET: AVX512F_128 63784 EXCEPTIONS: AVX512-E4 63785 REAL_OPCODE: Y 63786 ATTRIBUTES: MASKOP_EVEX 63787 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8() 63788 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b 63789 IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 63790 } 63791 63792 { 63793 ICLASS: VPSRAQ 63794 CPL: 3 63795 CATEGORY: AVX512 63796 EXTENSION: AVX512EVEX 63797 ISA_SET: AVX512F_128 63798 EXCEPTIONS: AVX512-E4 63799 REAL_OPCODE: Y 63800 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63801 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 63802 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 63803 IFORM: VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 63804 } 63805 63806 63807 # EMITTING VPSRAQ (VPSRAQ-256-1) 63808 { 63809 ICLASS: VPSRAQ 63810 CPL: 3 63811 CATEGORY: AVX512 63812 EXTENSION: AVX512EVEX 63813 ISA_SET: AVX512F_256 63814 EXCEPTIONS: AVX512-E4NF 63815 REAL_OPCODE: Y 63816 ATTRIBUTES: MASKOP_EVEX 63817 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 63818 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 63819 IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 63820 } 63821 63822 { 63823 ICLASS: VPSRAQ 63824 CPL: 3 63825 CATEGORY: AVX512 63826 EXTENSION: AVX512EVEX 63827 ISA_SET: AVX512F_256 63828 EXCEPTIONS: AVX512-E4NF 63829 REAL_OPCODE: Y 63830 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 63831 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() 63832 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 63833 IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 63834 } 63835 63836 63837 # EMITTING VPSRAQ (VPSRAQ-256-2) 63838 { 63839 ICLASS: VPSRAQ 63840 CPL: 3 63841 CATEGORY: AVX512 63842 EXTENSION: AVX512EVEX 63843 ISA_SET: AVX512F_256 63844 EXCEPTIONS: AVX512-E4 63845 REAL_OPCODE: Y 63846 ATTRIBUTES: MASKOP_EVEX 63847 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8() 63848 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 63849 IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 63850 } 63851 63852 { 63853 ICLASS: VPSRAQ 63854 CPL: 3 63855 CATEGORY: AVX512 63856 EXTENSION: AVX512EVEX 63857 ISA_SET: AVX512F_256 63858 EXCEPTIONS: AVX512-E4 63859 REAL_OPCODE: Y 63860 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63861 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 63862 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 63863 IFORM: VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 63864 } 63865 63866 63867 # EMITTING VPSRAVD (VPSRAVD-128-1) 63868 { 63869 ICLASS: VPSRAVD 63870 CPL: 3 63871 CATEGORY: AVX512 63872 EXTENSION: AVX512EVEX 63873 ISA_SET: AVX512F_128 63874 EXCEPTIONS: AVX512-E4 63875 REAL_OPCODE: Y 63876 ATTRIBUTES: MASKOP_EVEX 63877 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 63878 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 63879 IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 63880 } 63881 63882 { 63883 ICLASS: VPSRAVD 63884 CPL: 3 63885 CATEGORY: AVX512 63886 EXTENSION: AVX512EVEX 63887 ISA_SET: AVX512F_128 63888 EXCEPTIONS: AVX512-E4 63889 REAL_OPCODE: Y 63890 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63891 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 63892 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 63893 IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 63894 } 63895 63896 63897 # EMITTING VPSRAVD (VPSRAVD-256-1) 63898 { 63899 ICLASS: VPSRAVD 63900 CPL: 3 63901 CATEGORY: AVX512 63902 EXTENSION: AVX512EVEX 63903 ISA_SET: AVX512F_256 63904 EXCEPTIONS: AVX512-E4 63905 REAL_OPCODE: Y 63906 ATTRIBUTES: MASKOP_EVEX 63907 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 63908 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 63909 IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 63910 } 63911 63912 { 63913 ICLASS: VPSRAVD 63914 CPL: 3 63915 CATEGORY: AVX512 63916 EXTENSION: AVX512EVEX 63917 ISA_SET: AVX512F_256 63918 EXCEPTIONS: AVX512-E4 63919 REAL_OPCODE: Y 63920 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63921 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 63922 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 63923 IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 63924 } 63925 63926 63927 # EMITTING VPSRAVQ (VPSRAVQ-128-1) 63928 { 63929 ICLASS: VPSRAVQ 63930 CPL: 3 63931 CATEGORY: AVX512 63932 EXTENSION: AVX512EVEX 63933 ISA_SET: AVX512F_128 63934 EXCEPTIONS: AVX512-E4 63935 REAL_OPCODE: Y 63936 ATTRIBUTES: MASKOP_EVEX 63937 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 63938 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 63939 IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 63940 } 63941 63942 { 63943 ICLASS: VPSRAVQ 63944 CPL: 3 63945 CATEGORY: AVX512 63946 EXTENSION: AVX512EVEX 63947 ISA_SET: AVX512F_128 63948 EXCEPTIONS: AVX512-E4 63949 REAL_OPCODE: Y 63950 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63951 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 63952 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 63953 IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 63954 } 63955 63956 63957 # EMITTING VPSRAVQ (VPSRAVQ-256-1) 63958 { 63959 ICLASS: VPSRAVQ 63960 CPL: 3 63961 CATEGORY: AVX512 63962 EXTENSION: AVX512EVEX 63963 ISA_SET: AVX512F_256 63964 EXCEPTIONS: AVX512-E4 63965 REAL_OPCODE: Y 63966 ATTRIBUTES: MASKOP_EVEX 63967 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 63968 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 63969 IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 63970 } 63971 63972 { 63973 ICLASS: VPSRAVQ 63974 CPL: 3 63975 CATEGORY: AVX512 63976 EXTENSION: AVX512EVEX 63977 ISA_SET: AVX512F_256 63978 EXCEPTIONS: AVX512-E4 63979 REAL_OPCODE: Y 63980 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 63981 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 63982 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 63983 IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 63984 } 63985 63986 63987 # EMITTING VPSRAVW (VPSRAVW-128-1) 63988 { 63989 ICLASS: VPSRAVW 63990 CPL: 3 63991 CATEGORY: AVX512 63992 EXTENSION: AVX512EVEX 63993 ISA_SET: AVX512BW_128 63994 EXCEPTIONS: AVX512-E4 63995 REAL_OPCODE: Y 63996 ATTRIBUTES: MASKOP_EVEX 63997 PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 63998 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 63999 IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 64000 } 64001 64002 { 64003 ICLASS: VPSRAVW 64004 CPL: 3 64005 CATEGORY: AVX512 64006 EXTENSION: AVX512EVEX 64007 ISA_SET: AVX512BW_128 64008 EXCEPTIONS: AVX512-E4 64009 REAL_OPCODE: Y 64010 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64011 PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 64012 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 64013 IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 64014 } 64015 64016 64017 # EMITTING VPSRAVW (VPSRAVW-256-1) 64018 { 64019 ICLASS: VPSRAVW 64020 CPL: 3 64021 CATEGORY: AVX512 64022 EXTENSION: AVX512EVEX 64023 ISA_SET: AVX512BW_256 64024 EXCEPTIONS: AVX512-E4 64025 REAL_OPCODE: Y 64026 ATTRIBUTES: MASKOP_EVEX 64027 PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 64028 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 64029 IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 64030 } 64031 64032 { 64033 ICLASS: VPSRAVW 64034 CPL: 3 64035 CATEGORY: AVX512 64036 EXTENSION: AVX512EVEX 64037 ISA_SET: AVX512BW_256 64038 EXCEPTIONS: AVX512-E4 64039 REAL_OPCODE: Y 64040 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64041 PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 64042 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 64043 IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 64044 } 64045 64046 64047 # EMITTING VPSRAVW (VPSRAVW-512-1) 64048 { 64049 ICLASS: VPSRAVW 64050 CPL: 3 64051 CATEGORY: AVX512 64052 EXTENSION: AVX512EVEX 64053 ISA_SET: AVX512BW_512 64054 EXCEPTIONS: AVX512-E4 64055 REAL_OPCODE: Y 64056 ATTRIBUTES: MASKOP_EVEX 64057 PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 64058 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 64059 IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 64060 } 64061 64062 { 64063 ICLASS: VPSRAVW 64064 CPL: 3 64065 CATEGORY: AVX512 64066 EXTENSION: AVX512EVEX 64067 ISA_SET: AVX512BW_512 64068 EXCEPTIONS: AVX512-E4 64069 REAL_OPCODE: Y 64070 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64071 PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 64072 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 64073 IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 64074 } 64075 64076 64077 # EMITTING VPSRAW (VPSRAW-128-1) 64078 { 64079 ICLASS: VPSRAW 64080 CPL: 3 64081 CATEGORY: AVX512 64082 EXTENSION: AVX512EVEX 64083 ISA_SET: AVX512BW_128 64084 EXCEPTIONS: AVX512-E4NF 64085 REAL_OPCODE: Y 64086 ATTRIBUTES: MASKOP_EVEX 64087 PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 64088 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 64089 IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 64090 } 64091 64092 { 64093 ICLASS: VPSRAW 64094 CPL: 3 64095 CATEGORY: AVX512 64096 EXTENSION: AVX512EVEX 64097 ISA_SET: AVX512BW_128 64098 EXCEPTIONS: AVX512-E4NF 64099 REAL_OPCODE: Y 64100 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 64101 PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() 64102 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 64103 IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 64104 } 64105 64106 64107 # EMITTING VPSRAW (VPSRAW-128-2) 64108 { 64109 ICLASS: VPSRAW 64110 CPL: 3 64111 CATEGORY: AVX512 64112 EXTENSION: AVX512EVEX 64113 ISA_SET: AVX512BW_128 64114 EXCEPTIONS: AVX512-E4 64115 REAL_OPCODE: Y 64116 ATTRIBUTES: MASKOP_EVEX 64117 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8() 64118 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b 64119 IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 64120 } 64121 64122 { 64123 ICLASS: VPSRAW 64124 CPL: 3 64125 CATEGORY: AVX512 64126 EXTENSION: AVX512EVEX 64127 ISA_SET: AVX512BW_128 64128 EXCEPTIONS: AVX512-E4 64129 REAL_OPCODE: Y 64130 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64131 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 64132 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b 64133 IFORM: VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 64134 } 64135 64136 64137 # EMITTING VPSRAW (VPSRAW-256-1) 64138 { 64139 ICLASS: VPSRAW 64140 CPL: 3 64141 CATEGORY: AVX512 64142 EXTENSION: AVX512EVEX 64143 ISA_SET: AVX512BW_256 64144 EXCEPTIONS: AVX512-E4NF 64145 REAL_OPCODE: Y 64146 ATTRIBUTES: MASKOP_EVEX 64147 PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 64148 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 64149 IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 64150 } 64151 64152 { 64153 ICLASS: VPSRAW 64154 CPL: 3 64155 CATEGORY: AVX512 64156 EXTENSION: AVX512EVEX 64157 ISA_SET: AVX512BW_256 64158 EXCEPTIONS: AVX512-E4NF 64159 REAL_OPCODE: Y 64160 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 64161 PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() 64162 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 64163 IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 64164 } 64165 64166 64167 # EMITTING VPSRAW (VPSRAW-256-2) 64168 { 64169 ICLASS: VPSRAW 64170 CPL: 3 64171 CATEGORY: AVX512 64172 EXTENSION: AVX512EVEX 64173 ISA_SET: AVX512BW_256 64174 EXCEPTIONS: AVX512-E4 64175 REAL_OPCODE: Y 64176 ATTRIBUTES: MASKOP_EVEX 64177 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8() 64178 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b 64179 IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 64180 } 64181 64182 { 64183 ICLASS: VPSRAW 64184 CPL: 3 64185 CATEGORY: AVX512 64186 EXTENSION: AVX512EVEX 64187 ISA_SET: AVX512BW_256 64188 EXCEPTIONS: AVX512-E4 64189 REAL_OPCODE: Y 64190 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64191 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 64192 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b 64193 IFORM: VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 64194 } 64195 64196 64197 # EMITTING VPSRAW (VPSRAW-512-1) 64198 { 64199 ICLASS: VPSRAW 64200 CPL: 3 64201 CATEGORY: AVX512 64202 EXTENSION: AVX512EVEX 64203 ISA_SET: AVX512BW_512 64204 EXCEPTIONS: AVX512-E4NF 64205 REAL_OPCODE: Y 64206 ATTRIBUTES: MASKOP_EVEX 64207 PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 64208 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 64209 IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 64210 } 64211 64212 { 64213 ICLASS: VPSRAW 64214 CPL: 3 64215 CATEGORY: AVX512 64216 EXTENSION: AVX512EVEX 64217 ISA_SET: AVX512BW_512 64218 EXCEPTIONS: AVX512-E4NF 64219 REAL_OPCODE: Y 64220 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 64221 PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() 64222 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 64223 IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 64224 } 64225 64226 64227 # EMITTING VPSRAW (VPSRAW-512-2) 64228 { 64229 ICLASS: VPSRAW 64230 CPL: 3 64231 CATEGORY: AVX512 64232 EXTENSION: AVX512EVEX 64233 ISA_SET: AVX512BW_512 64234 EXCEPTIONS: AVX512-E4 64235 REAL_OPCODE: Y 64236 ATTRIBUTES: MASKOP_EVEX 64237 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8() 64238 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b 64239 IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 64240 } 64241 64242 { 64243 ICLASS: VPSRAW 64244 CPL: 3 64245 CATEGORY: AVX512 64246 EXTENSION: AVX512EVEX 64247 ISA_SET: AVX512BW_512 64248 EXCEPTIONS: AVX512-E4 64249 REAL_OPCODE: Y 64250 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64251 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 64252 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b 64253 IFORM: VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 64254 } 64255 64256 64257 # EMITTING VPSRLD (VPSRLD-128-1) 64258 { 64259 ICLASS: VPSRLD 64260 CPL: 3 64261 CATEGORY: AVX512 64262 EXTENSION: AVX512EVEX 64263 ISA_SET: AVX512F_128 64264 EXCEPTIONS: AVX512-E4NF 64265 REAL_OPCODE: Y 64266 ATTRIBUTES: MASKOP_EVEX 64267 PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 64268 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 64269 IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 64270 } 64271 64272 { 64273 ICLASS: VPSRLD 64274 CPL: 3 64275 CATEGORY: AVX512 64276 EXTENSION: AVX512EVEX 64277 ISA_SET: AVX512F_128 64278 EXCEPTIONS: AVX512-E4NF 64279 REAL_OPCODE: Y 64280 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 64281 PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() 64282 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 64283 IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 64284 } 64285 64286 64287 # EMITTING VPSRLD (VPSRLD-128-2) 64288 { 64289 ICLASS: VPSRLD 64290 CPL: 3 64291 CATEGORY: AVX512 64292 EXTENSION: AVX512EVEX 64293 ISA_SET: AVX512F_128 64294 EXCEPTIONS: AVX512-E4 64295 REAL_OPCODE: Y 64296 ATTRIBUTES: MASKOP_EVEX 64297 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8() 64298 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 64299 IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 64300 } 64301 64302 { 64303 ICLASS: VPSRLD 64304 CPL: 3 64305 CATEGORY: AVX512 64306 EXTENSION: AVX512EVEX 64307 ISA_SET: AVX512F_128 64308 EXCEPTIONS: AVX512-E4 64309 REAL_OPCODE: Y 64310 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 64311 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 64312 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 64313 IFORM: VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 64314 } 64315 64316 64317 # EMITTING VPSRLD (VPSRLD-256-1) 64318 { 64319 ICLASS: VPSRLD 64320 CPL: 3 64321 CATEGORY: AVX512 64322 EXTENSION: AVX512EVEX 64323 ISA_SET: AVX512F_256 64324 EXCEPTIONS: AVX512-E4NF 64325 REAL_OPCODE: Y 64326 ATTRIBUTES: MASKOP_EVEX 64327 PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 64328 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 64329 IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 64330 } 64331 64332 { 64333 ICLASS: VPSRLD 64334 CPL: 3 64335 CATEGORY: AVX512 64336 EXTENSION: AVX512EVEX 64337 ISA_SET: AVX512F_256 64338 EXCEPTIONS: AVX512-E4NF 64339 REAL_OPCODE: Y 64340 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 64341 PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() 64342 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 64343 IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 64344 } 64345 64346 64347 # EMITTING VPSRLD (VPSRLD-256-2) 64348 { 64349 ICLASS: VPSRLD 64350 CPL: 3 64351 CATEGORY: AVX512 64352 EXTENSION: AVX512EVEX 64353 ISA_SET: AVX512F_256 64354 EXCEPTIONS: AVX512-E4 64355 REAL_OPCODE: Y 64356 ATTRIBUTES: MASKOP_EVEX 64357 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8() 64358 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 64359 IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 64360 } 64361 64362 { 64363 ICLASS: VPSRLD 64364 CPL: 3 64365 CATEGORY: AVX512 64366 EXTENSION: AVX512EVEX 64367 ISA_SET: AVX512F_256 64368 EXCEPTIONS: AVX512-E4 64369 REAL_OPCODE: Y 64370 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 64371 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 64372 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 64373 IFORM: VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 64374 } 64375 64376 64377 # EMITTING VPSRLDQ (VPSRLDQ-128-1) 64378 { 64379 ICLASS: VPSRLDQ 64380 CPL: 3 64381 CATEGORY: AVX512 64382 EXTENSION: AVX512EVEX 64383 ISA_SET: AVX512BW_128 64384 EXCEPTIONS: AVX512-E4NF 64385 REAL_OPCODE: Y 64386 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() 64387 OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b 64388 IFORM: VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 64389 } 64390 64391 { 64392 ICLASS: VPSRLDQ 64393 CPL: 3 64394 CATEGORY: AVX512 64395 EXTENSION: AVX512EVEX 64396 ISA_SET: AVX512BW_128 64397 EXCEPTIONS: AVX512-E4NF 64398 REAL_OPCODE: Y 64399 ATTRIBUTES: DISP8_FULLMEM 64400 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 64401 OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b 64402 IFORM: VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 64403 } 64404 64405 64406 # EMITTING VPSRLDQ (VPSRLDQ-256-1) 64407 { 64408 ICLASS: VPSRLDQ 64409 CPL: 3 64410 CATEGORY: AVX512 64411 EXTENSION: AVX512EVEX 64412 ISA_SET: AVX512BW_256 64413 EXCEPTIONS: AVX512-E4NF 64414 REAL_OPCODE: Y 64415 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() 64416 OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b 64417 IFORM: VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 64418 } 64419 64420 { 64421 ICLASS: VPSRLDQ 64422 CPL: 3 64423 CATEGORY: AVX512 64424 EXTENSION: AVX512EVEX 64425 ISA_SET: AVX512BW_256 64426 EXCEPTIONS: AVX512-E4NF 64427 REAL_OPCODE: Y 64428 ATTRIBUTES: DISP8_FULLMEM 64429 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 64430 OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b 64431 IFORM: VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 64432 } 64433 64434 64435 # EMITTING VPSRLDQ (VPSRLDQ-512-1) 64436 { 64437 ICLASS: VPSRLDQ 64438 CPL: 3 64439 CATEGORY: AVX512 64440 EXTENSION: AVX512EVEX 64441 ISA_SET: AVX512BW_512 64442 EXCEPTIONS: AVX512-E4NF 64443 REAL_OPCODE: Y 64444 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() 64445 OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b 64446 IFORM: VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 64447 } 64448 64449 { 64450 ICLASS: VPSRLDQ 64451 CPL: 3 64452 CATEGORY: AVX512 64453 EXTENSION: AVX512EVEX 64454 ISA_SET: AVX512BW_512 64455 EXCEPTIONS: AVX512-E4NF 64456 REAL_OPCODE: Y 64457 ATTRIBUTES: DISP8_FULLMEM 64458 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 64459 OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b 64460 IFORM: VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 64461 } 64462 64463 64464 # EMITTING VPSRLQ (VPSRLQ-128-1) 64465 { 64466 ICLASS: VPSRLQ 64467 CPL: 3 64468 CATEGORY: AVX512 64469 EXTENSION: AVX512EVEX 64470 ISA_SET: AVX512F_128 64471 EXCEPTIONS: AVX512-E4NF 64472 REAL_OPCODE: Y 64473 ATTRIBUTES: MASKOP_EVEX 64474 PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 64475 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 64476 IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 64477 } 64478 64479 { 64480 ICLASS: VPSRLQ 64481 CPL: 3 64482 CATEGORY: AVX512 64483 EXTENSION: AVX512EVEX 64484 ISA_SET: AVX512F_128 64485 EXCEPTIONS: AVX512-E4NF 64486 REAL_OPCODE: Y 64487 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 64488 PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() 64489 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 64490 IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 64491 } 64492 64493 64494 # EMITTING VPSRLQ (VPSRLQ-128-2) 64495 { 64496 ICLASS: VPSRLQ 64497 CPL: 3 64498 CATEGORY: AVX512 64499 EXTENSION: AVX512EVEX 64500 ISA_SET: AVX512F_128 64501 EXCEPTIONS: AVX512-E4 64502 REAL_OPCODE: Y 64503 ATTRIBUTES: MASKOP_EVEX 64504 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8() 64505 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b 64506 IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 64507 } 64508 64509 { 64510 ICLASS: VPSRLQ 64511 CPL: 3 64512 CATEGORY: AVX512 64513 EXTENSION: AVX512EVEX 64514 ISA_SET: AVX512F_128 64515 EXCEPTIONS: AVX512-E4 64516 REAL_OPCODE: Y 64517 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 64518 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 64519 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 64520 IFORM: VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 64521 } 64522 64523 64524 # EMITTING VPSRLQ (VPSRLQ-256-1) 64525 { 64526 ICLASS: VPSRLQ 64527 CPL: 3 64528 CATEGORY: AVX512 64529 EXTENSION: AVX512EVEX 64530 ISA_SET: AVX512F_256 64531 EXCEPTIONS: AVX512-E4NF 64532 REAL_OPCODE: Y 64533 ATTRIBUTES: MASKOP_EVEX 64534 PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 64535 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 64536 IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 64537 } 64538 64539 { 64540 ICLASS: VPSRLQ 64541 CPL: 3 64542 CATEGORY: AVX512 64543 EXTENSION: AVX512EVEX 64544 ISA_SET: AVX512F_256 64545 EXCEPTIONS: AVX512-E4NF 64546 REAL_OPCODE: Y 64547 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 64548 PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() 64549 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 64550 IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 64551 } 64552 64553 64554 # EMITTING VPSRLQ (VPSRLQ-256-2) 64555 { 64556 ICLASS: VPSRLQ 64557 CPL: 3 64558 CATEGORY: AVX512 64559 EXTENSION: AVX512EVEX 64560 ISA_SET: AVX512F_256 64561 EXCEPTIONS: AVX512-E4 64562 REAL_OPCODE: Y 64563 ATTRIBUTES: MASKOP_EVEX 64564 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8() 64565 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 64566 IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 64567 } 64568 64569 { 64570 ICLASS: VPSRLQ 64571 CPL: 3 64572 CATEGORY: AVX512 64573 EXTENSION: AVX512EVEX 64574 ISA_SET: AVX512F_256 64575 EXCEPTIONS: AVX512-E4 64576 REAL_OPCODE: Y 64577 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 64578 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 64579 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 64580 IFORM: VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 64581 } 64582 64583 64584 # EMITTING VPSRLVD (VPSRLVD-128-1) 64585 { 64586 ICLASS: VPSRLVD 64587 CPL: 3 64588 CATEGORY: AVX512 64589 EXTENSION: AVX512EVEX 64590 ISA_SET: AVX512F_128 64591 EXCEPTIONS: AVX512-E4 64592 REAL_OPCODE: Y 64593 ATTRIBUTES: MASKOP_EVEX 64594 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 64595 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 64596 IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 64597 } 64598 64599 { 64600 ICLASS: VPSRLVD 64601 CPL: 3 64602 CATEGORY: AVX512 64603 EXTENSION: AVX512EVEX 64604 ISA_SET: AVX512F_128 64605 EXCEPTIONS: AVX512-E4 64606 REAL_OPCODE: Y 64607 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 64608 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 64609 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 64610 IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 64611 } 64612 64613 64614 # EMITTING VPSRLVD (VPSRLVD-256-1) 64615 { 64616 ICLASS: VPSRLVD 64617 CPL: 3 64618 CATEGORY: AVX512 64619 EXTENSION: AVX512EVEX 64620 ISA_SET: AVX512F_256 64621 EXCEPTIONS: AVX512-E4 64622 REAL_OPCODE: Y 64623 ATTRIBUTES: MASKOP_EVEX 64624 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 64625 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 64626 IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 64627 } 64628 64629 { 64630 ICLASS: VPSRLVD 64631 CPL: 3 64632 CATEGORY: AVX512 64633 EXTENSION: AVX512EVEX 64634 ISA_SET: AVX512F_256 64635 EXCEPTIONS: AVX512-E4 64636 REAL_OPCODE: Y 64637 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 64638 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 64639 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 64640 IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 64641 } 64642 64643 64644 # EMITTING VPSRLVQ (VPSRLVQ-128-1) 64645 { 64646 ICLASS: VPSRLVQ 64647 CPL: 3 64648 CATEGORY: AVX512 64649 EXTENSION: AVX512EVEX 64650 ISA_SET: AVX512F_128 64651 EXCEPTIONS: AVX512-E4 64652 REAL_OPCODE: Y 64653 ATTRIBUTES: MASKOP_EVEX 64654 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 64655 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 64656 IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 64657 } 64658 64659 { 64660 ICLASS: VPSRLVQ 64661 CPL: 3 64662 CATEGORY: AVX512 64663 EXTENSION: AVX512EVEX 64664 ISA_SET: AVX512F_128 64665 EXCEPTIONS: AVX512-E4 64666 REAL_OPCODE: Y 64667 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 64668 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 64669 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 64670 IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 64671 } 64672 64673 64674 # EMITTING VPSRLVQ (VPSRLVQ-256-1) 64675 { 64676 ICLASS: VPSRLVQ 64677 CPL: 3 64678 CATEGORY: AVX512 64679 EXTENSION: AVX512EVEX 64680 ISA_SET: AVX512F_256 64681 EXCEPTIONS: AVX512-E4 64682 REAL_OPCODE: Y 64683 ATTRIBUTES: MASKOP_EVEX 64684 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 64685 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 64686 IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 64687 } 64688 64689 { 64690 ICLASS: VPSRLVQ 64691 CPL: 3 64692 CATEGORY: AVX512 64693 EXTENSION: AVX512EVEX 64694 ISA_SET: AVX512F_256 64695 EXCEPTIONS: AVX512-E4 64696 REAL_OPCODE: Y 64697 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 64698 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 64699 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 64700 IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 64701 } 64702 64703 64704 # EMITTING VPSRLVW (VPSRLVW-128-1) 64705 { 64706 ICLASS: VPSRLVW 64707 CPL: 3 64708 CATEGORY: AVX512 64709 EXTENSION: AVX512EVEX 64710 ISA_SET: AVX512BW_128 64711 EXCEPTIONS: AVX512-E4 64712 REAL_OPCODE: Y 64713 ATTRIBUTES: MASKOP_EVEX 64714 PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 64715 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 64716 IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 64717 } 64718 64719 { 64720 ICLASS: VPSRLVW 64721 CPL: 3 64722 CATEGORY: AVX512 64723 EXTENSION: AVX512EVEX 64724 ISA_SET: AVX512BW_128 64725 EXCEPTIONS: AVX512-E4 64726 REAL_OPCODE: Y 64727 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64728 PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 64729 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 64730 IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 64731 } 64732 64733 64734 # EMITTING VPSRLVW (VPSRLVW-256-1) 64735 { 64736 ICLASS: VPSRLVW 64737 CPL: 3 64738 CATEGORY: AVX512 64739 EXTENSION: AVX512EVEX 64740 ISA_SET: AVX512BW_256 64741 EXCEPTIONS: AVX512-E4 64742 REAL_OPCODE: Y 64743 ATTRIBUTES: MASKOP_EVEX 64744 PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 64745 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 64746 IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 64747 } 64748 64749 { 64750 ICLASS: VPSRLVW 64751 CPL: 3 64752 CATEGORY: AVX512 64753 EXTENSION: AVX512EVEX 64754 ISA_SET: AVX512BW_256 64755 EXCEPTIONS: AVX512-E4 64756 REAL_OPCODE: Y 64757 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64758 PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 64759 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 64760 IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 64761 } 64762 64763 64764 # EMITTING VPSRLVW (VPSRLVW-512-1) 64765 { 64766 ICLASS: VPSRLVW 64767 CPL: 3 64768 CATEGORY: AVX512 64769 EXTENSION: AVX512EVEX 64770 ISA_SET: AVX512BW_512 64771 EXCEPTIONS: AVX512-E4 64772 REAL_OPCODE: Y 64773 ATTRIBUTES: MASKOP_EVEX 64774 PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 64775 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 64776 IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 64777 } 64778 64779 { 64780 ICLASS: VPSRLVW 64781 CPL: 3 64782 CATEGORY: AVX512 64783 EXTENSION: AVX512EVEX 64784 ISA_SET: AVX512BW_512 64785 EXCEPTIONS: AVX512-E4 64786 REAL_OPCODE: Y 64787 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64788 PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 64789 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 64790 IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 64791 } 64792 64793 64794 # EMITTING VPSRLW (VPSRLW-128-1) 64795 { 64796 ICLASS: VPSRLW 64797 CPL: 3 64798 CATEGORY: AVX512 64799 EXTENSION: AVX512EVEX 64800 ISA_SET: AVX512BW_128 64801 EXCEPTIONS: AVX512-E4NF 64802 REAL_OPCODE: Y 64803 ATTRIBUTES: MASKOP_EVEX 64804 PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 64805 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 64806 IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 64807 } 64808 64809 { 64810 ICLASS: VPSRLW 64811 CPL: 3 64812 CATEGORY: AVX512 64813 EXTENSION: AVX512EVEX 64814 ISA_SET: AVX512BW_128 64815 EXCEPTIONS: AVX512-E4NF 64816 REAL_OPCODE: Y 64817 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 64818 PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() 64819 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 64820 IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 64821 } 64822 64823 64824 # EMITTING VPSRLW (VPSRLW-128-2) 64825 { 64826 ICLASS: VPSRLW 64827 CPL: 3 64828 CATEGORY: AVX512 64829 EXTENSION: AVX512EVEX 64830 ISA_SET: AVX512BW_128 64831 EXCEPTIONS: AVX512-E4 64832 REAL_OPCODE: Y 64833 ATTRIBUTES: MASKOP_EVEX 64834 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8() 64835 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b 64836 IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 64837 } 64838 64839 { 64840 ICLASS: VPSRLW 64841 CPL: 3 64842 CATEGORY: AVX512 64843 EXTENSION: AVX512EVEX 64844 ISA_SET: AVX512BW_128 64845 EXCEPTIONS: AVX512-E4 64846 REAL_OPCODE: Y 64847 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64848 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 64849 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b 64850 IFORM: VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 64851 } 64852 64853 64854 # EMITTING VPSRLW (VPSRLW-256-1) 64855 { 64856 ICLASS: VPSRLW 64857 CPL: 3 64858 CATEGORY: AVX512 64859 EXTENSION: AVX512EVEX 64860 ISA_SET: AVX512BW_256 64861 EXCEPTIONS: AVX512-E4NF 64862 REAL_OPCODE: Y 64863 ATTRIBUTES: MASKOP_EVEX 64864 PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 64865 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 64866 IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 64867 } 64868 64869 { 64870 ICLASS: VPSRLW 64871 CPL: 3 64872 CATEGORY: AVX512 64873 EXTENSION: AVX512EVEX 64874 ISA_SET: AVX512BW_256 64875 EXCEPTIONS: AVX512-E4NF 64876 REAL_OPCODE: Y 64877 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 64878 PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() 64879 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 64880 IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 64881 } 64882 64883 64884 # EMITTING VPSRLW (VPSRLW-256-2) 64885 { 64886 ICLASS: VPSRLW 64887 CPL: 3 64888 CATEGORY: AVX512 64889 EXTENSION: AVX512EVEX 64890 ISA_SET: AVX512BW_256 64891 EXCEPTIONS: AVX512-E4 64892 REAL_OPCODE: Y 64893 ATTRIBUTES: MASKOP_EVEX 64894 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8() 64895 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b 64896 IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 64897 } 64898 64899 { 64900 ICLASS: VPSRLW 64901 CPL: 3 64902 CATEGORY: AVX512 64903 EXTENSION: AVX512EVEX 64904 ISA_SET: AVX512BW_256 64905 EXCEPTIONS: AVX512-E4 64906 REAL_OPCODE: Y 64907 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64908 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 64909 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b 64910 IFORM: VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 64911 } 64912 64913 64914 # EMITTING VPSRLW (VPSRLW-512-1) 64915 { 64916 ICLASS: VPSRLW 64917 CPL: 3 64918 CATEGORY: AVX512 64919 EXTENSION: AVX512EVEX 64920 ISA_SET: AVX512BW_512 64921 EXCEPTIONS: AVX512-E4NF 64922 REAL_OPCODE: Y 64923 ATTRIBUTES: MASKOP_EVEX 64924 PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 64925 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 64926 IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 64927 } 64928 64929 { 64930 ICLASS: VPSRLW 64931 CPL: 3 64932 CATEGORY: AVX512 64933 EXTENSION: AVX512EVEX 64934 ISA_SET: AVX512BW_512 64935 EXCEPTIONS: AVX512-E4NF 64936 REAL_OPCODE: Y 64937 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 64938 PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() 64939 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 64940 IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 64941 } 64942 64943 64944 # EMITTING VPSRLW (VPSRLW-512-2) 64945 { 64946 ICLASS: VPSRLW 64947 CPL: 3 64948 CATEGORY: AVX512 64949 EXTENSION: AVX512EVEX 64950 ISA_SET: AVX512BW_512 64951 EXCEPTIONS: AVX512-E4 64952 REAL_OPCODE: Y 64953 ATTRIBUTES: MASKOP_EVEX 64954 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8() 64955 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b 64956 IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 64957 } 64958 64959 { 64960 ICLASS: VPSRLW 64961 CPL: 3 64962 CATEGORY: AVX512 64963 EXTENSION: AVX512EVEX 64964 ISA_SET: AVX512BW_512 64965 EXCEPTIONS: AVX512-E4 64966 REAL_OPCODE: Y 64967 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64968 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 64969 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b 64970 IFORM: VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 64971 } 64972 64973 64974 # EMITTING VPSUBB (VPSUBB-128-1) 64975 { 64976 ICLASS: VPSUBB 64977 CPL: 3 64978 CATEGORY: AVX512 64979 EXTENSION: AVX512EVEX 64980 ISA_SET: AVX512BW_128 64981 EXCEPTIONS: AVX512-E4 64982 REAL_OPCODE: Y 64983 ATTRIBUTES: MASKOP_EVEX 64984 PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 64985 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 64986 IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 64987 } 64988 64989 { 64990 ICLASS: VPSUBB 64991 CPL: 3 64992 CATEGORY: AVX512 64993 EXTENSION: AVX512EVEX 64994 ISA_SET: AVX512BW_128 64995 EXCEPTIONS: AVX512-E4 64996 REAL_OPCODE: Y 64997 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 64998 PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 64999 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 65000 IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 65001 } 65002 65003 65004 # EMITTING VPSUBB (VPSUBB-256-1) 65005 { 65006 ICLASS: VPSUBB 65007 CPL: 3 65008 CATEGORY: AVX512 65009 EXTENSION: AVX512EVEX 65010 ISA_SET: AVX512BW_256 65011 EXCEPTIONS: AVX512-E4 65012 REAL_OPCODE: Y 65013 ATTRIBUTES: MASKOP_EVEX 65014 PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 65015 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 65016 IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 65017 } 65018 65019 { 65020 ICLASS: VPSUBB 65021 CPL: 3 65022 CATEGORY: AVX512 65023 EXTENSION: AVX512EVEX 65024 ISA_SET: AVX512BW_256 65025 EXCEPTIONS: AVX512-E4 65026 REAL_OPCODE: Y 65027 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65028 PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 65029 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 65030 IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 65031 } 65032 65033 65034 # EMITTING VPSUBB (VPSUBB-512-1) 65035 { 65036 ICLASS: VPSUBB 65037 CPL: 3 65038 CATEGORY: AVX512 65039 EXTENSION: AVX512EVEX 65040 ISA_SET: AVX512BW_512 65041 EXCEPTIONS: AVX512-E4 65042 REAL_OPCODE: Y 65043 ATTRIBUTES: MASKOP_EVEX 65044 PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 65045 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 65046 IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 65047 } 65048 65049 { 65050 ICLASS: VPSUBB 65051 CPL: 3 65052 CATEGORY: AVX512 65053 EXTENSION: AVX512EVEX 65054 ISA_SET: AVX512BW_512 65055 EXCEPTIONS: AVX512-E4 65056 REAL_OPCODE: Y 65057 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65058 PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 65059 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 65060 IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 65061 } 65062 65063 65064 # EMITTING VPSUBD (VPSUBD-128-1) 65065 { 65066 ICLASS: VPSUBD 65067 CPL: 3 65068 CATEGORY: AVX512 65069 EXTENSION: AVX512EVEX 65070 ISA_SET: AVX512F_128 65071 EXCEPTIONS: AVX512-E4 65072 REAL_OPCODE: Y 65073 ATTRIBUTES: MASKOP_EVEX 65074 PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 65075 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 65076 IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 65077 } 65078 65079 { 65080 ICLASS: VPSUBD 65081 CPL: 3 65082 CATEGORY: AVX512 65083 EXTENSION: AVX512EVEX 65084 ISA_SET: AVX512F_128 65085 EXCEPTIONS: AVX512-E4 65086 REAL_OPCODE: Y 65087 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65088 PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 65089 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 65090 IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 65091 } 65092 65093 65094 # EMITTING VPSUBD (VPSUBD-256-1) 65095 { 65096 ICLASS: VPSUBD 65097 CPL: 3 65098 CATEGORY: AVX512 65099 EXTENSION: AVX512EVEX 65100 ISA_SET: AVX512F_256 65101 EXCEPTIONS: AVX512-E4 65102 REAL_OPCODE: Y 65103 ATTRIBUTES: MASKOP_EVEX 65104 PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 65105 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 65106 IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 65107 } 65108 65109 { 65110 ICLASS: VPSUBD 65111 CPL: 3 65112 CATEGORY: AVX512 65113 EXTENSION: AVX512EVEX 65114 ISA_SET: AVX512F_256 65115 EXCEPTIONS: AVX512-E4 65116 REAL_OPCODE: Y 65117 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65118 PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 65119 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 65120 IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 65121 } 65122 65123 65124 # EMITTING VPSUBQ (VPSUBQ-128-1) 65125 { 65126 ICLASS: VPSUBQ 65127 CPL: 3 65128 CATEGORY: AVX512 65129 EXTENSION: AVX512EVEX 65130 ISA_SET: AVX512F_128 65131 EXCEPTIONS: AVX512-E4 65132 REAL_OPCODE: Y 65133 ATTRIBUTES: MASKOP_EVEX 65134 PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 65135 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 65136 IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 65137 } 65138 65139 { 65140 ICLASS: VPSUBQ 65141 CPL: 3 65142 CATEGORY: AVX512 65143 EXTENSION: AVX512EVEX 65144 ISA_SET: AVX512F_128 65145 EXCEPTIONS: AVX512-E4 65146 REAL_OPCODE: Y 65147 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65148 PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 65149 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 65150 IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 65151 } 65152 65153 65154 # EMITTING VPSUBQ (VPSUBQ-256-1) 65155 { 65156 ICLASS: VPSUBQ 65157 CPL: 3 65158 CATEGORY: AVX512 65159 EXTENSION: AVX512EVEX 65160 ISA_SET: AVX512F_256 65161 EXCEPTIONS: AVX512-E4 65162 REAL_OPCODE: Y 65163 ATTRIBUTES: MASKOP_EVEX 65164 PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 65165 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 65166 IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 65167 } 65168 65169 { 65170 ICLASS: VPSUBQ 65171 CPL: 3 65172 CATEGORY: AVX512 65173 EXTENSION: AVX512EVEX 65174 ISA_SET: AVX512F_256 65175 EXCEPTIONS: AVX512-E4 65176 REAL_OPCODE: Y 65177 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65178 PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 65179 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 65180 IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 65181 } 65182 65183 65184 # EMITTING VPSUBSB (VPSUBSB-128-1) 65185 { 65186 ICLASS: VPSUBSB 65187 CPL: 3 65188 CATEGORY: AVX512 65189 EXTENSION: AVX512EVEX 65190 ISA_SET: AVX512BW_128 65191 EXCEPTIONS: AVX512-E4 65192 REAL_OPCODE: Y 65193 ATTRIBUTES: MASKOP_EVEX 65194 PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 65195 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 65196 IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 65197 } 65198 65199 { 65200 ICLASS: VPSUBSB 65201 CPL: 3 65202 CATEGORY: AVX512 65203 EXTENSION: AVX512EVEX 65204 ISA_SET: AVX512BW_128 65205 EXCEPTIONS: AVX512-E4 65206 REAL_OPCODE: Y 65207 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65208 PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 65209 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 65210 IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 65211 } 65212 65213 65214 # EMITTING VPSUBSB (VPSUBSB-256-1) 65215 { 65216 ICLASS: VPSUBSB 65217 CPL: 3 65218 CATEGORY: AVX512 65219 EXTENSION: AVX512EVEX 65220 ISA_SET: AVX512BW_256 65221 EXCEPTIONS: AVX512-E4 65222 REAL_OPCODE: Y 65223 ATTRIBUTES: MASKOP_EVEX 65224 PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 65225 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 65226 IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 65227 } 65228 65229 { 65230 ICLASS: VPSUBSB 65231 CPL: 3 65232 CATEGORY: AVX512 65233 EXTENSION: AVX512EVEX 65234 ISA_SET: AVX512BW_256 65235 EXCEPTIONS: AVX512-E4 65236 REAL_OPCODE: Y 65237 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65238 PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 65239 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 65240 IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 65241 } 65242 65243 65244 # EMITTING VPSUBSB (VPSUBSB-512-1) 65245 { 65246 ICLASS: VPSUBSB 65247 CPL: 3 65248 CATEGORY: AVX512 65249 EXTENSION: AVX512EVEX 65250 ISA_SET: AVX512BW_512 65251 EXCEPTIONS: AVX512-E4 65252 REAL_OPCODE: Y 65253 ATTRIBUTES: MASKOP_EVEX 65254 PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 65255 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 65256 IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 65257 } 65258 65259 { 65260 ICLASS: VPSUBSB 65261 CPL: 3 65262 CATEGORY: AVX512 65263 EXTENSION: AVX512EVEX 65264 ISA_SET: AVX512BW_512 65265 EXCEPTIONS: AVX512-E4 65266 REAL_OPCODE: Y 65267 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65268 PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 65269 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 65270 IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 65271 } 65272 65273 65274 # EMITTING VPSUBSW (VPSUBSW-128-1) 65275 { 65276 ICLASS: VPSUBSW 65277 CPL: 3 65278 CATEGORY: AVX512 65279 EXTENSION: AVX512EVEX 65280 ISA_SET: AVX512BW_128 65281 EXCEPTIONS: AVX512-E4 65282 REAL_OPCODE: Y 65283 ATTRIBUTES: MASKOP_EVEX 65284 PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 65285 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 65286 IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 65287 } 65288 65289 { 65290 ICLASS: VPSUBSW 65291 CPL: 3 65292 CATEGORY: AVX512 65293 EXTENSION: AVX512EVEX 65294 ISA_SET: AVX512BW_128 65295 EXCEPTIONS: AVX512-E4 65296 REAL_OPCODE: Y 65297 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65298 PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 65299 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 65300 IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 65301 } 65302 65303 65304 # EMITTING VPSUBSW (VPSUBSW-256-1) 65305 { 65306 ICLASS: VPSUBSW 65307 CPL: 3 65308 CATEGORY: AVX512 65309 EXTENSION: AVX512EVEX 65310 ISA_SET: AVX512BW_256 65311 EXCEPTIONS: AVX512-E4 65312 REAL_OPCODE: Y 65313 ATTRIBUTES: MASKOP_EVEX 65314 PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 65315 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 65316 IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 65317 } 65318 65319 { 65320 ICLASS: VPSUBSW 65321 CPL: 3 65322 CATEGORY: AVX512 65323 EXTENSION: AVX512EVEX 65324 ISA_SET: AVX512BW_256 65325 EXCEPTIONS: AVX512-E4 65326 REAL_OPCODE: Y 65327 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65328 PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 65329 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 65330 IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 65331 } 65332 65333 65334 # EMITTING VPSUBSW (VPSUBSW-512-1) 65335 { 65336 ICLASS: VPSUBSW 65337 CPL: 3 65338 CATEGORY: AVX512 65339 EXTENSION: AVX512EVEX 65340 ISA_SET: AVX512BW_512 65341 EXCEPTIONS: AVX512-E4 65342 REAL_OPCODE: Y 65343 ATTRIBUTES: MASKOP_EVEX 65344 PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 65345 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 65346 IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 65347 } 65348 65349 { 65350 ICLASS: VPSUBSW 65351 CPL: 3 65352 CATEGORY: AVX512 65353 EXTENSION: AVX512EVEX 65354 ISA_SET: AVX512BW_512 65355 EXCEPTIONS: AVX512-E4 65356 REAL_OPCODE: Y 65357 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65358 PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 65359 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 65360 IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 65361 } 65362 65363 65364 # EMITTING VPSUBUSB (VPSUBUSB-128-1) 65365 { 65366 ICLASS: VPSUBUSB 65367 CPL: 3 65368 CATEGORY: AVX512 65369 EXTENSION: AVX512EVEX 65370 ISA_SET: AVX512BW_128 65371 EXCEPTIONS: AVX512-E4 65372 REAL_OPCODE: Y 65373 ATTRIBUTES: MASKOP_EVEX 65374 PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 65375 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 65376 IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 65377 } 65378 65379 { 65380 ICLASS: VPSUBUSB 65381 CPL: 3 65382 CATEGORY: AVX512 65383 EXTENSION: AVX512EVEX 65384 ISA_SET: AVX512BW_128 65385 EXCEPTIONS: AVX512-E4 65386 REAL_OPCODE: Y 65387 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65388 PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 65389 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 65390 IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 65391 } 65392 65393 65394 # EMITTING VPSUBUSB (VPSUBUSB-256-1) 65395 { 65396 ICLASS: VPSUBUSB 65397 CPL: 3 65398 CATEGORY: AVX512 65399 EXTENSION: AVX512EVEX 65400 ISA_SET: AVX512BW_256 65401 EXCEPTIONS: AVX512-E4 65402 REAL_OPCODE: Y 65403 ATTRIBUTES: MASKOP_EVEX 65404 PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 65405 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 65406 IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 65407 } 65408 65409 { 65410 ICLASS: VPSUBUSB 65411 CPL: 3 65412 CATEGORY: AVX512 65413 EXTENSION: AVX512EVEX 65414 ISA_SET: AVX512BW_256 65415 EXCEPTIONS: AVX512-E4 65416 REAL_OPCODE: Y 65417 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65418 PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 65419 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 65420 IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 65421 } 65422 65423 65424 # EMITTING VPSUBUSB (VPSUBUSB-512-1) 65425 { 65426 ICLASS: VPSUBUSB 65427 CPL: 3 65428 CATEGORY: AVX512 65429 EXTENSION: AVX512EVEX 65430 ISA_SET: AVX512BW_512 65431 EXCEPTIONS: AVX512-E4 65432 REAL_OPCODE: Y 65433 ATTRIBUTES: MASKOP_EVEX 65434 PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 65435 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 65436 IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 65437 } 65438 65439 { 65440 ICLASS: VPSUBUSB 65441 CPL: 3 65442 CATEGORY: AVX512 65443 EXTENSION: AVX512EVEX 65444 ISA_SET: AVX512BW_512 65445 EXCEPTIONS: AVX512-E4 65446 REAL_OPCODE: Y 65447 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65448 PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 65449 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 65450 IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 65451 } 65452 65453 65454 # EMITTING VPSUBUSW (VPSUBUSW-128-1) 65455 { 65456 ICLASS: VPSUBUSW 65457 CPL: 3 65458 CATEGORY: AVX512 65459 EXTENSION: AVX512EVEX 65460 ISA_SET: AVX512BW_128 65461 EXCEPTIONS: AVX512-E4 65462 REAL_OPCODE: Y 65463 ATTRIBUTES: MASKOP_EVEX 65464 PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 65465 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 65466 IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 65467 } 65468 65469 { 65470 ICLASS: VPSUBUSW 65471 CPL: 3 65472 CATEGORY: AVX512 65473 EXTENSION: AVX512EVEX 65474 ISA_SET: AVX512BW_128 65475 EXCEPTIONS: AVX512-E4 65476 REAL_OPCODE: Y 65477 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65478 PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 65479 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 65480 IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 65481 } 65482 65483 65484 # EMITTING VPSUBUSW (VPSUBUSW-256-1) 65485 { 65486 ICLASS: VPSUBUSW 65487 CPL: 3 65488 CATEGORY: AVX512 65489 EXTENSION: AVX512EVEX 65490 ISA_SET: AVX512BW_256 65491 EXCEPTIONS: AVX512-E4 65492 REAL_OPCODE: Y 65493 ATTRIBUTES: MASKOP_EVEX 65494 PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 65495 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 65496 IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 65497 } 65498 65499 { 65500 ICLASS: VPSUBUSW 65501 CPL: 3 65502 CATEGORY: AVX512 65503 EXTENSION: AVX512EVEX 65504 ISA_SET: AVX512BW_256 65505 EXCEPTIONS: AVX512-E4 65506 REAL_OPCODE: Y 65507 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65508 PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 65509 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 65510 IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 65511 } 65512 65513 65514 # EMITTING VPSUBUSW (VPSUBUSW-512-1) 65515 { 65516 ICLASS: VPSUBUSW 65517 CPL: 3 65518 CATEGORY: AVX512 65519 EXTENSION: AVX512EVEX 65520 ISA_SET: AVX512BW_512 65521 EXCEPTIONS: AVX512-E4 65522 REAL_OPCODE: Y 65523 ATTRIBUTES: MASKOP_EVEX 65524 PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 65525 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 65526 IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 65527 } 65528 65529 { 65530 ICLASS: VPSUBUSW 65531 CPL: 3 65532 CATEGORY: AVX512 65533 EXTENSION: AVX512EVEX 65534 ISA_SET: AVX512BW_512 65535 EXCEPTIONS: AVX512-E4 65536 REAL_OPCODE: Y 65537 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65538 PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 65539 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 65540 IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 65541 } 65542 65543 65544 # EMITTING VPSUBW (VPSUBW-128-1) 65545 { 65546 ICLASS: VPSUBW 65547 CPL: 3 65548 CATEGORY: AVX512 65549 EXTENSION: AVX512EVEX 65550 ISA_SET: AVX512BW_128 65551 EXCEPTIONS: AVX512-E4 65552 REAL_OPCODE: Y 65553 ATTRIBUTES: MASKOP_EVEX 65554 PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 65555 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 65556 IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 65557 } 65558 65559 { 65560 ICLASS: VPSUBW 65561 CPL: 3 65562 CATEGORY: AVX512 65563 EXTENSION: AVX512EVEX 65564 ISA_SET: AVX512BW_128 65565 EXCEPTIONS: AVX512-E4 65566 REAL_OPCODE: Y 65567 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65568 PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 65569 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 65570 IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 65571 } 65572 65573 65574 # EMITTING VPSUBW (VPSUBW-256-1) 65575 { 65576 ICLASS: VPSUBW 65577 CPL: 3 65578 CATEGORY: AVX512 65579 EXTENSION: AVX512EVEX 65580 ISA_SET: AVX512BW_256 65581 EXCEPTIONS: AVX512-E4 65582 REAL_OPCODE: Y 65583 ATTRIBUTES: MASKOP_EVEX 65584 PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 65585 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 65586 IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 65587 } 65588 65589 { 65590 ICLASS: VPSUBW 65591 CPL: 3 65592 CATEGORY: AVX512 65593 EXTENSION: AVX512EVEX 65594 ISA_SET: AVX512BW_256 65595 EXCEPTIONS: AVX512-E4 65596 REAL_OPCODE: Y 65597 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65598 PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 65599 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 65600 IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 65601 } 65602 65603 65604 # EMITTING VPSUBW (VPSUBW-512-1) 65605 { 65606 ICLASS: VPSUBW 65607 CPL: 3 65608 CATEGORY: AVX512 65609 EXTENSION: AVX512EVEX 65610 ISA_SET: AVX512BW_512 65611 EXCEPTIONS: AVX512-E4 65612 REAL_OPCODE: Y 65613 ATTRIBUTES: MASKOP_EVEX 65614 PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 65615 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 65616 IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 65617 } 65618 65619 { 65620 ICLASS: VPSUBW 65621 CPL: 3 65622 CATEGORY: AVX512 65623 EXTENSION: AVX512EVEX 65624 ISA_SET: AVX512BW_512 65625 EXCEPTIONS: AVX512-E4 65626 REAL_OPCODE: Y 65627 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65628 PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 65629 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 65630 IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 65631 } 65632 65633 65634 # EMITTING VPTERNLOGD (VPTERNLOGD-128-1) 65635 { 65636 ICLASS: VPTERNLOGD 65637 CPL: 3 65638 CATEGORY: LOGICAL 65639 EXTENSION: AVX512EVEX 65640 ISA_SET: AVX512F_128 65641 EXCEPTIONS: AVX512-E4 65642 REAL_OPCODE: Y 65643 ATTRIBUTES: MASKOP_EVEX 65644 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 65645 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 65646 IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 65647 } 65648 65649 { 65650 ICLASS: VPTERNLOGD 65651 CPL: 3 65652 CATEGORY: LOGICAL 65653 EXTENSION: AVX512EVEX 65654 ISA_SET: AVX512F_128 65655 EXCEPTIONS: AVX512-E4 65656 REAL_OPCODE: Y 65657 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65658 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 65659 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 65660 IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 65661 } 65662 65663 65664 # EMITTING VPTERNLOGD (VPTERNLOGD-256-1) 65665 { 65666 ICLASS: VPTERNLOGD 65667 CPL: 3 65668 CATEGORY: LOGICAL 65669 EXTENSION: AVX512EVEX 65670 ISA_SET: AVX512F_256 65671 EXCEPTIONS: AVX512-E4 65672 REAL_OPCODE: Y 65673 ATTRIBUTES: MASKOP_EVEX 65674 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 65675 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 65676 IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 65677 } 65678 65679 { 65680 ICLASS: VPTERNLOGD 65681 CPL: 3 65682 CATEGORY: LOGICAL 65683 EXTENSION: AVX512EVEX 65684 ISA_SET: AVX512F_256 65685 EXCEPTIONS: AVX512-E4 65686 REAL_OPCODE: Y 65687 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65688 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 65689 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 65690 IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 65691 } 65692 65693 65694 # EMITTING VPTERNLOGQ (VPTERNLOGQ-128-1) 65695 { 65696 ICLASS: VPTERNLOGQ 65697 CPL: 3 65698 CATEGORY: LOGICAL 65699 EXTENSION: AVX512EVEX 65700 ISA_SET: AVX512F_128 65701 EXCEPTIONS: AVX512-E4 65702 REAL_OPCODE: Y 65703 ATTRIBUTES: MASKOP_EVEX 65704 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 65705 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 65706 IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 65707 } 65708 65709 { 65710 ICLASS: VPTERNLOGQ 65711 CPL: 3 65712 CATEGORY: LOGICAL 65713 EXTENSION: AVX512EVEX 65714 ISA_SET: AVX512F_128 65715 EXCEPTIONS: AVX512-E4 65716 REAL_OPCODE: Y 65717 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65718 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 65719 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 65720 IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 65721 } 65722 65723 65724 # EMITTING VPTERNLOGQ (VPTERNLOGQ-256-1) 65725 { 65726 ICLASS: VPTERNLOGQ 65727 CPL: 3 65728 CATEGORY: LOGICAL 65729 EXTENSION: AVX512EVEX 65730 ISA_SET: AVX512F_256 65731 EXCEPTIONS: AVX512-E4 65732 REAL_OPCODE: Y 65733 ATTRIBUTES: MASKOP_EVEX 65734 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 65735 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 65736 IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 65737 } 65738 65739 { 65740 ICLASS: VPTERNLOGQ 65741 CPL: 3 65742 CATEGORY: LOGICAL 65743 EXTENSION: AVX512EVEX 65744 ISA_SET: AVX512F_256 65745 EXCEPTIONS: AVX512-E4 65746 REAL_OPCODE: Y 65747 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65748 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 65749 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 65750 IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 65751 } 65752 65753 65754 # EMITTING VPTESTMB (VPTESTMB-128-1) 65755 { 65756 ICLASS: VPTESTMB 65757 CPL: 3 65758 CATEGORY: LOGICAL 65759 EXTENSION: AVX512EVEX 65760 ISA_SET: AVX512BW_128 65761 EXCEPTIONS: AVX512-E4 65762 REAL_OPCODE: Y 65763 ATTRIBUTES: MASKOP_EVEX 65764 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 65765 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 65766 IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 65767 } 65768 65769 { 65770 ICLASS: VPTESTMB 65771 CPL: 3 65772 CATEGORY: LOGICAL 65773 EXTENSION: AVX512EVEX 65774 ISA_SET: AVX512BW_128 65775 EXCEPTIONS: AVX512-E4 65776 REAL_OPCODE: Y 65777 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65778 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 65779 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 65780 IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 65781 } 65782 65783 65784 # EMITTING VPTESTMB (VPTESTMB-256-1) 65785 { 65786 ICLASS: VPTESTMB 65787 CPL: 3 65788 CATEGORY: LOGICAL 65789 EXTENSION: AVX512EVEX 65790 ISA_SET: AVX512BW_256 65791 EXCEPTIONS: AVX512-E4 65792 REAL_OPCODE: Y 65793 ATTRIBUTES: MASKOP_EVEX 65794 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 65795 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 65796 IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 65797 } 65798 65799 { 65800 ICLASS: VPTESTMB 65801 CPL: 3 65802 CATEGORY: LOGICAL 65803 EXTENSION: AVX512EVEX 65804 ISA_SET: AVX512BW_256 65805 EXCEPTIONS: AVX512-E4 65806 REAL_OPCODE: Y 65807 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65808 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 65809 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 65810 IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 65811 } 65812 65813 65814 # EMITTING VPTESTMB (VPTESTMB-512-1) 65815 { 65816 ICLASS: VPTESTMB 65817 CPL: 3 65818 CATEGORY: LOGICAL 65819 EXTENSION: AVX512EVEX 65820 ISA_SET: AVX512BW_512 65821 EXCEPTIONS: AVX512-E4 65822 REAL_OPCODE: Y 65823 ATTRIBUTES: MASKOP_EVEX 65824 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 65825 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 65826 IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 65827 } 65828 65829 { 65830 ICLASS: VPTESTMB 65831 CPL: 3 65832 CATEGORY: LOGICAL 65833 EXTENSION: AVX512EVEX 65834 ISA_SET: AVX512BW_512 65835 EXCEPTIONS: AVX512-E4 65836 REAL_OPCODE: Y 65837 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65838 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 65839 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 65840 IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 65841 } 65842 65843 65844 # EMITTING VPTESTMD (VPTESTMD-128-1) 65845 { 65846 ICLASS: VPTESTMD 65847 CPL: 3 65848 CATEGORY: LOGICAL 65849 EXTENSION: AVX512EVEX 65850 ISA_SET: AVX512F_128 65851 EXCEPTIONS: AVX512-E4 65852 REAL_OPCODE: Y 65853 ATTRIBUTES: MASKOP_EVEX 65854 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 65855 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 65856 IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 65857 } 65858 65859 { 65860 ICLASS: VPTESTMD 65861 CPL: 3 65862 CATEGORY: LOGICAL 65863 EXTENSION: AVX512EVEX 65864 ISA_SET: AVX512F_128 65865 EXCEPTIONS: AVX512-E4 65866 REAL_OPCODE: Y 65867 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65868 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 65869 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 65870 IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 65871 } 65872 65873 65874 # EMITTING VPTESTMD (VPTESTMD-256-1) 65875 { 65876 ICLASS: VPTESTMD 65877 CPL: 3 65878 CATEGORY: LOGICAL 65879 EXTENSION: AVX512EVEX 65880 ISA_SET: AVX512F_256 65881 EXCEPTIONS: AVX512-E4 65882 REAL_OPCODE: Y 65883 ATTRIBUTES: MASKOP_EVEX 65884 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 65885 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 65886 IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 65887 } 65888 65889 { 65890 ICLASS: VPTESTMD 65891 CPL: 3 65892 CATEGORY: LOGICAL 65893 EXTENSION: AVX512EVEX 65894 ISA_SET: AVX512F_256 65895 EXCEPTIONS: AVX512-E4 65896 REAL_OPCODE: Y 65897 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65898 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 65899 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 65900 IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 65901 } 65902 65903 65904 # EMITTING VPTESTMQ (VPTESTMQ-128-1) 65905 { 65906 ICLASS: VPTESTMQ 65907 CPL: 3 65908 CATEGORY: LOGICAL 65909 EXTENSION: AVX512EVEX 65910 ISA_SET: AVX512F_128 65911 EXCEPTIONS: AVX512-E4 65912 REAL_OPCODE: Y 65913 ATTRIBUTES: MASKOP_EVEX 65914 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 65915 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 65916 IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 65917 } 65918 65919 { 65920 ICLASS: VPTESTMQ 65921 CPL: 3 65922 CATEGORY: LOGICAL 65923 EXTENSION: AVX512EVEX 65924 ISA_SET: AVX512F_128 65925 EXCEPTIONS: AVX512-E4 65926 REAL_OPCODE: Y 65927 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65928 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 65929 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 65930 IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 65931 } 65932 65933 65934 # EMITTING VPTESTMQ (VPTESTMQ-256-1) 65935 { 65936 ICLASS: VPTESTMQ 65937 CPL: 3 65938 CATEGORY: LOGICAL 65939 EXTENSION: AVX512EVEX 65940 ISA_SET: AVX512F_256 65941 EXCEPTIONS: AVX512-E4 65942 REAL_OPCODE: Y 65943 ATTRIBUTES: MASKOP_EVEX 65944 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 65945 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 65946 IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 65947 } 65948 65949 { 65950 ICLASS: VPTESTMQ 65951 CPL: 3 65952 CATEGORY: LOGICAL 65953 EXTENSION: AVX512EVEX 65954 ISA_SET: AVX512F_256 65955 EXCEPTIONS: AVX512-E4 65956 REAL_OPCODE: Y 65957 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 65958 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 65959 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 65960 IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 65961 } 65962 65963 65964 # EMITTING VPTESTMW (VPTESTMW-128-1) 65965 { 65966 ICLASS: VPTESTMW 65967 CPL: 3 65968 CATEGORY: LOGICAL 65969 EXTENSION: AVX512EVEX 65970 ISA_SET: AVX512BW_128 65971 EXCEPTIONS: AVX512-E4 65972 REAL_OPCODE: Y 65973 ATTRIBUTES: MASKOP_EVEX 65974 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 65975 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 65976 IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 65977 } 65978 65979 { 65980 ICLASS: VPTESTMW 65981 CPL: 3 65982 CATEGORY: LOGICAL 65983 EXTENSION: AVX512EVEX 65984 ISA_SET: AVX512BW_128 65985 EXCEPTIONS: AVX512-E4 65986 REAL_OPCODE: Y 65987 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 65988 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 65989 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 65990 IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 65991 } 65992 65993 65994 # EMITTING VPTESTMW (VPTESTMW-256-1) 65995 { 65996 ICLASS: VPTESTMW 65997 CPL: 3 65998 CATEGORY: LOGICAL 65999 EXTENSION: AVX512EVEX 66000 ISA_SET: AVX512BW_256 66001 EXCEPTIONS: AVX512-E4 66002 REAL_OPCODE: Y 66003 ATTRIBUTES: MASKOP_EVEX 66004 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 66005 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 66006 IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 66007 } 66008 66009 { 66010 ICLASS: VPTESTMW 66011 CPL: 3 66012 CATEGORY: LOGICAL 66013 EXTENSION: AVX512EVEX 66014 ISA_SET: AVX512BW_256 66015 EXCEPTIONS: AVX512-E4 66016 REAL_OPCODE: Y 66017 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 66018 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 66019 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 66020 IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 66021 } 66022 66023 66024 # EMITTING VPTESTMW (VPTESTMW-512-1) 66025 { 66026 ICLASS: VPTESTMW 66027 CPL: 3 66028 CATEGORY: LOGICAL 66029 EXTENSION: AVX512EVEX 66030 ISA_SET: AVX512BW_512 66031 EXCEPTIONS: AVX512-E4 66032 REAL_OPCODE: Y 66033 ATTRIBUTES: MASKOP_EVEX 66034 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 66035 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 66036 IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 66037 } 66038 66039 { 66040 ICLASS: VPTESTMW 66041 CPL: 3 66042 CATEGORY: LOGICAL 66043 EXTENSION: AVX512EVEX 66044 ISA_SET: AVX512BW_512 66045 EXCEPTIONS: AVX512-E4 66046 REAL_OPCODE: Y 66047 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 66048 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 66049 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 66050 IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 66051 } 66052 66053 66054 # EMITTING VPTESTNMB (VPTESTNMB-128-1) 66055 { 66056 ICLASS: VPTESTNMB 66057 CPL: 3 66058 CATEGORY: LOGICAL 66059 EXTENSION: AVX512EVEX 66060 ISA_SET: AVX512BW_128 66061 EXCEPTIONS: AVX512-E4 66062 REAL_OPCODE: Y 66063 ATTRIBUTES: MASKOP_EVEX 66064 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 66065 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 66066 IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 66067 } 66068 66069 { 66070 ICLASS: VPTESTNMB 66071 CPL: 3 66072 CATEGORY: LOGICAL 66073 EXTENSION: AVX512EVEX 66074 ISA_SET: AVX512BW_128 66075 EXCEPTIONS: AVX512-E4 66076 REAL_OPCODE: Y 66077 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 66078 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 66079 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 66080 IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 66081 } 66082 66083 66084 # EMITTING VPTESTNMB (VPTESTNMB-256-1) 66085 { 66086 ICLASS: VPTESTNMB 66087 CPL: 3 66088 CATEGORY: LOGICAL 66089 EXTENSION: AVX512EVEX 66090 ISA_SET: AVX512BW_256 66091 EXCEPTIONS: AVX512-E4 66092 REAL_OPCODE: Y 66093 ATTRIBUTES: MASKOP_EVEX 66094 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 66095 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 66096 IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 66097 } 66098 66099 { 66100 ICLASS: VPTESTNMB 66101 CPL: 3 66102 CATEGORY: LOGICAL 66103 EXTENSION: AVX512EVEX 66104 ISA_SET: AVX512BW_256 66105 EXCEPTIONS: AVX512-E4 66106 REAL_OPCODE: Y 66107 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 66108 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 66109 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 66110 IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 66111 } 66112 66113 66114 # EMITTING VPTESTNMB (VPTESTNMB-512-1) 66115 { 66116 ICLASS: VPTESTNMB 66117 CPL: 3 66118 CATEGORY: LOGICAL 66119 EXTENSION: AVX512EVEX 66120 ISA_SET: AVX512BW_512 66121 EXCEPTIONS: AVX512-E4 66122 REAL_OPCODE: Y 66123 ATTRIBUTES: MASKOP_EVEX 66124 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 66125 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 66126 IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 66127 } 66128 66129 { 66130 ICLASS: VPTESTNMB 66131 CPL: 3 66132 CATEGORY: LOGICAL 66133 EXTENSION: AVX512EVEX 66134 ISA_SET: AVX512BW_512 66135 EXCEPTIONS: AVX512-E4 66136 REAL_OPCODE: Y 66137 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 66138 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 66139 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 66140 IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 66141 } 66142 66143 66144 # EMITTING VPTESTNMD (VPTESTNMD-128-1) 66145 { 66146 ICLASS: VPTESTNMD 66147 CPL: 3 66148 CATEGORY: LOGICAL 66149 EXTENSION: AVX512EVEX 66150 ISA_SET: AVX512F_128 66151 EXCEPTIONS: AVX512-E4 66152 REAL_OPCODE: Y 66153 ATTRIBUTES: MASKOP_EVEX 66154 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 66155 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 66156 IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 66157 } 66158 66159 { 66160 ICLASS: VPTESTNMD 66161 CPL: 3 66162 CATEGORY: LOGICAL 66163 EXTENSION: AVX512EVEX 66164 ISA_SET: AVX512F_128 66165 EXCEPTIONS: AVX512-E4 66166 REAL_OPCODE: Y 66167 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66168 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 66169 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 66170 IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 66171 } 66172 66173 66174 # EMITTING VPTESTNMD (VPTESTNMD-256-1) 66175 { 66176 ICLASS: VPTESTNMD 66177 CPL: 3 66178 CATEGORY: LOGICAL 66179 EXTENSION: AVX512EVEX 66180 ISA_SET: AVX512F_256 66181 EXCEPTIONS: AVX512-E4 66182 REAL_OPCODE: Y 66183 ATTRIBUTES: MASKOP_EVEX 66184 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 66185 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 66186 IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 66187 } 66188 66189 { 66190 ICLASS: VPTESTNMD 66191 CPL: 3 66192 CATEGORY: LOGICAL 66193 EXTENSION: AVX512EVEX 66194 ISA_SET: AVX512F_256 66195 EXCEPTIONS: AVX512-E4 66196 REAL_OPCODE: Y 66197 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66198 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 66199 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 66200 IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 66201 } 66202 66203 66204 # EMITTING VPTESTNMQ (VPTESTNMQ-128-1) 66205 { 66206 ICLASS: VPTESTNMQ 66207 CPL: 3 66208 CATEGORY: LOGICAL 66209 EXTENSION: AVX512EVEX 66210 ISA_SET: AVX512F_128 66211 EXCEPTIONS: AVX512-E4 66212 REAL_OPCODE: Y 66213 ATTRIBUTES: MASKOP_EVEX 66214 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 66215 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 66216 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 66217 } 66218 66219 { 66220 ICLASS: VPTESTNMQ 66221 CPL: 3 66222 CATEGORY: LOGICAL 66223 EXTENSION: AVX512EVEX 66224 ISA_SET: AVX512F_128 66225 EXCEPTIONS: AVX512-E4 66226 REAL_OPCODE: Y 66227 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66228 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 66229 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 66230 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 66231 } 66232 66233 66234 # EMITTING VPTESTNMQ (VPTESTNMQ-256-1) 66235 { 66236 ICLASS: VPTESTNMQ 66237 CPL: 3 66238 CATEGORY: LOGICAL 66239 EXTENSION: AVX512EVEX 66240 ISA_SET: AVX512F_256 66241 EXCEPTIONS: AVX512-E4 66242 REAL_OPCODE: Y 66243 ATTRIBUTES: MASKOP_EVEX 66244 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 66245 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 66246 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 66247 } 66248 66249 { 66250 ICLASS: VPTESTNMQ 66251 CPL: 3 66252 CATEGORY: LOGICAL 66253 EXTENSION: AVX512EVEX 66254 ISA_SET: AVX512F_256 66255 EXCEPTIONS: AVX512-E4 66256 REAL_OPCODE: Y 66257 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66258 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 66259 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 66260 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 66261 } 66262 66263 66264 # EMITTING VPTESTNMW (VPTESTNMW-128-1) 66265 { 66266 ICLASS: VPTESTNMW 66267 CPL: 3 66268 CATEGORY: LOGICAL 66269 EXTENSION: AVX512EVEX 66270 ISA_SET: AVX512BW_128 66271 EXCEPTIONS: AVX512-E4 66272 REAL_OPCODE: Y 66273 ATTRIBUTES: MASKOP_EVEX 66274 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 66275 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 66276 IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 66277 } 66278 66279 { 66280 ICLASS: VPTESTNMW 66281 CPL: 3 66282 CATEGORY: LOGICAL 66283 EXTENSION: AVX512EVEX 66284 ISA_SET: AVX512BW_128 66285 EXCEPTIONS: AVX512-E4 66286 REAL_OPCODE: Y 66287 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 66288 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 66289 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 66290 IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 66291 } 66292 66293 66294 # EMITTING VPTESTNMW (VPTESTNMW-256-1) 66295 { 66296 ICLASS: VPTESTNMW 66297 CPL: 3 66298 CATEGORY: LOGICAL 66299 EXTENSION: AVX512EVEX 66300 ISA_SET: AVX512BW_256 66301 EXCEPTIONS: AVX512-E4 66302 REAL_OPCODE: Y 66303 ATTRIBUTES: MASKOP_EVEX 66304 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 66305 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 66306 IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 66307 } 66308 66309 { 66310 ICLASS: VPTESTNMW 66311 CPL: 3 66312 CATEGORY: LOGICAL 66313 EXTENSION: AVX512EVEX 66314 ISA_SET: AVX512BW_256 66315 EXCEPTIONS: AVX512-E4 66316 REAL_OPCODE: Y 66317 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 66318 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 66319 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 66320 IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 66321 } 66322 66323 66324 # EMITTING VPTESTNMW (VPTESTNMW-512-1) 66325 { 66326 ICLASS: VPTESTNMW 66327 CPL: 3 66328 CATEGORY: LOGICAL 66329 EXTENSION: AVX512EVEX 66330 ISA_SET: AVX512BW_512 66331 EXCEPTIONS: AVX512-E4 66332 REAL_OPCODE: Y 66333 ATTRIBUTES: MASKOP_EVEX 66334 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 66335 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 66336 IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 66337 } 66338 66339 { 66340 ICLASS: VPTESTNMW 66341 CPL: 3 66342 CATEGORY: LOGICAL 66343 EXTENSION: AVX512EVEX 66344 ISA_SET: AVX512BW_512 66345 EXCEPTIONS: AVX512-E4 66346 REAL_OPCODE: Y 66347 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 66348 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 66349 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 66350 IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 66351 } 66352 66353 66354 # EMITTING VPUNPCKHBW (VPUNPCKHBW-128-1) 66355 { 66356 ICLASS: VPUNPCKHBW 66357 CPL: 3 66358 CATEGORY: AVX512 66359 EXTENSION: AVX512EVEX 66360 ISA_SET: AVX512BW_128 66361 EXCEPTIONS: AVX512-E4NF 66362 REAL_OPCODE: Y 66363 ATTRIBUTES: MASKOP_EVEX 66364 PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 66365 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 66366 IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 66367 } 66368 66369 { 66370 ICLASS: VPUNPCKHBW 66371 CPL: 3 66372 CATEGORY: AVX512 66373 EXTENSION: AVX512EVEX 66374 ISA_SET: AVX512BW_128 66375 EXCEPTIONS: AVX512-E4NF 66376 REAL_OPCODE: Y 66377 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66378 PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 66379 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 66380 IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 66381 } 66382 66383 66384 # EMITTING VPUNPCKHBW (VPUNPCKHBW-256-1) 66385 { 66386 ICLASS: VPUNPCKHBW 66387 CPL: 3 66388 CATEGORY: AVX512 66389 EXTENSION: AVX512EVEX 66390 ISA_SET: AVX512BW_256 66391 EXCEPTIONS: AVX512-E4NF 66392 REAL_OPCODE: Y 66393 ATTRIBUTES: MASKOP_EVEX 66394 PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 66395 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 66396 IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 66397 } 66398 66399 { 66400 ICLASS: VPUNPCKHBW 66401 CPL: 3 66402 CATEGORY: AVX512 66403 EXTENSION: AVX512EVEX 66404 ISA_SET: AVX512BW_256 66405 EXCEPTIONS: AVX512-E4NF 66406 REAL_OPCODE: Y 66407 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66408 PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 66409 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 66410 IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 66411 } 66412 66413 66414 # EMITTING VPUNPCKHBW (VPUNPCKHBW-512-1) 66415 { 66416 ICLASS: VPUNPCKHBW 66417 CPL: 3 66418 CATEGORY: AVX512 66419 EXTENSION: AVX512EVEX 66420 ISA_SET: AVX512BW_512 66421 EXCEPTIONS: AVX512-E4NF 66422 REAL_OPCODE: Y 66423 ATTRIBUTES: MASKOP_EVEX 66424 PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 66425 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 66426 IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 66427 } 66428 66429 { 66430 ICLASS: VPUNPCKHBW 66431 CPL: 3 66432 CATEGORY: AVX512 66433 EXTENSION: AVX512EVEX 66434 ISA_SET: AVX512BW_512 66435 EXCEPTIONS: AVX512-E4NF 66436 REAL_OPCODE: Y 66437 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66438 PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 66439 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 66440 IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 66441 } 66442 66443 66444 # EMITTING VPUNPCKHDQ (VPUNPCKHDQ-128-1) 66445 { 66446 ICLASS: VPUNPCKHDQ 66447 CPL: 3 66448 CATEGORY: AVX512 66449 EXTENSION: AVX512EVEX 66450 ISA_SET: AVX512F_128 66451 EXCEPTIONS: AVX512-E4NF 66452 REAL_OPCODE: Y 66453 ATTRIBUTES: MASKOP_EVEX 66454 PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 66455 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 66456 IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 66457 } 66458 66459 { 66460 ICLASS: VPUNPCKHDQ 66461 CPL: 3 66462 CATEGORY: AVX512 66463 EXTENSION: AVX512EVEX 66464 ISA_SET: AVX512F_128 66465 EXCEPTIONS: AVX512-E4NF 66466 REAL_OPCODE: Y 66467 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66468 PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 66469 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 66470 IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 66471 } 66472 66473 66474 # EMITTING VPUNPCKHDQ (VPUNPCKHDQ-256-1) 66475 { 66476 ICLASS: VPUNPCKHDQ 66477 CPL: 3 66478 CATEGORY: AVX512 66479 EXTENSION: AVX512EVEX 66480 ISA_SET: AVX512F_256 66481 EXCEPTIONS: AVX512-E4NF 66482 REAL_OPCODE: Y 66483 ATTRIBUTES: MASKOP_EVEX 66484 PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 66485 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 66486 IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 66487 } 66488 66489 { 66490 ICLASS: VPUNPCKHDQ 66491 CPL: 3 66492 CATEGORY: AVX512 66493 EXTENSION: AVX512EVEX 66494 ISA_SET: AVX512F_256 66495 EXCEPTIONS: AVX512-E4NF 66496 REAL_OPCODE: Y 66497 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66498 PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 66499 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 66500 IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 66501 } 66502 66503 66504 # EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-128-1) 66505 { 66506 ICLASS: VPUNPCKHQDQ 66507 CPL: 3 66508 CATEGORY: AVX512 66509 EXTENSION: AVX512EVEX 66510 ISA_SET: AVX512F_128 66511 EXCEPTIONS: AVX512-E4NF 66512 REAL_OPCODE: Y 66513 ATTRIBUTES: MASKOP_EVEX 66514 PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 66515 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 66516 IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 66517 } 66518 66519 { 66520 ICLASS: VPUNPCKHQDQ 66521 CPL: 3 66522 CATEGORY: AVX512 66523 EXTENSION: AVX512EVEX 66524 ISA_SET: AVX512F_128 66525 EXCEPTIONS: AVX512-E4NF 66526 REAL_OPCODE: Y 66527 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66528 PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 66529 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 66530 IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 66531 } 66532 66533 66534 # EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-256-1) 66535 { 66536 ICLASS: VPUNPCKHQDQ 66537 CPL: 3 66538 CATEGORY: AVX512 66539 EXTENSION: AVX512EVEX 66540 ISA_SET: AVX512F_256 66541 EXCEPTIONS: AVX512-E4NF 66542 REAL_OPCODE: Y 66543 ATTRIBUTES: MASKOP_EVEX 66544 PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 66545 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 66546 IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 66547 } 66548 66549 { 66550 ICLASS: VPUNPCKHQDQ 66551 CPL: 3 66552 CATEGORY: AVX512 66553 EXTENSION: AVX512EVEX 66554 ISA_SET: AVX512F_256 66555 EXCEPTIONS: AVX512-E4NF 66556 REAL_OPCODE: Y 66557 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66558 PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 66559 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 66560 IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 66561 } 66562 66563 66564 # EMITTING VPUNPCKHWD (VPUNPCKHWD-128-1) 66565 { 66566 ICLASS: VPUNPCKHWD 66567 CPL: 3 66568 CATEGORY: AVX512 66569 EXTENSION: AVX512EVEX 66570 ISA_SET: AVX512BW_128 66571 EXCEPTIONS: AVX512-E4NF 66572 REAL_OPCODE: Y 66573 ATTRIBUTES: MASKOP_EVEX 66574 PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 66575 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 66576 IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 66577 } 66578 66579 { 66580 ICLASS: VPUNPCKHWD 66581 CPL: 3 66582 CATEGORY: AVX512 66583 EXTENSION: AVX512EVEX 66584 ISA_SET: AVX512BW_128 66585 EXCEPTIONS: AVX512-E4NF 66586 REAL_OPCODE: Y 66587 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66588 PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 66589 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 66590 IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 66591 } 66592 66593 66594 # EMITTING VPUNPCKHWD (VPUNPCKHWD-256-1) 66595 { 66596 ICLASS: VPUNPCKHWD 66597 CPL: 3 66598 CATEGORY: AVX512 66599 EXTENSION: AVX512EVEX 66600 ISA_SET: AVX512BW_256 66601 EXCEPTIONS: AVX512-E4NF 66602 REAL_OPCODE: Y 66603 ATTRIBUTES: MASKOP_EVEX 66604 PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 66605 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 66606 IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 66607 } 66608 66609 { 66610 ICLASS: VPUNPCKHWD 66611 CPL: 3 66612 CATEGORY: AVX512 66613 EXTENSION: AVX512EVEX 66614 ISA_SET: AVX512BW_256 66615 EXCEPTIONS: AVX512-E4NF 66616 REAL_OPCODE: Y 66617 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66618 PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 66619 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 66620 IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 66621 } 66622 66623 66624 # EMITTING VPUNPCKHWD (VPUNPCKHWD-512-1) 66625 { 66626 ICLASS: VPUNPCKHWD 66627 CPL: 3 66628 CATEGORY: AVX512 66629 EXTENSION: AVX512EVEX 66630 ISA_SET: AVX512BW_512 66631 EXCEPTIONS: AVX512-E4NF 66632 REAL_OPCODE: Y 66633 ATTRIBUTES: MASKOP_EVEX 66634 PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 66635 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 66636 IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 66637 } 66638 66639 { 66640 ICLASS: VPUNPCKHWD 66641 CPL: 3 66642 CATEGORY: AVX512 66643 EXTENSION: AVX512EVEX 66644 ISA_SET: AVX512BW_512 66645 EXCEPTIONS: AVX512-E4NF 66646 REAL_OPCODE: Y 66647 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66648 PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 66649 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 66650 IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 66651 } 66652 66653 66654 # EMITTING VPUNPCKLBW (VPUNPCKLBW-128-1) 66655 { 66656 ICLASS: VPUNPCKLBW 66657 CPL: 3 66658 CATEGORY: AVX512 66659 EXTENSION: AVX512EVEX 66660 ISA_SET: AVX512BW_128 66661 EXCEPTIONS: AVX512-E4NF 66662 REAL_OPCODE: Y 66663 ATTRIBUTES: MASKOP_EVEX 66664 PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 66665 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 66666 IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 66667 } 66668 66669 { 66670 ICLASS: VPUNPCKLBW 66671 CPL: 3 66672 CATEGORY: AVX512 66673 EXTENSION: AVX512EVEX 66674 ISA_SET: AVX512BW_128 66675 EXCEPTIONS: AVX512-E4NF 66676 REAL_OPCODE: Y 66677 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66678 PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 66679 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 66680 IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 66681 } 66682 66683 66684 # EMITTING VPUNPCKLBW (VPUNPCKLBW-256-1) 66685 { 66686 ICLASS: VPUNPCKLBW 66687 CPL: 3 66688 CATEGORY: AVX512 66689 EXTENSION: AVX512EVEX 66690 ISA_SET: AVX512BW_256 66691 EXCEPTIONS: AVX512-E4NF 66692 REAL_OPCODE: Y 66693 ATTRIBUTES: MASKOP_EVEX 66694 PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 66695 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 66696 IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 66697 } 66698 66699 { 66700 ICLASS: VPUNPCKLBW 66701 CPL: 3 66702 CATEGORY: AVX512 66703 EXTENSION: AVX512EVEX 66704 ISA_SET: AVX512BW_256 66705 EXCEPTIONS: AVX512-E4NF 66706 REAL_OPCODE: Y 66707 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66708 PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 66709 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 66710 IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 66711 } 66712 66713 66714 # EMITTING VPUNPCKLBW (VPUNPCKLBW-512-1) 66715 { 66716 ICLASS: VPUNPCKLBW 66717 CPL: 3 66718 CATEGORY: AVX512 66719 EXTENSION: AVX512EVEX 66720 ISA_SET: AVX512BW_512 66721 EXCEPTIONS: AVX512-E4NF 66722 REAL_OPCODE: Y 66723 ATTRIBUTES: MASKOP_EVEX 66724 PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 66725 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 66726 IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 66727 } 66728 66729 { 66730 ICLASS: VPUNPCKLBW 66731 CPL: 3 66732 CATEGORY: AVX512 66733 EXTENSION: AVX512EVEX 66734 ISA_SET: AVX512BW_512 66735 EXCEPTIONS: AVX512-E4NF 66736 REAL_OPCODE: Y 66737 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66738 PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 66739 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 66740 IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 66741 } 66742 66743 66744 # EMITTING VPUNPCKLDQ (VPUNPCKLDQ-128-1) 66745 { 66746 ICLASS: VPUNPCKLDQ 66747 CPL: 3 66748 CATEGORY: AVX512 66749 EXTENSION: AVX512EVEX 66750 ISA_SET: AVX512F_128 66751 EXCEPTIONS: AVX512-E4NF 66752 REAL_OPCODE: Y 66753 ATTRIBUTES: MASKOP_EVEX 66754 PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 66755 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 66756 IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 66757 } 66758 66759 { 66760 ICLASS: VPUNPCKLDQ 66761 CPL: 3 66762 CATEGORY: AVX512 66763 EXTENSION: AVX512EVEX 66764 ISA_SET: AVX512F_128 66765 EXCEPTIONS: AVX512-E4NF 66766 REAL_OPCODE: Y 66767 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66768 PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 66769 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 66770 IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 66771 } 66772 66773 66774 # EMITTING VPUNPCKLDQ (VPUNPCKLDQ-256-1) 66775 { 66776 ICLASS: VPUNPCKLDQ 66777 CPL: 3 66778 CATEGORY: AVX512 66779 EXTENSION: AVX512EVEX 66780 ISA_SET: AVX512F_256 66781 EXCEPTIONS: AVX512-E4NF 66782 REAL_OPCODE: Y 66783 ATTRIBUTES: MASKOP_EVEX 66784 PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 66785 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 66786 IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 66787 } 66788 66789 { 66790 ICLASS: VPUNPCKLDQ 66791 CPL: 3 66792 CATEGORY: AVX512 66793 EXTENSION: AVX512EVEX 66794 ISA_SET: AVX512F_256 66795 EXCEPTIONS: AVX512-E4NF 66796 REAL_OPCODE: Y 66797 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66798 PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 66799 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 66800 IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 66801 } 66802 66803 66804 # EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-128-1) 66805 { 66806 ICLASS: VPUNPCKLQDQ 66807 CPL: 3 66808 CATEGORY: AVX512 66809 EXTENSION: AVX512EVEX 66810 ISA_SET: AVX512F_128 66811 EXCEPTIONS: AVX512-E4NF 66812 REAL_OPCODE: Y 66813 ATTRIBUTES: MASKOP_EVEX 66814 PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 66815 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 66816 IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 66817 } 66818 66819 { 66820 ICLASS: VPUNPCKLQDQ 66821 CPL: 3 66822 CATEGORY: AVX512 66823 EXTENSION: AVX512EVEX 66824 ISA_SET: AVX512F_128 66825 EXCEPTIONS: AVX512-E4NF 66826 REAL_OPCODE: Y 66827 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66828 PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 66829 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 66830 IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 66831 } 66832 66833 66834 # EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-256-1) 66835 { 66836 ICLASS: VPUNPCKLQDQ 66837 CPL: 3 66838 CATEGORY: AVX512 66839 EXTENSION: AVX512EVEX 66840 ISA_SET: AVX512F_256 66841 EXCEPTIONS: AVX512-E4NF 66842 REAL_OPCODE: Y 66843 ATTRIBUTES: MASKOP_EVEX 66844 PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 66845 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 66846 IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 66847 } 66848 66849 { 66850 ICLASS: VPUNPCKLQDQ 66851 CPL: 3 66852 CATEGORY: AVX512 66853 EXTENSION: AVX512EVEX 66854 ISA_SET: AVX512F_256 66855 EXCEPTIONS: AVX512-E4NF 66856 REAL_OPCODE: Y 66857 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66858 PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 66859 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 66860 IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 66861 } 66862 66863 66864 # EMITTING VPUNPCKLWD (VPUNPCKLWD-128-1) 66865 { 66866 ICLASS: VPUNPCKLWD 66867 CPL: 3 66868 CATEGORY: AVX512 66869 EXTENSION: AVX512EVEX 66870 ISA_SET: AVX512BW_128 66871 EXCEPTIONS: AVX512-E4NF 66872 REAL_OPCODE: Y 66873 ATTRIBUTES: MASKOP_EVEX 66874 PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 66875 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 66876 IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 66877 } 66878 66879 { 66880 ICLASS: VPUNPCKLWD 66881 CPL: 3 66882 CATEGORY: AVX512 66883 EXTENSION: AVX512EVEX 66884 ISA_SET: AVX512BW_128 66885 EXCEPTIONS: AVX512-E4NF 66886 REAL_OPCODE: Y 66887 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66888 PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 66889 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 66890 IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 66891 } 66892 66893 66894 # EMITTING VPUNPCKLWD (VPUNPCKLWD-256-1) 66895 { 66896 ICLASS: VPUNPCKLWD 66897 CPL: 3 66898 CATEGORY: AVX512 66899 EXTENSION: AVX512EVEX 66900 ISA_SET: AVX512BW_256 66901 EXCEPTIONS: AVX512-E4NF 66902 REAL_OPCODE: Y 66903 ATTRIBUTES: MASKOP_EVEX 66904 PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 66905 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 66906 IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 66907 } 66908 66909 { 66910 ICLASS: VPUNPCKLWD 66911 CPL: 3 66912 CATEGORY: AVX512 66913 EXTENSION: AVX512EVEX 66914 ISA_SET: AVX512BW_256 66915 EXCEPTIONS: AVX512-E4NF 66916 REAL_OPCODE: Y 66917 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66918 PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 66919 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 66920 IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 66921 } 66922 66923 66924 # EMITTING VPUNPCKLWD (VPUNPCKLWD-512-1) 66925 { 66926 ICLASS: VPUNPCKLWD 66927 CPL: 3 66928 CATEGORY: AVX512 66929 EXTENSION: AVX512EVEX 66930 ISA_SET: AVX512BW_512 66931 EXCEPTIONS: AVX512-E4NF 66932 REAL_OPCODE: Y 66933 ATTRIBUTES: MASKOP_EVEX 66934 PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 66935 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 66936 IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 66937 } 66938 66939 { 66940 ICLASS: VPUNPCKLWD 66941 CPL: 3 66942 CATEGORY: AVX512 66943 EXTENSION: AVX512EVEX 66944 ISA_SET: AVX512BW_512 66945 EXCEPTIONS: AVX512-E4NF 66946 REAL_OPCODE: Y 66947 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 66948 PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 66949 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 66950 IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 66951 } 66952 66953 66954 # EMITTING VPXORD (VPXORD-128-1) 66955 { 66956 ICLASS: VPXORD 66957 CPL: 3 66958 CATEGORY: LOGICAL 66959 EXTENSION: AVX512EVEX 66960 ISA_SET: AVX512F_128 66961 EXCEPTIONS: AVX512-E4 66962 REAL_OPCODE: Y 66963 ATTRIBUTES: MASKOP_EVEX 66964 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 66965 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 66966 IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 66967 } 66968 66969 { 66970 ICLASS: VPXORD 66971 CPL: 3 66972 CATEGORY: LOGICAL 66973 EXTENSION: AVX512EVEX 66974 ISA_SET: AVX512F_128 66975 EXCEPTIONS: AVX512-E4 66976 REAL_OPCODE: Y 66977 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 66978 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 66979 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 66980 IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 66981 } 66982 66983 66984 # EMITTING VPXORD (VPXORD-256-1) 66985 { 66986 ICLASS: VPXORD 66987 CPL: 3 66988 CATEGORY: LOGICAL 66989 EXTENSION: AVX512EVEX 66990 ISA_SET: AVX512F_256 66991 EXCEPTIONS: AVX512-E4 66992 REAL_OPCODE: Y 66993 ATTRIBUTES: MASKOP_EVEX 66994 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 66995 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 66996 IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 66997 } 66998 66999 { 67000 ICLASS: VPXORD 67001 CPL: 3 67002 CATEGORY: LOGICAL 67003 EXTENSION: AVX512EVEX 67004 ISA_SET: AVX512F_256 67005 EXCEPTIONS: AVX512-E4 67006 REAL_OPCODE: Y 67007 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67008 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 67009 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 67010 IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 67011 } 67012 67013 67014 # EMITTING VPXORQ (VPXORQ-128-1) 67015 { 67016 ICLASS: VPXORQ 67017 CPL: 3 67018 CATEGORY: LOGICAL 67019 EXTENSION: AVX512EVEX 67020 ISA_SET: AVX512F_128 67021 EXCEPTIONS: AVX512-E4 67022 REAL_OPCODE: Y 67023 ATTRIBUTES: MASKOP_EVEX 67024 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 67025 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 67026 IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 67027 } 67028 67029 { 67030 ICLASS: VPXORQ 67031 CPL: 3 67032 CATEGORY: LOGICAL 67033 EXTENSION: AVX512EVEX 67034 ISA_SET: AVX512F_128 67035 EXCEPTIONS: AVX512-E4 67036 REAL_OPCODE: Y 67037 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67038 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 67039 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 67040 IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 67041 } 67042 67043 67044 # EMITTING VPXORQ (VPXORQ-256-1) 67045 { 67046 ICLASS: VPXORQ 67047 CPL: 3 67048 CATEGORY: LOGICAL 67049 EXTENSION: AVX512EVEX 67050 ISA_SET: AVX512F_256 67051 EXCEPTIONS: AVX512-E4 67052 REAL_OPCODE: Y 67053 ATTRIBUTES: MASKOP_EVEX 67054 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 67055 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 67056 IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 67057 } 67058 67059 { 67060 ICLASS: VPXORQ 67061 CPL: 3 67062 CATEGORY: LOGICAL 67063 EXTENSION: AVX512EVEX 67064 ISA_SET: AVX512F_256 67065 EXCEPTIONS: AVX512-E4 67066 REAL_OPCODE: Y 67067 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67068 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 67069 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 67070 IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 67071 } 67072 67073 67074 # EMITTING VRANGEPD (VRANGEPD-128-1) 67075 { 67076 ICLASS: VRANGEPD 67077 CPL: 3 67078 CATEGORY: AVX512 67079 EXTENSION: AVX512EVEX 67080 ISA_SET: AVX512DQ_128 67081 EXCEPTIONS: AVX512-E2 67082 REAL_OPCODE: Y 67083 ATTRIBUTES: MXCSR MASKOP_EVEX 67084 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 67085 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 67086 IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 67087 } 67088 67089 { 67090 ICLASS: VRANGEPD 67091 CPL: 3 67092 CATEGORY: AVX512 67093 EXTENSION: AVX512EVEX 67094 ISA_SET: AVX512DQ_128 67095 EXCEPTIONS: AVX512-E2 67096 REAL_OPCODE: Y 67097 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67098 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 67099 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 67100 IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 67101 } 67102 67103 67104 # EMITTING VRANGEPD (VRANGEPD-256-1) 67105 { 67106 ICLASS: VRANGEPD 67107 CPL: 3 67108 CATEGORY: AVX512 67109 EXTENSION: AVX512EVEX 67110 ISA_SET: AVX512DQ_256 67111 EXCEPTIONS: AVX512-E2 67112 REAL_OPCODE: Y 67113 ATTRIBUTES: MXCSR MASKOP_EVEX 67114 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 67115 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 67116 IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 67117 } 67118 67119 { 67120 ICLASS: VRANGEPD 67121 CPL: 3 67122 CATEGORY: AVX512 67123 EXTENSION: AVX512EVEX 67124 ISA_SET: AVX512DQ_256 67125 EXCEPTIONS: AVX512-E2 67126 REAL_OPCODE: Y 67127 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67128 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 67129 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 67130 IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 67131 } 67132 67133 67134 # EMITTING VRANGEPD (VRANGEPD-512-1) 67135 { 67136 ICLASS: VRANGEPD 67137 CPL: 3 67138 CATEGORY: AVX512 67139 EXTENSION: AVX512EVEX 67140 ISA_SET: AVX512DQ_512 67141 EXCEPTIONS: AVX512-E2 67142 REAL_OPCODE: Y 67143 ATTRIBUTES: MXCSR MASKOP_EVEX 67144 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 67145 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 67146 IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 67147 } 67148 67149 { 67150 ICLASS: VRANGEPD 67151 CPL: 3 67152 CATEGORY: AVX512 67153 EXTENSION: AVX512EVEX 67154 ISA_SET: AVX512DQ_512 67155 EXCEPTIONS: AVX512-E2 67156 REAL_OPCODE: Y 67157 ATTRIBUTES: MXCSR MASKOP_EVEX 67158 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() 67159 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 67160 IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 67161 } 67162 67163 { 67164 ICLASS: VRANGEPD 67165 CPL: 3 67166 CATEGORY: AVX512 67167 EXTENSION: AVX512EVEX 67168 ISA_SET: AVX512DQ_512 67169 EXCEPTIONS: AVX512-E2 67170 REAL_OPCODE: Y 67171 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67172 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 67173 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 67174 IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 67175 } 67176 67177 67178 # EMITTING VRANGEPS (VRANGEPS-128-1) 67179 { 67180 ICLASS: VRANGEPS 67181 CPL: 3 67182 CATEGORY: AVX512 67183 EXTENSION: AVX512EVEX 67184 ISA_SET: AVX512DQ_128 67185 EXCEPTIONS: AVX512-E2 67186 REAL_OPCODE: Y 67187 ATTRIBUTES: MXCSR MASKOP_EVEX 67188 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 67189 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 67190 IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 67191 } 67192 67193 { 67194 ICLASS: VRANGEPS 67195 CPL: 3 67196 CATEGORY: AVX512 67197 EXTENSION: AVX512EVEX 67198 ISA_SET: AVX512DQ_128 67199 EXCEPTIONS: AVX512-E2 67200 REAL_OPCODE: Y 67201 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67202 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 67203 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 67204 IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 67205 } 67206 67207 67208 # EMITTING VRANGEPS (VRANGEPS-256-1) 67209 { 67210 ICLASS: VRANGEPS 67211 CPL: 3 67212 CATEGORY: AVX512 67213 EXTENSION: AVX512EVEX 67214 ISA_SET: AVX512DQ_256 67215 EXCEPTIONS: AVX512-E2 67216 REAL_OPCODE: Y 67217 ATTRIBUTES: MXCSR MASKOP_EVEX 67218 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 67219 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 67220 IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 67221 } 67222 67223 { 67224 ICLASS: VRANGEPS 67225 CPL: 3 67226 CATEGORY: AVX512 67227 EXTENSION: AVX512EVEX 67228 ISA_SET: AVX512DQ_256 67229 EXCEPTIONS: AVX512-E2 67230 REAL_OPCODE: Y 67231 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67232 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 67233 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 67234 IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 67235 } 67236 67237 67238 # EMITTING VRANGEPS (VRANGEPS-512-1) 67239 { 67240 ICLASS: VRANGEPS 67241 CPL: 3 67242 CATEGORY: AVX512 67243 EXTENSION: AVX512EVEX 67244 ISA_SET: AVX512DQ_512 67245 EXCEPTIONS: AVX512-E2 67246 REAL_OPCODE: Y 67247 ATTRIBUTES: MXCSR MASKOP_EVEX 67248 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 67249 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 67250 IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 67251 } 67252 67253 { 67254 ICLASS: VRANGEPS 67255 CPL: 3 67256 CATEGORY: AVX512 67257 EXTENSION: AVX512EVEX 67258 ISA_SET: AVX512DQ_512 67259 EXCEPTIONS: AVX512-E2 67260 REAL_OPCODE: Y 67261 ATTRIBUTES: MXCSR MASKOP_EVEX 67262 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() 67263 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 67264 IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 67265 } 67266 67267 { 67268 ICLASS: VRANGEPS 67269 CPL: 3 67270 CATEGORY: AVX512 67271 EXTENSION: AVX512EVEX 67272 ISA_SET: AVX512DQ_512 67273 EXCEPTIONS: AVX512-E2 67274 REAL_OPCODE: Y 67275 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67276 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 67277 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 67278 IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 67279 } 67280 67281 67282 # EMITTING VRANGESD (VRANGESD-128-1) 67283 { 67284 ICLASS: VRANGESD 67285 CPL: 3 67286 CATEGORY: AVX512 67287 EXTENSION: AVX512EVEX 67288 ISA_SET: AVX512DQ_SCALAR 67289 EXCEPTIONS: AVX512-E3 67290 REAL_OPCODE: Y 67291 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 67292 PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() 67293 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 67294 IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 67295 } 67296 67297 { 67298 ICLASS: VRANGESD 67299 CPL: 3 67300 CATEGORY: AVX512 67301 EXTENSION: AVX512EVEX 67302 ISA_SET: AVX512DQ_SCALAR 67303 EXCEPTIONS: AVX512-E3 67304 REAL_OPCODE: Y 67305 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 67306 PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() 67307 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 67308 IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 67309 } 67310 67311 { 67312 ICLASS: VRANGESD 67313 CPL: 3 67314 CATEGORY: AVX512 67315 EXTENSION: AVX512EVEX 67316 ISA_SET: AVX512DQ_SCALAR 67317 EXCEPTIONS: AVX512-E3 67318 REAL_OPCODE: Y 67319 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 67320 PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 67321 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 67322 IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 67323 } 67324 67325 67326 # EMITTING VRANGESS (VRANGESS-128-1) 67327 { 67328 ICLASS: VRANGESS 67329 CPL: 3 67330 CATEGORY: AVX512 67331 EXTENSION: AVX512EVEX 67332 ISA_SET: AVX512DQ_SCALAR 67333 EXCEPTIONS: AVX512-E3 67334 REAL_OPCODE: Y 67335 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 67336 PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() 67337 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 67338 IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 67339 } 67340 67341 { 67342 ICLASS: VRANGESS 67343 CPL: 3 67344 CATEGORY: AVX512 67345 EXTENSION: AVX512EVEX 67346 ISA_SET: AVX512DQ_SCALAR 67347 EXCEPTIONS: AVX512-E3 67348 REAL_OPCODE: Y 67349 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 67350 PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() 67351 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 67352 IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 67353 } 67354 67355 { 67356 ICLASS: VRANGESS 67357 CPL: 3 67358 CATEGORY: AVX512 67359 EXTENSION: AVX512EVEX 67360 ISA_SET: AVX512DQ_SCALAR 67361 EXCEPTIONS: AVX512-E3 67362 REAL_OPCODE: Y 67363 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 67364 PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 67365 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 67366 IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 67367 } 67368 67369 67370 # EMITTING VRCP14PD (VRCP14PD-128-1) 67371 { 67372 ICLASS: VRCP14PD 67373 CPL: 3 67374 CATEGORY: AVX512 67375 EXTENSION: AVX512EVEX 67376 ISA_SET: AVX512F_128 67377 EXCEPTIONS: AVX512-E4 67378 REAL_OPCODE: Y 67379 ATTRIBUTES: MXCSR MASKOP_EVEX 67380 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 67381 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 67382 IFORM: VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 67383 } 67384 67385 { 67386 ICLASS: VRCP14PD 67387 CPL: 3 67388 CATEGORY: AVX512 67389 EXTENSION: AVX512EVEX 67390 ISA_SET: AVX512F_128 67391 EXCEPTIONS: AVX512-E4 67392 REAL_OPCODE: Y 67393 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67394 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 67395 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 67396 IFORM: VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 67397 } 67398 67399 67400 # EMITTING VRCP14PD (VRCP14PD-256-1) 67401 { 67402 ICLASS: VRCP14PD 67403 CPL: 3 67404 CATEGORY: AVX512 67405 EXTENSION: AVX512EVEX 67406 ISA_SET: AVX512F_256 67407 EXCEPTIONS: AVX512-E4 67408 REAL_OPCODE: Y 67409 ATTRIBUTES: MXCSR MASKOP_EVEX 67410 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 67411 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 67412 IFORM: VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 67413 } 67414 67415 { 67416 ICLASS: VRCP14PD 67417 CPL: 3 67418 CATEGORY: AVX512 67419 EXTENSION: AVX512EVEX 67420 ISA_SET: AVX512F_256 67421 EXCEPTIONS: AVX512-E4 67422 REAL_OPCODE: Y 67423 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67424 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 67425 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 67426 IFORM: VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 67427 } 67428 67429 67430 # EMITTING VRCP14PS (VRCP14PS-128-1) 67431 { 67432 ICLASS: VRCP14PS 67433 CPL: 3 67434 CATEGORY: AVX512 67435 EXTENSION: AVX512EVEX 67436 ISA_SET: AVX512F_128 67437 EXCEPTIONS: AVX512-E4 67438 REAL_OPCODE: Y 67439 ATTRIBUTES: MXCSR MASKOP_EVEX 67440 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 67441 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 67442 IFORM: VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 67443 } 67444 67445 { 67446 ICLASS: VRCP14PS 67447 CPL: 3 67448 CATEGORY: AVX512 67449 EXTENSION: AVX512EVEX 67450 ISA_SET: AVX512F_128 67451 EXCEPTIONS: AVX512-E4 67452 REAL_OPCODE: Y 67453 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67454 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 67455 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 67456 IFORM: VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 67457 } 67458 67459 67460 # EMITTING VRCP14PS (VRCP14PS-256-1) 67461 { 67462 ICLASS: VRCP14PS 67463 CPL: 3 67464 CATEGORY: AVX512 67465 EXTENSION: AVX512EVEX 67466 ISA_SET: AVX512F_256 67467 EXCEPTIONS: AVX512-E4 67468 REAL_OPCODE: Y 67469 ATTRIBUTES: MXCSR MASKOP_EVEX 67470 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 67471 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 67472 IFORM: VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 67473 } 67474 67475 { 67476 ICLASS: VRCP14PS 67477 CPL: 3 67478 CATEGORY: AVX512 67479 EXTENSION: AVX512EVEX 67480 ISA_SET: AVX512F_256 67481 EXCEPTIONS: AVX512-E4 67482 REAL_OPCODE: Y 67483 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67484 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 67485 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 67486 IFORM: VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 67487 } 67488 67489 67490 # EMITTING VREDUCEPD (VREDUCEPD-128-1) 67491 { 67492 ICLASS: VREDUCEPD 67493 CPL: 3 67494 CATEGORY: AVX512 67495 EXTENSION: AVX512EVEX 67496 ISA_SET: AVX512DQ_128 67497 EXCEPTIONS: AVX512-E2 67498 REAL_OPCODE: Y 67499 ATTRIBUTES: MXCSR MASKOP_EVEX 67500 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() 67501 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b 67502 IFORM: VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 67503 } 67504 67505 { 67506 ICLASS: VREDUCEPD 67507 CPL: 3 67508 CATEGORY: AVX512 67509 EXTENSION: AVX512EVEX 67510 ISA_SET: AVX512DQ_128 67511 EXCEPTIONS: AVX512-E2 67512 REAL_OPCODE: Y 67513 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67514 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 67515 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 67516 IFORM: VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 67517 } 67518 67519 67520 # EMITTING VREDUCEPD (VREDUCEPD-256-1) 67521 { 67522 ICLASS: VREDUCEPD 67523 CPL: 3 67524 CATEGORY: AVX512 67525 EXTENSION: AVX512EVEX 67526 ISA_SET: AVX512DQ_256 67527 EXCEPTIONS: AVX512-E2 67528 REAL_OPCODE: Y 67529 ATTRIBUTES: MXCSR MASKOP_EVEX 67530 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 67531 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b 67532 IFORM: VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 67533 } 67534 67535 { 67536 ICLASS: VREDUCEPD 67537 CPL: 3 67538 CATEGORY: AVX512 67539 EXTENSION: AVX512EVEX 67540 ISA_SET: AVX512DQ_256 67541 EXCEPTIONS: AVX512-E2 67542 REAL_OPCODE: Y 67543 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67544 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 67545 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 67546 IFORM: VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 67547 } 67548 67549 67550 # EMITTING VREDUCEPD (VREDUCEPD-512-1) 67551 { 67552 ICLASS: VREDUCEPD 67553 CPL: 3 67554 CATEGORY: AVX512 67555 EXTENSION: AVX512EVEX 67556 ISA_SET: AVX512DQ_512 67557 EXCEPTIONS: AVX512-E2 67558 REAL_OPCODE: Y 67559 ATTRIBUTES: MXCSR MASKOP_EVEX 67560 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 67561 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 67562 IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 67563 } 67564 67565 { 67566 ICLASS: VREDUCEPD 67567 CPL: 3 67568 CATEGORY: AVX512 67569 EXTENSION: AVX512EVEX 67570 ISA_SET: AVX512DQ_512 67571 EXCEPTIONS: AVX512-E2 67572 REAL_OPCODE: Y 67573 ATTRIBUTES: MXCSR MASKOP_EVEX 67574 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() 67575 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 67576 IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 67577 } 67578 67579 { 67580 ICLASS: VREDUCEPD 67581 CPL: 3 67582 CATEGORY: AVX512 67583 EXTENSION: AVX512EVEX 67584 ISA_SET: AVX512DQ_512 67585 EXCEPTIONS: AVX512-E2 67586 REAL_OPCODE: Y 67587 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67588 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 67589 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 67590 IFORM: VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 67591 } 67592 67593 67594 # EMITTING VREDUCEPS (VREDUCEPS-128-1) 67595 { 67596 ICLASS: VREDUCEPS 67597 CPL: 3 67598 CATEGORY: AVX512 67599 EXTENSION: AVX512EVEX 67600 ISA_SET: AVX512DQ_128 67601 EXCEPTIONS: AVX512-E2 67602 REAL_OPCODE: Y 67603 ATTRIBUTES: MXCSR MASKOP_EVEX 67604 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 67605 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b 67606 IFORM: VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 67607 } 67608 67609 { 67610 ICLASS: VREDUCEPS 67611 CPL: 3 67612 CATEGORY: AVX512 67613 EXTENSION: AVX512EVEX 67614 ISA_SET: AVX512DQ_128 67615 EXCEPTIONS: AVX512-E2 67616 REAL_OPCODE: Y 67617 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67618 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 67619 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 67620 IFORM: VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 67621 } 67622 67623 67624 # EMITTING VREDUCEPS (VREDUCEPS-256-1) 67625 { 67626 ICLASS: VREDUCEPS 67627 CPL: 3 67628 CATEGORY: AVX512 67629 EXTENSION: AVX512EVEX 67630 ISA_SET: AVX512DQ_256 67631 EXCEPTIONS: AVX512-E2 67632 REAL_OPCODE: Y 67633 ATTRIBUTES: MXCSR MASKOP_EVEX 67634 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 67635 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b 67636 IFORM: VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 67637 } 67638 67639 { 67640 ICLASS: VREDUCEPS 67641 CPL: 3 67642 CATEGORY: AVX512 67643 EXTENSION: AVX512EVEX 67644 ISA_SET: AVX512DQ_256 67645 EXCEPTIONS: AVX512-E2 67646 REAL_OPCODE: Y 67647 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67648 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 67649 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 67650 IFORM: VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 67651 } 67652 67653 67654 # EMITTING VREDUCEPS (VREDUCEPS-512-1) 67655 { 67656 ICLASS: VREDUCEPS 67657 CPL: 3 67658 CATEGORY: AVX512 67659 EXTENSION: AVX512EVEX 67660 ISA_SET: AVX512DQ_512 67661 EXCEPTIONS: AVX512-E2 67662 REAL_OPCODE: Y 67663 ATTRIBUTES: MXCSR MASKOP_EVEX 67664 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 67665 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 67666 IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 67667 } 67668 67669 { 67670 ICLASS: VREDUCEPS 67671 CPL: 3 67672 CATEGORY: AVX512 67673 EXTENSION: AVX512EVEX 67674 ISA_SET: AVX512DQ_512 67675 EXCEPTIONS: AVX512-E2 67676 REAL_OPCODE: Y 67677 ATTRIBUTES: MXCSR MASKOP_EVEX 67678 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() 67679 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 67680 IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 67681 } 67682 67683 { 67684 ICLASS: VREDUCEPS 67685 CPL: 3 67686 CATEGORY: AVX512 67687 EXTENSION: AVX512EVEX 67688 ISA_SET: AVX512DQ_512 67689 EXCEPTIONS: AVX512-E2 67690 REAL_OPCODE: Y 67691 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67692 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 67693 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 67694 IFORM: VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 67695 } 67696 67697 67698 # EMITTING VREDUCESD (VREDUCESD-128-1) 67699 { 67700 ICLASS: VREDUCESD 67701 CPL: 3 67702 CATEGORY: AVX512 67703 EXTENSION: AVX512EVEX 67704 ISA_SET: AVX512DQ_SCALAR 67705 EXCEPTIONS: AVX512-E3 67706 REAL_OPCODE: Y 67707 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 67708 PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() 67709 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 67710 IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 67711 } 67712 67713 { 67714 ICLASS: VREDUCESD 67715 CPL: 3 67716 CATEGORY: AVX512 67717 EXTENSION: AVX512EVEX 67718 ISA_SET: AVX512DQ_SCALAR 67719 EXCEPTIONS: AVX512-E3 67720 REAL_OPCODE: Y 67721 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 67722 PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() 67723 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 67724 IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 67725 } 67726 67727 { 67728 ICLASS: VREDUCESD 67729 CPL: 3 67730 CATEGORY: AVX512 67731 EXTENSION: AVX512EVEX 67732 ISA_SET: AVX512DQ_SCALAR 67733 EXCEPTIONS: AVX512-E3 67734 REAL_OPCODE: Y 67735 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 67736 PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 67737 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 67738 IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 67739 } 67740 67741 67742 # EMITTING VREDUCESS (VREDUCESS-128-1) 67743 { 67744 ICLASS: VREDUCESS 67745 CPL: 3 67746 CATEGORY: AVX512 67747 EXTENSION: AVX512EVEX 67748 ISA_SET: AVX512DQ_SCALAR 67749 EXCEPTIONS: AVX512-E3 67750 REAL_OPCODE: Y 67751 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 67752 PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() 67753 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 67754 IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 67755 } 67756 67757 { 67758 ICLASS: VREDUCESS 67759 CPL: 3 67760 CATEGORY: AVX512 67761 EXTENSION: AVX512EVEX 67762 ISA_SET: AVX512DQ_SCALAR 67763 EXCEPTIONS: AVX512-E3 67764 REAL_OPCODE: Y 67765 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 67766 PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() 67767 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 67768 IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 67769 } 67770 67771 { 67772 ICLASS: VREDUCESS 67773 CPL: 3 67774 CATEGORY: AVX512 67775 EXTENSION: AVX512EVEX 67776 ISA_SET: AVX512DQ_SCALAR 67777 EXCEPTIONS: AVX512-E3 67778 REAL_OPCODE: Y 67779 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 67780 PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 67781 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 67782 IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 67783 } 67784 67785 67786 # EMITTING VRNDSCALEPD (VRNDSCALEPD-128-1) 67787 { 67788 ICLASS: VRNDSCALEPD 67789 CPL: 3 67790 CATEGORY: AVX512 67791 EXTENSION: AVX512EVEX 67792 ISA_SET: AVX512F_128 67793 EXCEPTIONS: AVX512-E2 67794 REAL_OPCODE: Y 67795 ATTRIBUTES: MXCSR MASKOP_EVEX 67796 PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() 67797 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b 67798 IFORM: VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 67799 } 67800 67801 { 67802 ICLASS: VRNDSCALEPD 67803 CPL: 3 67804 CATEGORY: AVX512 67805 EXTENSION: AVX512EVEX 67806 ISA_SET: AVX512F_128 67807 EXCEPTIONS: AVX512-E2 67808 REAL_OPCODE: Y 67809 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67810 PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 67811 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 67812 IFORM: VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 67813 } 67814 67815 67816 # EMITTING VRNDSCALEPD (VRNDSCALEPD-256-1) 67817 { 67818 ICLASS: VRNDSCALEPD 67819 CPL: 3 67820 CATEGORY: AVX512 67821 EXTENSION: AVX512EVEX 67822 ISA_SET: AVX512F_256 67823 EXCEPTIONS: AVX512-E2 67824 REAL_OPCODE: Y 67825 ATTRIBUTES: MXCSR MASKOP_EVEX 67826 PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 67827 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b 67828 IFORM: VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 67829 } 67830 67831 { 67832 ICLASS: VRNDSCALEPD 67833 CPL: 3 67834 CATEGORY: AVX512 67835 EXTENSION: AVX512EVEX 67836 ISA_SET: AVX512F_256 67837 EXCEPTIONS: AVX512-E2 67838 REAL_OPCODE: Y 67839 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67840 PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 67841 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 67842 IFORM: VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 67843 } 67844 67845 67846 # EMITTING VRNDSCALEPS (VRNDSCALEPS-128-1) 67847 { 67848 ICLASS: VRNDSCALEPS 67849 CPL: 3 67850 CATEGORY: AVX512 67851 EXTENSION: AVX512EVEX 67852 ISA_SET: AVX512F_128 67853 EXCEPTIONS: AVX512-E2 67854 REAL_OPCODE: Y 67855 ATTRIBUTES: MXCSR MASKOP_EVEX 67856 PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 67857 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b 67858 IFORM: VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 67859 } 67860 67861 { 67862 ICLASS: VRNDSCALEPS 67863 CPL: 3 67864 CATEGORY: AVX512 67865 EXTENSION: AVX512EVEX 67866 ISA_SET: AVX512F_128 67867 EXCEPTIONS: AVX512-E2 67868 REAL_OPCODE: Y 67869 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67870 PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 67871 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 67872 IFORM: VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 67873 } 67874 67875 67876 # EMITTING VRNDSCALEPS (VRNDSCALEPS-256-1) 67877 { 67878 ICLASS: VRNDSCALEPS 67879 CPL: 3 67880 CATEGORY: AVX512 67881 EXTENSION: AVX512EVEX 67882 ISA_SET: AVX512F_256 67883 EXCEPTIONS: AVX512-E2 67884 REAL_OPCODE: Y 67885 ATTRIBUTES: MXCSR MASKOP_EVEX 67886 PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 67887 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b 67888 IFORM: VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 67889 } 67890 67891 { 67892 ICLASS: VRNDSCALEPS 67893 CPL: 3 67894 CATEGORY: AVX512 67895 EXTENSION: AVX512EVEX 67896 ISA_SET: AVX512F_256 67897 EXCEPTIONS: AVX512-E2 67898 REAL_OPCODE: Y 67899 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67900 PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 67901 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 67902 IFORM: VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 67903 } 67904 67905 67906 # EMITTING VRSQRT14PD (VRSQRT14PD-128-1) 67907 { 67908 ICLASS: VRSQRT14PD 67909 CPL: 3 67910 CATEGORY: AVX512 67911 EXTENSION: AVX512EVEX 67912 ISA_SET: AVX512F_128 67913 EXCEPTIONS: AVX512-E4 67914 REAL_OPCODE: Y 67915 ATTRIBUTES: MXCSR MASKOP_EVEX 67916 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 67917 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 67918 IFORM: VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 67919 } 67920 67921 { 67922 ICLASS: VRSQRT14PD 67923 CPL: 3 67924 CATEGORY: AVX512 67925 EXTENSION: AVX512EVEX 67926 ISA_SET: AVX512F_128 67927 EXCEPTIONS: AVX512-E4 67928 REAL_OPCODE: Y 67929 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67930 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 67931 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 67932 IFORM: VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 67933 } 67934 67935 67936 # EMITTING VRSQRT14PD (VRSQRT14PD-256-1) 67937 { 67938 ICLASS: VRSQRT14PD 67939 CPL: 3 67940 CATEGORY: AVX512 67941 EXTENSION: AVX512EVEX 67942 ISA_SET: AVX512F_256 67943 EXCEPTIONS: AVX512-E4 67944 REAL_OPCODE: Y 67945 ATTRIBUTES: MXCSR MASKOP_EVEX 67946 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 67947 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 67948 IFORM: VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 67949 } 67950 67951 { 67952 ICLASS: VRSQRT14PD 67953 CPL: 3 67954 CATEGORY: AVX512 67955 EXTENSION: AVX512EVEX 67956 ISA_SET: AVX512F_256 67957 EXCEPTIONS: AVX512-E4 67958 REAL_OPCODE: Y 67959 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67960 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 67961 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 67962 IFORM: VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 67963 } 67964 67965 67966 # EMITTING VRSQRT14PS (VRSQRT14PS-128-1) 67967 { 67968 ICLASS: VRSQRT14PS 67969 CPL: 3 67970 CATEGORY: AVX512 67971 EXTENSION: AVX512EVEX 67972 ISA_SET: AVX512F_128 67973 EXCEPTIONS: AVX512-E4 67974 REAL_OPCODE: Y 67975 ATTRIBUTES: MXCSR MASKOP_EVEX 67976 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 67977 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 67978 IFORM: VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 67979 } 67980 67981 { 67982 ICLASS: VRSQRT14PS 67983 CPL: 3 67984 CATEGORY: AVX512 67985 EXTENSION: AVX512EVEX 67986 ISA_SET: AVX512F_128 67987 EXCEPTIONS: AVX512-E4 67988 REAL_OPCODE: Y 67989 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 67990 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 67991 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 67992 IFORM: VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 67993 } 67994 67995 67996 # EMITTING VRSQRT14PS (VRSQRT14PS-256-1) 67997 { 67998 ICLASS: VRSQRT14PS 67999 CPL: 3 68000 CATEGORY: AVX512 68001 EXTENSION: AVX512EVEX 68002 ISA_SET: AVX512F_256 68003 EXCEPTIONS: AVX512-E4 68004 REAL_OPCODE: Y 68005 ATTRIBUTES: MXCSR MASKOP_EVEX 68006 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 68007 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 68008 IFORM: VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 68009 } 68010 68011 { 68012 ICLASS: VRSQRT14PS 68013 CPL: 3 68014 CATEGORY: AVX512 68015 EXTENSION: AVX512EVEX 68016 ISA_SET: AVX512F_256 68017 EXCEPTIONS: AVX512-E4 68018 REAL_OPCODE: Y 68019 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68020 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 68021 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 68022 IFORM: VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 68023 } 68024 68025 68026 # EMITTING VSCALEFPD (VSCALEFPD-128-1) 68027 { 68028 ICLASS: VSCALEFPD 68029 CPL: 3 68030 CATEGORY: AVX512 68031 EXTENSION: AVX512EVEX 68032 ISA_SET: AVX512F_128 68033 EXCEPTIONS: AVX512-E2 68034 REAL_OPCODE: Y 68035 ATTRIBUTES: MXCSR MASKOP_EVEX 68036 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 68037 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 68038 IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 68039 } 68040 68041 { 68042 ICLASS: VSCALEFPD 68043 CPL: 3 68044 CATEGORY: AVX512 68045 EXTENSION: AVX512EVEX 68046 ISA_SET: AVX512F_128 68047 EXCEPTIONS: AVX512-E2 68048 REAL_OPCODE: Y 68049 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68050 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 68051 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 68052 IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 68053 } 68054 68055 68056 # EMITTING VSCALEFPD (VSCALEFPD-256-1) 68057 { 68058 ICLASS: VSCALEFPD 68059 CPL: 3 68060 CATEGORY: AVX512 68061 EXTENSION: AVX512EVEX 68062 ISA_SET: AVX512F_256 68063 EXCEPTIONS: AVX512-E2 68064 REAL_OPCODE: Y 68065 ATTRIBUTES: MXCSR MASKOP_EVEX 68066 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 68067 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 68068 IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 68069 } 68070 68071 { 68072 ICLASS: VSCALEFPD 68073 CPL: 3 68074 CATEGORY: AVX512 68075 EXTENSION: AVX512EVEX 68076 ISA_SET: AVX512F_256 68077 EXCEPTIONS: AVX512-E2 68078 REAL_OPCODE: Y 68079 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68080 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 68081 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 68082 IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 68083 } 68084 68085 68086 # EMITTING VSCALEFPS (VSCALEFPS-128-1) 68087 { 68088 ICLASS: VSCALEFPS 68089 CPL: 3 68090 CATEGORY: AVX512 68091 EXTENSION: AVX512EVEX 68092 ISA_SET: AVX512F_128 68093 EXCEPTIONS: AVX512-E2 68094 REAL_OPCODE: Y 68095 ATTRIBUTES: MXCSR MASKOP_EVEX 68096 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 68097 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 68098 IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 68099 } 68100 68101 { 68102 ICLASS: VSCALEFPS 68103 CPL: 3 68104 CATEGORY: AVX512 68105 EXTENSION: AVX512EVEX 68106 ISA_SET: AVX512F_128 68107 EXCEPTIONS: AVX512-E2 68108 REAL_OPCODE: Y 68109 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68110 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 68111 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 68112 IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 68113 } 68114 68115 68116 # EMITTING VSCALEFPS (VSCALEFPS-256-1) 68117 { 68118 ICLASS: VSCALEFPS 68119 CPL: 3 68120 CATEGORY: AVX512 68121 EXTENSION: AVX512EVEX 68122 ISA_SET: AVX512F_256 68123 EXCEPTIONS: AVX512-E2 68124 REAL_OPCODE: Y 68125 ATTRIBUTES: MXCSR MASKOP_EVEX 68126 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 68127 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 68128 IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 68129 } 68130 68131 { 68132 ICLASS: VSCALEFPS 68133 CPL: 3 68134 CATEGORY: AVX512 68135 EXTENSION: AVX512EVEX 68136 ISA_SET: AVX512F_256 68137 EXCEPTIONS: AVX512-E2 68138 REAL_OPCODE: Y 68139 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68140 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 68141 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 68142 IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 68143 } 68144 68145 68146 # EMITTING VSCATTERDPD (VSCATTERDPD-128-1) 68147 { 68148 ICLASS: VSCATTERDPD 68149 CPL: 3 68150 CATEGORY: SCATTER 68151 EXTENSION: AVX512EVEX 68152 ISA_SET: AVX512F_128 68153 EXCEPTIONS: AVX512-E12 68154 REAL_OPCODE: Y 68155 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 68156 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 68157 OPERANDS: MEM0:w:dq:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 68158 IFORM: VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 68159 } 68160 68161 68162 # EMITTING VSCATTERDPD (VSCATTERDPD-256-1) 68163 { 68164 ICLASS: VSCATTERDPD 68165 CPL: 3 68166 CATEGORY: SCATTER 68167 EXTENSION: AVX512EVEX 68168 ISA_SET: AVX512F_256 68169 EXCEPTIONS: AVX512-E12 68170 REAL_OPCODE: Y 68171 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 68172 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 68173 OPERANDS: MEM0:w:qq:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 68174 IFORM: VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 68175 } 68176 68177 68178 # EMITTING VSCATTERDPS (VSCATTERDPS-128-1) 68179 { 68180 ICLASS: VSCATTERDPS 68181 CPL: 3 68182 CATEGORY: SCATTER 68183 EXTENSION: AVX512EVEX 68184 ISA_SET: AVX512F_128 68185 EXCEPTIONS: AVX512-E12 68186 REAL_OPCODE: Y 68187 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 68188 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 68189 OPERANDS: MEM0:w:dq:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 68190 IFORM: VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 68191 } 68192 68193 68194 # EMITTING VSCATTERDPS (VSCATTERDPS-256-1) 68195 { 68196 ICLASS: VSCATTERDPS 68197 CPL: 3 68198 CATEGORY: SCATTER 68199 EXTENSION: AVX512EVEX 68200 ISA_SET: AVX512F_256 68201 EXCEPTIONS: AVX512-E12 68202 REAL_OPCODE: Y 68203 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 68204 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 68205 OPERANDS: MEM0:w:qq:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 68206 IFORM: VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 68207 } 68208 68209 68210 # EMITTING VSCATTERQPD (VSCATTERQPD-128-1) 68211 { 68212 ICLASS: VSCATTERQPD 68213 CPL: 3 68214 CATEGORY: SCATTER 68215 EXTENSION: AVX512EVEX 68216 ISA_SET: AVX512F_128 68217 EXCEPTIONS: AVX512-E12 68218 REAL_OPCODE: Y 68219 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 68220 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W1 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 68221 OPERANDS: MEM0:w:dq:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 68222 IFORM: VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 68223 } 68224 68225 68226 # EMITTING VSCATTERQPD (VSCATTERQPD-256-1) 68227 { 68228 ICLASS: VSCATTERQPD 68229 CPL: 3 68230 CATEGORY: SCATTER 68231 EXTENSION: AVX512EVEX 68232 ISA_SET: AVX512F_256 68233 EXCEPTIONS: AVX512-E12 68234 REAL_OPCODE: Y 68235 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 68236 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 68237 OPERANDS: MEM0:w:qq:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 68238 IFORM: VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 68239 } 68240 68241 68242 # EMITTING VSCATTERQPS (VSCATTERQPS-128-1) 68243 { 68244 ICLASS: VSCATTERQPS 68245 CPL: 3 68246 CATEGORY: SCATTER 68247 EXTENSION: AVX512EVEX 68248 ISA_SET: AVX512F_128 68249 EXCEPTIONS: AVX512-E12 68250 REAL_OPCODE: Y 68251 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 68252 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL128 W0 RM=4 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 68253 OPERANDS: MEM0:w:q:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 68254 IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 68255 } 68256 68257 68258 # EMITTING VSCATTERQPS (VSCATTERQPS-256-1) 68259 { 68260 ICLASS: VSCATTERQPS 68261 CPL: 3 68262 CATEGORY: SCATTER 68263 EXTENSION: AVX512EVEX 68264 ISA_SET: AVX512F_256 68265 EXCEPTIONS: AVX512-E12 68266 REAL_OPCODE: Y 68267 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER MASKOP_EVEX DISP8_GSCAT 68268 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 VL256 W0 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 68269 OPERANDS: MEM0:w:dq:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 68270 IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 68271 } 68272 68273 68274 # EMITTING VSHUFF32X4 (VSHUFF32X4-256-1) 68275 { 68276 ICLASS: VSHUFF32X4 68277 CPL: 3 68278 CATEGORY: AVX512 68279 EXTENSION: AVX512EVEX 68280 ISA_SET: AVX512F_256 68281 EXCEPTIONS: AVX512-E4NF 68282 REAL_OPCODE: Y 68283 ATTRIBUTES: MASKOP_EVEX 68284 PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 68285 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 68286 IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 68287 } 68288 68289 { 68290 ICLASS: VSHUFF32X4 68291 CPL: 3 68292 CATEGORY: AVX512 68293 EXTENSION: AVX512EVEX 68294 ISA_SET: AVX512F_256 68295 EXCEPTIONS: AVX512-E4NF 68296 REAL_OPCODE: Y 68297 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68298 PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 68299 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 68300 IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 68301 } 68302 68303 68304 # EMITTING VSHUFF64X2 (VSHUFF64X2-256-1) 68305 { 68306 ICLASS: VSHUFF64X2 68307 CPL: 3 68308 CATEGORY: AVX512 68309 EXTENSION: AVX512EVEX 68310 ISA_SET: AVX512F_256 68311 EXCEPTIONS: AVX512-E4NF 68312 REAL_OPCODE: Y 68313 ATTRIBUTES: MASKOP_EVEX 68314 PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 68315 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 68316 IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 68317 } 68318 68319 { 68320 ICLASS: VSHUFF64X2 68321 CPL: 3 68322 CATEGORY: AVX512 68323 EXTENSION: AVX512EVEX 68324 ISA_SET: AVX512F_256 68325 EXCEPTIONS: AVX512-E4NF 68326 REAL_OPCODE: Y 68327 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68328 PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 68329 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 68330 IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 68331 } 68332 68333 68334 # EMITTING VSHUFI32X4 (VSHUFI32X4-256-1) 68335 { 68336 ICLASS: VSHUFI32X4 68337 CPL: 3 68338 CATEGORY: AVX512 68339 EXTENSION: AVX512EVEX 68340 ISA_SET: AVX512F_256 68341 EXCEPTIONS: AVX512-E4NF 68342 REAL_OPCODE: Y 68343 ATTRIBUTES: MASKOP_EVEX 68344 PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 68345 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 68346 IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 68347 } 68348 68349 { 68350 ICLASS: VSHUFI32X4 68351 CPL: 3 68352 CATEGORY: AVX512 68353 EXTENSION: AVX512EVEX 68354 ISA_SET: AVX512F_256 68355 EXCEPTIONS: AVX512-E4NF 68356 REAL_OPCODE: Y 68357 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68358 PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 68359 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 68360 IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 68361 } 68362 68363 68364 # EMITTING VSHUFI64X2 (VSHUFI64X2-256-1) 68365 { 68366 ICLASS: VSHUFI64X2 68367 CPL: 3 68368 CATEGORY: AVX512 68369 EXTENSION: AVX512EVEX 68370 ISA_SET: AVX512F_256 68371 EXCEPTIONS: AVX512-E4NF 68372 REAL_OPCODE: Y 68373 ATTRIBUTES: MASKOP_EVEX 68374 PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 68375 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 68376 IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 68377 } 68378 68379 { 68380 ICLASS: VSHUFI64X2 68381 CPL: 3 68382 CATEGORY: AVX512 68383 EXTENSION: AVX512EVEX 68384 ISA_SET: AVX512F_256 68385 EXCEPTIONS: AVX512-E4NF 68386 REAL_OPCODE: Y 68387 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68388 PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 68389 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 68390 IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 68391 } 68392 68393 68394 # EMITTING VSHUFPD (VSHUFPD-128-1) 68395 { 68396 ICLASS: VSHUFPD 68397 CPL: 3 68398 CATEGORY: AVX512 68399 EXTENSION: AVX512EVEX 68400 ISA_SET: AVX512F_128 68401 EXCEPTIONS: AVX512-E4NF 68402 REAL_OPCODE: Y 68403 ATTRIBUTES: MASKOP_EVEX 68404 PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 68405 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 68406 IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 68407 } 68408 68409 { 68410 ICLASS: VSHUFPD 68411 CPL: 3 68412 CATEGORY: AVX512 68413 EXTENSION: AVX512EVEX 68414 ISA_SET: AVX512F_128 68415 EXCEPTIONS: AVX512-E4NF 68416 REAL_OPCODE: Y 68417 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68418 PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 68419 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 68420 IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 68421 } 68422 68423 68424 # EMITTING VSHUFPD (VSHUFPD-256-1) 68425 { 68426 ICLASS: VSHUFPD 68427 CPL: 3 68428 CATEGORY: AVX512 68429 EXTENSION: AVX512EVEX 68430 ISA_SET: AVX512F_256 68431 EXCEPTIONS: AVX512-E4NF 68432 REAL_OPCODE: Y 68433 ATTRIBUTES: MASKOP_EVEX 68434 PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 68435 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 68436 IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 68437 } 68438 68439 { 68440 ICLASS: VSHUFPD 68441 CPL: 3 68442 CATEGORY: AVX512 68443 EXTENSION: AVX512EVEX 68444 ISA_SET: AVX512F_256 68445 EXCEPTIONS: AVX512-E4NF 68446 REAL_OPCODE: Y 68447 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68448 PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 68449 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 68450 IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 68451 } 68452 68453 68454 # EMITTING VSHUFPS (VSHUFPS-128-1) 68455 { 68456 ICLASS: VSHUFPS 68457 CPL: 3 68458 CATEGORY: AVX512 68459 EXTENSION: AVX512EVEX 68460 ISA_SET: AVX512F_128 68461 EXCEPTIONS: AVX512-E4NF 68462 REAL_OPCODE: Y 68463 ATTRIBUTES: MASKOP_EVEX 68464 PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 68465 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 68466 IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 68467 } 68468 68469 { 68470 ICLASS: VSHUFPS 68471 CPL: 3 68472 CATEGORY: AVX512 68473 EXTENSION: AVX512EVEX 68474 ISA_SET: AVX512F_128 68475 EXCEPTIONS: AVX512-E4NF 68476 REAL_OPCODE: Y 68477 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68478 PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 68479 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 68480 IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 68481 } 68482 68483 68484 # EMITTING VSHUFPS (VSHUFPS-256-1) 68485 { 68486 ICLASS: VSHUFPS 68487 CPL: 3 68488 CATEGORY: AVX512 68489 EXTENSION: AVX512EVEX 68490 ISA_SET: AVX512F_256 68491 EXCEPTIONS: AVX512-E4NF 68492 REAL_OPCODE: Y 68493 ATTRIBUTES: MASKOP_EVEX 68494 PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 68495 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 68496 IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 68497 } 68498 68499 { 68500 ICLASS: VSHUFPS 68501 CPL: 3 68502 CATEGORY: AVX512 68503 EXTENSION: AVX512EVEX 68504 ISA_SET: AVX512F_256 68505 EXCEPTIONS: AVX512-E4NF 68506 REAL_OPCODE: Y 68507 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68508 PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 68509 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 68510 IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 68511 } 68512 68513 68514 # EMITTING VSQRTPD (VSQRTPD-128-1) 68515 { 68516 ICLASS: VSQRTPD 68517 CPL: 3 68518 CATEGORY: AVX512 68519 EXTENSION: AVX512EVEX 68520 ISA_SET: AVX512F_128 68521 EXCEPTIONS: AVX512-E2 68522 REAL_OPCODE: Y 68523 ATTRIBUTES: MXCSR MASKOP_EVEX 68524 PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 68525 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 68526 IFORM: VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 68527 } 68528 68529 { 68530 ICLASS: VSQRTPD 68531 CPL: 3 68532 CATEGORY: AVX512 68533 EXTENSION: AVX512EVEX 68534 ISA_SET: AVX512F_128 68535 EXCEPTIONS: AVX512-E2 68536 REAL_OPCODE: Y 68537 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68538 PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 68539 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 68540 IFORM: VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 68541 } 68542 68543 68544 # EMITTING VSQRTPD (VSQRTPD-256-1) 68545 { 68546 ICLASS: VSQRTPD 68547 CPL: 3 68548 CATEGORY: AVX512 68549 EXTENSION: AVX512EVEX 68550 ISA_SET: AVX512F_256 68551 EXCEPTIONS: AVX512-E2 68552 REAL_OPCODE: Y 68553 ATTRIBUTES: MXCSR MASKOP_EVEX 68554 PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 68555 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 68556 IFORM: VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 68557 } 68558 68559 { 68560 ICLASS: VSQRTPD 68561 CPL: 3 68562 CATEGORY: AVX512 68563 EXTENSION: AVX512EVEX 68564 ISA_SET: AVX512F_256 68565 EXCEPTIONS: AVX512-E2 68566 REAL_OPCODE: Y 68567 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68568 PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 68569 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 68570 IFORM: VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 68571 } 68572 68573 68574 # EMITTING VSQRTPS (VSQRTPS-128-1) 68575 { 68576 ICLASS: VSQRTPS 68577 CPL: 3 68578 CATEGORY: AVX512 68579 EXTENSION: AVX512EVEX 68580 ISA_SET: AVX512F_128 68581 EXCEPTIONS: AVX512-E2 68582 REAL_OPCODE: Y 68583 ATTRIBUTES: MXCSR MASKOP_EVEX 68584 PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 68585 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 68586 IFORM: VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 68587 } 68588 68589 { 68590 ICLASS: VSQRTPS 68591 CPL: 3 68592 CATEGORY: AVX512 68593 EXTENSION: AVX512EVEX 68594 ISA_SET: AVX512F_128 68595 EXCEPTIONS: AVX512-E2 68596 REAL_OPCODE: Y 68597 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68598 PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 68599 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 68600 IFORM: VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 68601 } 68602 68603 68604 # EMITTING VSQRTPS (VSQRTPS-256-1) 68605 { 68606 ICLASS: VSQRTPS 68607 CPL: 3 68608 CATEGORY: AVX512 68609 EXTENSION: AVX512EVEX 68610 ISA_SET: AVX512F_256 68611 EXCEPTIONS: AVX512-E2 68612 REAL_OPCODE: Y 68613 ATTRIBUTES: MXCSR MASKOP_EVEX 68614 PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 68615 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 68616 IFORM: VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 68617 } 68618 68619 { 68620 ICLASS: VSQRTPS 68621 CPL: 3 68622 CATEGORY: AVX512 68623 EXTENSION: AVX512EVEX 68624 ISA_SET: AVX512F_256 68625 EXCEPTIONS: AVX512-E2 68626 REAL_OPCODE: Y 68627 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68628 PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 68629 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 68630 IFORM: VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 68631 } 68632 68633 68634 # EMITTING VSUBPD (VSUBPD-128-1) 68635 { 68636 ICLASS: VSUBPD 68637 CPL: 3 68638 CATEGORY: AVX512 68639 EXTENSION: AVX512EVEX 68640 ISA_SET: AVX512F_128 68641 EXCEPTIONS: AVX512-E2 68642 REAL_OPCODE: Y 68643 ATTRIBUTES: MXCSR MASKOP_EVEX 68644 PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 68645 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 68646 IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 68647 } 68648 68649 { 68650 ICLASS: VSUBPD 68651 CPL: 3 68652 CATEGORY: AVX512 68653 EXTENSION: AVX512EVEX 68654 ISA_SET: AVX512F_128 68655 EXCEPTIONS: AVX512-E2 68656 REAL_OPCODE: Y 68657 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68658 PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 68659 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 68660 IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 68661 } 68662 68663 68664 # EMITTING VSUBPD (VSUBPD-256-1) 68665 { 68666 ICLASS: VSUBPD 68667 CPL: 3 68668 CATEGORY: AVX512 68669 EXTENSION: AVX512EVEX 68670 ISA_SET: AVX512F_256 68671 EXCEPTIONS: AVX512-E2 68672 REAL_OPCODE: Y 68673 ATTRIBUTES: MXCSR MASKOP_EVEX 68674 PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 68675 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 68676 IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 68677 } 68678 68679 { 68680 ICLASS: VSUBPD 68681 CPL: 3 68682 CATEGORY: AVX512 68683 EXTENSION: AVX512EVEX 68684 ISA_SET: AVX512F_256 68685 EXCEPTIONS: AVX512-E2 68686 REAL_OPCODE: Y 68687 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68688 PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 68689 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 68690 IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 68691 } 68692 68693 68694 # EMITTING VSUBPS (VSUBPS-128-1) 68695 { 68696 ICLASS: VSUBPS 68697 CPL: 3 68698 CATEGORY: AVX512 68699 EXTENSION: AVX512EVEX 68700 ISA_SET: AVX512F_128 68701 EXCEPTIONS: AVX512-E2 68702 REAL_OPCODE: Y 68703 ATTRIBUTES: MXCSR MASKOP_EVEX 68704 PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 68705 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 68706 IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 68707 } 68708 68709 { 68710 ICLASS: VSUBPS 68711 CPL: 3 68712 CATEGORY: AVX512 68713 EXTENSION: AVX512EVEX 68714 ISA_SET: AVX512F_128 68715 EXCEPTIONS: AVX512-E2 68716 REAL_OPCODE: Y 68717 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68718 PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 68719 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 68720 IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 68721 } 68722 68723 68724 # EMITTING VSUBPS (VSUBPS-256-1) 68725 { 68726 ICLASS: VSUBPS 68727 CPL: 3 68728 CATEGORY: AVX512 68729 EXTENSION: AVX512EVEX 68730 ISA_SET: AVX512F_256 68731 EXCEPTIONS: AVX512-E2 68732 REAL_OPCODE: Y 68733 ATTRIBUTES: MXCSR MASKOP_EVEX 68734 PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 68735 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 68736 IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 68737 } 68738 68739 { 68740 ICLASS: VSUBPS 68741 CPL: 3 68742 CATEGORY: AVX512 68743 EXTENSION: AVX512EVEX 68744 ISA_SET: AVX512F_256 68745 EXCEPTIONS: AVX512-E2 68746 REAL_OPCODE: Y 68747 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68748 PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 68749 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 68750 IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 68751 } 68752 68753 68754 # EMITTING VUNPCKHPD (VUNPCKHPD-128-1) 68755 { 68756 ICLASS: VUNPCKHPD 68757 CPL: 3 68758 CATEGORY: AVX512 68759 EXTENSION: AVX512EVEX 68760 ISA_SET: AVX512F_128 68761 EXCEPTIONS: AVX512-E4NF 68762 REAL_OPCODE: Y 68763 ATTRIBUTES: MASKOP_EVEX 68764 PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 68765 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 68766 IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 68767 } 68768 68769 { 68770 ICLASS: VUNPCKHPD 68771 CPL: 3 68772 CATEGORY: AVX512 68773 EXTENSION: AVX512EVEX 68774 ISA_SET: AVX512F_128 68775 EXCEPTIONS: AVX512-E4NF 68776 REAL_OPCODE: Y 68777 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68778 PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 68779 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 68780 IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 68781 } 68782 68783 68784 # EMITTING VUNPCKHPD (VUNPCKHPD-256-1) 68785 { 68786 ICLASS: VUNPCKHPD 68787 CPL: 3 68788 CATEGORY: AVX512 68789 EXTENSION: AVX512EVEX 68790 ISA_SET: AVX512F_256 68791 EXCEPTIONS: AVX512-E4NF 68792 REAL_OPCODE: Y 68793 ATTRIBUTES: MASKOP_EVEX 68794 PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 68795 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 68796 IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 68797 } 68798 68799 { 68800 ICLASS: VUNPCKHPD 68801 CPL: 3 68802 CATEGORY: AVX512 68803 EXTENSION: AVX512EVEX 68804 ISA_SET: AVX512F_256 68805 EXCEPTIONS: AVX512-E4NF 68806 REAL_OPCODE: Y 68807 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68808 PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 68809 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 68810 IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 68811 } 68812 68813 68814 # EMITTING VUNPCKHPS (VUNPCKHPS-128-1) 68815 { 68816 ICLASS: VUNPCKHPS 68817 CPL: 3 68818 CATEGORY: AVX512 68819 EXTENSION: AVX512EVEX 68820 ISA_SET: AVX512F_128 68821 EXCEPTIONS: AVX512-E4NF 68822 REAL_OPCODE: Y 68823 ATTRIBUTES: MASKOP_EVEX 68824 PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 68825 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 68826 IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 68827 } 68828 68829 { 68830 ICLASS: VUNPCKHPS 68831 CPL: 3 68832 CATEGORY: AVX512 68833 EXTENSION: AVX512EVEX 68834 ISA_SET: AVX512F_128 68835 EXCEPTIONS: AVX512-E4NF 68836 REAL_OPCODE: Y 68837 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68838 PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 68839 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 68840 IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 68841 } 68842 68843 68844 # EMITTING VUNPCKHPS (VUNPCKHPS-256-1) 68845 { 68846 ICLASS: VUNPCKHPS 68847 CPL: 3 68848 CATEGORY: AVX512 68849 EXTENSION: AVX512EVEX 68850 ISA_SET: AVX512F_256 68851 EXCEPTIONS: AVX512-E4NF 68852 REAL_OPCODE: Y 68853 ATTRIBUTES: MASKOP_EVEX 68854 PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 68855 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 68856 IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 68857 } 68858 68859 { 68860 ICLASS: VUNPCKHPS 68861 CPL: 3 68862 CATEGORY: AVX512 68863 EXTENSION: AVX512EVEX 68864 ISA_SET: AVX512F_256 68865 EXCEPTIONS: AVX512-E4NF 68866 REAL_OPCODE: Y 68867 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68868 PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 68869 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 68870 IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 68871 } 68872 68873 68874 # EMITTING VUNPCKLPD (VUNPCKLPD-128-1) 68875 { 68876 ICLASS: VUNPCKLPD 68877 CPL: 3 68878 CATEGORY: AVX512 68879 EXTENSION: AVX512EVEX 68880 ISA_SET: AVX512F_128 68881 EXCEPTIONS: AVX512-E4NF 68882 REAL_OPCODE: Y 68883 ATTRIBUTES: MASKOP_EVEX 68884 PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 68885 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 68886 IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 68887 } 68888 68889 { 68890 ICLASS: VUNPCKLPD 68891 CPL: 3 68892 CATEGORY: AVX512 68893 EXTENSION: AVX512EVEX 68894 ISA_SET: AVX512F_128 68895 EXCEPTIONS: AVX512-E4NF 68896 REAL_OPCODE: Y 68897 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68898 PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 68899 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 68900 IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 68901 } 68902 68903 68904 # EMITTING VUNPCKLPD (VUNPCKLPD-256-1) 68905 { 68906 ICLASS: VUNPCKLPD 68907 CPL: 3 68908 CATEGORY: AVX512 68909 EXTENSION: AVX512EVEX 68910 ISA_SET: AVX512F_256 68911 EXCEPTIONS: AVX512-E4NF 68912 REAL_OPCODE: Y 68913 ATTRIBUTES: MASKOP_EVEX 68914 PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 68915 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 68916 IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 68917 } 68918 68919 { 68920 ICLASS: VUNPCKLPD 68921 CPL: 3 68922 CATEGORY: AVX512 68923 EXTENSION: AVX512EVEX 68924 ISA_SET: AVX512F_256 68925 EXCEPTIONS: AVX512-E4NF 68926 REAL_OPCODE: Y 68927 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68928 PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 68929 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 68930 IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 68931 } 68932 68933 68934 # EMITTING VUNPCKLPS (VUNPCKLPS-128-1) 68935 { 68936 ICLASS: VUNPCKLPS 68937 CPL: 3 68938 CATEGORY: AVX512 68939 EXTENSION: AVX512EVEX 68940 ISA_SET: AVX512F_128 68941 EXCEPTIONS: AVX512-E4NF 68942 REAL_OPCODE: Y 68943 ATTRIBUTES: MASKOP_EVEX 68944 PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 68945 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 68946 IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 68947 } 68948 68949 { 68950 ICLASS: VUNPCKLPS 68951 CPL: 3 68952 CATEGORY: AVX512 68953 EXTENSION: AVX512EVEX 68954 ISA_SET: AVX512F_128 68955 EXCEPTIONS: AVX512-E4NF 68956 REAL_OPCODE: Y 68957 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68958 PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 68959 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 68960 IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 68961 } 68962 68963 68964 # EMITTING VUNPCKLPS (VUNPCKLPS-256-1) 68965 { 68966 ICLASS: VUNPCKLPS 68967 CPL: 3 68968 CATEGORY: AVX512 68969 EXTENSION: AVX512EVEX 68970 ISA_SET: AVX512F_256 68971 EXCEPTIONS: AVX512-E4NF 68972 REAL_OPCODE: Y 68973 ATTRIBUTES: MASKOP_EVEX 68974 PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 68975 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 68976 IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 68977 } 68978 68979 { 68980 ICLASS: VUNPCKLPS 68981 CPL: 3 68982 CATEGORY: AVX512 68983 EXTENSION: AVX512EVEX 68984 ISA_SET: AVX512F_256 68985 EXCEPTIONS: AVX512-E4NF 68986 REAL_OPCODE: Y 68987 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 68988 PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 68989 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 68990 IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 68991 } 68992 68993 68994 # EMITTING VXORPD (VXORPD-128-1) 68995 { 68996 ICLASS: VXORPD 68997 CPL: 3 68998 CATEGORY: LOGICAL_FP 68999 EXTENSION: AVX512EVEX 69000 ISA_SET: AVX512DQ_128 69001 EXCEPTIONS: AVX512-E4 69002 REAL_OPCODE: Y 69003 ATTRIBUTES: MASKOP_EVEX 69004 PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 69005 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 69006 IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 69007 } 69008 69009 { 69010 ICLASS: VXORPD 69011 CPL: 3 69012 CATEGORY: LOGICAL_FP 69013 EXTENSION: AVX512EVEX 69014 ISA_SET: AVX512DQ_128 69015 EXCEPTIONS: AVX512-E4 69016 REAL_OPCODE: Y 69017 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 69018 PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 69019 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 69020 IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 69021 } 69022 69023 69024 # EMITTING VXORPD (VXORPD-256-1) 69025 { 69026 ICLASS: VXORPD 69027 CPL: 3 69028 CATEGORY: LOGICAL_FP 69029 EXTENSION: AVX512EVEX 69030 ISA_SET: AVX512DQ_256 69031 EXCEPTIONS: AVX512-E4 69032 REAL_OPCODE: Y 69033 ATTRIBUTES: MASKOP_EVEX 69034 PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 69035 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 69036 IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 69037 } 69038 69039 { 69040 ICLASS: VXORPD 69041 CPL: 3 69042 CATEGORY: LOGICAL_FP 69043 EXTENSION: AVX512EVEX 69044 ISA_SET: AVX512DQ_256 69045 EXCEPTIONS: AVX512-E4 69046 REAL_OPCODE: Y 69047 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 69048 PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 69049 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 69050 IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 69051 } 69052 69053 69054 # EMITTING VXORPD (VXORPD-512-1) 69055 { 69056 ICLASS: VXORPD 69057 CPL: 3 69058 CATEGORY: LOGICAL_FP 69059 EXTENSION: AVX512EVEX 69060 ISA_SET: AVX512DQ_512 69061 EXCEPTIONS: AVX512-E4 69062 REAL_OPCODE: Y 69063 ATTRIBUTES: MASKOP_EVEX 69064 PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 69065 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 69066 IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 69067 } 69068 69069 { 69070 ICLASS: VXORPD 69071 CPL: 3 69072 CATEGORY: LOGICAL_FP 69073 EXTENSION: AVX512EVEX 69074 ISA_SET: AVX512DQ_512 69075 EXCEPTIONS: AVX512-E4 69076 REAL_OPCODE: Y 69077 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 69078 PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 69079 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 69080 IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 69081 } 69082 69083 69084 # EMITTING VXORPS (VXORPS-128-1) 69085 { 69086 ICLASS: VXORPS 69087 CPL: 3 69088 CATEGORY: LOGICAL_FP 69089 EXTENSION: AVX512EVEX 69090 ISA_SET: AVX512DQ_128 69091 EXCEPTIONS: AVX512-E4 69092 REAL_OPCODE: Y 69093 ATTRIBUTES: MASKOP_EVEX 69094 PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 69095 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 69096 IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 69097 } 69098 69099 { 69100 ICLASS: VXORPS 69101 CPL: 3 69102 CATEGORY: LOGICAL_FP 69103 EXTENSION: AVX512EVEX 69104 ISA_SET: AVX512DQ_128 69105 EXCEPTIONS: AVX512-E4 69106 REAL_OPCODE: Y 69107 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 69108 PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 69109 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 69110 IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 69111 } 69112 69113 69114 # EMITTING VXORPS (VXORPS-256-1) 69115 { 69116 ICLASS: VXORPS 69117 CPL: 3 69118 CATEGORY: LOGICAL_FP 69119 EXTENSION: AVX512EVEX 69120 ISA_SET: AVX512DQ_256 69121 EXCEPTIONS: AVX512-E4 69122 REAL_OPCODE: Y 69123 ATTRIBUTES: MASKOP_EVEX 69124 PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 69125 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 69126 IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 69127 } 69128 69129 { 69130 ICLASS: VXORPS 69131 CPL: 3 69132 CATEGORY: LOGICAL_FP 69133 EXTENSION: AVX512EVEX 69134 ISA_SET: AVX512DQ_256 69135 EXCEPTIONS: AVX512-E4 69136 REAL_OPCODE: Y 69137 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 69138 PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 69139 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 69140 IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 69141 } 69142 69143 69144 # EMITTING VXORPS (VXORPS-512-1) 69145 { 69146 ICLASS: VXORPS 69147 CPL: 3 69148 CATEGORY: LOGICAL_FP 69149 EXTENSION: AVX512EVEX 69150 ISA_SET: AVX512DQ_512 69151 EXCEPTIONS: AVX512-E4 69152 REAL_OPCODE: Y 69153 ATTRIBUTES: MASKOP_EVEX 69154 PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 69155 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 69156 IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 69157 } 69158 69159 { 69160 ICLASS: VXORPS 69161 CPL: 3 69162 CATEGORY: LOGICAL_FP 69163 EXTENSION: AVX512EVEX 69164 ISA_SET: AVX512DQ_512 69165 EXCEPTIONS: AVX512-E4 69166 REAL_OPCODE: Y 69167 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 69168 PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 69169 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 69170 IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 69171 } 69172 69173 69174 AVX_INSTRUCTIONS():: 69175 # EMITTING KADDB (KADDB-256-1) 69176 { 69177 ICLASS: KADDB 69178 CPL: 3 69179 CATEGORY: KMASK 69180 EXTENSION: AVX512VEX 69181 ISA_SET: AVX512DQ_KOP 69182 EXCEPTIONS: AVX512-K20 69183 REAL_OPCODE: Y 69184 ATTRIBUTES: KMASK 69185 PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 69186 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69187 IFORM: KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 69188 } 69189 69190 69191 # EMITTING KADDD (KADDD-256-1) 69192 { 69193 ICLASS: KADDD 69194 CPL: 3 69195 CATEGORY: KMASK 69196 EXTENSION: AVX512VEX 69197 ISA_SET: AVX512BW_KOP 69198 EXCEPTIONS: AVX512-K20 69199 REAL_OPCODE: Y 69200 ATTRIBUTES: KMASK 69201 PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69202 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69203 IFORM: KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 69204 } 69205 69206 69207 # EMITTING KADDQ (KADDQ-256-1) 69208 { 69209 ICLASS: KADDQ 69210 CPL: 3 69211 CATEGORY: KMASK 69212 EXTENSION: AVX512VEX 69213 ISA_SET: AVX512BW_KOP 69214 EXCEPTIONS: AVX512-K20 69215 REAL_OPCODE: Y 69216 ATTRIBUTES: KMASK 69217 PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69218 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69219 IFORM: KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 69220 } 69221 69222 69223 # EMITTING KADDW (KADDW-256-1) 69224 { 69225 ICLASS: KADDW 69226 CPL: 3 69227 CATEGORY: KMASK 69228 EXTENSION: AVX512VEX 69229 ISA_SET: AVX512DQ_KOP 69230 EXCEPTIONS: AVX512-K20 69231 REAL_OPCODE: Y 69232 ATTRIBUTES: KMASK 69233 PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 69234 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69235 IFORM: KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 69236 } 69237 69238 69239 # EMITTING KANDB (KANDB-256-1) 69240 { 69241 ICLASS: KANDB 69242 CPL: 3 69243 CATEGORY: KMASK 69244 EXTENSION: AVX512VEX 69245 ISA_SET: AVX512DQ_KOP 69246 EXCEPTIONS: AVX512-K20 69247 REAL_OPCODE: Y 69248 ATTRIBUTES: KMASK 69249 PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 69250 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69251 IFORM: KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 69252 } 69253 69254 69255 # EMITTING KANDD (KANDD-256-1) 69256 { 69257 ICLASS: KANDD 69258 CPL: 3 69259 CATEGORY: KMASK 69260 EXTENSION: AVX512VEX 69261 ISA_SET: AVX512BW_KOP 69262 EXCEPTIONS: AVX512-K20 69263 REAL_OPCODE: Y 69264 ATTRIBUTES: KMASK 69265 PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69266 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69267 IFORM: KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 69268 } 69269 69270 69271 # EMITTING KANDNB (KANDNB-256-1) 69272 { 69273 ICLASS: KANDNB 69274 CPL: 3 69275 CATEGORY: KMASK 69276 EXTENSION: AVX512VEX 69277 ISA_SET: AVX512DQ_KOP 69278 EXCEPTIONS: AVX512-K20 69279 REAL_OPCODE: Y 69280 ATTRIBUTES: KMASK 69281 PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 69282 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69283 IFORM: KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 69284 } 69285 69286 69287 # EMITTING KANDND (KANDND-256-1) 69288 { 69289 ICLASS: KANDND 69290 CPL: 3 69291 CATEGORY: KMASK 69292 EXTENSION: AVX512VEX 69293 ISA_SET: AVX512BW_KOP 69294 EXCEPTIONS: AVX512-K20 69295 REAL_OPCODE: Y 69296 ATTRIBUTES: KMASK 69297 PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69298 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69299 IFORM: KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 69300 } 69301 69302 69303 # EMITTING KANDNQ (KANDNQ-256-1) 69304 { 69305 ICLASS: KANDNQ 69306 CPL: 3 69307 CATEGORY: KMASK 69308 EXTENSION: AVX512VEX 69309 ISA_SET: AVX512BW_KOP 69310 EXCEPTIONS: AVX512-K20 69311 REAL_OPCODE: Y 69312 ATTRIBUTES: KMASK 69313 PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69314 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69315 IFORM: KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 69316 } 69317 69318 69319 # EMITTING KANDQ (KANDQ-256-1) 69320 { 69321 ICLASS: KANDQ 69322 CPL: 3 69323 CATEGORY: KMASK 69324 EXTENSION: AVX512VEX 69325 ISA_SET: AVX512BW_KOP 69326 EXCEPTIONS: AVX512-K20 69327 REAL_OPCODE: Y 69328 ATTRIBUTES: KMASK 69329 PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69330 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69331 IFORM: KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 69332 } 69333 69334 69335 # EMITTING KMOVB (KMOVB-128-1) 69336 { 69337 ICLASS: KMOVB 69338 CPL: 3 69339 CATEGORY: KMASK 69340 EXTENSION: AVX512VEX 69341 ISA_SET: AVX512DQ_KOP 69342 EXCEPTIONS: AVX512-K21 69343 REAL_OPCODE: Y 69344 ATTRIBUTES: KMASK 69345 PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 69346 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u8 69347 IFORM: KMOVB_MASKmskw_MASKu8_AVX512 69348 } 69349 69350 { 69351 ICLASS: KMOVB 69352 CPL: 3 69353 CATEGORY: KMASK 69354 EXTENSION: AVX512VEX 69355 ISA_SET: AVX512DQ_KOP 69356 EXCEPTIONS: AVX512-K21 69357 REAL_OPCODE: Y 69358 ATTRIBUTES: KMASK 69359 PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR 69360 OPERANDS: REG0=MASK_R():w:mskw MEM0:r:b:u8 69361 IFORM: KMOVB_MASKmskw_MEMu8_AVX512 69362 } 69363 69364 69365 # EMITTING KMOVB (KMOVB-128-2) 69366 { 69367 ICLASS: KMOVB 69368 CPL: 3 69369 CATEGORY: KMASK 69370 EXTENSION: AVX512VEX 69371 ISA_SET: AVX512DQ_KOP 69372 EXCEPTIONS: AVX512-K21 69373 REAL_OPCODE: Y 69374 ATTRIBUTES: KMASK 69375 PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR 69376 OPERANDS: MEM0:w:b:u8 REG0=MASK_R():r:mskw 69377 IFORM: KMOVB_MEMu8_MASKmskw_AVX512 69378 } 69379 69380 69381 # EMITTING KMOVB (KMOVB-128-3) 69382 { 69383 ICLASS: KMOVB 69384 CPL: 3 69385 CATEGORY: KMASK 69386 EXTENSION: AVX512VEX 69387 ISA_SET: AVX512DQ_KOP 69388 EXCEPTIONS: AVX512-K20 69389 REAL_OPCODE: Y 69390 ATTRIBUTES: KMASK 69391 PATTERN: VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 69392 OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 69393 IFORM: KMOVB_MASKmskw_GPR32u32_AVX512 69394 } 69395 69396 69397 # EMITTING KMOVB (KMOVB-128-4) 69398 { 69399 ICLASS: KMOVB 69400 CPL: 3 69401 CATEGORY: KMASK 69402 EXTENSION: AVX512VEX 69403 ISA_SET: AVX512DQ_KOP 69404 EXCEPTIONS: AVX512-K20 69405 REAL_OPCODE: Y 69406 ATTRIBUTES: KMASK 69407 PATTERN: VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 69408 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw 69409 IFORM: KMOVB_GPR32u32_MASKmskw_AVX512 69410 } 69411 69412 69413 # EMITTING KMOVD (KMOVD-128-1) 69414 { 69415 ICLASS: KMOVD 69416 CPL: 3 69417 CATEGORY: KMASK 69418 EXTENSION: AVX512VEX 69419 ISA_SET: AVX512BW_KOP 69420 EXCEPTIONS: AVX512-K21 69421 REAL_OPCODE: Y 69422 ATTRIBUTES: KMASK 69423 PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 69424 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u32 69425 IFORM: KMOVD_MASKmskw_MASKu32_AVX512 69426 } 69427 69428 { 69429 ICLASS: KMOVD 69430 CPL: 3 69431 CATEGORY: KMASK 69432 EXTENSION: AVX512VEX 69433 ISA_SET: AVX512BW_KOP 69434 EXCEPTIONS: AVX512-K21 69435 REAL_OPCODE: Y 69436 ATTRIBUTES: KMASK 69437 PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR 69438 OPERANDS: REG0=MASK_R():w:mskw MEM0:r:d:u32 69439 IFORM: KMOVD_MASKmskw_MEMu32_AVX512 69440 } 69441 69442 69443 # EMITTING KMOVD (KMOVD-128-2) 69444 { 69445 ICLASS: KMOVD 69446 CPL: 3 69447 CATEGORY: KMASK 69448 EXTENSION: AVX512VEX 69449 ISA_SET: AVX512BW_KOP 69450 EXCEPTIONS: AVX512-K21 69451 REAL_OPCODE: Y 69452 ATTRIBUTES: KMASK 69453 PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR 69454 OPERANDS: MEM0:w:d:u32 REG0=MASK_R():r:mskw 69455 IFORM: KMOVD_MEMu32_MASKmskw_AVX512 69456 } 69457 69458 69459 # EMITTING KMOVD (KMOVD-128-3) 69460 { 69461 ICLASS: KMOVD 69462 CPL: 3 69463 CATEGORY: KMASK 69464 EXTENSION: AVX512VEX 69465 ISA_SET: AVX512BW_KOP 69466 EXCEPTIONS: AVX512-K20 69467 REAL_OPCODE: Y 69468 ATTRIBUTES: KMASK 69469 PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 69470 OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 69471 IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 69472 } 69473 69474 69475 # EMITTING KMOVD (KMOVD-128-4) 69476 { 69477 ICLASS: KMOVD 69478 CPL: 3 69479 CATEGORY: KMASK 69480 EXTENSION: AVX512VEX 69481 ISA_SET: AVX512BW_KOP 69482 EXCEPTIONS: AVX512-K20 69483 REAL_OPCODE: Y 69484 ATTRIBUTES: KMASK 69485 PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 69486 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw 69487 IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 69488 } 69489 69490 69491 # EMITTING KMOVQ (KMOVQ-128-1) 69492 { 69493 ICLASS: KMOVQ 69494 CPL: 3 69495 CATEGORY: KMASK 69496 EXTENSION: AVX512VEX 69497 ISA_SET: AVX512BW_KOP 69498 EXCEPTIONS: AVX512-K21 69499 REAL_OPCODE: Y 69500 ATTRIBUTES: KMASK 69501 PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 69502 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64 69503 IFORM: KMOVQ_MASKmskw_MASKu64_AVX512 69504 } 69505 69506 { 69507 ICLASS: KMOVQ 69508 CPL: 3 69509 CATEGORY: KMASK 69510 EXTENSION: AVX512VEX 69511 ISA_SET: AVX512BW_KOP 69512 EXCEPTIONS: AVX512-K21 69513 REAL_OPCODE: Y 69514 ATTRIBUTES: KMASK 69515 PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR 69516 OPERANDS: REG0=MASK_R():w:mskw MEM0:r:q:u64 69517 IFORM: KMOVQ_MASKmskw_MEMu64_AVX512 69518 } 69519 69520 69521 # EMITTING KMOVQ (KMOVQ-128-2) 69522 { 69523 ICLASS: KMOVQ 69524 CPL: 3 69525 CATEGORY: KMASK 69526 EXTENSION: AVX512VEX 69527 ISA_SET: AVX512BW_KOP 69528 EXCEPTIONS: AVX512-K21 69529 REAL_OPCODE: Y 69530 ATTRIBUTES: KMASK 69531 PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR 69532 OPERANDS: MEM0:w:q:u64 REG0=MASK_R():r:mskw 69533 IFORM: KMOVQ_MEMu64_MASKmskw_AVX512 69534 } 69535 69536 69537 # EMITTING KMOVQ (KMOVQ-128-3) 69538 { 69539 ICLASS: KMOVQ 69540 CPL: 3 69541 CATEGORY: KMASK 69542 EXTENSION: AVX512VEX 69543 ISA_SET: AVX512BW_KOP 69544 EXCEPTIONS: AVX512-K20 69545 REAL_OPCODE: Y 69546 ATTRIBUTES: KMASK 69547 PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR 69548 OPERANDS: REG0=MASK_R():w:mskw REG1=GPR64_B():r:q:u64 69549 IFORM: KMOVQ_MASKmskw_GPR64u64_AVX512 69550 } 69551 69552 69553 # EMITTING KMOVQ (KMOVQ-128-4) 69554 { 69555 ICLASS: KMOVQ 69556 CPL: 3 69557 CATEGORY: KMASK 69558 EXTENSION: AVX512VEX 69559 ISA_SET: AVX512BW_KOP 69560 EXCEPTIONS: AVX512-K20 69561 REAL_OPCODE: Y 69562 ATTRIBUTES: KMASK 69563 PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR 69564 OPERANDS: REG0=GPR64_R():w:q:u64 REG1=MASK_B():r:mskw 69565 IFORM: KMOVQ_GPR64u64_MASKmskw_AVX512 69566 } 69567 69568 69569 # EMITTING KNOTB (KNOTB-128-1) 69570 { 69571 ICLASS: KNOTB 69572 CPL: 3 69573 CATEGORY: KMASK 69574 EXTENSION: AVX512VEX 69575 ISA_SET: AVX512DQ_KOP 69576 EXCEPTIONS: AVX512-K20 69577 REAL_OPCODE: Y 69578 ATTRIBUTES: KMASK 69579 PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 69580 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw 69581 IFORM: KNOTB_MASKmskw_MASKmskw_AVX512 69582 } 69583 69584 69585 # EMITTING KNOTD (KNOTD-128-1) 69586 { 69587 ICLASS: KNOTD 69588 CPL: 3 69589 CATEGORY: KMASK 69590 EXTENSION: AVX512VEX 69591 ISA_SET: AVX512BW_KOP 69592 EXCEPTIONS: AVX512-K20 69593 REAL_OPCODE: Y 69594 ATTRIBUTES: KMASK 69595 PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 69596 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw 69597 IFORM: KNOTD_MASKmskw_MASKmskw_AVX512 69598 } 69599 69600 69601 # EMITTING KNOTQ (KNOTQ-128-1) 69602 { 69603 ICLASS: KNOTQ 69604 CPL: 3 69605 CATEGORY: KMASK 69606 EXTENSION: AVX512VEX 69607 ISA_SET: AVX512BW_KOP 69608 EXCEPTIONS: AVX512-K20 69609 REAL_OPCODE: Y 69610 ATTRIBUTES: KMASK 69611 PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 69612 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw 69613 IFORM: KNOTQ_MASKmskw_MASKmskw_AVX512 69614 } 69615 69616 69617 # EMITTING KORB (KORB-256-1) 69618 { 69619 ICLASS: KORB 69620 CPL: 3 69621 CATEGORY: KMASK 69622 EXTENSION: AVX512VEX 69623 ISA_SET: AVX512DQ_KOP 69624 EXCEPTIONS: AVX512-K20 69625 REAL_OPCODE: Y 69626 ATTRIBUTES: KMASK 69627 PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 69628 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69629 IFORM: KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 69630 } 69631 69632 69633 # EMITTING KORD (KORD-256-1) 69634 { 69635 ICLASS: KORD 69636 CPL: 3 69637 CATEGORY: KMASK 69638 EXTENSION: AVX512VEX 69639 ISA_SET: AVX512BW_KOP 69640 EXCEPTIONS: AVX512-K20 69641 REAL_OPCODE: Y 69642 ATTRIBUTES: KMASK 69643 PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69644 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69645 IFORM: KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 69646 } 69647 69648 69649 # EMITTING KORQ (KORQ-256-1) 69650 { 69651 ICLASS: KORQ 69652 CPL: 3 69653 CATEGORY: KMASK 69654 EXTENSION: AVX512VEX 69655 ISA_SET: AVX512BW_KOP 69656 EXCEPTIONS: AVX512-K20 69657 REAL_OPCODE: Y 69658 ATTRIBUTES: KMASK 69659 PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69660 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69661 IFORM: KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 69662 } 69663 69664 69665 # EMITTING KORTESTB (KORTESTB-128-1) 69666 { 69667 ICLASS: KORTESTB 69668 CPL: 3 69669 CATEGORY: KMASK 69670 EXTENSION: AVX512VEX 69671 ISA_SET: AVX512DQ_KOP 69672 EXCEPTIONS: AVX512-K20 69673 REAL_OPCODE: Y 69674 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 69675 ATTRIBUTES: KMASK 69676 PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 69677 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 69678 IFORM: KORTESTB_MASKmskw_MASKmskw_AVX512 69679 } 69680 69681 69682 # EMITTING KORTESTD (KORTESTD-128-1) 69683 { 69684 ICLASS: KORTESTD 69685 CPL: 3 69686 CATEGORY: KMASK 69687 EXTENSION: AVX512VEX 69688 ISA_SET: AVX512BW_KOP 69689 EXCEPTIONS: AVX512-K20 69690 REAL_OPCODE: Y 69691 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 69692 ATTRIBUTES: KMASK 69693 PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 69694 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 69695 IFORM: KORTESTD_MASKmskw_MASKmskw_AVX512 69696 } 69697 69698 69699 # EMITTING KORTESTQ (KORTESTQ-128-1) 69700 { 69701 ICLASS: KORTESTQ 69702 CPL: 3 69703 CATEGORY: KMASK 69704 EXTENSION: AVX512VEX 69705 ISA_SET: AVX512BW_KOP 69706 EXCEPTIONS: AVX512-K20 69707 REAL_OPCODE: Y 69708 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 69709 ATTRIBUTES: KMASK 69710 PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 69711 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 69712 IFORM: KORTESTQ_MASKmskw_MASKmskw_AVX512 69713 } 69714 69715 69716 # EMITTING KSHIFTLB (KSHIFTLB-128-1) 69717 { 69718 ICLASS: KSHIFTLB 69719 CPL: 3 69720 CATEGORY: KMASK 69721 EXTENSION: AVX512VEX 69722 ISA_SET: AVX512DQ_KOP 69723 EXCEPTIONS: AVX512-K20 69724 REAL_OPCODE: Y 69725 ATTRIBUTES: KMASK 69726 PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() 69727 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 69728 IFORM: KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 69729 } 69730 69731 69732 # EMITTING KSHIFTLD (KSHIFTLD-128-1) 69733 { 69734 ICLASS: KSHIFTLD 69735 CPL: 3 69736 CATEGORY: KMASK 69737 EXTENSION: AVX512VEX 69738 ISA_SET: AVX512BW_KOP 69739 EXCEPTIONS: AVX512-K20 69740 REAL_OPCODE: Y 69741 ATTRIBUTES: KMASK 69742 PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() 69743 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 69744 IFORM: KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 69745 } 69746 69747 69748 # EMITTING KSHIFTLQ (KSHIFTLQ-128-1) 69749 { 69750 ICLASS: KSHIFTLQ 69751 CPL: 3 69752 CATEGORY: KMASK 69753 EXTENSION: AVX512VEX 69754 ISA_SET: AVX512BW_KOP 69755 EXCEPTIONS: AVX512-K20 69756 REAL_OPCODE: Y 69757 ATTRIBUTES: KMASK 69758 PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() 69759 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 69760 IFORM: KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 69761 } 69762 69763 69764 # EMITTING KSHIFTRB (KSHIFTRB-128-1) 69765 { 69766 ICLASS: KSHIFTRB 69767 CPL: 3 69768 CATEGORY: KMASK 69769 EXTENSION: AVX512VEX 69770 ISA_SET: AVX512DQ_KOP 69771 EXCEPTIONS: AVX512-K20 69772 REAL_OPCODE: Y 69773 ATTRIBUTES: KMASK 69774 PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() 69775 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 69776 IFORM: KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 69777 } 69778 69779 69780 # EMITTING KSHIFTRD (KSHIFTRD-128-1) 69781 { 69782 ICLASS: KSHIFTRD 69783 CPL: 3 69784 CATEGORY: KMASK 69785 EXTENSION: AVX512VEX 69786 ISA_SET: AVX512BW_KOP 69787 EXCEPTIONS: AVX512-K20 69788 REAL_OPCODE: Y 69789 ATTRIBUTES: KMASK 69790 PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() 69791 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 69792 IFORM: KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 69793 } 69794 69795 69796 # EMITTING KSHIFTRQ (KSHIFTRQ-128-1) 69797 { 69798 ICLASS: KSHIFTRQ 69799 CPL: 3 69800 CATEGORY: KMASK 69801 EXTENSION: AVX512VEX 69802 ISA_SET: AVX512BW_KOP 69803 EXCEPTIONS: AVX512-K20 69804 REAL_OPCODE: Y 69805 ATTRIBUTES: KMASK 69806 PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() 69807 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 69808 IFORM: KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 69809 } 69810 69811 69812 # EMITTING KTESTB (KTESTB-128-1) 69813 { 69814 ICLASS: KTESTB 69815 CPL: 3 69816 CATEGORY: KMASK 69817 EXTENSION: AVX512VEX 69818 ISA_SET: AVX512DQ_KOP 69819 EXCEPTIONS: AVX512-K20 69820 REAL_OPCODE: Y 69821 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 69822 ATTRIBUTES: KMASK 69823 PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 69824 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 69825 IFORM: KTESTB_MASKmskw_MASKmskw_AVX512 69826 } 69827 69828 69829 # EMITTING KTESTD (KTESTD-128-1) 69830 { 69831 ICLASS: KTESTD 69832 CPL: 3 69833 CATEGORY: KMASK 69834 EXTENSION: AVX512VEX 69835 ISA_SET: AVX512BW_KOP 69836 EXCEPTIONS: AVX512-K20 69837 REAL_OPCODE: Y 69838 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 69839 ATTRIBUTES: KMASK 69840 PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 69841 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 69842 IFORM: KTESTD_MASKmskw_MASKmskw_AVX512 69843 } 69844 69845 69846 # EMITTING KTESTQ (KTESTQ-128-1) 69847 { 69848 ICLASS: KTESTQ 69849 CPL: 3 69850 CATEGORY: KMASK 69851 EXTENSION: AVX512VEX 69852 ISA_SET: AVX512BW_KOP 69853 EXCEPTIONS: AVX512-K20 69854 REAL_OPCODE: Y 69855 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 69856 ATTRIBUTES: KMASK 69857 PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 69858 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 69859 IFORM: KTESTQ_MASKmskw_MASKmskw_AVX512 69860 } 69861 69862 69863 # EMITTING KTESTW (KTESTW-128-1) 69864 { 69865 ICLASS: KTESTW 69866 CPL: 3 69867 CATEGORY: KMASK 69868 EXTENSION: AVX512VEX 69869 ISA_SET: AVX512DQ_KOP 69870 EXCEPTIONS: AVX512-K20 69871 REAL_OPCODE: Y 69872 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 69873 ATTRIBUTES: KMASK 69874 PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 69875 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 69876 IFORM: KTESTW_MASKmskw_MASKmskw_AVX512 69877 } 69878 69879 69880 # EMITTING KUNPCKDQ (KUNPCKDQ-256-1) 69881 { 69882 ICLASS: KUNPCKDQ 69883 CPL: 3 69884 CATEGORY: KMASK 69885 EXTENSION: AVX512VEX 69886 ISA_SET: AVX512BW_KOP 69887 EXCEPTIONS: AVX512-K20 69888 REAL_OPCODE: Y 69889 ATTRIBUTES: KMASK 69890 PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69891 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69892 IFORM: KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 69893 } 69894 69895 69896 # EMITTING KUNPCKWD (KUNPCKWD-256-1) 69897 { 69898 ICLASS: KUNPCKWD 69899 CPL: 3 69900 CATEGORY: KMASK 69901 EXTENSION: AVX512VEX 69902 ISA_SET: AVX512BW_KOP 69903 EXCEPTIONS: AVX512-K20 69904 REAL_OPCODE: Y 69905 ATTRIBUTES: KMASK 69906 PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 69907 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69908 IFORM: KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 69909 } 69910 69911 69912 # EMITTING KXNORB (KXNORB-256-1) 69913 { 69914 ICLASS: KXNORB 69915 CPL: 3 69916 CATEGORY: KMASK 69917 EXTENSION: AVX512VEX 69918 ISA_SET: AVX512DQ_KOP 69919 EXCEPTIONS: AVX512-K20 69920 REAL_OPCODE: Y 69921 ATTRIBUTES: KMASK 69922 PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 69923 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69924 IFORM: KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 69925 } 69926 69927 69928 # EMITTING KXNORD (KXNORD-256-1) 69929 { 69930 ICLASS: KXNORD 69931 CPL: 3 69932 CATEGORY: KMASK 69933 EXTENSION: AVX512VEX 69934 ISA_SET: AVX512BW_KOP 69935 EXCEPTIONS: AVX512-K20 69936 REAL_OPCODE: Y 69937 ATTRIBUTES: KMASK 69938 PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69939 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69940 IFORM: KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 69941 } 69942 69943 69944 # EMITTING KXNORQ (KXNORQ-256-1) 69945 { 69946 ICLASS: KXNORQ 69947 CPL: 3 69948 CATEGORY: KMASK 69949 EXTENSION: AVX512VEX 69950 ISA_SET: AVX512BW_KOP 69951 EXCEPTIONS: AVX512-K20 69952 REAL_OPCODE: Y 69953 ATTRIBUTES: KMASK 69954 PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69955 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69956 IFORM: KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 69957 } 69958 69959 69960 # EMITTING KXORB (KXORB-256-1) 69961 { 69962 ICLASS: KXORB 69963 CPL: 3 69964 CATEGORY: KMASK 69965 EXTENSION: AVX512VEX 69966 ISA_SET: AVX512DQ_KOP 69967 EXCEPTIONS: AVX512-K20 69968 REAL_OPCODE: Y 69969 ATTRIBUTES: KMASK 69970 PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 69971 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69972 IFORM: KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 69973 } 69974 69975 69976 # EMITTING KXORD (KXORD-256-1) 69977 { 69978 ICLASS: KXORD 69979 CPL: 3 69980 CATEGORY: KMASK 69981 EXTENSION: AVX512VEX 69982 ISA_SET: AVX512BW_KOP 69983 EXCEPTIONS: AVX512-K20 69984 REAL_OPCODE: Y 69985 ATTRIBUTES: KMASK 69986 PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 69987 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 69988 IFORM: KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 69989 } 69990 69991 69992 # EMITTING KXORQ (KXORQ-256-1) 69993 { 69994 ICLASS: KXORQ 69995 CPL: 3 69996 CATEGORY: KMASK 69997 EXTENSION: AVX512VEX 69998 ISA_SET: AVX512BW_KOP 69999 EXCEPTIONS: AVX512-K20 70000 REAL_OPCODE: Y 70001 ATTRIBUTES: KMASK 70002 PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 70003 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 70004 IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 70005 } 70006 70007 70008 70009 70010 ###FILE: ../xed/datafiles/avx512ifma/ifma-isa.xed.txt 70011 70012 #BEGIN_LEGAL 70013 # 70014 #Copyright (c) 2016 Intel Corporation 70015 # 70016 # Licensed under the Apache License, Version 2.0 (the "License"); 70017 # you may not use this file except in compliance with the License. 70018 # You may obtain a copy of the License at 70019 # 70020 # http://www.apache.org/licenses/LICENSE-2.0 70021 # 70022 # Unless required by applicable law or agreed to in writing, software 70023 # distributed under the License is distributed on an "AS IS" BASIS, 70024 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 70025 # See the License for the specific language governing permissions and 70026 # limitations under the License. 70027 # 70028 #END_LEGAL 70029 # 70030 # 70031 # 70032 # ***** GENERATED FILE -- DO NOT EDIT! ***** 70033 # ***** GENERATED FILE -- DO NOT EDIT! ***** 70034 # ***** GENERATED FILE -- DO NOT EDIT! ***** 70035 # 70036 # 70037 # 70038 EVEX_INSTRUCTIONS():: 70039 # EMITTING VPMADD52HUQ (VPMADD52HUQ-128-1) 70040 { 70041 ICLASS: VPMADD52HUQ 70042 CPL: 3 70043 CATEGORY: IFMA 70044 EXTENSION: AVX512EVEX 70045 ISA_SET: AVX512IFMA_128 70046 EXCEPTIONS: AVX512-E4 70047 REAL_OPCODE: Y 70048 ATTRIBUTES: MASKOP_EVEX 70049 PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 70050 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 70051 IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 70052 } 70053 70054 { 70055 ICLASS: VPMADD52HUQ 70056 CPL: 3 70057 CATEGORY: IFMA 70058 EXTENSION: AVX512EVEX 70059 ISA_SET: AVX512IFMA_128 70060 EXCEPTIONS: AVX512-E4 70061 REAL_OPCODE: Y 70062 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 70063 PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 70064 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 70065 IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 70066 } 70067 70068 70069 # EMITTING VPMADD52HUQ (VPMADD52HUQ-256-1) 70070 { 70071 ICLASS: VPMADD52HUQ 70072 CPL: 3 70073 CATEGORY: IFMA 70074 EXTENSION: AVX512EVEX 70075 ISA_SET: AVX512IFMA_256 70076 EXCEPTIONS: AVX512-E4 70077 REAL_OPCODE: Y 70078 ATTRIBUTES: MASKOP_EVEX 70079 PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 70080 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 70081 IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 70082 } 70083 70084 { 70085 ICLASS: VPMADD52HUQ 70086 CPL: 3 70087 CATEGORY: IFMA 70088 EXTENSION: AVX512EVEX 70089 ISA_SET: AVX512IFMA_256 70090 EXCEPTIONS: AVX512-E4 70091 REAL_OPCODE: Y 70092 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 70093 PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 70094 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 70095 IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 70096 } 70097 70098 70099 # EMITTING VPMADD52HUQ (VPMADD52HUQ-512-1) 70100 { 70101 ICLASS: VPMADD52HUQ 70102 CPL: 3 70103 CATEGORY: IFMA 70104 EXTENSION: AVX512EVEX 70105 ISA_SET: AVX512IFMA_512 70106 EXCEPTIONS: AVX512-E4 70107 REAL_OPCODE: Y 70108 ATTRIBUTES: MASKOP_EVEX 70109 PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 70110 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 70111 IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 70112 } 70113 70114 { 70115 ICLASS: VPMADD52HUQ 70116 CPL: 3 70117 CATEGORY: IFMA 70118 EXTENSION: AVX512EVEX 70119 ISA_SET: AVX512IFMA_512 70120 EXCEPTIONS: AVX512-E4 70121 REAL_OPCODE: Y 70122 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 70123 PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 70124 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 70125 IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 70126 } 70127 70128 70129 # EMITTING VPMADD52LUQ (VPMADD52LUQ-128-1) 70130 { 70131 ICLASS: VPMADD52LUQ 70132 CPL: 3 70133 CATEGORY: IFMA 70134 EXTENSION: AVX512EVEX 70135 ISA_SET: AVX512IFMA_128 70136 EXCEPTIONS: AVX512-E4 70137 REAL_OPCODE: Y 70138 ATTRIBUTES: MASKOP_EVEX 70139 PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 70140 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 70141 IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 70142 } 70143 70144 { 70145 ICLASS: VPMADD52LUQ 70146 CPL: 3 70147 CATEGORY: IFMA 70148 EXTENSION: AVX512EVEX 70149 ISA_SET: AVX512IFMA_128 70150 EXCEPTIONS: AVX512-E4 70151 REAL_OPCODE: Y 70152 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 70153 PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 70154 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 70155 IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 70156 } 70157 70158 70159 # EMITTING VPMADD52LUQ (VPMADD52LUQ-256-1) 70160 { 70161 ICLASS: VPMADD52LUQ 70162 CPL: 3 70163 CATEGORY: IFMA 70164 EXTENSION: AVX512EVEX 70165 ISA_SET: AVX512IFMA_256 70166 EXCEPTIONS: AVX512-E4 70167 REAL_OPCODE: Y 70168 ATTRIBUTES: MASKOP_EVEX 70169 PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 70170 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 70171 IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 70172 } 70173 70174 { 70175 ICLASS: VPMADD52LUQ 70176 CPL: 3 70177 CATEGORY: IFMA 70178 EXTENSION: AVX512EVEX 70179 ISA_SET: AVX512IFMA_256 70180 EXCEPTIONS: AVX512-E4 70181 REAL_OPCODE: Y 70182 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 70183 PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 70184 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 70185 IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 70186 } 70187 70188 70189 # EMITTING VPMADD52LUQ (VPMADD52LUQ-512-1) 70190 { 70191 ICLASS: VPMADD52LUQ 70192 CPL: 3 70193 CATEGORY: IFMA 70194 EXTENSION: AVX512EVEX 70195 ISA_SET: AVX512IFMA_512 70196 EXCEPTIONS: AVX512-E4 70197 REAL_OPCODE: Y 70198 ATTRIBUTES: MASKOP_EVEX 70199 PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 70200 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 70201 IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 70202 } 70203 70204 { 70205 ICLASS: VPMADD52LUQ 70206 CPL: 3 70207 CATEGORY: IFMA 70208 EXTENSION: AVX512EVEX 70209 ISA_SET: AVX512IFMA_512 70210 EXCEPTIONS: AVX512-E4 70211 REAL_OPCODE: Y 70212 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 70213 PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 70214 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 70215 IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 70216 } 70217 70218 70219 70220 70221 ###FILE: ../xed/datafiles/avx512vbmi/vbmi-isa.xed.txt 70222 70223 #BEGIN_LEGAL 70224 # 70225 #Copyright (c) 2016 Intel Corporation 70226 # 70227 # Licensed under the Apache License, Version 2.0 (the "License"); 70228 # you may not use this file except in compliance with the License. 70229 # You may obtain a copy of the License at 70230 # 70231 # http://www.apache.org/licenses/LICENSE-2.0 70232 # 70233 # Unless required by applicable law or agreed to in writing, software 70234 # distributed under the License is distributed on an "AS IS" BASIS, 70235 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 70236 # See the License for the specific language governing permissions and 70237 # limitations under the License. 70238 # 70239 #END_LEGAL 70240 # 70241 # 70242 # 70243 # ***** GENERATED FILE -- DO NOT EDIT! ***** 70244 # ***** GENERATED FILE -- DO NOT EDIT! ***** 70245 # ***** GENERATED FILE -- DO NOT EDIT! ***** 70246 # 70247 # 70248 # 70249 EVEX_INSTRUCTIONS():: 70250 # EMITTING VPERMB (VPERMB-128-1) 70251 { 70252 ICLASS: VPERMB 70253 CPL: 3 70254 CATEGORY: AVX512VBMI 70255 EXTENSION: AVX512EVEX 70256 ISA_SET: AVX512VBMI_128 70257 EXCEPTIONS: AVX512-E4NF 70258 REAL_OPCODE: Y 70259 ATTRIBUTES: MASKOP_EVEX 70260 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 70261 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 70262 IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 70263 } 70264 70265 { 70266 ICLASS: VPERMB 70267 CPL: 3 70268 CATEGORY: AVX512VBMI 70269 EXTENSION: AVX512EVEX 70270 ISA_SET: AVX512VBMI_128 70271 EXCEPTIONS: AVX512-E4NF 70272 REAL_OPCODE: Y 70273 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 70274 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() 70275 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 70276 IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 70277 } 70278 70279 70280 # EMITTING VPERMB (VPERMB-256-1) 70281 { 70282 ICLASS: VPERMB 70283 CPL: 3 70284 CATEGORY: AVX512VBMI 70285 EXTENSION: AVX512EVEX 70286 ISA_SET: AVX512VBMI_256 70287 EXCEPTIONS: AVX512-E4NF 70288 REAL_OPCODE: Y 70289 ATTRIBUTES: MASKOP_EVEX 70290 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 70291 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 70292 IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 70293 } 70294 70295 { 70296 ICLASS: VPERMB 70297 CPL: 3 70298 CATEGORY: AVX512VBMI 70299 EXTENSION: AVX512EVEX 70300 ISA_SET: AVX512VBMI_256 70301 EXCEPTIONS: AVX512-E4NF 70302 REAL_OPCODE: Y 70303 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 70304 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() 70305 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 70306 IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 70307 } 70308 70309 70310 # EMITTING VPERMB (VPERMB-512-1) 70311 { 70312 ICLASS: VPERMB 70313 CPL: 3 70314 CATEGORY: AVX512VBMI 70315 EXTENSION: AVX512EVEX 70316 ISA_SET: AVX512VBMI_512 70317 EXCEPTIONS: AVX512-E4NF 70318 REAL_OPCODE: Y 70319 ATTRIBUTES: MASKOP_EVEX 70320 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 70321 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 70322 IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 70323 } 70324 70325 { 70326 ICLASS: VPERMB 70327 CPL: 3 70328 CATEGORY: AVX512VBMI 70329 EXTENSION: AVX512EVEX 70330 ISA_SET: AVX512VBMI_512 70331 EXCEPTIONS: AVX512-E4NF 70332 REAL_OPCODE: Y 70333 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 70334 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() 70335 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 70336 IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 70337 } 70338 70339 70340 # EMITTING VPERMI2B (VPERMI2B-128-1) 70341 { 70342 ICLASS: VPERMI2B 70343 CPL: 3 70344 CATEGORY: AVX512VBMI 70345 EXTENSION: AVX512EVEX 70346 ISA_SET: AVX512VBMI_128 70347 EXCEPTIONS: AVX512-E4NF 70348 REAL_OPCODE: Y 70349 ATTRIBUTES: MASKOP_EVEX 70350 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 70351 OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 70352 IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 70353 } 70354 70355 { 70356 ICLASS: VPERMI2B 70357 CPL: 3 70358 CATEGORY: AVX512VBMI 70359 EXTENSION: AVX512EVEX 70360 ISA_SET: AVX512VBMI_128 70361 EXCEPTIONS: AVX512-E4NF 70362 REAL_OPCODE: Y 70363 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 70364 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() 70365 OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 70366 IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 70367 } 70368 70369 70370 # EMITTING VPERMI2B (VPERMI2B-256-1) 70371 { 70372 ICLASS: VPERMI2B 70373 CPL: 3 70374 CATEGORY: AVX512VBMI 70375 EXTENSION: AVX512EVEX 70376 ISA_SET: AVX512VBMI_256 70377 EXCEPTIONS: AVX512-E4NF 70378 REAL_OPCODE: Y 70379 ATTRIBUTES: MASKOP_EVEX 70380 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 70381 OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 70382 IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 70383 } 70384 70385 { 70386 ICLASS: VPERMI2B 70387 CPL: 3 70388 CATEGORY: AVX512VBMI 70389 EXTENSION: AVX512EVEX 70390 ISA_SET: AVX512VBMI_256 70391 EXCEPTIONS: AVX512-E4NF 70392 REAL_OPCODE: Y 70393 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 70394 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() 70395 OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 70396 IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 70397 } 70398 70399 70400 # EMITTING VPERMI2B (VPERMI2B-512-1) 70401 { 70402 ICLASS: VPERMI2B 70403 CPL: 3 70404 CATEGORY: AVX512VBMI 70405 EXTENSION: AVX512EVEX 70406 ISA_SET: AVX512VBMI_512 70407 EXCEPTIONS: AVX512-E4NF 70408 REAL_OPCODE: Y 70409 ATTRIBUTES: MASKOP_EVEX 70410 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 70411 OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 70412 IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 70413 } 70414 70415 { 70416 ICLASS: VPERMI2B 70417 CPL: 3 70418 CATEGORY: AVX512VBMI 70419 EXTENSION: AVX512EVEX 70420 ISA_SET: AVX512VBMI_512 70421 EXCEPTIONS: AVX512-E4NF 70422 REAL_OPCODE: Y 70423 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 70424 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() 70425 OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 70426 IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 70427 } 70428 70429 70430 # EMITTING VPERMT2B (VPERMT2B-128-1) 70431 { 70432 ICLASS: VPERMT2B 70433 CPL: 3 70434 CATEGORY: AVX512VBMI 70435 EXTENSION: AVX512EVEX 70436 ISA_SET: AVX512VBMI_128 70437 EXCEPTIONS: AVX512-E4NF 70438 REAL_OPCODE: Y 70439 ATTRIBUTES: MASKOP_EVEX 70440 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 70441 OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 70442 IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 70443 } 70444 70445 { 70446 ICLASS: VPERMT2B 70447 CPL: 3 70448 CATEGORY: AVX512VBMI 70449 EXTENSION: AVX512EVEX 70450 ISA_SET: AVX512VBMI_128 70451 EXCEPTIONS: AVX512-E4NF 70452 REAL_OPCODE: Y 70453 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 70454 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() 70455 OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 70456 IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 70457 } 70458 70459 70460 # EMITTING VPERMT2B (VPERMT2B-256-1) 70461 { 70462 ICLASS: VPERMT2B 70463 CPL: 3 70464 CATEGORY: AVX512VBMI 70465 EXTENSION: AVX512EVEX 70466 ISA_SET: AVX512VBMI_256 70467 EXCEPTIONS: AVX512-E4NF 70468 REAL_OPCODE: Y 70469 ATTRIBUTES: MASKOP_EVEX 70470 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 70471 OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 70472 IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 70473 } 70474 70475 { 70476 ICLASS: VPERMT2B 70477 CPL: 3 70478 CATEGORY: AVX512VBMI 70479 EXTENSION: AVX512EVEX 70480 ISA_SET: AVX512VBMI_256 70481 EXCEPTIONS: AVX512-E4NF 70482 REAL_OPCODE: Y 70483 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 70484 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() 70485 OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 70486 IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 70487 } 70488 70489 70490 # EMITTING VPERMT2B (VPERMT2B-512-1) 70491 { 70492 ICLASS: VPERMT2B 70493 CPL: 3 70494 CATEGORY: AVX512VBMI 70495 EXTENSION: AVX512EVEX 70496 ISA_SET: AVX512VBMI_512 70497 EXCEPTIONS: AVX512-E4NF 70498 REAL_OPCODE: Y 70499 ATTRIBUTES: MASKOP_EVEX 70500 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 70501 OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 70502 IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 70503 } 70504 70505 { 70506 ICLASS: VPERMT2B 70507 CPL: 3 70508 CATEGORY: AVX512VBMI 70509 EXTENSION: AVX512EVEX 70510 ISA_SET: AVX512VBMI_512 70511 EXCEPTIONS: AVX512-E4NF 70512 REAL_OPCODE: Y 70513 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 70514 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() 70515 OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 70516 IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 70517 } 70518 70519 70520 # EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-128-1) 70521 { 70522 ICLASS: VPMULTISHIFTQB 70523 CPL: 3 70524 CATEGORY: AVX512VBMI 70525 EXTENSION: AVX512EVEX 70526 ISA_SET: AVX512VBMI_128 70527 EXCEPTIONS: AVX512-E4NF 70528 REAL_OPCODE: Y 70529 ATTRIBUTES: MASKOP_EVEX 70530 PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 70531 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 70532 IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 70533 } 70534 70535 { 70536 ICLASS: VPMULTISHIFTQB 70537 CPL: 3 70538 CATEGORY: AVX512VBMI 70539 EXTENSION: AVX512EVEX 70540 ISA_SET: AVX512VBMI_128 70541 EXCEPTIONS: AVX512-E4NF 70542 REAL_OPCODE: Y 70543 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 70544 PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 70545 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR 70546 IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 70547 } 70548 70549 70550 # EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-256-1) 70551 { 70552 ICLASS: VPMULTISHIFTQB 70553 CPL: 3 70554 CATEGORY: AVX512VBMI 70555 EXTENSION: AVX512EVEX 70556 ISA_SET: AVX512VBMI_256 70557 EXCEPTIONS: AVX512-E4NF 70558 REAL_OPCODE: Y 70559 ATTRIBUTES: MASKOP_EVEX 70560 PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 70561 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 70562 IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 70563 } 70564 70565 { 70566 ICLASS: VPMULTISHIFTQB 70567 CPL: 3 70568 CATEGORY: AVX512VBMI 70569 EXTENSION: AVX512EVEX 70570 ISA_SET: AVX512VBMI_256 70571 EXCEPTIONS: AVX512-E4NF 70572 REAL_OPCODE: Y 70573 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 70574 PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 70575 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR 70576 IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 70577 } 70578 70579 70580 # EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-512-1) 70581 { 70582 ICLASS: VPMULTISHIFTQB 70583 CPL: 3 70584 CATEGORY: AVX512VBMI 70585 EXTENSION: AVX512EVEX 70586 ISA_SET: AVX512VBMI_512 70587 EXCEPTIONS: AVX512-E4NF 70588 REAL_OPCODE: Y 70589 ATTRIBUTES: MASKOP_EVEX 70590 PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 70591 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 70592 IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 70593 } 70594 70595 { 70596 ICLASS: VPMULTISHIFTQB 70597 CPL: 3 70598 CATEGORY: AVX512VBMI 70599 EXTENSION: AVX512EVEX 70600 ISA_SET: AVX512VBMI_512 70601 EXCEPTIONS: AVX512-E4NF 70602 REAL_OPCODE: Y 70603 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 70604 PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 70605 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR 70606 IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 70607 } 70608 70609 70610
